Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	55	1			T12	1		T21	1		T70	1
class_index[0x1]	56	1			T4	1		T70	1		T27	1
class_index[0x2]	52	1			T4	1		T21	1		T24	1
class_index[0x3]	62	1			T20	1		T31	2		T27	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	76	1			T21	1		T70	1		T31	1
intr_timeout_cnt[1]	33	1			T12	1		T21	1		T24	1
intr_timeout_cnt[2]	25	1			T70	1		T27	1		T74	1
intr_timeout_cnt[3]	20	1			T31	2		T51	1		T40	1
intr_timeout_cnt[4]	23	1			T20	1		T27	1		T233	2
intr_timeout_cnt[5]	10	1			T4	1		T234	1		T233	1
intr_timeout_cnt[6]	11	1			T66	1		T31	1		T27	1
intr_timeout_cnt[7]	9	1			T27	1		T77	1		T78	1
intr_timeout_cnt[8]	14	1			T27	1		T50	1		T235	2
intr_timeout_cnt[9]	4	1			T4	1		T27	1		T236	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	22	1			T21	1		T70	1		T27	1
class_index[0x0]	intr_timeout_cnt[1]	5	1			T12	1		T80	1		T237	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T74	1		T104	1		T57	1
class_index[0x0]	intr_timeout_cnt[3]	9	1			T31	1		T111	1		T238	1
class_index[0x0]	intr_timeout_cnt[4]	5	1			T87	1		T239	1		T240	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T210	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	1	1			T241	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T242	1		T113	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T235	1		T243	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T27	1		T236	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	18	1			T49	3		T80	1		T83	1
class_index[0x1]	intr_timeout_cnt[1]	4	1			T82	1		T244	1		T111	1
class_index[0x1]	intr_timeout_cnt[2]	11	1			T70	1		T27	1		T52	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T51	1		T245	1		T246	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T106	1		T247	1		T239	1
class_index[0x1]	intr_timeout_cnt[5]	5	1			T4	1		T234	1		T233	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T238	1		T184	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	3	1			T77	1		T78	1		T238	1
class_index[0x1]	intr_timeout_cnt[8]	5	1			T235	1		T248	4		-	-
class_index[0x2]	intr_timeout_cnt[0]	18	1			T31	1		T74	1		T78	2
class_index[0x2]	intr_timeout_cnt[1]	6	1			T21	1		T24	1		T249	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T50	1		T81	1		T235	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T243	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	8	1			T27	1		T233	2		T250	2
class_index[0x2]	intr_timeout_cnt[5]	1	1			T113	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	3	1			T66	1		T236	1		T230	1
class_index[0x2]	intr_timeout_cnt[7]	3	1			T27	1		T234	1		T235	1
class_index[0x2]	intr_timeout_cnt[8]	5	1			T50	1		T248	3		T247	1
class_index[0x2]	intr_timeout_cnt[9]	2	1			T4	1		T251	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	18	1			T49	1		T78	1		T88	1
class_index[0x3]	intr_timeout_cnt[1]	18	1			T78	1		T50	3		T53	1
class_index[0x3]	intr_timeout_cnt[2]	3	1			T57	1		T252	1		T224	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T31	1		T40	1		T111	1
class_index[0x3]	intr_timeout_cnt[4]	7	1			T20	1		T59	1		T111	1
class_index[0x3]	intr_timeout_cnt[5]	3	1			T253	1		T254	1		T255	1
class_index[0x3]	intr_timeout_cnt[6]	5	1			T31	1		T27	1		T78	2
class_index[0x3]	intr_timeout_cnt[7]	1	1			T256	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T27	1		T243	1		-	-