Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	353427	1			T1	1191		T3	9		T4	2158
all_values[1]	353427	1			T1	1191		T3	9		T4	2158
all_values[2]	353427	1			T1	1191		T3	9		T4	2158
all_values[3]	353427	1			T1	1191		T3	9		T4	2158

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

703518

1

T1

2446

T3

22

T4

4297

auto[1]

710190

1

T1

2318

T3

14

T4

4335

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

851229

1

T1

2420

T3

6

T4

4588

auto[1]

562479

1

T1

2344

T3

30

T4

4044

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102033	1			T1	327		T3	1		T4	605
all_values[0]	auto[0]	auto[1]	73866	1			T1	293		T3	4		T4	466
all_values[0]	auto[1]	auto[0]	103195	1			T1	295		T4	610		T11	474
all_values[0]	auto[1]	auto[1]	74333	1			T1	276		T3	4		T4	477
all_values[1]	auto[0]	auto[0]	107296	1			T1	316		T3	1		T4	596
all_values[1]	auto[0]	auto[1]	68274	1			T1	306		T3	5		T4	484
all_values[1]	auto[1]	auto[0]	109051	1			T1	289		T4	586		T11	455
all_values[1]	auto[1]	auto[1]	68806	1			T1	280		T3	3		T4	492
all_values[2]	auto[0]	auto[0]	106582	1			T1	302		T3	2		T4	541
all_values[2]	auto[0]	auto[1]	69358	1			T1	300		T3	3		T4	526
all_values[2]	auto[1]	auto[0]	108317	1			T1	295		T3	1		T4	557
all_values[2]	auto[1]	auto[1]	69170	1			T1	294		T3	3		T4	534
all_values[3]	auto[0]	auto[0]	106778	1			T1	301		T3	1		T4	543
all_values[3]	auto[0]	auto[1]	69331	1			T1	301		T3	5		T4	536
all_values[3]	auto[1]	auto[0]	107977	1			T1	295		T4	550		T11	442
all_values[3]	auto[1]	auto[1]	69341	1			T1	294		T3	3		T4	529