Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	353427	1			T1	1191		T3	9		T4	2158
all_pins[1]	353427	1			T1	1191		T3	9		T4	2158
all_pins[2]	353427	1			T1	1191		T3	9		T4	2158
all_pins[3]	353427	1			T1	1191		T3	9		T4	2158

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1132058	1			T1	3620		T3	23		T4	6600
values[0x1]	281650	1			T1	1144		T3	13		T4	2032
transitions[0x0=>0x1]	188556	1			T1	744		T3	7		T4	1298
transitions[0x1=>0x0]	188799	1			T1	745		T3	7		T4	1298

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	279094	1			T1	915		T3	5		T4	1681
all_pins[0]	values[0x1]	74333	1			T1	276		T3	4		T4	477
all_pins[0]	transitions[0x0=>0x1]	73691	1			T1	275		T3	2		T4	476
all_pins[0]	transitions[0x1=>0x0]	68942	1			T1	294		T3	1		T4	528
all_pins[1]	values[0x0]	284621	1			T1	911		T3	6		T4	1666
all_pins[1]	values[0x1]	68806	1			T1	280		T3	3		T4	492
all_pins[1]	transitions[0x0=>0x1]	37845	1			T1	149		T3	2		T4	271
all_pins[1]	transitions[0x1=>0x0]	43372	1			T1	145		T3	3		T4	256
all_pins[2]	values[0x0]	284257	1			T1	897		T3	6		T4	1624
all_pins[2]	values[0x1]	69170	1			T1	294		T3	3		T4	534
all_pins[2]	transitions[0x0=>0x1]	38569	1			T1	158		T3	1		T4	295
all_pins[2]	transitions[0x1=>0x0]	38205	1			T1	144		T3	1		T4	253
all_pins[3]	values[0x0]	284086	1			T1	897		T3	6		T4	1629
all_pins[3]	values[0x1]	69341	1			T1	294		T3	3		T4	529
all_pins[3]	transitions[0x0=>0x1]	38451	1			T1	162		T3	2		T4	256
all_pins[3]	transitions[0x1=>0x0]	38280	1			T1	162		T3	2		T4	261