Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1			T153	7		T154	7		T213	7
all_values[1]	275	1			T153	7		T154	7		T213	7
all_values[2]	275	1			T153	7		T154	7		T213	7
all_values[3]	275	1			T153	7		T154	7		T213	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

604

1

T153

17

T154

18

T213

17

auto[1]

496

1

T153

11

T154

10

T213

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

451

1

T153

13

T154

12

T213

4

auto[1]

649

1

T153

15

T154

16

T213

24

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

650

1

T153

17

T154

16

T213

13

auto[1]

450

1

T153

11

T154

12

T213

15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

60

1

T153

2

T154

5

T323

1

all_values[0]

auto[0]

auto[0]

auto[1]

27

1

T153

1

T154

1

T213

2

all_values[0]

auto[0]

auto[1]

auto[0]

43

1

T153

2

T323

3

T324

1

all_values[0]

auto[0]

auto[1]

auto[1]

26

1

T213

2

T323

1

T324

2

all_values[0]

auto[1]

auto[0]

auto[1]

65

1

T153

2

T154

1

T213

3

all_values[0]

auto[1]

auto[1]

auto[1]

54

1

T323

2

T324

1

T325

4

all_values[1]

auto[0]

auto[0]

auto[0]

64

1

T153

1

T324

1

T325

3

all_values[1]

auto[0]

auto[0]

auto[1]

24

1

T153

1

T213

1

T323

2

all_values[1]

auto[0]

auto[1]

auto[0]

50

1

T154

2

T324

2

T325

1

all_values[1]

auto[0]

auto[1]

auto[1]

25

1

T153

1

T154

1

T213

1

all_values[1]

auto[1]

auto[0]

auto[1]

70

1

T153

2

T154

2

T213

3

all_values[1]

auto[1]

auto[1]

auto[1]

42

1

T153

2

T154

2

T213

2

all_values[2]

auto[0]

auto[0]

auto[0]

74

1

T153

2

T154

1

T213

3

all_values[2]

auto[0]

auto[0]

auto[1]

20

1

T154

1

T323

2

T324

2

all_values[2]

auto[0]

auto[1]

auto[0]

50

1

T153

2

T154

2

T213

1

all_values[2]

auto[0]

auto[1]

auto[1]

27

1

T213

1

T325

1

T326

1

all_values[2]

auto[1]

auto[0]

auto[1]

57

1

T153

3

T154

3

T323

1

all_values[2]

auto[1]

auto[1]

auto[1]

47

1

T213

2

T323

3

T324

2

all_values[3]

auto[0]

auto[0]

auto[0]

68

1

T153

2

T323

1

T325

1

all_values[3]

auto[0]

auto[0]

auto[1]

16

1

T154

1

T213

2

T324

1

all_values[3]

auto[0]

auto[1]

auto[0]

42

1

T153

2

T154

2

T323

3

all_values[3]

auto[0]

auto[1]

auto[1]

34

1

T153

1

T323

1

T324

1

all_values[3]

auto[1]

auto[0]

auto[1]

59

1

T153

1

T154

3

T213

3

all_values[3]

auto[1]

auto[1]

auto[1]

56

1

T153

1

T154

1

T213

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal