Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	89258	1			T1	597		T4	341		T12	225
accum_cnt_1000	240023	1			T1	1821		T4	1147		T12	1086
accum_cnt_100	27960	1			T1	91		T4	90		T12	216
accum_cnt_50	67844	1			T1	956		T3	3		T4	72
accum_cnt_10	169727	1			T1	32		T3	14		T4	3126
accum_cnt_0	415234	1			T1	5		T3	19		T4	1616

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	260459	1			T1	879		T3	9		T4	1598
class_index[0x1]	260459	1			T1	879		T3	9		T4	1598
class_index[0x2]	260459	1			T1	879		T3	9		T4	1598
class_index[0x3]	260459	1			T1	879		T3	9		T4	1598

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	20857	1			T4	341		T21	207		T24	211
class_index[0x0]	accum_cnt_1000	63577	1			T1	792		T4	1057		T12	72
class_index[0x0]	accum_cnt_100	8044	1			T1	39		T4	90		T12	20
class_index[0x0]	accum_cnt_50	15222	1			T1	35		T4	71		T12	19
class_index[0x0]	accum_cnt_10	34841	1			T1	13		T3	8		T4	26
class_index[0x0]	accum_cnt_0	109039	1			T3	1		T4	13		T11	1319
class_index[0x1]	accum_cnt_2000	20180	1			T1	161		T14	570		T15	73
class_index[0x1]	accum_cnt_1000	52132	1			T1	644		T4	90		T12	608
class_index[0x1]	accum_cnt_100	5675	1			T1	33		T12	122		T17	16
class_index[0x1]	accum_cnt_50	16021	1			T1	35		T12	101		T17	13
class_index[0x1]	accum_cnt_10	49689	1			T1	6		T4	1503		T11	1319
class_index[0x1]	accum_cnt_0	106925	1			T3	9		T4	5		T12	454
class_index[0x2]	accum_cnt_2000	27085	1			T13	279		T14	689		T15	252
class_index[0x2]	accum_cnt_1000	65253	1			T13	498		T14	642		T44	41
class_index[0x2]	accum_cnt_100	7111	1			T13	29		T14	29		T44	19
class_index[0x2]	accum_cnt_50	20588	1			T1	869		T4	1		T13	24
class_index[0x2]	accum_cnt_10	40429	1			T1	7		T4	10		T12	162
class_index[0x2]	accum_cnt_0	92668	1			T1	3		T3	9		T4	1587
class_index[0x3]	accum_cnt_2000	21136	1			T1	436		T12	225		T67	175
class_index[0x3]	accum_cnt_1000	59061	1			T1	385		T12	406		T17	42
class_index[0x3]	accum_cnt_100	7130	1			T1	19		T12	74		T17	22
class_index[0x3]	accum_cnt_50	16013	1			T1	17		T3	3		T12	120
class_index[0x3]	accum_cnt_10	44768	1			T1	6		T3	6		T4	1587
class_index[0x3]	accum_cnt_0	106602	1			T1	2		T4	11		T11	2