Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5371	1			T11	569		T12	39		T31	8
alert[0x1]	4834	1			T4	424		T11	297		T12	1
alert[0x2]	11011	1			T4	61		T11	1363		T15	5
alert[0x3]	7929	1			T4	1316		T12	123		T6	1
alert[0x4]	4403	1			T4	6		T6	1		T26	452
alert[0x5]	2249	1			T15	4		T31	9		T25	140
alert[0x6]	5123	1			T12	36		T6	1		T15	38
alert[0x7]	7425	1			T11	17		T15	11		T7	1
alert[0x8]	9905	1			T4	473		T12	9		T6	1
alert[0x9]	5362	1			T4	36		T11	318		T24	152
alert[0xa]	7571	1			T4	941		T15	6		T66	3
alert[0xb]	4768	1			T4	198		T11	61		T7	1
alert[0xc]	5265	1			T4	98		T11	148		T24	439
alert[0xd]	2642	1			T3	7		T66	10		T31	36
alert[0xe]	6694	1			T11	62		T24	29		T25	135
alert[0xf]	9114	1			T11	119		T15	3121		T31	1177
alert[0x10]	6453	1			T4	20		T6	1		T15	25
alert[0x11]	5229	1			T24	225		T31	10		T27	769
alert[0x12]	5619	1			T12	21		T24	1220		T31	294
alert[0x13]	4326	1			T15	9		T25	196		T26	39
alert[0x14]	3771	1			T27	148		T221	1		T219	1
alert[0x15]	4445	1			T3	1		T12	7		T31	29
alert[0x16]	4487	1			T4	2		T12	50		T31	1880
alert[0x17]	12250	1			T12	10		T5	1		T15	1927
alert[0x18]	4727	1			T11	97		T7	1		T25	76
alert[0x19]	4408	1			T4	27		T11	32		T15	215
alert[0x1a]	3850	1			T4	21		T11	24		T6	1
alert[0x1b]	8478	1			T11	13		T15	462		T24	35
alert[0x1c]	4394	1			T15	11		T24	28		T67	1
alert[0x1d]	1899	1			T25	521		T26	81		T74	19
alert[0x1e]	6226	1			T12	327		T24	188		T72	1
alert[0x1f]	10710	1			T15	241		T24	127		T72	1
alert[0x20]	5019	1			T25	69		T27	4		T26	261
alert[0x21]	8474	1			T11	2393		T12	20		T31	20
alert[0x22]	8040	1			T11	81		T15	18		T24	511
alert[0x23]	12660	1			T4	9		T11	22		T12	19
alert[0x24]	5497	1			T11	453		T15	4		T31	1
alert[0x25]	3803	1			T31	307		T25	33		T27	487
alert[0x26]	6467	1			T3	10		T11	416		T15	1313
alert[0x27]	3527	1			T11	31		T15	88		T24	15
alert[0x28]	5584	1			T4	26		T25	126		T215	1
alert[0x29]	3856	1			T66	1		T31	24		T72	1
alert[0x2a]	4304	1			T12	5		T24	149		T31	308
alert[0x2b]	3419	1			T24	112		T27	1		T220	22
alert[0x2c]	4331	1			T3	1		T12	49		T66	8
alert[0x2d]	9453	1			T11	31		T5	1		T15	2
alert[0x2e]	2198	1			T31	196		T72	1		T74	40
alert[0x2f]	6791	1			T3	25		T4	285		T12	32
alert[0x30]	4745	1			T12	404		T49	2		T50	53
alert[0x31]	1972	1			T11	15		T12	36		T15	193
alert[0x32]	10477	1			T24	3		T25	3233		T27	3
alert[0x33]	4489	1			T11	421		T15	318		T24	22
alert[0x34]	8302	1			T4	34		T5	1		T15	2041
alert[0x35]	6353	1			T11	187		T12	20		T5	1
alert[0x36]	5124	1			T11	11		T5	1		T24	21
alert[0x37]	3534	1			T11	35		T15	35		T215	1
alert[0x38]	7875	1			T11	32		T5	1		T24	113
alert[0x39]	4927	1			T12	51		T15	14		T24	19
alert[0x3a]	8773	1			T11	19		T15	55		T31	178
alert[0x3b]	5325	1			T11	23		T12	1		T72	1
alert[0x3c]	8330	1			T4	18		T11	156		T12	335
alert[0x3d]	7015	1			T15	6		T24	705		T66	6
alert[0x3e]	6306	1			T11	7		T12	34		T31	35
alert[0x3f]	2332	1			T24	91		T27	13		T74	57
alert[0x40]	4446	1			T3	3		T4	170		T11	313

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	134106	1			T3	2		T4	2		T12	1
class_i[0x1]	96128	1			T3	45		T4	9		T15	10510
class_i[0x2]	62814	1			T4	4154		T11	7766		T12	1625
class_i[0x3]	91638	1			T12	3		T6	1		T7	2

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

384010

1

T3

47

T4

4165

T11

7766

alert_ping_fail

676

1

T5

6

T6

7

T7

8

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5363	1			T11	569		T12	39		T31	8
alert_integrity_fail	alert[0x1]	4829	1			T4	424		T11	297		T12	1
alert_integrity_fail	alert[0x2]	10999	1			T4	61		T11	1363		T15	5
alert_integrity_fail	alert[0x3]	7914	1			T4	1316		T12	123		T24	108
alert_integrity_fail	alert[0x4]	4398	1			T4	6		T26	452		T49	32
alert_integrity_fail	alert[0x5]	2236	1			T15	4		T31	9		T25	140
alert_integrity_fail	alert[0x6]	5115	1			T12	36		T15	38		T25	341
alert_integrity_fail	alert[0x7]	7407	1			T11	17		T15	11		T74	518
alert_integrity_fail	alert[0x8]	9884	1			T4	473		T12	9		T24	2277
alert_integrity_fail	alert[0x9]	5352	1			T4	36		T11	318		T24	152
alert_integrity_fail	alert[0xa]	7554	1			T4	941		T15	6		T66	3
alert_integrity_fail	alert[0xb]	4760	1			T4	198		T11	61		T31	23
alert_integrity_fail	alert[0xc]	5258	1			T4	98		T11	148		T24	439
alert_integrity_fail	alert[0xd]	2632	1			T3	7		T66	10		T31	36
alert_integrity_fail	alert[0xe]	6683	1			T11	62		T24	29		T25	135
alert_integrity_fail	alert[0xf]	9104	1			T11	119		T15	3121		T31	1177
alert_integrity_fail	alert[0x10]	6442	1			T4	20		T15	25		T24	83
alert_integrity_fail	alert[0x11]	5221	1			T24	225		T31	10		T27	769
alert_integrity_fail	alert[0x12]	5609	1			T12	21		T24	1220		T31	294
alert_integrity_fail	alert[0x13]	4317	1			T15	9		T25	196		T26	39
alert_integrity_fail	alert[0x14]	3755	1			T27	148		T49	6		T50	5
alert_integrity_fail	alert[0x15]	4427	1			T3	1		T12	7		T31	29
alert_integrity_fail	alert[0x16]	4475	1			T4	2		T12	50		T31	1880
alert_integrity_fail	alert[0x17]	12239	1			T12	10		T15	1927		T66	1
alert_integrity_fail	alert[0x18]	4712	1			T11	97		T25	76		T74	561
alert_integrity_fail	alert[0x19]	4400	1			T4	27		T11	32		T15	215
alert_integrity_fail	alert[0x1a]	3840	1			T4	21		T11	24		T66	1
alert_integrity_fail	alert[0x1b]	8469	1			T11	13		T15	462		T24	35
alert_integrity_fail	alert[0x1c]	4383	1			T15	11		T24	28		T31	18
alert_integrity_fail	alert[0x1d]	1896	1			T25	521		T26	81		T74	19
alert_integrity_fail	alert[0x1e]	6218	1			T12	327		T24	188		T48	3
alert_integrity_fail	alert[0x1f]	10696	1			T15	241		T24	127		T25	25
alert_integrity_fail	alert[0x20]	5007	1			T25	69		T27	4		T26	261
alert_integrity_fail	alert[0x21]	8459	1			T11	2393		T12	20		T31	20
alert_integrity_fail	alert[0x22]	8030	1			T11	81		T15	18		T24	511
alert_integrity_fail	alert[0x23]	12649	1			T4	9		T11	22		T12	19
alert_integrity_fail	alert[0x24]	5490	1			T11	453		T15	4		T31	1
alert_integrity_fail	alert[0x25]	3794	1			T31	307		T25	33		T27	487
alert_integrity_fail	alert[0x26]	6457	1			T3	10		T11	416		T15	1313
alert_integrity_fail	alert[0x27]	3513	1			T11	31		T15	88		T24	15
alert_integrity_fail	alert[0x28]	5569	1			T4	26		T25	126		T27	101
alert_integrity_fail	alert[0x29]	3849	1			T66	1		T31	24		T25	311
alert_integrity_fail	alert[0x2a]	4294	1			T12	5		T24	149		T31	308
alert_integrity_fail	alert[0x2b]	3407	1			T24	112		T27	1		T220	22
alert_integrity_fail	alert[0x2c]	4318	1			T3	1		T12	49		T66	8
alert_integrity_fail	alert[0x2d]	9439	1			T11	31		T15	2		T25	27
alert_integrity_fail	alert[0x2e]	2187	1			T31	196		T74	40		T220	81
alert_integrity_fail	alert[0x2f]	6782	1			T3	25		T4	285		T12	32
alert_integrity_fail	alert[0x30]	4735	1			T12	404		T49	2		T50	53
alert_integrity_fail	alert[0x31]	1967	1			T11	15		T12	36		T15	193
alert_integrity_fail	alert[0x32]	10471	1			T24	3		T25	3233		T27	3
alert_integrity_fail	alert[0x33]	4480	1			T11	421		T15	318		T24	22
alert_integrity_fail	alert[0x34]	8289	1			T4	34		T15	2041		T24	133
alert_integrity_fail	alert[0x35]	6342	1			T11	187		T12	20		T24	276
alert_integrity_fail	alert[0x36]	5109	1			T11	11		T24	21		T25	28
alert_integrity_fail	alert[0x37]	3526	1			T11	35		T15	35		T27	3
alert_integrity_fail	alert[0x38]	7866	1			T11	32		T24	113		T31	749
alert_integrity_fail	alert[0x39]	4917	1			T12	51		T15	14		T24	19
alert_integrity_fail	alert[0x3a]	8766	1			T11	19		T15	55		T31	178
alert_integrity_fail	alert[0x3b]	5314	1			T11	23		T12	1		T25	394
alert_integrity_fail	alert[0x3c]	8321	1			T4	18		T11	156		T12	335
alert_integrity_fail	alert[0x3d]	7007	1			T15	6		T24	705		T66	6
alert_integrity_fail	alert[0x3e]	6300	1			T11	7		T12	34		T31	35
alert_integrity_fail	alert[0x3f]	2330	1			T24	91		T27	13		T74	57
alert_integrity_fail	alert[0x40]	4439	1			T3	3		T4	170		T11	313
alert_ping_fail	alert[0x0]	8	1			T36	1		T282	1		T264	1
alert_ping_fail	alert[0x1]	5	1			T7	2		T283	1		T282	1
alert_ping_fail	alert[0x2]	12	1			T7	1		T215	2		T219	1
alert_ping_fail	alert[0x3]	15	1			T6	1		T257	1		T283	2
alert_ping_fail	alert[0x4]	5	1			T6	1		T257	1		T284	1
alert_ping_fail	alert[0x5]	13	1			T221	1		T257	1		T285	1
alert_ping_fail	alert[0x6]	8	1			T6	1		T215	1		T221	1
alert_ping_fail	alert[0x7]	18	1			T7	1		T221	1		T281	2
alert_ping_fail	alert[0x8]	21	1			T6	1		T216	3		T39	2
alert_ping_fail	alert[0x9]	10	1			T72	1		T217	1		T257	1
alert_ping_fail	alert[0xa]	17	1			T219	1		T281	2		T286	1
alert_ping_fail	alert[0xb]	8	1			T7	1		T219	1		T264	1
alert_ping_fail	alert[0xc]	7	1			T221	1		T257	1		T285	1
alert_ping_fail	alert[0xd]	10	1			T215	1		T287	1		T38	1
alert_ping_fail	alert[0xe]	11	1			T215	1		T282	1		T285	1
alert_ping_fail	alert[0xf]	10	1			T283	1		T288	1		T289	1
alert_ping_fail	alert[0x10]	11	1			T6	1		T215	1		T283	1
alert_ping_fail	alert[0x11]	8	1			T219	1		T38	1		T285	2
alert_ping_fail	alert[0x12]	10	1			T215	1		T288	1		T284	1
alert_ping_fail	alert[0x13]	9	1			T98	2		T34	1		T284	1
alert_ping_fail	alert[0x14]	16	1			T221	1		T219	1		T217	1
alert_ping_fail	alert[0x15]	18	1			T277	1		T98	1		T257	1
alert_ping_fail	alert[0x16]	12	1			T219	1		T217	2		T279	1
alert_ping_fail	alert[0x17]	11	1			T5	1		T282	2		T285	1
alert_ping_fail	alert[0x18]	15	1			T7	1		T219	2		T257	1
alert_ping_fail	alert[0x19]	8	1			T72	2		T215	1		T221	1
alert_ping_fail	alert[0x1a]	10	1			T6	1		T290	1		T286	1
alert_ping_fail	alert[0x1b]	9	1			T221	1		T217	1		T283	1
alert_ping_fail	alert[0x1c]	11	1			T67	1		T72	1		T215	1
alert_ping_fail	alert[0x1d]	3	1			T291	1		T292	1		T289	1
alert_ping_fail	alert[0x1e]	8	1			T72	1		T257	1		T283	1
alert_ping_fail	alert[0x1f]	14	1			T72	1		T38	1		T293	1
alert_ping_fail	alert[0x20]	12	1			T219	1		T257	1		T90	1
alert_ping_fail	alert[0x21]	15	1			T72	1		T290	1		T217	1
alert_ping_fail	alert[0x22]	10	1			T72	1		T278	1		T294	1
alert_ping_fail	alert[0x23]	11	1			T215	1		T219	2		T283	1
alert_ping_fail	alert[0x24]	7	1			T219	1		T217	1		T286	1
alert_ping_fail	alert[0x25]	9	1			T290	1		T173	1		T295	1
alert_ping_fail	alert[0x26]	10	1			T257	1		T283	2		T36	1
alert_ping_fail	alert[0x27]	14	1			T7	2		T72	1		T282	1
alert_ping_fail	alert[0x28]	15	1			T215	1		T221	1		T257	1
alert_ping_fail	alert[0x29]	7	1			T72	1		T221	1		T296	1
alert_ping_fail	alert[0x2a]	10	1			T72	1		T219	1		T257	1
alert_ping_fail	alert[0x2b]	12	1			T257	1		T283	1		T34	1
alert_ping_fail	alert[0x2c]	13	1			T72	2		T297	1		T298	1
alert_ping_fail	alert[0x2d]	14	1			T5	1		T219	1		T290	1
alert_ping_fail	alert[0x2e]	11	1			T72	1		T280	1		T38	1
alert_ping_fail	alert[0x2f]	9	1			T290	1		T264	1		T294	1
alert_ping_fail	alert[0x30]	10	1			T38	1		T299	1		T264	2
alert_ping_fail	alert[0x31]	5	1			T217	1		T285	1		T300	1
alert_ping_fail	alert[0x32]	6	1			T257	1		T283	1		T297	1
alert_ping_fail	alert[0x33]	9	1			T217	1		T283	1		T38	1
alert_ping_fail	alert[0x34]	13	1			T5	1		T215	2		T217	1
alert_ping_fail	alert[0x35]	11	1			T5	1		T72	1		T283	2
alert_ping_fail	alert[0x36]	15	1			T5	1		T72	1		T221	1
alert_ping_fail	alert[0x37]	8	1			T215	1		T286	1		T284	1
alert_ping_fail	alert[0x38]	9	1			T5	1		T219	1		T283	1
alert_ping_fail	alert[0x39]	10	1			T72	1		T282	1		T285	1
alert_ping_fail	alert[0x3a]	7	1			T221	1		T219	1		T301	1
alert_ping_fail	alert[0x3b]	11	1			T72	1		T215	1		T257	1
alert_ping_fail	alert[0x3c]	9	1			T72	2		T215	1		T38	1
alert_ping_fail	alert[0x3d]	8	1			T215	1		T217	1		T282	1
alert_ping_fail	alert[0x3e]	6	1			T257	1		T291	1		T299	1
alert_ping_fail	alert[0x3f]	2	1			T298	1		T300	1		-	-
alert_ping_fail	alert[0x40]	7	1			T6	1		T221	2		T264	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	133871	1			T3	2		T4	2		T12	1
alert_integrity_fail	class_i[0x1]	96013	1			T3	45		T4	9		T15	10510
alert_integrity_fail	class_i[0x2]	62670	1			T4	4154		T11	7766		T12	1625
alert_integrity_fail	class_i[0x3]	91456	1			T12	3		T66	13		T31	384
alert_ping_fail	class_i[0x0]	235	1			T5	6		T6	3		T72	16
alert_ping_fail	class_i[0x1]	115	1			T7	5		T72	1		T290	2
alert_ping_fail	class_i[0x2]	144	1			T6	3		T7	1		T72	1
alert_ping_fail	class_i[0x3]	182	1			T6	1		T7	2		T67	1