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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.68 99.99 98.70 100.00 100.00 100.00 99.38 99.68


Total test records in report: 830
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T765 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1118831293 Jun 05 05:55:56 PM PDT 24 Jun 05 05:55:58 PM PDT 24 11367991 ps
T144 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2864289325 Jun 05 05:56:04 PM PDT 24 Jun 05 05:58:26 PM PDT 24 9976682823 ps
T766 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.4147995146 Jun 05 05:56:15 PM PDT 24 Jun 05 05:56:17 PM PDT 24 39695433 ps
T767 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2121552887 Jun 05 05:56:20 PM PDT 24 Jun 05 05:56:41 PM PDT 24 326592790 ps
T768 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.901634101 Jun 05 05:56:36 PM PDT 24 Jun 05 05:56:41 PM PDT 24 285492471 ps
T769 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4246175409 Jun 05 05:56:28 PM PDT 24 Jun 05 05:56:29 PM PDT 24 14880345 ps
T770 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3477583017 Jun 05 05:56:08 PM PDT 24 Jun 05 06:02:01 PM PDT 24 5883740644 ps
T771 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1851086824 Jun 05 05:56:00 PM PDT 24 Jun 05 05:56:09 PM PDT 24 76007784 ps
T772 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3547870170 Jun 05 05:56:29 PM PDT 24 Jun 05 05:56:31 PM PDT 24 6790979 ps
T773 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.339727294 Jun 05 05:56:08 PM PDT 24 Jun 05 05:56:31 PM PDT 24 347456404 ps
T774 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2995953833 Jun 05 05:56:36 PM PDT 24 Jun 05 05:56:46 PM PDT 24 124622449 ps
T140 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1148471954 Jun 05 05:56:19 PM PDT 24 Jun 05 06:01:08 PM PDT 24 2049113295 ps
T775 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1961287581 Jun 05 05:56:01 PM PDT 24 Jun 05 05:56:51 PM PDT 24 1353849020 ps
T143 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3885719706 Jun 05 05:56:02 PM PDT 24 Jun 05 06:05:05 PM PDT 24 31514450035 ps
T776 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3598586824 Jun 05 05:56:30 PM PDT 24 Jun 05 05:56:32 PM PDT 24 10724462 ps
T777 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4192567331 Jun 05 05:56:01 PM PDT 24 Jun 05 05:56:09 PM PDT 24 38963608 ps
T778 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.675542804 Jun 05 05:56:31 PM PDT 24 Jun 05 05:56:33 PM PDT 24 9414040 ps
T779 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2641291349 Jun 05 05:56:32 PM PDT 24 Jun 05 05:56:41 PM PDT 24 280202640 ps
T162 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.4251250810 Jun 05 05:56:17 PM PDT 24 Jun 05 05:56:21 PM PDT 24 564696679 ps
T780 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2985808861 Jun 05 05:56:29 PM PDT 24 Jun 05 05:56:31 PM PDT 24 6423271 ps
T781 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1814773017 Jun 05 05:56:12 PM PDT 24 Jun 05 05:56:13 PM PDT 24 7540842 ps
T782 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2843239432 Jun 05 05:56:03 PM PDT 24 Jun 05 05:56:09 PM PDT 24 20508715 ps
T783 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2989238461 Jun 05 05:56:15 PM PDT 24 Jun 05 05:56:17 PM PDT 24 11293113 ps
T784 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1780824955 Jun 05 05:56:05 PM PDT 24 Jun 05 05:56:08 PM PDT 24 7661461 ps
T142 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2380542763 Jun 05 05:55:56 PM PDT 24 Jun 05 05:58:40 PM PDT 24 9168816900 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1097289476 Jun 05 05:56:03 PM PDT 24 Jun 05 05:56:11 PM PDT 24 184316842 ps
T786 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3435645717 Jun 05 05:56:08 PM PDT 24 Jun 05 05:56:25 PM PDT 24 168778008 ps
T787 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3620329290 Jun 05 05:56:17 PM PDT 24 Jun 05 05:56:19 PM PDT 24 12351737 ps
T788 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1135353893 Jun 05 05:56:05 PM PDT 24 Jun 05 06:00:03 PM PDT 24 3274302093 ps
T789 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3302835874 Jun 05 05:56:24 PM PDT 24 Jun 05 05:56:30 PM PDT 24 35750296 ps
T168 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4188589948 Jun 05 05:55:57 PM PDT 24 Jun 05 05:57:01 PM PDT 24 11070514104 ps
T790 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3901535409 Jun 05 05:55:57 PM PDT 24 Jun 05 05:56:00 PM PDT 24 7878293 ps
T148 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2363733379 Jun 05 05:56:25 PM PDT 24 Jun 05 05:58:04 PM PDT 24 827149680 ps
T791 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3449768434 Jun 05 05:56:30 PM PDT 24 Jun 05 05:56:32 PM PDT 24 27066030 ps
T792 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2107273907 Jun 05 05:56:00 PM PDT 24 Jun 05 05:58:24 PM PDT 24 4449085916 ps
T793 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1958493330 Jun 05 05:56:07 PM PDT 24 Jun 05 05:56:13 PM PDT 24 625788937 ps
T794 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.670035576 Jun 05 05:56:29 PM PDT 24 Jun 05 05:58:32 PM PDT 24 1892405053 ps
T795 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4290963563 Jun 05 05:56:03 PM PDT 24 Jun 05 05:56:13 PM PDT 24 323889379 ps
T157 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3838259524 Jun 05 05:55:59 PM PDT 24 Jun 05 05:56:05 PM PDT 24 39001093 ps
T796 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1891010875 Jun 05 05:56:09 PM PDT 24 Jun 05 06:00:08 PM PDT 24 4458880363 ps
T797 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3048364861 Jun 05 05:56:30 PM PDT 24 Jun 05 05:56:39 PM PDT 24 96630426 ps
T798 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1874319192 Jun 05 05:56:14 PM PDT 24 Jun 05 05:56:17 PM PDT 24 89701293 ps
T799 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1888291660 Jun 05 05:56:33 PM PDT 24 Jun 05 05:56:44 PM PDT 24 520941370 ps
T800 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.125735261 Jun 05 05:55:59 PM PDT 24 Jun 05 05:56:06 PM PDT 24 1202253078 ps
T801 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2462023898 Jun 05 05:56:13 PM PDT 24 Jun 05 05:56:33 PM PDT 24 1037269323 ps
T802 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3016246967 Jun 05 05:56:15 PM PDT 24 Jun 05 05:56:28 PM PDT 24 370702526 ps
T803 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1911374716 Jun 05 05:55:58 PM PDT 24 Jun 05 05:56:16 PM PDT 24 88029074 ps
T804 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.415782010 Jun 05 05:56:06 PM PDT 24 Jun 05 05:56:12 PM PDT 24 59835763 ps
T135 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1106914818 Jun 05 05:56:31 PM PDT 24 Jun 05 06:01:55 PM PDT 24 4843576580 ps
T147 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.41878313 Jun 05 05:56:07 PM PDT 24 Jun 05 05:57:28 PM PDT 24 719823600 ps
T136 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3321371924 Jun 05 05:56:03 PM PDT 24 Jun 05 06:11:38 PM PDT 24 15026982377 ps
T805 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3649611017 Jun 05 05:56:27 PM PDT 24 Jun 05 05:56:48 PM PDT 24 5674578940 ps
T806 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.896962909 Jun 05 05:56:03 PM PDT 24 Jun 05 05:57:45 PM PDT 24 3325825909 ps
T807 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.788372383 Jun 05 05:56:02 PM PDT 24 Jun 05 06:05:02 PM PDT 24 15682516009 ps
T808 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1418166279 Jun 05 05:56:04 PM PDT 24 Jun 05 05:56:29 PM PDT 24 333553231 ps
T809 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.343946397 Jun 05 05:56:01 PM PDT 24 Jun 05 05:56:23 PM PDT 24 2166016752 ps
T810 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2866460009 Jun 05 05:56:21 PM PDT 24 Jun 05 05:56:29 PM PDT 24 196680666 ps
T811 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2388257552 Jun 05 05:56:29 PM PDT 24 Jun 05 05:56:31 PM PDT 24 6392218 ps
T812 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1797767865 Jun 05 05:56:28 PM PDT 24 Jun 05 05:56:52 PM PDT 24 1125209731 ps
T149 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1204344643 Jun 05 05:56:19 PM PDT 24 Jun 05 06:00:50 PM PDT 24 54171331197 ps
T813 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2733416608 Jun 05 05:56:32 PM PDT 24 Jun 05 05:56:35 PM PDT 24 12708940 ps
T814 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3762277750 Jun 05 05:56:17 PM PDT 24 Jun 05 05:56:19 PM PDT 24 8532443 ps
T815 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.641056413 Jun 05 05:55:59 PM PDT 24 Jun 05 05:56:04 PM PDT 24 47658295 ps
T816 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.777962635 Jun 05 05:56:02 PM PDT 24 Jun 05 05:56:05 PM PDT 24 13728852 ps
T817 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1248593203 Jun 05 05:56:08 PM PDT 24 Jun 05 05:56:16 PM PDT 24 302985381 ps
T818 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2386663806 Jun 05 05:56:06 PM PDT 24 Jun 05 05:56:15 PM PDT 24 177394495 ps
T819 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.914884787 Jun 05 05:56:01 PM PDT 24 Jun 05 05:56:16 PM PDT 24 97766859 ps
T820 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.632360565 Jun 05 05:56:01 PM PDT 24 Jun 05 05:56:09 PM PDT 24 134564823 ps
T165 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1458340062 Jun 05 05:56:12 PM PDT 24 Jun 05 05:56:26 PM PDT 24 196112898 ps
T821 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3892935310 Jun 05 05:56:01 PM PDT 24 Jun 05 05:56:45 PM PDT 24 2106144923 ps
T822 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.4002567179 Jun 05 05:56:15 PM PDT 24 Jun 05 05:56:30 PM PDT 24 146428026 ps
T823 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1105800113 Jun 05 05:56:00 PM PDT 24 Jun 05 05:56:04 PM PDT 24 16459231 ps
T824 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2802090174 Jun 05 05:56:27 PM PDT 24 Jun 05 05:56:29 PM PDT 24 12596729 ps
T825 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1119281483 Jun 05 05:56:40 PM PDT 24 Jun 05 05:56:42 PM PDT 24 8961661 ps
T826 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1025256205 Jun 05 05:56:00 PM PDT 24 Jun 05 05:56:04 PM PDT 24 10245211 ps
T827 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3805218871 Jun 05 05:56:37 PM PDT 24 Jun 05 05:56:38 PM PDT 24 48795399 ps
T330 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2657316354 Jun 05 05:56:17 PM PDT 24 Jun 05 06:03:42 PM PDT 24 6057632050 ps
T828 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.51184557 Jun 05 05:56:47 PM PDT 24 Jun 05 05:56:49 PM PDT 24 7710696 ps
T829 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2772517263 Jun 05 05:56:33 PM PDT 24 Jun 05 05:56:35 PM PDT 24 10770322 ps
T830 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1103660726 Jun 05 05:56:12 PM PDT 24 Jun 05 05:56:15 PM PDT 24 35890934 ps

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.596115425
Short name T12
Test name
Test status
Simulation time 46815584823 ps
CPU time 4034.79 seconds
Started Jun 05 06:17:35 PM PDT 24
Finished Jun 05 07:24:51 PM PDT 24
Peak memory 306348 kb
Host smart-ed43a311-c0c0-4be4-bc82-a2ba06906c9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596115425 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.596115425
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1924316369
Short name T31
Test name
Test status
Simulation time 175433649095 ps
CPU time 2325.84 seconds
Started Jun 05 06:28:38 PM PDT 24
Finished Jun 05 07:07:25 PM PDT 24
Peak memory 305472 kb
Host smart-0633f064-1202-4d99-8851-fe992869cd84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924316369 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1924316369
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.232968892
Short name T8
Test name
Test status
Simulation time 1280629746 ps
CPU time 18.62 seconds
Started Jun 05 06:16:33 PM PDT 24
Finished Jun 05 06:16:52 PM PDT 24
Peak memory 273604 kb
Host smart-85be5f1e-11d4-4eae-b2d9-9f8ad14dc2e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=232968892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.232968892
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2336147295
Short name T15
Test name
Test status
Simulation time 95451253129 ps
CPU time 1544.02 seconds
Started Jun 05 06:22:25 PM PDT 24
Finished Jun 05 06:48:10 PM PDT 24
Peak memory 273400 kb
Host smart-dff1616e-30c9-4660-928e-386b4eb1d43d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336147295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2336147295
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3261371321
Short name T159
Test name
Test status
Simulation time 4672277798 ps
CPU time 65.73 seconds
Started Jun 05 05:56:06 PM PDT 24
Finished Jun 05 05:57:13 PM PDT 24
Peak memory 238484 kb
Host smart-398048a7-13fd-4a01-9062-8e94f18d48b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3261371321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3261371321
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1364219938
Short name T49
Test name
Test status
Simulation time 227512215622 ps
CPU time 5143.59 seconds
Started Jun 05 06:16:08 PM PDT 24
Finished Jun 05 07:41:53 PM PDT 24
Peak memory 355408 kb
Host smart-0b4acf4b-2cbe-479e-886b-0eabdd1f7ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364219938 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1364219938
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2428875612
Short name T89
Test name
Test status
Simulation time 8370415924 ps
CPU time 846.46 seconds
Started Jun 05 06:28:06 PM PDT 24
Finished Jun 05 06:42:13 PM PDT 24
Peak memory 267604 kb
Host smart-67ae86aa-6a72-418f-a410-827cdad236b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428875612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2428875612
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3513769981
Short name T2
Test name
Test status
Simulation time 208850267 ps
CPU time 12.05 seconds
Started Jun 05 06:18:21 PM PDT 24
Finished Jun 05 06:18:33 PM PDT 24
Peak memory 248772 kb
Host smart-77ab5abf-d3d0-4d1f-94dc-33dff74e7012
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3513769981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3513769981
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1345529112
Short name T129
Test name
Test status
Simulation time 4600795866 ps
CPU time 292.21 seconds
Started Jun 05 05:56:06 PM PDT 24
Finished Jun 05 06:01:00 PM PDT 24
Peak memory 265496 kb
Host smart-0ad7d1cb-f5d2-4d24-a497-0f38e1ef6ee4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1345529112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1345529112
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3790970879
Short name T293
Test name
Test status
Simulation time 72648460382 ps
CPU time 1228.33 seconds
Started Jun 05 06:17:45 PM PDT 24
Finished Jun 05 06:38:14 PM PDT 24
Peak memory 285844 kb
Host smart-52f0856d-b58d-46a4-a1dc-7f7887789c2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790970879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3790970879
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.587277272
Short name T98
Test name
Test status
Simulation time 44925937576 ps
CPU time 1943.25 seconds
Started Jun 05 06:18:39 PM PDT 24
Finished Jun 05 06:51:03 PM PDT 24
Peak memory 273336 kb
Host smart-84be5683-e46c-4552-b856-131668be8819
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587277272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.587277272
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3917637078
Short name T108
Test name
Test status
Simulation time 60215541300 ps
CPU time 1559.17 seconds
Started Jun 05 06:20:04 PM PDT 24
Finished Jun 05 06:46:04 PM PDT 24
Peak memory 289588 kb
Host smart-c1daf35f-cf91-41e3-b652-8f54424775f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917637078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3917637078
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2679255434
Short name T114
Test name
Test status
Simulation time 4484872426 ps
CPU time 616.32 seconds
Started Jun 05 05:55:58 PM PDT 24
Finished Jun 05 06:06:16 PM PDT 24
Peak memory 265640 kb
Host smart-f47054c0-0021-4298-b9b1-dc19e2a5027d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679255434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2679255434
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3411317768
Short name T72
Test name
Test status
Simulation time 82847195015 ps
CPU time 553.86 seconds
Started Jun 05 06:18:46 PM PDT 24
Finished Jun 05 06:28:01 PM PDT 24
Peak memory 256136 kb
Host smart-ee9e22e1-2faa-4adb-a707-d192946a550f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411317768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3411317768
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.117951019
Short name T131
Test name
Test status
Simulation time 7417270667 ps
CPU time 214.07 seconds
Started Jun 05 05:56:14 PM PDT 24
Finished Jun 05 05:59:49 PM PDT 24
Peak memory 265632 kb
Host smart-dbc6a0ac-ac5c-487b-9cf5-b9ac3d5e35c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=117951019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.117951019
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3512989351
Short name T125
Test name
Test status
Simulation time 8692118609 ps
CPU time 616 seconds
Started Jun 05 05:56:14 PM PDT 24
Finished Jun 05 06:06:30 PM PDT 24
Peak memory 272636 kb
Host smart-ce4f93cb-e067-49cd-9ca1-c24d841247cf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512989351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3512989351
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3974841451
Short name T27
Test name
Test status
Simulation time 51576770857 ps
CPU time 3596.8 seconds
Started Jun 05 06:20:32 PM PDT 24
Finished Jun 05 07:20:29 PM PDT 24
Peak memory 305908 kb
Host smart-0a663bf8-955c-4ca1-a01b-5c7b39c466a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974841451 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3974841451
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.290580900
Short name T153
Test name
Test status
Simulation time 8263523 ps
CPU time 1.34 seconds
Started Jun 05 05:55:57 PM PDT 24
Finished Jun 05 05:55:59 PM PDT 24
Peak memory 237080 kb
Host smart-e83967c6-e299-4c8e-b958-8669a931e65c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=290580900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.290580900
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1204344643
Short name T149
Test name
Test status
Simulation time 54171331197 ps
CPU time 270.55 seconds
Started Jun 05 05:56:19 PM PDT 24
Finished Jun 05 06:00:50 PM PDT 24
Peak memory 265448 kb
Host smart-418a4370-6f4c-4ef0-ac79-ffebea0c3e5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1204344643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1204344643
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3309504397
Short name T257
Test name
Test status
Simulation time 12219991313 ps
CPU time 508.6 seconds
Started Jun 05 06:19:31 PM PDT 24
Finished Jun 05 06:28:00 PM PDT 24
Peak memory 247084 kb
Host smart-172e487a-dfa9-4e07-b626-85e906e7978a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309504397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3309504397
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1739422913
Short name T308
Test name
Test status
Simulation time 76568605314 ps
CPU time 2409.54 seconds
Started Jun 05 06:19:41 PM PDT 24
Finished Jun 05 06:59:51 PM PDT 24
Peak memory 272632 kb
Host smart-75284de6-49bc-4e1b-abc0-c5bcbc914ccb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739422913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1739422913
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3099926999
Short name T127
Test name
Test status
Simulation time 13264258470 ps
CPU time 930.57 seconds
Started Jun 05 05:56:04 PM PDT 24
Finished Jun 05 06:11:37 PM PDT 24
Peak memory 265236 kb
Host smart-ffb65a59-c754-40d4-a691-4d70626bb69a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099926999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3099926999
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4253676305
Short name T219
Test name
Test status
Simulation time 45052268937 ps
CPU time 462.42 seconds
Started Jun 05 06:25:27 PM PDT 24
Finished Jun 05 06:33:10 PM PDT 24
Peak memory 248020 kb
Host smart-bb0e0e41-fa88-476e-9f98-e865ec264f2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253676305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4253676305
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.866916930
Short name T269
Test name
Test status
Simulation time 62433878630 ps
CPU time 1086.51 seconds
Started Jun 05 06:19:25 PM PDT 24
Finished Jun 05 06:37:32 PM PDT 24
Peak memory 281664 kb
Host smart-bc0b7177-6fb7-49d2-9911-fae3793cceda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866916930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.866916930
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.816627233
Short name T138
Test name
Test status
Simulation time 2046755106 ps
CPU time 142.51 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 05:58:23 PM PDT 24
Peak memory 267064 kb
Host smart-dbbaf986-6fff-470b-8c74-6b7e1e32ba2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=816627233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.816627233
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3086978882
Short name T4
Test name
Test status
Simulation time 60737266346 ps
CPU time 3264.05 seconds
Started Jun 05 06:29:34 PM PDT 24
Finished Jun 05 07:23:59 PM PDT 24
Peak memory 289344 kb
Host smart-9b2b97ff-f3fa-4a1b-a7fc-0b2b9a595c42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086978882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3086978882
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2462636523
Short name T282
Test name
Test status
Simulation time 52421725747 ps
CPU time 567.18 seconds
Started Jun 05 06:18:32 PM PDT 24
Finished Jun 05 06:28:00 PM PDT 24
Peak memory 248196 kb
Host smart-31125b92-4cca-432a-9dce-2aa817ebf183
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462636523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2462636523
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.4030702892
Short name T24
Test name
Test status
Simulation time 71704348662 ps
CPU time 6627.11 seconds
Started Jun 05 06:26:24 PM PDT 24
Finished Jun 05 08:16:53 PM PDT 24
Peak memory 355488 kb
Host smart-60ff1269-f752-4167-9e65-4b2269e59a6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030702892 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.4030702892
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4166279055
Short name T123
Test name
Test status
Simulation time 4296403014 ps
CPU time 309.32 seconds
Started Jun 05 05:56:10 PM PDT 24
Finished Jun 05 06:01:20 PM PDT 24
Peak memory 265508 kb
Host smart-19cf05bf-5471-4549-99f8-feb7aa5314a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4166279055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.4166279055
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.4085492334
Short name T304
Test name
Test status
Simulation time 33390801150 ps
CPU time 1794.33 seconds
Started Jun 05 06:27:01 PM PDT 24
Finished Jun 05 06:56:56 PM PDT 24
Peak memory 269344 kb
Host smart-98c2c8bd-96f2-45d8-8379-60bb1b4224c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085492334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.4085492334
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2317380234
Short name T111
Test name
Test status
Simulation time 22774645512 ps
CPU time 2902.66 seconds
Started Jun 05 06:29:05 PM PDT 24
Finished Jun 05 07:17:28 PM PDT 24
Peak memory 306188 kb
Host smart-bfb8a7cc-7ec8-41ed-82bd-d4e039b27b70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317380234 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2317380234
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2727188596
Short name T119
Test name
Test status
Simulation time 4154826823 ps
CPU time 294.48 seconds
Started Jun 05 05:56:28 PM PDT 24
Finished Jun 05 06:01:23 PM PDT 24
Peak memory 265484 kb
Host smart-b00e0549-0240-4959-8348-db672702ad87
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727188596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2727188596
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1435771700
Short name T51
Test name
Test status
Simulation time 25025621637 ps
CPU time 2354.81 seconds
Started Jun 05 06:16:46 PM PDT 24
Finished Jun 05 06:56:01 PM PDT 24
Peak memory 306308 kb
Host smart-55293e72-9bc6-4d64-8f7c-2a22320116a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435771700 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1435771700
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2363378699
Short name T718
Test name
Test status
Simulation time 10362628 ps
CPU time 1.31 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 05:55:59 PM PDT 24
Peak memory 237064 kb
Host smart-912d160f-8f8e-4b22-b9ac-323bb2018d76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2363378699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2363378699
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1377347524
Short name T295
Test name
Test status
Simulation time 35109142020 ps
CPU time 367.7 seconds
Started Jun 05 06:17:05 PM PDT 24
Finished Jun 05 06:23:13 PM PDT 24
Peak memory 248104 kb
Host smart-1437c281-a305-40e3-822a-1111f6245062
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377347524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1377347524
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.188756462
Short name T132
Test name
Test status
Simulation time 49580775049 ps
CPU time 909.31 seconds
Started Jun 05 05:55:54 PM PDT 24
Finished Jun 05 06:11:05 PM PDT 24
Peak memory 265568 kb
Host smart-9a59e307-2964-4f46-a4bf-8917d7aeb268
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188756462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.188756462
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1291408168
Short name T459
Test name
Test status
Simulation time 130264259911 ps
CPU time 2334.24 seconds
Started Jun 05 06:20:58 PM PDT 24
Finished Jun 05 06:59:53 PM PDT 24
Peak memory 289068 kb
Host smart-26a33a77-fd00-446c-8124-3824e3e8907b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291408168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1291408168
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2334377832
Short name T78
Test name
Test status
Simulation time 45249962134 ps
CPU time 2739.93 seconds
Started Jun 05 06:24:25 PM PDT 24
Finished Jun 05 07:10:06 PM PDT 24
Peak memory 289512 kb
Host smart-862cbcff-7115-49fb-a10e-864afd1500ed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334377832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2334377832
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1090011810
Short name T57
Test name
Test status
Simulation time 81516734982 ps
CPU time 4304.21 seconds
Started Jun 05 06:15:42 PM PDT 24
Finished Jun 05 07:27:27 PM PDT 24
Peak memory 314504 kb
Host smart-f86c7ab0-a0c9-41ca-a041-5a96be2e7184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090011810 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1090011810
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3670005815
Short name T289
Test name
Test status
Simulation time 9782339461 ps
CPU time 421.75 seconds
Started Jun 05 06:25:11 PM PDT 24
Finished Jun 05 06:32:13 PM PDT 24
Peak memory 255036 kb
Host smart-6e63ce99-5aa8-478c-9d0c-8ba8fbb21a87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670005815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3670005815
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3321371924
Short name T136
Test name
Test status
Simulation time 15026982377 ps
CPU time 933.34 seconds
Started Jun 05 05:56:03 PM PDT 24
Finished Jun 05 06:11:38 PM PDT 24
Peak memory 265424 kb
Host smart-5d1e71ce-1a13-49a4-9c5d-78d52d9de676
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321371924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3321371924
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2280963229
Short name T169
Test name
Test status
Simulation time 267141059 ps
CPU time 4.03 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 05:56:36 PM PDT 24
Peak memory 237128 kb
Host smart-5919b9b9-4b44-43e2-951f-83a9986a3b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2280963229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2280963229
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3095404316
Short name T278
Test name
Test status
Simulation time 77385975228 ps
CPU time 1588.26 seconds
Started Jun 05 06:17:55 PM PDT 24
Finished Jun 05 06:44:23 PM PDT 24
Peak memory 289384 kb
Host smart-a15ae1e3-0ad6-486b-b411-06d5d1f33e13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095404316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3095404316
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2537488928
Short name T271
Test name
Test status
Simulation time 29059989077 ps
CPU time 546.2 seconds
Started Jun 05 06:19:04 PM PDT 24
Finished Jun 05 06:28:10 PM PDT 24
Peak memory 248124 kb
Host smart-2d9c0dd9-33c8-4d6f-b1ae-aef0f32cc111
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537488928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2537488928
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3507082933
Short name T113
Test name
Test status
Simulation time 73557638188 ps
CPU time 4007.21 seconds
Started Jun 05 06:19:41 PM PDT 24
Finished Jun 05 07:26:29 PM PDT 24
Peak memory 299948 kb
Host smart-b5f69e40-fec2-407a-bba2-271801470649
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507082933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3507082933
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.4028461764
Short name T208
Test name
Test status
Simulation time 208101241850 ps
CPU time 1409.36 seconds
Started Jun 05 06:22:59 PM PDT 24
Finished Jun 05 06:46:29 PM PDT 24
Peak memory 289316 kb
Host smart-c04cdd20-438c-413c-9da2-7802b969dbbb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028461764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.4028461764
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2035102878
Short name T235
Test name
Test status
Simulation time 59207471699 ps
CPU time 2142.6 seconds
Started Jun 05 06:27:09 PM PDT 24
Finished Jun 05 07:02:53 PM PDT 24
Peak memory 289244 kb
Host smart-06212226-fb75-46ff-b723-e45ccbb671b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035102878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2035102878
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2112192658
Short name T239
Test name
Test status
Simulation time 57669445954 ps
CPU time 1695.04 seconds
Started Jun 05 06:28:31 PM PDT 24
Finished Jun 05 06:56:47 PM PDT 24
Peak memory 305648 kb
Host smart-e670c3f1-fa2a-4b0e-8d97-0fc2b7c1b851
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112192658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2112192658
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.386935129
Short name T59
Test name
Test status
Simulation time 56526171265 ps
CPU time 2222.97 seconds
Started Jun 05 06:17:44 PM PDT 24
Finished Jun 05 06:54:48 PM PDT 24
Peak memory 289020 kb
Host smart-ce3d59bb-46be-4cac-a244-9a1c80d3dcbe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386935129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.386935129
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3160124813
Short name T120
Test name
Test status
Simulation time 7080366104 ps
CPU time 122.1 seconds
Started Jun 05 05:56:02 PM PDT 24
Finished Jun 05 05:58:06 PM PDT 24
Peak memory 257300 kb
Host smart-66efb236-b9d0-429a-a16a-10a09257874b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3160124813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3160124813
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3741853537
Short name T199
Test name
Test status
Simulation time 33198697 ps
CPU time 3.34 seconds
Started Jun 05 06:15:36 PM PDT 24
Finished Jun 05 06:15:40 PM PDT 24
Peak memory 248956 kb
Host smart-746cb869-7065-41c2-933e-e0714458fcb5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3741853537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3741853537
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.359568623
Short name T191
Test name
Test status
Simulation time 54274517 ps
CPU time 3.3 seconds
Started Jun 05 06:17:56 PM PDT 24
Finished Jun 05 06:17:59 PM PDT 24
Peak memory 248924 kb
Host smart-b0a0d9d7-61b0-485f-b460-c3da5f58045e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=359568623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.359568623
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1353512424
Short name T200
Test name
Test status
Simulation time 76985737 ps
CPU time 3.68 seconds
Started Jun 05 06:18:38 PM PDT 24
Finished Jun 05 06:18:42 PM PDT 24
Peak memory 248920 kb
Host smart-c8c624b4-d072-4b8f-892c-33b06f3b0205
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1353512424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1353512424
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.348905133
Short name T45
Test name
Test status
Simulation time 99348957 ps
CPU time 3.07 seconds
Started Jun 05 06:19:54 PM PDT 24
Finished Jun 05 06:19:57 PM PDT 24
Peak memory 248932 kb
Host smart-013d454f-7ad0-4b5f-8571-8c494e865c6f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=348905133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.348905133
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3998850466
Short name T589
Test name
Test status
Simulation time 37704940669 ps
CPU time 1632.19 seconds
Started Jun 05 06:18:48 PM PDT 24
Finished Jun 05 06:46:01 PM PDT 24
Peak memory 287860 kb
Host smart-9fa8d0c4-772e-4840-bf2b-fed2f8488eb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998850466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3998850466
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.859852718
Short name T241
Test name
Test status
Simulation time 2977152073 ps
CPU time 56.39 seconds
Started Jun 05 06:20:04 PM PDT 24
Finished Jun 05 06:21:01 PM PDT 24
Peak memory 255088 kb
Host smart-45bbb5bd-3de6-4364-92fa-98daf75404e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85985
2718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.859852718
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2157261263
Short name T566
Test name
Test status
Simulation time 16015816238 ps
CPU time 331.5 seconds
Started Jun 05 06:21:17 PM PDT 24
Finished Jun 05 06:26:49 PM PDT 24
Peak memory 248052 kb
Host smart-088ba38b-0ccb-4bf2-a344-5d97b20406ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157261263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2157261263
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1114218444
Short name T39
Test name
Test status
Simulation time 16054568840 ps
CPU time 1355.74 seconds
Started Jun 05 06:24:41 PM PDT 24
Finished Jun 05 06:47:17 PM PDT 24
Peak memory 289824 kb
Host smart-0017dd35-7d7b-41bc-9515-7dff3a0e73f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114218444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1114218444
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1729821588
Short name T256
Test name
Test status
Simulation time 116339521673 ps
CPU time 5351.14 seconds
Started Jun 05 06:30:25 PM PDT 24
Finished Jun 05 07:59:37 PM PDT 24
Peak memory 300856 kb
Host smart-e0a5bd33-a788-4dd5-bdc9-25d3779c069b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729821588 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1729821588
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.344257148
Short name T122
Test name
Test status
Simulation time 4462597502 ps
CPU time 561.84 seconds
Started Jun 05 05:56:27 PM PDT 24
Finished Jun 05 06:05:55 PM PDT 24
Peak memory 265480 kb
Host smart-d5aeb9b2-f094-4c4a-b03b-94e0583df93e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344257148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.344257148
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1934004368
Short name T126
Test name
Test status
Simulation time 3849805024 ps
CPU time 134.04 seconds
Started Jun 05 05:56:19 PM PDT 24
Finished Jun 05 05:58:34 PM PDT 24
Peak memory 266452 kb
Host smart-b8573501-2c82-42c9-9f1d-8b8341c8b4bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1934004368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1934004368
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2678841026
Short name T713
Test name
Test status
Simulation time 32045097 ps
CPU time 1.39 seconds
Started Jun 05 05:56:37 PM PDT 24
Finished Jun 05 05:56:39 PM PDT 24
Peak memory 236068 kb
Host smart-9d71cc03-6b8b-4558-8547-2fd229c13b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2678841026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2678841026
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1456176541
Short name T251
Test name
Test status
Simulation time 18059089550 ps
CPU time 1828.4 seconds
Started Jun 05 06:17:55 PM PDT 24
Finished Jun 05 06:48:24 PM PDT 24
Peak memory 297448 kb
Host smart-1a687657-ddd3-4861-8a90-50402930eab1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456176541 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1456176541
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.787399839
Short name T236
Test name
Test status
Simulation time 954719596 ps
CPU time 18.05 seconds
Started Jun 05 06:19:06 PM PDT 24
Finished Jun 05 06:19:24 PM PDT 24
Peak memory 252932 kb
Host smart-fa360822-c0cb-4c27-989e-a95aff5484eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78739
9839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.787399839
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2378130540
Short name T254
Test name
Test status
Simulation time 911343589 ps
CPU time 23.92 seconds
Started Jun 05 06:19:19 PM PDT 24
Finished Jun 05 06:19:43 PM PDT 24
Peak memory 247704 kb
Host smart-e8894f30-c4f3-4c59-b3ab-dc8f0cd90dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23781
30540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2378130540
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1047293058
Short name T272
Test name
Test status
Simulation time 2133328607 ps
CPU time 17.03 seconds
Started Jun 05 06:19:58 PM PDT 24
Finished Jun 05 06:20:15 PM PDT 24
Peak memory 249080 kb
Host smart-09627b12-c1bd-4a88-932a-c0a764584a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10472
93058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1047293058
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.787936865
Short name T90
Test name
Test status
Simulation time 138294890074 ps
CPU time 2431.03 seconds
Started Jun 05 06:20:05 PM PDT 24
Finished Jun 05 07:00:37 PM PDT 24
Peak memory 286244 kb
Host smart-4ebbf276-9d47-482e-808f-e6df08901ea2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787936865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.787936865
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3219481445
Short name T611
Test name
Test status
Simulation time 3283020806 ps
CPU time 134.43 seconds
Started Jun 05 06:20:05 PM PDT 24
Finished Jun 05 06:22:19 PM PDT 24
Peak memory 248412 kb
Host smart-b5dc38fc-b950-4cc7-b6a0-4cc5f83793c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219481445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3219481445
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.701950991
Short name T247
Test name
Test status
Simulation time 6604113986 ps
CPU time 59.84 seconds
Started Jun 05 06:20:59 PM PDT 24
Finished Jun 05 06:21:59 PM PDT 24
Peak memory 248856 kb
Host smart-f2bf8eef-ea44-4ccf-a270-23c2051a9619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70195
0991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.701950991
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3950199293
Short name T238
Test name
Test status
Simulation time 41377952534 ps
CPU time 1251.39 seconds
Started Jun 05 06:21:18 PM PDT 24
Finished Jun 05 06:42:11 PM PDT 24
Peak memory 265236 kb
Host smart-994bedd4-5e14-4932-be8b-0b43d6d4174e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950199293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3950199293
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2304326543
Short name T275
Test name
Test status
Simulation time 15901859620 ps
CPU time 1531.08 seconds
Started Jun 05 06:22:30 PM PDT 24
Finished Jun 05 06:48:02 PM PDT 24
Peak memory 284120 kb
Host smart-0b86a0f8-7c6a-4495-bbb2-2d6485992492
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304326543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2304326543
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3463258397
Short name T243
Test name
Test status
Simulation time 73745251938 ps
CPU time 5717.77 seconds
Started Jun 05 06:24:46 PM PDT 24
Finished Jun 05 08:00:04 PM PDT 24
Peak memory 321600 kb
Host smart-448d02f6-c000-4c37-914b-58edb1d546f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463258397 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3463258397
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2905891326
Short name T300
Test name
Test status
Simulation time 27717066380 ps
CPU time 308.28 seconds
Started Jun 05 06:26:03 PM PDT 24
Finished Jun 05 06:31:11 PM PDT 24
Peak memory 247396 kb
Host smart-bfa7b5c3-ad80-46a2-ae7c-708c0beca21e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905891326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2905891326
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1019842530
Short name T210
Test name
Test status
Simulation time 3103166719 ps
CPU time 55.45 seconds
Started Jun 05 06:26:56 PM PDT 24
Finished Jun 05 06:27:52 PM PDT 24
Peak memory 248200 kb
Host smart-1094d715-192a-47b2-9af9-25a5438be518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10198
42530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1019842530
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3724899143
Short name T73
Test name
Test status
Simulation time 283977096 ps
CPU time 34.75 seconds
Started Jun 05 06:16:28 PM PDT 24
Finished Jun 05 06:17:03 PM PDT 24
Peak memory 248888 kb
Host smart-e64687da-8328-4646-9ba6-f9c3d74983e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37248
99143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3724899143
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3450002098
Short name T277
Test name
Test status
Simulation time 41905257702 ps
CPU time 1322.38 seconds
Started Jun 05 06:29:36 PM PDT 24
Finished Jun 05 06:51:39 PM PDT 24
Peak memory 273104 kb
Host smart-07a84b88-21b1-45e9-9146-6f476e47f5f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450002098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3450002098
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.176682642
Short name T103
Test name
Test status
Simulation time 906035123 ps
CPU time 17.39 seconds
Started Jun 05 06:18:39 PM PDT 24
Finished Jun 05 06:18:57 PM PDT 24
Peak memory 254088 kb
Host smart-321586b9-e09e-4301-97d4-417ed26137f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17668
2642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.176682642
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3403973787
Short name T117
Test name
Test status
Simulation time 8271223118 ps
CPU time 302.84 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 06:01:04 PM PDT 24
Peak memory 265496 kb
Host smart-84e74419-8288-4c37-9e08-b750528e1355
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3403973787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3403973787
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1856093561
Short name T156
Test name
Test status
Simulation time 502143078 ps
CPU time 2.62 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 05:56:00 PM PDT 24
Peak memory 237008 kb
Host smart-a0baf272-a290-4f74-b1a2-3ac19c81bf56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1856093561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1856093561
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3516285450
Short name T158
Test name
Test status
Simulation time 3534752409 ps
CPU time 61.55 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 239916 kb
Host smart-7ed13b7e-1167-4dbd-9029-2e2126d63156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3516285450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3516285450
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3838259524
Short name T157
Test name
Test status
Simulation time 39001093 ps
CPU time 3.44 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 05:56:05 PM PDT 24
Peak memory 237424 kb
Host smart-b3097538-d38e-41af-bede-3cf63fd0ed58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3838259524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3838259524
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1458340062
Short name T165
Test name
Test status
Simulation time 196112898 ps
CPU time 8.67 seconds
Started Jun 05 05:56:12 PM PDT 24
Finished Jun 05 05:56:26 PM PDT 24
Peak memory 237060 kb
Host smart-0f865487-c695-408e-a78c-b1a83cd463c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1458340062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1458340062
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3413988981
Short name T150
Test name
Test status
Simulation time 156077840 ps
CPU time 19.5 seconds
Started Jun 05 05:56:27 PM PDT 24
Finished Jun 05 05:56:46 PM PDT 24
Peak memory 240536 kb
Host smart-87352b15-6ec8-4ec3-9d17-36d6ce2b5ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3413988981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3413988981
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2380542763
Short name T142
Test name
Test status
Simulation time 9168816900 ps
CPU time 157 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 05:58:40 PM PDT 24
Peak memory 257364 kb
Host smart-4202621d-b6c2-423b-a80c-da688f2789c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2380542763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2380542763
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3302672951
Short name T164
Test name
Test status
Simulation time 902919369 ps
CPU time 48.32 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 05:56:50 PM PDT 24
Peak memory 237524 kb
Host smart-2e4b8157-4199-446d-a982-8b89e77ce98e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3302672951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3302672951
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2236959457
Short name T152
Test name
Test status
Simulation time 1764928318 ps
CPU time 31.6 seconds
Started Jun 05 05:55:58 PM PDT 24
Finished Jun 05 05:56:31 PM PDT 24
Peak memory 240540 kb
Host smart-b14399a8-fc12-45b7-ba41-9f4eaf6a5b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2236959457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2236959457
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2945362240
Short name T163
Test name
Test status
Simulation time 153512314 ps
CPU time 2.63 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 05:56:04 PM PDT 24
Peak memory 237064 kb
Host smart-4e08b3ce-f1ec-4e4b-8d8d-937c140a56ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2945362240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2945362240
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3852564733
Short name T161
Test name
Test status
Simulation time 623369817 ps
CPU time 41.53 seconds
Started Jun 05 05:56:10 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 245628 kb
Host smart-b7590a17-ffdd-4c4b-90cd-08355d3efdc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3852564733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3852564733
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.4251250810
Short name T162
Test name
Test status
Simulation time 564696679 ps
CPU time 3.33 seconds
Started Jun 05 05:56:17 PM PDT 24
Finished Jun 05 05:56:21 PM PDT 24
Peak memory 236912 kb
Host smart-2a7d807d-ba41-425f-84ef-35e473e523bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4251250810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.4251250810
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1994626084
Short name T170
Test name
Test status
Simulation time 790699852 ps
CPU time 31.58 seconds
Started Jun 05 05:56:00 PM PDT 24
Finished Jun 05 05:56:34 PM PDT 24
Peak memory 240704 kb
Host smart-bc3c3296-cb9b-4e04-a9bc-14ec08ea6955
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1994626084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1994626084
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3841204674
Short name T160
Test name
Test status
Simulation time 62840238 ps
CPU time 4.12 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 05:56:05 PM PDT 24
Peak memory 236104 kb
Host smart-d09ad66e-4673-4d88-b26f-0d4c207e11fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3841204674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3841204674
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4188589948
Short name T168
Test name
Test status
Simulation time 11070514104 ps
CPU time 62.88 seconds
Started Jun 05 05:55:57 PM PDT 24
Finished Jun 05 05:57:01 PM PDT 24
Peak memory 240408 kb
Host smart-30dcb689-9a52-4b73-85c8-4ee86821198a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4188589948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.4188589948
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1061441035
Short name T23
Test name
Test status
Simulation time 636705595 ps
CPU time 34.16 seconds
Started Jun 05 06:18:38 PM PDT 24
Finished Jun 05 06:19:12 PM PDT 24
Peak memory 254560 kb
Host smart-244f9928-1921-4bc9-bf36-a9173048309c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10614
41035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1061441035
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.4110273958
Short name T19
Test name
Test status
Simulation time 55552672777 ps
CPU time 1319.37 seconds
Started Jun 05 06:16:01 PM PDT 24
Finished Jun 05 06:38:01 PM PDT 24
Peak memory 288896 kb
Host smart-7a388567-dfe1-4f33-a949-abd568119fc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110273958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4110273958
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3778390457
Short name T763
Test name
Test status
Simulation time 7105887008 ps
CPU time 245.42 seconds
Started Jun 05 05:56:28 PM PDT 24
Finished Jun 05 06:00:34 PM PDT 24
Peak memory 240524 kb
Host smart-3fe1fdb2-6b0f-46ab-91ed-803e4f4501e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3778390457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3778390457
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.864048649
Short name T741
Test name
Test status
Simulation time 17495207627 ps
CPU time 512.3 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 06:04:30 PM PDT 24
Peak memory 240540 kb
Host smart-976ef1c4-6456-4f42-9741-a9d2f6f62f05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=864048649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.864048649
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.588099327
Short name T180
Test name
Test status
Simulation time 150550555 ps
CPU time 3.55 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 05:56:01 PM PDT 24
Peak memory 240452 kb
Host smart-1f1237dc-dde0-4c76-9d04-4f444af9d616
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=588099327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.588099327
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1958493330
Short name T793
Test name
Test status
Simulation time 625788937 ps
CPU time 5.24 seconds
Started Jun 05 05:56:07 PM PDT 24
Finished Jun 05 05:56:13 PM PDT 24
Peak memory 240776 kb
Host smart-3e7877b9-1264-41d2-9395-64e1aa88230a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958493330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1958493330
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.820691513
Short name T709
Test name
Test status
Simulation time 36406870 ps
CPU time 2.94 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 05:56:00 PM PDT 24
Peak memory 236036 kb
Host smart-7ce51bc8-f9a0-4384-aa9b-711071e889dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=820691513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.820691513
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2812963141
Short name T725
Test name
Test status
Simulation time 172672111 ps
CPU time 18.66 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 05:56:16 PM PDT 24
Peak memory 244312 kb
Host smart-930d3ca8-67e1-4b61-a74f-391b9a01fd0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2812963141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2812963141
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.731738202
Short name T134
Test name
Test status
Simulation time 25521028474 ps
CPU time 485.51 seconds
Started Jun 05 05:56:15 PM PDT 24
Finished Jun 05 06:04:21 PM PDT 24
Peak memory 265456 kb
Host smart-60fd5803-2f73-4c0b-a0fc-2987c9de7f41
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731738202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.731738202
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1299744841
Short name T743
Test name
Test status
Simulation time 2976594302 ps
CPU time 14.23 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 05:56:12 PM PDT 24
Peak memory 248848 kb
Host smart-bb4fe68f-ec07-42e6-bd7b-510fb16b1746
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1299744841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1299744841
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4198823678
Short name T730
Test name
Test status
Simulation time 2062303217 ps
CPU time 136.7 seconds
Started Jun 05 05:56:04 PM PDT 24
Finished Jun 05 05:58:23 PM PDT 24
Peak memory 240476 kb
Host smart-01399029-85f6-4359-9324-b5652d417213
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4198823678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.4198823678
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2529486368
Short name T179
Test name
Test status
Simulation time 5108262471 ps
CPU time 98.27 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 05:57:39 PM PDT 24
Peak memory 236888 kb
Host smart-a8fe9ab6-3ed7-4a07-b841-9dd2a8067031
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2529486368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2529486368
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4137258861
Short name T155
Test name
Test status
Simulation time 102978354 ps
CPU time 8.47 seconds
Started Jun 05 05:56:04 PM PDT 24
Finished Jun 05 05:56:15 PM PDT 24
Peak memory 240480 kb
Host smart-5014e6e5-5b3b-4b69-a0de-51b3a325a766
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4137258861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.4137258861
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.138332572
Short name T735
Test name
Test status
Simulation time 73908232 ps
CPU time 6.35 seconds
Started Jun 05 05:56:01 PM PDT 24
Finished Jun 05 05:56:10 PM PDT 24
Peak memory 240572 kb
Host smart-81d5a649-b5d7-4938-a37e-26082bf89bf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138332572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.138332572
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1569872583
Short name T185
Test name
Test status
Simulation time 35344664 ps
CPU time 5.84 seconds
Started Jun 05 05:56:01 PM PDT 24
Finished Jun 05 05:56:09 PM PDT 24
Peak memory 236984 kb
Host smart-d0ff8a9b-9a42-4c5b-8568-1b665a33c09d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1569872583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1569872583
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2462023898
Short name T801
Test name
Test status
Simulation time 1037269323 ps
CPU time 19.24 seconds
Started Jun 05 05:56:13 PM PDT 24
Finished Jun 05 05:56:33 PM PDT 24
Peak memory 245228 kb
Host smart-93c52e04-ee20-4e3e-855a-b6b43a6cf35e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2462023898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2462023898
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1148471954
Short name T140
Test name
Test status
Simulation time 2049113295 ps
CPU time 288.8 seconds
Started Jun 05 05:56:19 PM PDT 24
Finished Jun 05 06:01:08 PM PDT 24
Peak memory 265432 kb
Host smart-16610141-e195-4b52-9884-c83874c7dc5c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148471954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1148471954
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2050982289
Short name T752
Test name
Test status
Simulation time 325126028 ps
CPU time 19.5 seconds
Started Jun 05 05:55:58 PM PDT 24
Finished Jun 05 05:56:19 PM PDT 24
Peak memory 253920 kb
Host smart-12ca8c02-51b8-4c17-8b2d-87f6f1f8a319
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2050982289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2050982289
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.4002567179
Short name T822
Test name
Test status
Simulation time 146428026 ps
CPU time 9.25 seconds
Started Jun 05 05:56:15 PM PDT 24
Finished Jun 05 05:56:30 PM PDT 24
Peak memory 240536 kb
Host smart-783d0289-994e-4288-a60f-d8a67041c7ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002567179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.4002567179
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.641056413
Short name T815
Test name
Test status
Simulation time 47658295 ps
CPU time 4.11 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 05:56:04 PM PDT 24
Peak memory 235856 kb
Host smart-35b03e0d-1f41-4824-bab5-11c6a05d3b04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=641056413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.641056413
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.504646615
Short name T721
Test name
Test status
Simulation time 514844875 ps
CPU time 34.37 seconds
Started Jun 05 05:56:38 PM PDT 24
Finished Jun 05 05:57:12 PM PDT 24
Peak memory 244264 kb
Host smart-e6400cc0-a0b8-4bd2-8ec3-db1201841ece
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=504646615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.504646615
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3261012990
Short name T118
Test name
Test status
Simulation time 54583216754 ps
CPU time 567.43 seconds
Started Jun 05 05:55:57 PM PDT 24
Finished Jun 05 06:05:26 PM PDT 24
Peak memory 265616 kb
Host smart-70008af2-ab60-4f82-af63-49b101f95edf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261012990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3261012990
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3048683065
Short name T708
Test name
Test status
Simulation time 270548615 ps
CPU time 9.73 seconds
Started Jun 05 05:56:17 PM PDT 24
Finished Jun 05 05:56:27 PM PDT 24
Peak memory 248796 kb
Host smart-c9d023d7-fc89-456f-8a0f-aff584819578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3048683065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3048683065
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2641291349
Short name T779
Test name
Test status
Simulation time 280202640 ps
CPU time 8.37 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 05:56:41 PM PDT 24
Peak memory 251012 kb
Host smart-51416298-4976-4846-911f-ecb49b55ddef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641291349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2641291349
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1550123811
Short name T739
Test name
Test status
Simulation time 111584496 ps
CPU time 4.67 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 05:56:05 PM PDT 24
Peak memory 235872 kb
Host smart-70934fb1-cb00-4d12-8ee6-b43f91abe5be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1550123811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1550123811
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2989238461
Short name T783
Test name
Test status
Simulation time 11293113 ps
CPU time 1.26 seconds
Started Jun 05 05:56:15 PM PDT 24
Finished Jun 05 05:56:17 PM PDT 24
Peak memory 237076 kb
Host smart-00f210de-cc13-42d3-b4c3-e854e9f83bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2989238461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2989238461
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.914884787
Short name T819
Test name
Test status
Simulation time 97766859 ps
CPU time 12.32 seconds
Started Jun 05 05:56:01 PM PDT 24
Finished Jun 05 05:56:16 PM PDT 24
Peak memory 245248 kb
Host smart-3d9ab658-83fd-4980-a205-15868fba1172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=914884787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.914884787
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4088733216
Short name T137
Test name
Test status
Simulation time 2274592369 ps
CPU time 291.57 seconds
Started Jun 05 05:56:26 PM PDT 24
Finished Jun 05 06:01:18 PM PDT 24
Peak memory 265480 kb
Host smart-5e03c92b-a3c3-4f61-82cd-3a5651f84839
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088733216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.4088733216
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3649611017
Short name T805
Test name
Test status
Simulation time 5674578940 ps
CPU time 20.22 seconds
Started Jun 05 05:56:27 PM PDT 24
Finished Jun 05 05:56:48 PM PDT 24
Peak memory 248920 kb
Host smart-567adee1-d508-492b-858e-34c6e416c66b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3649611017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3649611017
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2995953833
Short name T774
Test name
Test status
Simulation time 124622449 ps
CPU time 9.76 seconds
Started Jun 05 05:56:36 PM PDT 24
Finished Jun 05 05:56:46 PM PDT 24
Peak memory 256968 kb
Host smart-cd8a4ec5-b040-4e70-a79f-ffeb5191c9f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995953833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2995953833
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3828787971
Short name T738
Test name
Test status
Simulation time 471801064 ps
CPU time 8.72 seconds
Started Jun 05 05:56:09 PM PDT 24
Finished Jun 05 05:56:19 PM PDT 24
Peak memory 236968 kb
Host smart-2b9024e4-ee93-4565-9ca7-50ae56f12381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3828787971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3828787971
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.4147995146
Short name T766
Test name
Test status
Simulation time 39695433 ps
CPU time 1.6 seconds
Started Jun 05 05:56:15 PM PDT 24
Finished Jun 05 05:56:17 PM PDT 24
Peak memory 235144 kb
Host smart-f92f7417-a6f4-479e-98c6-f9908a609d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4147995146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.4147995146
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.339727294
Short name T773
Test name
Test status
Simulation time 347456404 ps
CPU time 21.66 seconds
Started Jun 05 05:56:08 PM PDT 24
Finished Jun 05 05:56:31 PM PDT 24
Peak memory 248712 kb
Host smart-60b6a58a-7679-484d-909d-a7c40261439a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=339727294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.339727294
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.41878313
Short name T147
Test name
Test status
Simulation time 719823600 ps
CPU time 79.19 seconds
Started Jun 05 05:56:07 PM PDT 24
Finished Jun 05 05:57:28 PM PDT 24
Peak memory 257228 kb
Host smart-6228119d-9ac2-4975-b27b-496f53c7552f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=41878313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_error
s.41878313
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.938255187
Short name T133
Test name
Test status
Simulation time 50217594028 ps
CPU time 874.15 seconds
Started Jun 05 05:56:06 PM PDT 24
Finished Jun 05 06:10:41 PM PDT 24
Peak memory 273488 kb
Host smart-619e11c6-b18e-45aa-9922-2463e0384b50
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938255187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.938255187
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2243977533
Short name T712
Test name
Test status
Simulation time 138951057 ps
CPU time 8.88 seconds
Started Jun 05 05:56:00 PM PDT 24
Finished Jun 05 05:56:12 PM PDT 24
Peak memory 248804 kb
Host smart-7cd335f0-972e-401f-ac8c-518cede2f7b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2243977533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2243977533
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1874319192
Short name T798
Test name
Test status
Simulation time 89701293 ps
CPU time 2.64 seconds
Started Jun 05 05:56:14 PM PDT 24
Finished Jun 05 05:56:17 PM PDT 24
Peak memory 236996 kb
Host smart-0229a44b-b671-4d57-a43f-2aa29b1cd4f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1874319192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1874319192
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.415782010
Short name T804
Test name
Test status
Simulation time 59835763 ps
CPU time 4.61 seconds
Started Jun 05 05:56:06 PM PDT 24
Finished Jun 05 05:56:12 PM PDT 24
Peak memory 241720 kb
Host smart-10728c7e-779f-439e-86da-7cbbe69ae748
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415782010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.415782010
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2039501163
Short name T181
Test name
Test status
Simulation time 75171362 ps
CPU time 4.47 seconds
Started Jun 05 05:56:04 PM PDT 24
Finished Jun 05 05:56:11 PM PDT 24
Peak memory 239680 kb
Host smart-d8567b5d-3a00-4652-9844-63af4de4e781
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2039501163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2039501163
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1105800113
Short name T823
Test name
Test status
Simulation time 16459231 ps
CPU time 1.28 seconds
Started Jun 05 05:56:00 PM PDT 24
Finished Jun 05 05:56:04 PM PDT 24
Peak memory 236304 kb
Host smart-e2a2f63c-11a6-410b-bda7-5051277b61f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1105800113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1105800113
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2103814882
Short name T183
Test name
Test status
Simulation time 174081867 ps
CPU time 21.13 seconds
Started Jun 05 05:56:25 PM PDT 24
Finished Jun 05 05:56:46 PM PDT 24
Peak memory 248636 kb
Host smart-8aca2b15-3a86-4b74-82af-14cfedc46d99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2103814882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2103814882
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2864289325
Short name T144
Test name
Test status
Simulation time 9976682823 ps
CPU time 140.33 seconds
Started Jun 05 05:56:04 PM PDT 24
Finished Jun 05 05:58:26 PM PDT 24
Peak memory 265424 kb
Host smart-7152432f-6653-469a-a4a1-36cbce3dff73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2864289325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2864289325
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.788372383
Short name T807
Test name
Test status
Simulation time 15682516009 ps
CPU time 538.19 seconds
Started Jun 05 05:56:02 PM PDT 24
Finished Jun 05 06:05:02 PM PDT 24
Peak memory 269284 kb
Host smart-31f1f9b4-8fba-4295-81d2-8667d5845447
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788372383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.788372383
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1529758105
Short name T733
Test name
Test status
Simulation time 102522999 ps
CPU time 7.09 seconds
Started Jun 05 05:56:08 PM PDT 24
Finished Jun 05 05:56:16 PM PDT 24
Peak memory 250244 kb
Host smart-c0f1377d-f4b4-4b8f-b919-3ec584606269
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1529758105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1529758105
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4192567331
Short name T777
Test name
Test status
Simulation time 38963608 ps
CPU time 5.22 seconds
Started Jun 05 05:56:01 PM PDT 24
Finished Jun 05 05:56:09 PM PDT 24
Peak memory 256884 kb
Host smart-02de5df8-0ac8-483b-8053-f923f42d4fc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192567331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.4192567331
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3506843029
Short name T182
Test name
Test status
Simulation time 21801977 ps
CPU time 3.25 seconds
Started Jun 05 05:55:57 PM PDT 24
Finished Jun 05 05:56:02 PM PDT 24
Peak memory 239684 kb
Host smart-23082f12-505c-488d-9961-45b68231f295
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3506843029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3506843029
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3762277750
Short name T814
Test name
Test status
Simulation time 8532443 ps
CPU time 1.32 seconds
Started Jun 05 05:56:17 PM PDT 24
Finished Jun 05 05:56:19 PM PDT 24
Peak memory 236120 kb
Host smart-7c935ba8-3bef-4cf8-9ea8-d4e233f58008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3762277750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3762277750
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3625106191
Short name T166
Test name
Test status
Simulation time 11512257972 ps
CPU time 47.07 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 248784 kb
Host smart-c5971999-0fda-485a-8140-6c1b5ebe5084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3625106191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3625106191
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1763333797
Short name T145
Test name
Test status
Simulation time 8822573852 ps
CPU time 150.15 seconds
Started Jun 05 05:56:04 PM PDT 24
Finished Jun 05 05:58:36 PM PDT 24
Peak memory 265472 kb
Host smart-4c31faf6-2c91-46c3-a7e8-a203a4f63a43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1763333797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1763333797
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2319840672
Short name T228
Test name
Test status
Simulation time 221219897 ps
CPU time 7.17 seconds
Started Jun 05 05:56:04 PM PDT 24
Finished Jun 05 05:56:13 PM PDT 24
Peak memory 248804 kb
Host smart-68e74fc5-d440-4e74-8a19-ea9baa6cad1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2319840672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2319840672
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.511431610
Short name T759
Test name
Test status
Simulation time 542423957 ps
CPU time 5.51 seconds
Started Jun 05 05:56:00 PM PDT 24
Finished Jun 05 05:56:08 PM PDT 24
Peak memory 239820 kb
Host smart-68187444-1b3b-466d-ba9d-e7d3692cb37a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511431610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.511431610
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3208604742
Short name T760
Test name
Test status
Simulation time 177686146 ps
CPU time 7.81 seconds
Started Jun 05 05:56:25 PM PDT 24
Finished Jun 05 05:56:33 PM PDT 24
Peak memory 236904 kb
Host smart-0071304e-6950-4c4f-aa44-3a539fd8cde9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3208604742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3208604742
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3177753829
Short name T213
Test name
Test status
Simulation time 13083279 ps
CPU time 1.78 seconds
Started Jun 05 05:56:29 PM PDT 24
Finished Jun 05 05:56:31 PM PDT 24
Peak memory 237068 kb
Host smart-4c665da5-1d74-424b-afe6-3b8d2e7e8a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3177753829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3177753829
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.343946397
Short name T809
Test name
Test status
Simulation time 2166016752 ps
CPU time 19 seconds
Started Jun 05 05:56:01 PM PDT 24
Finished Jun 05 05:56:23 PM PDT 24
Peak memory 244380 kb
Host smart-4f794a0d-cd72-4bca-8945-99ed4697764a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=343946397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.343946397
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1415528033
Short name T703
Test name
Test status
Simulation time 99007530 ps
CPU time 3.73 seconds
Started Jun 05 05:56:08 PM PDT 24
Finished Jun 05 05:56:17 PM PDT 24
Peak memory 240524 kb
Host smart-44748a36-a227-43c0-9fab-c4f65d9dc2a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1415528033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1415528033
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.729894242
Short name T186
Test name
Test status
Simulation time 67722799 ps
CPU time 4.03 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 05:56:36 PM PDT 24
Peak memory 237064 kb
Host smart-7b99ee64-b7f9-48e5-a2cb-5401085a0721
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=729894242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.729894242
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.901634101
Short name T768
Test name
Test status
Simulation time 285492471 ps
CPU time 4.4 seconds
Started Jun 05 05:56:36 PM PDT 24
Finished Jun 05 05:56:41 PM PDT 24
Peak memory 240844 kb
Host smart-970667db-66c3-41f4-b43f-bad7fc7f8fec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901634101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.901634101
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.125735261
Short name T800
Test name
Test status
Simulation time 1202253078 ps
CPU time 4.7 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 05:56:06 PM PDT 24
Peak memory 236836 kb
Host smart-0ab6f1a1-e2d6-411d-a689-b1ec1364f36d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=125735261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.125735261
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.29902127
Short name T325
Test name
Test status
Simulation time 20743664 ps
CPU time 1.36 seconds
Started Jun 05 05:56:13 PM PDT 24
Finished Jun 05 05:56:15 PM PDT 24
Peak memory 237032 kb
Host smart-417f14bd-a0f2-4503-a0df-9d04e7d6a91e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=29902127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.29902127
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3554952082
Short name T736
Test name
Test status
Simulation time 351128772 ps
CPU time 21.86 seconds
Started Jun 05 05:56:12 PM PDT 24
Finished Jun 05 05:56:35 PM PDT 24
Peak memory 245244 kb
Host smart-e45288f1-992b-4e1e-be3b-2e3a52285dc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3554952082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3554952082
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3885719706
Short name T143
Test name
Test status
Simulation time 31514450035 ps
CPU time 540.96 seconds
Started Jun 05 05:56:02 PM PDT 24
Finished Jun 05 06:05:05 PM PDT 24
Peak memory 265492 kb
Host smart-2357729d-7bfc-47e2-a4b8-2fba1f9a6729
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885719706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3885719706
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3016246967
Short name T802
Test name
Test status
Simulation time 370702526 ps
CPU time 12.23 seconds
Started Jun 05 05:56:15 PM PDT 24
Finished Jun 05 05:56:28 PM PDT 24
Peak memory 248488 kb
Host smart-ca4a8d05-e703-43d8-9dec-869200a53ce7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3016246967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3016246967
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1888291660
Short name T799
Test name
Test status
Simulation time 520941370 ps
CPU time 10.12 seconds
Started Jun 05 05:56:33 PM PDT 24
Finished Jun 05 05:56:44 PM PDT 24
Peak memory 240584 kb
Host smart-e45e6e5f-47ef-41cc-aaf9-7c07dd658a3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888291660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1888291660
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1380192672
Short name T734
Test name
Test status
Simulation time 63972153 ps
CPU time 3.2 seconds
Started Jun 05 05:56:39 PM PDT 24
Finished Jun 05 05:56:43 PM PDT 24
Peak memory 236032 kb
Host smart-d39fd424-bfb7-4e35-852f-cefec7d95e24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1380192672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1380192672
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4286731735
Short name T761
Test name
Test status
Simulation time 9107568 ps
CPU time 1.2 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 05:56:34 PM PDT 24
Peak memory 235116 kb
Host smart-df21d48d-702f-4120-b9d8-90c8a860df3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4286731735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.4286731735
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3454196895
Short name T753
Test name
Test status
Simulation time 278570451 ps
CPU time 21.49 seconds
Started Jun 05 05:56:21 PM PDT 24
Finished Jun 05 05:56:43 PM PDT 24
Peak memory 245252 kb
Host smart-a3c3714e-5c53-4dc3-b24b-5edcc34b17ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3454196895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3454196895
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.670035576
Short name T794
Test name
Test status
Simulation time 1892405053 ps
CPU time 123.25 seconds
Started Jun 05 05:56:29 PM PDT 24
Finished Jun 05 05:58:32 PM PDT 24
Peak memory 257228 kb
Host smart-d3cc939e-8ca3-426c-b304-179fadeca066
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=670035576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.670035576
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1648393858
Short name T128
Test name
Test status
Simulation time 67686026124 ps
CPU time 478.38 seconds
Started Jun 05 05:56:24 PM PDT 24
Finished Jun 05 06:04:23 PM PDT 24
Peak memory 265696 kb
Host smart-3d8d571b-9993-4fc6-b7ff-e80ddbdfa6bb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648393858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1648393858
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1248593203
Short name T817
Test name
Test status
Simulation time 302985381 ps
CPU time 6.49 seconds
Started Jun 05 05:56:08 PM PDT 24
Finished Jun 05 05:56:16 PM PDT 24
Peak memory 253780 kb
Host smart-f72d3177-12c5-4388-9c5f-d77ff004fe9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1248593203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1248593203
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.82474741
Short name T151
Test name
Test status
Simulation time 105644292 ps
CPU time 2.5 seconds
Started Jun 05 05:56:28 PM PDT 24
Finished Jun 05 05:56:31 PM PDT 24
Peak memory 237072 kb
Host smart-28b69519-da0d-4b5a-8b2e-9f776c13739f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=82474741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.82474741
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3161414
Short name T229
Test name
Test status
Simulation time 1887631412 ps
CPU time 12.57 seconds
Started Jun 05 05:56:20 PM PDT 24
Finished Jun 05 05:56:33 PM PDT 24
Peak memory 250944 kb
Host smart-1a1b406c-926e-4204-8b3e-7480ada7f6ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 18.alert_handler_csr_mem_rw_with_rand_reset.3161414
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1402676071
Short name T707
Test name
Test status
Simulation time 22508614 ps
CPU time 3.71 seconds
Started Jun 05 05:56:34 PM PDT 24
Finished Jun 05 05:56:39 PM PDT 24
Peak memory 236968 kb
Host smart-6a29f1b8-ca09-4267-995e-fd50ae2969e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1402676071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1402676071
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3752963824
Short name T751
Test name
Test status
Simulation time 9572178 ps
CPU time 1.28 seconds
Started Jun 05 05:56:12 PM PDT 24
Finished Jun 05 05:56:14 PM PDT 24
Peak memory 237068 kb
Host smart-e931e819-a425-4548-b667-65938844c8e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3752963824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3752963824
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2754579207
Short name T715
Test name
Test status
Simulation time 1017834350 ps
CPU time 35.83 seconds
Started Jun 05 05:56:19 PM PDT 24
Finished Jun 05 05:56:56 PM PDT 24
Peak memory 248724 kb
Host smart-ebb3e0ac-1e83-4a9c-a914-c41af58ca2f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2754579207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2754579207
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1399778776
Short name T130
Test name
Test status
Simulation time 1561540580 ps
CPU time 106.85 seconds
Started Jun 05 05:56:21 PM PDT 24
Finished Jun 05 05:58:08 PM PDT 24
Peak memory 265412 kb
Host smart-ee29da8f-0e5d-489c-b777-dd073f2bcce3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1399778776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1399778776
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1106914818
Short name T135
Test name
Test status
Simulation time 4843576580 ps
CPU time 323.62 seconds
Started Jun 05 05:56:31 PM PDT 24
Finished Jun 05 06:01:55 PM PDT 24
Peak memory 265724 kb
Host smart-646cdf11-363a-4c9c-9449-dae7cc0c9a73
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106914818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1106914818
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1651948184
Short name T737
Test name
Test status
Simulation time 45242767 ps
CPU time 6.08 seconds
Started Jun 05 05:56:34 PM PDT 24
Finished Jun 05 05:56:41 PM PDT 24
Peak memory 248580 kb
Host smart-50b32ab1-cac9-411d-9e17-10e82a13db92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1651948184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1651948184
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.46477306
Short name T720
Test name
Test status
Simulation time 66531220 ps
CPU time 5.92 seconds
Started Jun 05 05:56:29 PM PDT 24
Finished Jun 05 05:56:36 PM PDT 24
Peak memory 239912 kb
Host smart-a2b3fc8f-14f8-4615-8086-0d9bc33cbe11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46477306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.alert_handler_csr_mem_rw_with_rand_reset.46477306
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3048364861
Short name T797
Test name
Test status
Simulation time 96630426 ps
CPU time 7.77 seconds
Started Jun 05 05:56:30 PM PDT 24
Finished Jun 05 05:56:39 PM PDT 24
Peak memory 236032 kb
Host smart-19c3b611-0727-4b26-b40d-ce44ecfd9176
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3048364861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3048364861
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2320215606
Short name T749
Test name
Test status
Simulation time 6640827 ps
CPU time 1.46 seconds
Started Jun 05 05:56:35 PM PDT 24
Finished Jun 05 05:56:37 PM PDT 24
Peak memory 236036 kb
Host smart-7c4b7eae-11b1-42aa-b01b-6abcec62f57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2320215606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2320215606
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1797767865
Short name T812
Test name
Test status
Simulation time 1125209731 ps
CPU time 23.39 seconds
Started Jun 05 05:56:28 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 245244 kb
Host smart-23b38d8b-1e8c-42ad-89f9-8608f8ef1363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1797767865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1797767865
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2363733379
Short name T148
Test name
Test status
Simulation time 827149680 ps
CPU time 99.22 seconds
Started Jun 05 05:56:25 PM PDT 24
Finished Jun 05 05:58:04 PM PDT 24
Peak memory 257144 kb
Host smart-2ac02699-d46d-49ef-b3c0-27c54fd876c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2363733379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2363733379
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2657316354
Short name T330
Test name
Test status
Simulation time 6057632050 ps
CPU time 444.98 seconds
Started Jun 05 05:56:17 PM PDT 24
Finished Jun 05 06:03:42 PM PDT 24
Peak memory 268504 kb
Host smart-098a8a1f-2fe1-43c1-a597-850f94a2ad1f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657316354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2657316354
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1818436315
Short name T755
Test name
Test status
Simulation time 630519619 ps
CPU time 11.39 seconds
Started Jun 05 05:56:29 PM PDT 24
Finished Jun 05 05:56:41 PM PDT 24
Peak memory 247452 kb
Host smart-1dd157c7-b6fa-41e8-b5d8-68cb2452ea1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1818436315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1818436315
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1157403712
Short name T331
Test name
Test status
Simulation time 904316856 ps
CPU time 66.9 seconds
Started Jun 05 05:56:28 PM PDT 24
Finished Jun 05 05:57:36 PM PDT 24
Peak memory 239736 kb
Host smart-235220b4-9498-4c9f-9442-aaa99c7dd9d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1157403712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1157403712
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1224000854
Short name T744
Test name
Test status
Simulation time 3320425251 ps
CPU time 106.35 seconds
Started Jun 05 05:56:22 PM PDT 24
Finished Jun 05 05:58:08 PM PDT 24
Peak memory 236996 kb
Host smart-a7816aeb-9c8e-43b4-abb8-26dffaba3886
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1224000854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1224000854
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1891010875
Short name T796
Test name
Test status
Simulation time 4458880363 ps
CPU time 238.45 seconds
Started Jun 05 05:56:09 PM PDT 24
Finished Jun 05 06:00:08 PM PDT 24
Peak memory 236984 kb
Host smart-2505aa55-dc3c-4e2e-991f-6857a1721dd6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1891010875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1891010875
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2042825660
Short name T717
Test name
Test status
Simulation time 22369999 ps
CPU time 3.48 seconds
Started Jun 05 05:56:15 PM PDT 24
Finished Jun 05 05:56:18 PM PDT 24
Peak memory 240396 kb
Host smart-2f80db3b-afd1-4a7e-a4cd-67f93131b5a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2042825660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2042825660
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.632360565
Short name T820
Test name
Test status
Simulation time 134564823 ps
CPU time 5.07 seconds
Started Jun 05 05:56:01 PM PDT 24
Finished Jun 05 05:56:09 PM PDT 24
Peak memory 256868 kb
Host smart-9485f70c-59a9-47d8-8c28-db594ccd3d45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632360565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.632360565
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2843239432
Short name T782
Test name
Test status
Simulation time 20508715 ps
CPU time 3.36 seconds
Started Jun 05 05:56:03 PM PDT 24
Finished Jun 05 05:56:09 PM PDT 24
Peak memory 236876 kb
Host smart-7ce0c976-e296-482f-bcad-43d201358b0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2843239432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2843239432
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1118831293
Short name T765
Test name
Test status
Simulation time 11367991 ps
CPU time 1.25 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 05:55:58 PM PDT 24
Peak memory 237080 kb
Host smart-d105d29a-1859-4f53-a251-c0c1eebfa2cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1118831293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1118831293
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1911374716
Short name T803
Test name
Test status
Simulation time 88029074 ps
CPU time 10.94 seconds
Started Jun 05 05:55:58 PM PDT 24
Finished Jun 05 05:56:16 PM PDT 24
Peak memory 248888 kb
Host smart-e2f73234-76e1-4fb6-b466-72941d5cc288
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1911374716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1911374716
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1153035459
Short name T764
Test name
Test status
Simulation time 51834439 ps
CPU time 5.98 seconds
Started Jun 05 05:56:01 PM PDT 24
Finished Jun 05 05:56:10 PM PDT 24
Peak memory 251272 kb
Host smart-c0af0d00-4542-431e-b8e9-f4e1028f6db4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1153035459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1153035459
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.675542804
Short name T778
Test name
Test status
Simulation time 9414040 ps
CPU time 1.33 seconds
Started Jun 05 05:56:31 PM PDT 24
Finished Jun 05 05:56:33 PM PDT 24
Peak memory 235088 kb
Host smart-cadac147-d91f-4fc9-a6ce-1f3af6bd3bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=675542804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.675542804
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4246175409
Short name T769
Test name
Test status
Simulation time 14880345 ps
CPU time 1.29 seconds
Started Jun 05 05:56:28 PM PDT 24
Finished Jun 05 05:56:29 PM PDT 24
Peak memory 236124 kb
Host smart-6cc05ff9-1ca5-4a1a-a75e-0e7d81b34ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4246175409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.4246175409
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2772517263
Short name T829
Test name
Test status
Simulation time 10770322 ps
CPU time 1.33 seconds
Started Jun 05 05:56:33 PM PDT 24
Finished Jun 05 05:56:35 PM PDT 24
Peak memory 236124 kb
Host smart-7c4c0e75-6071-46c2-b9d2-50f480bb8741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2772517263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2772517263
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.51184557
Short name T828
Test name
Test status
Simulation time 7710696 ps
CPU time 1.52 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 237012 kb
Host smart-d59f7995-a6e0-47a9-b8f6-7c1821187173
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=51184557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.51184557
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2802090174
Short name T824
Test name
Test status
Simulation time 12596729 ps
CPU time 1.65 seconds
Started Jun 05 05:56:27 PM PDT 24
Finished Jun 05 05:56:29 PM PDT 24
Peak memory 236172 kb
Host smart-8bf88f80-b8c9-4c44-a00a-1d60aaf38dcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2802090174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2802090174
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2779968878
Short name T323
Test name
Test status
Simulation time 9542817 ps
CPU time 1.6 seconds
Started Jun 05 05:56:38 PM PDT 24
Finished Jun 05 05:56:40 PM PDT 24
Peak memory 237088 kb
Host smart-d424d568-d864-4a7d-a037-ddc950bb544b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2779968878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2779968878
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.137927708
Short name T711
Test name
Test status
Simulation time 12086797 ps
CPU time 1.26 seconds
Started Jun 05 05:56:28 PM PDT 24
Finished Jun 05 05:56:30 PM PDT 24
Peak memory 237076 kb
Host smart-7db2ce41-dc7b-4639-9c73-7b07fe3f3794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=137927708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.137927708
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.4055949348
Short name T757
Test name
Test status
Simulation time 15352645 ps
CPU time 1.27 seconds
Started Jun 05 05:56:21 PM PDT 24
Finished Jun 05 05:56:23 PM PDT 24
Peak memory 237060 kb
Host smart-8e4c0f48-eeca-4a8e-994a-1070b629a522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4055949348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.4055949348
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2742164816
Short name T326
Test name
Test status
Simulation time 7354009 ps
CPU time 1.51 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 05:56:35 PM PDT 24
Peak memory 237080 kb
Host smart-8f6e60c2-a34f-472b-b270-17d4774f62ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2742164816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2742164816
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2756241771
Short name T747
Test name
Test status
Simulation time 18491410 ps
CPU time 1.29 seconds
Started Jun 05 05:56:28 PM PDT 24
Finished Jun 05 05:56:30 PM PDT 24
Peak memory 237000 kb
Host smart-d97c9625-b582-4f41-bf31-23e251ac0568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2756241771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2756241771
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2107273907
Short name T792
Test name
Test status
Simulation time 4449085916 ps
CPU time 140.77 seconds
Started Jun 05 05:56:00 PM PDT 24
Finished Jun 05 05:58:24 PM PDT 24
Peak memory 240448 kb
Host smart-0e588cfb-7864-4b55-9610-2ba2f0eae7a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2107273907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2107273907
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3477583017
Short name T770
Test name
Test status
Simulation time 5883740644 ps
CPU time 351.68 seconds
Started Jun 05 05:56:08 PM PDT 24
Finished Jun 05 06:02:01 PM PDT 24
Peak memory 237060 kb
Host smart-6c097bc9-cee8-4d31-be54-e7cd1f45aa93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3477583017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3477583017
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.326374433
Short name T758
Test name
Test status
Simulation time 351176310 ps
CPU time 3.64 seconds
Started Jun 05 05:56:27 PM PDT 24
Finished Jun 05 05:56:31 PM PDT 24
Peak memory 240456 kb
Host smart-c99fd7f4-b3f2-49a9-af0c-c07049b7d973
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=326374433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.326374433
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2386663806
Short name T818
Test name
Test status
Simulation time 177394495 ps
CPU time 7.89 seconds
Started Jun 05 05:56:06 PM PDT 24
Finished Jun 05 05:56:15 PM PDT 24
Peak memory 238752 kb
Host smart-be5605d6-0973-42ee-a26b-1c22eafa9b80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386663806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2386663806
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3547119884
Short name T167
Test name
Test status
Simulation time 20308599 ps
CPU time 3.12 seconds
Started Jun 05 05:56:03 PM PDT 24
Finished Jun 05 05:56:09 PM PDT 24
Peak memory 236016 kb
Host smart-5c2159c9-0dfb-432a-9cef-830db09d7c58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3547119884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3547119884
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3901535409
Short name T790
Test name
Test status
Simulation time 7878293 ps
CPU time 1.43 seconds
Started Jun 05 05:55:57 PM PDT 24
Finished Jun 05 05:56:00 PM PDT 24
Peak memory 236144 kb
Host smart-2837058a-7850-4957-bfb6-6d01a2ef63dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3901535409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3901535409
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3892935310
Short name T821
Test name
Test status
Simulation time 2106144923 ps
CPU time 41.69 seconds
Started Jun 05 05:56:01 PM PDT 24
Finished Jun 05 05:56:45 PM PDT 24
Peak memory 245260 kb
Host smart-f12e250c-9abd-4d59-bad1-c45b2f351c80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3892935310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3892935310
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2482525100
Short name T115
Test name
Test status
Simulation time 1898212182 ps
CPU time 185.04 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 05:59:02 PM PDT 24
Peak memory 265416 kb
Host smart-994bf428-5cfd-48d2-80a7-c0cf7a6f2aba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2482525100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2482525100
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4290963563
Short name T795
Test name
Test status
Simulation time 323889379 ps
CPU time 8.18 seconds
Started Jun 05 05:56:03 PM PDT 24
Finished Jun 05 05:56:13 PM PDT 24
Peak memory 256872 kb
Host smart-dfc529ac-f59a-414a-91ff-800b47499f62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4290963563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.4290963563
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.366424592
Short name T719
Test name
Test status
Simulation time 8315381 ps
CPU time 1.37 seconds
Started Jun 05 05:56:27 PM PDT 24
Finished Jun 05 05:56:29 PM PDT 24
Peak memory 236064 kb
Host smart-6f9e9b29-aed4-4ae3-b982-9a7db02b929e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=366424592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.366424592
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2637896599
Short name T324
Test name
Test status
Simulation time 11624847 ps
CPU time 1.39 seconds
Started Jun 05 05:56:31 PM PDT 24
Finished Jun 05 05:56:33 PM PDT 24
Peak memory 237228 kb
Host smart-215e8383-a574-4732-a203-6412674ba2e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2637896599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2637896599
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3449768434
Short name T791
Test name
Test status
Simulation time 27066030 ps
CPU time 1.34 seconds
Started Jun 05 05:56:30 PM PDT 24
Finished Jun 05 05:56:32 PM PDT 24
Peak memory 237068 kb
Host smart-116edb54-8f3f-4a0b-9598-a67d2955acd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3449768434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3449768434
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.473419712
Short name T748
Test name
Test status
Simulation time 8566708 ps
CPU time 1.51 seconds
Started Jun 05 05:56:33 PM PDT 24
Finished Jun 05 05:56:35 PM PDT 24
Peak memory 236100 kb
Host smart-4b6ee943-7d02-458e-92b4-647a2fb5b6ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=473419712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.473419712
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.4293994144
Short name T731
Test name
Test status
Simulation time 18767646 ps
CPU time 1.93 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 05:56:34 PM PDT 24
Peak memory 237232 kb
Host smart-b0aada51-86ec-44ab-be02-633041e6e0f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4293994144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.4293994144
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2897778307
Short name T726
Test name
Test status
Simulation time 18745481 ps
CPU time 1.42 seconds
Started Jun 05 05:56:34 PM PDT 24
Finished Jun 05 05:56:36 PM PDT 24
Peak memory 235100 kb
Host smart-15bec356-397f-458c-ac02-1626587365e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2897778307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2897778307
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3805218871
Short name T827
Test name
Test status
Simulation time 48795399 ps
CPU time 1.34 seconds
Started Jun 05 05:56:37 PM PDT 24
Finished Jun 05 05:56:38 PM PDT 24
Peak memory 235032 kb
Host smart-de50d1b3-fc4b-47f9-b020-1be6a60a4a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3805218871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3805218871
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.4210039386
Short name T724
Test name
Test status
Simulation time 7518529 ps
CPU time 1.37 seconds
Started Jun 05 05:56:40 PM PDT 24
Finished Jun 05 05:56:41 PM PDT 24
Peak memory 237080 kb
Host smart-39199000-e4af-4532-9132-50a7f62c1921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4210039386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.4210039386
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2388257552
Short name T811
Test name
Test status
Simulation time 6392218 ps
CPU time 1.46 seconds
Started Jun 05 05:56:29 PM PDT 24
Finished Jun 05 05:56:31 PM PDT 24
Peak memory 237080 kb
Host smart-4925a8ce-faba-40da-b093-f4310fe13142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2388257552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2388257552
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1745643205
Short name T732
Test name
Test status
Simulation time 8797386 ps
CPU time 1.51 seconds
Started Jun 05 05:56:31 PM PDT 24
Finished Jun 05 05:56:33 PM PDT 24
Peak memory 236144 kb
Host smart-f731dea7-67b9-4dc2-9730-eca054360474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1745643205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1745643205
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1135353893
Short name T788
Test name
Test status
Simulation time 3274302093 ps
CPU time 236.69 seconds
Started Jun 05 05:56:05 PM PDT 24
Finished Jun 05 06:00:03 PM PDT 24
Peak memory 240844 kb
Host smart-b4c7eb5f-5352-443b-a282-e7116aebaf2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1135353893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1135353893
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.510662309
Short name T225
Test name
Test status
Simulation time 3845751713 ps
CPU time 202.06 seconds
Started Jun 05 05:55:58 PM PDT 24
Finished Jun 05 05:59:22 PM PDT 24
Peak memory 236084 kb
Host smart-cc81ded0-eecd-48db-8670-687880004365
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=510662309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.510662309
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1734081277
Short name T762
Test name
Test status
Simulation time 22392648 ps
CPU time 3.58 seconds
Started Jun 05 05:56:02 PM PDT 24
Finished Jun 05 05:56:08 PM PDT 24
Peak memory 240460 kb
Host smart-e52a585d-0185-4e0d-b703-f55db307a70b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1734081277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1734081277
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.250897189
Short name T329
Test name
Test status
Simulation time 95302799 ps
CPU time 9.23 seconds
Started Jun 05 05:56:14 PM PDT 24
Finished Jun 05 05:56:24 PM PDT 24
Peak memory 252688 kb
Host smart-7e274658-081d-4dc6-b357-aa4859ae9aab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250897189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.250897189
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.931540221
Short name T706
Test name
Test status
Simulation time 131881001 ps
CPU time 7.39 seconds
Started Jun 05 05:56:00 PM PDT 24
Finished Jun 05 05:56:10 PM PDT 24
Peak memory 236988 kb
Host smart-211d2be5-2c1e-4368-8815-fee9f33bf9e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=931540221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.931540221
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1814773017
Short name T781
Test name
Test status
Simulation time 7540842 ps
CPU time 1.3 seconds
Started Jun 05 05:56:12 PM PDT 24
Finished Jun 05 05:56:13 PM PDT 24
Peak memory 235096 kb
Host smart-aa65c10f-9c59-4965-92cf-8839ad7aada0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1814773017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1814773017
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3738292043
Short name T227
Test name
Test status
Simulation time 1075979202 ps
CPU time 49.2 seconds
Started Jun 05 05:56:25 PM PDT 24
Finished Jun 05 05:57:14 PM PDT 24
Peak memory 248732 kb
Host smart-742669fc-fef0-422f-a717-141505a4b95b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3738292043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3738292043
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.896962909
Short name T806
Test name
Test status
Simulation time 3325825909 ps
CPU time 100.54 seconds
Started Jun 05 05:56:03 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 265496 kb
Host smart-af772df7-0730-4d27-b81f-5a8bb5cfb037
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=896962909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.896962909
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.539158552
Short name T146
Test name
Test status
Simulation time 9009352231 ps
CPU time 632.8 seconds
Started Jun 05 05:56:23 PM PDT 24
Finished Jun 05 06:06:56 PM PDT 24
Peak memory 265580 kb
Host smart-5871f033-0eff-4ed8-9acb-59fa8fc4c269
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539158552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.539158552
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1097289476
Short name T785
Test name
Test status
Simulation time 184316842 ps
CPU time 6.27 seconds
Started Jun 05 05:56:03 PM PDT 24
Finished Jun 05 05:56:11 PM PDT 24
Peak memory 248784 kb
Host smart-afde4ed0-2761-4eb9-acdb-a6746edc8373
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1097289476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1097289476
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.942011619
Short name T714
Test name
Test status
Simulation time 14739737 ps
CPU time 1.35 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 05:56:34 PM PDT 24
Peak memory 236116 kb
Host smart-5e77b728-cd6b-4d3f-9d86-87a03a395523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=942011619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.942011619
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3801496064
Short name T154
Test name
Test status
Simulation time 10834750 ps
CPU time 1.51 seconds
Started Jun 05 05:56:28 PM PDT 24
Finished Jun 05 05:56:30 PM PDT 24
Peak memory 236136 kb
Host smart-16a8c847-127f-4f26-a8b9-50fb3a80a9e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3801496064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3801496064
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3547870170
Short name T772
Test name
Test status
Simulation time 6790979 ps
CPU time 1.45 seconds
Started Jun 05 05:56:29 PM PDT 24
Finished Jun 05 05:56:31 PM PDT 24
Peak memory 237080 kb
Host smart-0e5d213a-3f76-47e2-8922-7d8e4b90fd8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3547870170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3547870170
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3620329290
Short name T787
Test name
Test status
Simulation time 12351737 ps
CPU time 1.27 seconds
Started Jun 05 05:56:17 PM PDT 24
Finished Jun 05 05:56:19 PM PDT 24
Peak memory 236068 kb
Host smart-4ecc72ff-7db0-4540-b225-e5c7e73bb5a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3620329290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3620329290
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2834365351
Short name T742
Test name
Test status
Simulation time 9505502 ps
CPU time 1.25 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 237032 kb
Host smart-ac2a2fd7-1990-40f5-91c9-7e3d01b65a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2834365351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2834365351
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2985808861
Short name T780
Test name
Test status
Simulation time 6423271 ps
CPU time 1.36 seconds
Started Jun 05 05:56:29 PM PDT 24
Finished Jun 05 05:56:31 PM PDT 24
Peak memory 235284 kb
Host smart-4cef0dcb-dbd3-4a51-a2cf-47f34ef9f286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2985808861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2985808861
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.669369597
Short name T722
Test name
Test status
Simulation time 14934822 ps
CPU time 1.53 seconds
Started Jun 05 05:56:41 PM PDT 24
Finished Jun 05 05:56:43 PM PDT 24
Peak memory 237088 kb
Host smart-3eb422dd-4109-4ebe-ac40-1e3c3fdaba62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=669369597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.669369597
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1119281483
Short name T825
Test name
Test status
Simulation time 8961661 ps
CPU time 1.49 seconds
Started Jun 05 05:56:40 PM PDT 24
Finished Jun 05 05:56:42 PM PDT 24
Peak memory 237024 kb
Host smart-09a67025-e7f1-40a7-9dac-f633a771f082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1119281483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1119281483
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2733416608
Short name T813
Test name
Test status
Simulation time 12708940 ps
CPU time 1.75 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 05:56:35 PM PDT 24
Peak memory 237080 kb
Host smart-1261db2a-c022-4f75-9a38-b5d312da7269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2733416608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2733416608
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.78589528
Short name T729
Test name
Test status
Simulation time 10512694 ps
CPU time 1.26 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 05:56:33 PM PDT 24
Peak memory 236292 kb
Host smart-c12c6182-2bd0-4548-a2a3-92fb8f46551a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=78589528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.78589528
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2178084530
Short name T226
Test name
Test status
Simulation time 433241956 ps
CPU time 7.5 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 05:56:05 PM PDT 24
Peak memory 237900 kb
Host smart-4a65d644-8253-42ef-81a9-994e5ff96464
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178084530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2178084530
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2390267945
Short name T723
Test name
Test status
Simulation time 340519604 ps
CPU time 8.27 seconds
Started Jun 05 05:56:16 PM PDT 24
Finished Jun 05 05:56:25 PM PDT 24
Peak memory 240464 kb
Host smart-a189f3c0-bd32-47c1-8120-2c3c4b3c0208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2390267945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2390267945
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1780824955
Short name T784
Test name
Test status
Simulation time 7661461 ps
CPU time 1.45 seconds
Started Jun 05 05:56:05 PM PDT 24
Finished Jun 05 05:56:08 PM PDT 24
Peak memory 237064 kb
Host smart-1784cca1-579d-4505-b953-3e5057a1d01b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1780824955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1780824955
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1418166279
Short name T808
Test name
Test status
Simulation time 333553231 ps
CPU time 22.95 seconds
Started Jun 05 05:56:04 PM PDT 24
Finished Jun 05 05:56:29 PM PDT 24
Peak memory 245232 kb
Host smart-f464548b-fa6e-4eca-a900-69cdf46a3be2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1418166279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1418166279
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3252950931
Short name T116
Test name
Test status
Simulation time 5819928769 ps
CPU time 342.54 seconds
Started Jun 05 05:56:09 PM PDT 24
Finished Jun 05 06:01:53 PM PDT 24
Peak memory 265496 kb
Host smart-d88d0e13-1ee9-478b-9a33-7d6cd5d4cd4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3252950931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3252950931
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3939084535
Short name T141
Test name
Test status
Simulation time 2274515686 ps
CPU time 296.89 seconds
Started Jun 05 05:55:57 PM PDT 24
Finished Jun 05 06:00:56 PM PDT 24
Peak memory 265456 kb
Host smart-8ffeb37b-f01f-4530-b2ca-fe10bdec1ac5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939084535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3939084535
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.4158806134
Short name T710
Test name
Test status
Simulation time 1066187199 ps
CPU time 19.75 seconds
Started Jun 05 05:56:20 PM PDT 24
Finished Jun 05 05:56:40 PM PDT 24
Peak memory 248632 kb
Host smart-505d2d0e-0dec-45d7-ba25-72b24028f4b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4158806134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.4158806134
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2866460009
Short name T810
Test name
Test status
Simulation time 196680666 ps
CPU time 7.2 seconds
Started Jun 05 05:56:21 PM PDT 24
Finished Jun 05 05:56:29 PM PDT 24
Peak memory 239956 kb
Host smart-d5abd71d-7e39-40c4-80d6-df3eaddb0748
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866460009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2866460009
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.331294105
Short name T746
Test name
Test status
Simulation time 19599518 ps
CPU time 3.16 seconds
Started Jun 05 05:56:07 PM PDT 24
Finished Jun 05 05:56:12 PM PDT 24
Peak memory 236988 kb
Host smart-a5b5eec8-f38e-4b0a-886d-60c691eea5c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=331294105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.331294105
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3598586824
Short name T776
Test name
Test status
Simulation time 10724462 ps
CPU time 1.44 seconds
Started Jun 05 05:56:30 PM PDT 24
Finished Jun 05 05:56:32 PM PDT 24
Peak memory 235100 kb
Host smart-87cd330a-ec3b-40de-9908-5f43df396c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3598586824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3598586824
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1961287581
Short name T775
Test name
Test status
Simulation time 1353849020 ps
CPU time 47.39 seconds
Started Jun 05 05:56:01 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 248732 kb
Host smart-e12cadee-ab54-440d-b9eb-e93dcd49bea5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1961287581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1961287581
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3435645717
Short name T786
Test name
Test status
Simulation time 168778008 ps
CPU time 11.06 seconds
Started Jun 05 05:56:08 PM PDT 24
Finished Jun 05 05:56:25 PM PDT 24
Peak memory 248332 kb
Host smart-c2a6e62b-e0f2-4ada-9270-01599e3c2504
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3435645717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3435645717
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2855097715
Short name T704
Test name
Test status
Simulation time 212627898 ps
CPU time 8.76 seconds
Started Jun 05 05:56:20 PM PDT 24
Finished Jun 05 05:56:29 PM PDT 24
Peak memory 248740 kb
Host smart-a9fe0a18-726a-4655-a0df-4e016b9c1e69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855097715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2855097715
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1103660726
Short name T830
Test name
Test status
Simulation time 35890934 ps
CPU time 2.93 seconds
Started Jun 05 05:56:12 PM PDT 24
Finished Jun 05 05:56:15 PM PDT 24
Peak memory 236040 kb
Host smart-195e8a35-6a23-4374-9214-c2ff9b08b42d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1103660726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1103660726
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2757670190
Short name T754
Test name
Test status
Simulation time 18093009 ps
CPU time 1.86 seconds
Started Jun 05 05:56:23 PM PDT 24
Finished Jun 05 05:56:25 PM PDT 24
Peak memory 236156 kb
Host smart-712f9cda-9542-4171-b4aa-3d715156c2f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2757670190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2757670190
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1287222926
Short name T745
Test name
Test status
Simulation time 1376922758 ps
CPU time 44.84 seconds
Started Jun 05 05:56:12 PM PDT 24
Finished Jun 05 05:56:57 PM PDT 24
Peak memory 248732 kb
Host smart-f8907130-4125-4021-913c-846c8bd18a69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1287222926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1287222926
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.846085130
Short name T124
Test name
Test status
Simulation time 7551121798 ps
CPU time 480.65 seconds
Started Jun 05 05:56:02 PM PDT 24
Finished Jun 05 06:04:05 PM PDT 24
Peak memory 265468 kb
Host smart-12728267-8a1d-4e0b-bbe0-b6f73af9b794
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846085130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.846085130
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2161417846
Short name T705
Test name
Test status
Simulation time 1076504332 ps
CPU time 17.16 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 05:56:18 PM PDT 24
Peak memory 254128 kb
Host smart-bf9ce640-bda1-4fb6-a48a-ae0c7decf201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2161417846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2161417846
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1851086824
Short name T771
Test name
Test status
Simulation time 76007784 ps
CPU time 6.1 seconds
Started Jun 05 05:56:00 PM PDT 24
Finished Jun 05 05:56:09 PM PDT 24
Peak memory 240584 kb
Host smart-2fe1247f-31fb-4a41-85a9-9de28eb173a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851086824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1851086824
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3302835874
Short name T789
Test name
Test status
Simulation time 35750296 ps
CPU time 5.47 seconds
Started Jun 05 05:56:24 PM PDT 24
Finished Jun 05 05:56:30 PM PDT 24
Peak memory 236972 kb
Host smart-2f1d5003-251b-4f84-8e5b-cf77a1a455ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3302835874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3302835874
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1025256205
Short name T826
Test name
Test status
Simulation time 10245211 ps
CPU time 1.27 seconds
Started Jun 05 05:56:00 PM PDT 24
Finished Jun 05 05:56:04 PM PDT 24
Peak memory 236920 kb
Host smart-9ee899d7-c11b-4718-865d-fe25e245deaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1025256205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1025256205
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2078899101
Short name T756
Test name
Test status
Simulation time 627284132 ps
CPU time 38.27 seconds
Started Jun 05 05:55:57 PM PDT 24
Finished Jun 05 05:56:37 PM PDT 24
Peak memory 248728 kb
Host smart-8a8a4329-40fe-467d-86a2-30d2ea8ff36b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2078899101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2078899101
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.4010674355
Short name T139
Test name
Test status
Simulation time 1303980124 ps
CPU time 111 seconds
Started Jun 05 05:56:13 PM PDT 24
Finished Jun 05 05:58:04 PM PDT 24
Peak memory 265412 kb
Host smart-37c4fc8c-18f8-480d-a80b-a76e58a22605
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4010674355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.4010674355
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2121552887
Short name T767
Test name
Test status
Simulation time 326592790 ps
CPU time 19.65 seconds
Started Jun 05 05:56:20 PM PDT 24
Finished Jun 05 05:56:41 PM PDT 24
Peak memory 248812 kb
Host smart-60077563-baae-4151-b0c4-7873c445921b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2121552887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2121552887
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3016389818
Short name T728
Test name
Test status
Simulation time 1714722219 ps
CPU time 34.17 seconds
Started Jun 05 05:56:11 PM PDT 24
Finished Jun 05 05:56:46 PM PDT 24
Peak memory 239920 kb
Host smart-3461b7e3-bfb0-4ce5-b92c-333d129fccd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3016389818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3016389818
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3267491706
Short name T740
Test name
Test status
Simulation time 377463340 ps
CPU time 7.62 seconds
Started Jun 05 05:56:00 PM PDT 24
Finished Jun 05 05:56:10 PM PDT 24
Peak memory 240584 kb
Host smart-39fa5359-4bfd-47e9-8807-9959cc80d531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267491706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3267491706
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2056935077
Short name T716
Test name
Test status
Simulation time 55454875 ps
CPU time 4.19 seconds
Started Jun 05 05:55:58 PM PDT 24
Finished Jun 05 05:56:04 PM PDT 24
Peak memory 238712 kb
Host smart-bfcb78f4-bded-4566-aae7-24d25a97cf87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2056935077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2056935077
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.777962635
Short name T816
Test name
Test status
Simulation time 13728852 ps
CPU time 1.33 seconds
Started Jun 05 05:56:02 PM PDT 24
Finished Jun 05 05:56:05 PM PDT 24
Peak memory 237028 kb
Host smart-533910ff-2922-474b-a120-213cb9552eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=777962635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.777962635
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.554854783
Short name T750
Test name
Test status
Simulation time 333303806 ps
CPU time 20.28 seconds
Started Jun 05 05:56:01 PM PDT 24
Finished Jun 05 05:56:24 PM PDT 24
Peak memory 244264 kb
Host smart-c95b2a67-a6b7-4e53-839f-607a672adc9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=554854783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.554854783
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1825329326
Short name T121
Test name
Test status
Simulation time 4036566620 ps
CPU time 114.5 seconds
Started Jun 05 05:55:57 PM PDT 24
Finished Jun 05 05:57:53 PM PDT 24
Peak memory 267216 kb
Host smart-d3da5b49-4abc-46a5-b235-24c37f70da22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1825329326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1825329326
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3050242648
Short name T727
Test name
Test status
Simulation time 447535606 ps
CPU time 10.49 seconds
Started Jun 05 05:55:57 PM PDT 24
Finished Jun 05 05:56:09 PM PDT 24
Peak memory 248812 kb
Host smart-66c95c42-6208-4c65-acb1-76a4b199ae95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3050242648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3050242648
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1513863768
Short name T445
Test name
Test status
Simulation time 55613823142 ps
CPU time 1762.91 seconds
Started Jun 05 06:15:32 PM PDT 24
Finished Jun 05 06:44:56 PM PDT 24
Peak memory 281608 kb
Host smart-ab7fd310-d810-4ad3-b019-66001138fea1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513863768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1513863768
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2860898943
Short name T428
Test name
Test status
Simulation time 1050995713 ps
CPU time 13.95 seconds
Started Jun 05 06:15:35 PM PDT 24
Finished Jun 05 06:15:50 PM PDT 24
Peak memory 240600 kb
Host smart-ba8e7946-a280-44b8-a5b7-6d741841b109
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2860898943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2860898943
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.903562265
Short name T440
Test name
Test status
Simulation time 4587500565 ps
CPU time 37.23 seconds
Started Jun 05 06:15:25 PM PDT 24
Finished Jun 05 06:16:02 PM PDT 24
Peak memory 256712 kb
Host smart-dfd90615-f2d4-4201-983b-4f4fbbc90113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90356
2265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.903562265
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3099100881
Short name T249
Test name
Test status
Simulation time 2757999721 ps
CPU time 30.02 seconds
Started Jun 05 06:15:24 PM PDT 24
Finished Jun 05 06:15:55 PM PDT 24
Peak memory 248824 kb
Host smart-48340a81-2b29-4f8d-ae30-3accb384d410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30991
00881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3099100881
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3566825042
Short name T517
Test name
Test status
Simulation time 22745498357 ps
CPU time 1108.51 seconds
Started Jun 05 06:15:38 PM PDT 24
Finished Jun 05 06:34:07 PM PDT 24
Peak memory 271472 kb
Host smart-63364f28-055d-4b99-8baa-ea9cde93c8b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566825042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3566825042
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.620537355
Short name T480
Test name
Test status
Simulation time 57103899109 ps
CPU time 1865.01 seconds
Started Jun 05 06:15:36 PM PDT 24
Finished Jun 05 06:46:42 PM PDT 24
Peak memory 270716 kb
Host smart-1f2f69b3-ee8b-47f7-86d0-1404be7bf3d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620537355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.620537355
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2559022057
Short name T36
Test name
Test status
Simulation time 3915782394 ps
CPU time 158.39 seconds
Started Jun 05 06:15:32 PM PDT 24
Finished Jun 05 06:18:11 PM PDT 24
Peak memory 248276 kb
Host smart-7118483e-613a-48f8-b2e1-6d42948ffed7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559022057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2559022057
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2656118085
Short name T175
Test name
Test status
Simulation time 282605164 ps
CPU time 12.35 seconds
Started Jun 05 06:15:26 PM PDT 24
Finished Jun 05 06:15:38 PM PDT 24
Peak memory 248796 kb
Host smart-167e6c95-f559-4843-994a-06801b4d34cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26561
18085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2656118085
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1517774146
Short name T376
Test name
Test status
Simulation time 723500715 ps
CPU time 24.83 seconds
Started Jun 05 06:15:27 PM PDT 24
Finished Jun 05 06:15:52 PM PDT 24
Peak memory 255628 kb
Host smart-281fcbfd-bb5e-4202-b984-08b67a29e927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15177
74146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1517774146
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2713237885
Short name T10
Test name
Test status
Simulation time 276114512 ps
CPU time 17.05 seconds
Started Jun 05 06:15:43 PM PDT 24
Finished Jun 05 06:16:00 PM PDT 24
Peak memory 270180 kb
Host smart-5964b505-fc22-452b-a187-a4dcebd10dd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2713237885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2713237885
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.94978544
Short name T402
Test name
Test status
Simulation time 251951379 ps
CPU time 14.12 seconds
Started Jun 05 06:15:25 PM PDT 24
Finished Jun 05 06:15:39 PM PDT 24
Peak memory 248764 kb
Host smart-84bf3d34-df8a-4cef-9286-6248fe9fb792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94978
544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.94978544
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.4229396587
Short name T387
Test name
Test status
Simulation time 1095398703 ps
CPU time 22.7 seconds
Started Jun 05 06:15:24 PM PDT 24
Finished Jun 05 06:15:47 PM PDT 24
Peak memory 249016 kb
Host smart-12dfe8a8-49d0-4956-b0a3-19ebc2d6d588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42293
96587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.4229396587
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3292279017
Short name T588
Test name
Test status
Simulation time 4573013997 ps
CPU time 42.29 seconds
Started Jun 05 06:15:37 PM PDT 24
Finished Jun 05 06:16:20 PM PDT 24
Peak memory 248684 kb
Host smart-c52b56ef-e11d-4a63-80c9-413326fbbc93
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292279017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3292279017
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1959054682
Short name T204
Test name
Test status
Simulation time 82164766 ps
CPU time 2.87 seconds
Started Jun 05 06:15:54 PM PDT 24
Finished Jun 05 06:15:58 PM PDT 24
Peak memory 248940 kb
Host smart-4f393434-3304-41ea-a922-c910c3e00c6d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1959054682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1959054682
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2229088765
Short name T702
Test name
Test status
Simulation time 50255829689 ps
CPU time 1151.68 seconds
Started Jun 05 06:15:50 PM PDT 24
Finished Jun 05 06:35:02 PM PDT 24
Peak memory 282676 kb
Host smart-4cfd31dc-473c-41c6-b212-bd25917aadd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229088765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2229088765
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3575872260
Short name T435
Test name
Test status
Simulation time 6290679835 ps
CPU time 75.94 seconds
Started Jun 05 06:15:55 PM PDT 24
Finished Jun 05 06:17:11 PM PDT 24
Peak memory 248796 kb
Host smart-e97bebfa-4d05-4adf-bf7b-53fb900c52e7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3575872260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3575872260
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.194992596
Short name T518
Test name
Test status
Simulation time 3280969590 ps
CPU time 146.19 seconds
Started Jun 05 06:15:43 PM PDT 24
Finished Jun 05 06:18:09 PM PDT 24
Peak memory 256900 kb
Host smart-4dda701a-b381-4915-8b36-7c2088fab0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19499
2596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.194992596
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2192264521
Short name T346
Test name
Test status
Simulation time 1158441795 ps
CPU time 26.64 seconds
Started Jun 05 06:15:43 PM PDT 24
Finished Jun 05 06:16:10 PM PDT 24
Peak memory 248772 kb
Host smart-d26ead4d-ec4e-44fa-b4c1-91ced64eb801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21922
64521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2192264521
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1829943767
Short name T311
Test name
Test status
Simulation time 32396484250 ps
CPU time 1354.28 seconds
Started Jun 05 06:15:56 PM PDT 24
Finished Jun 05 06:38:31 PM PDT 24
Peak memory 288740 kb
Host smart-da8a95d6-022a-47b8-993f-baaca89b9442
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829943767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1829943767
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1582269244
Short name T605
Test name
Test status
Simulation time 34425024077 ps
CPU time 1988.2 seconds
Started Jun 05 06:15:56 PM PDT 24
Finished Jun 05 06:49:05 PM PDT 24
Peak memory 284028 kb
Host smart-c3b6945f-8f6a-4f4f-80ac-b991e60180ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582269244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1582269244
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2101462382
Short name T301
Test name
Test status
Simulation time 5844227318 ps
CPU time 244.7 seconds
Started Jun 05 06:15:55 PM PDT 24
Finished Jun 05 06:20:00 PM PDT 24
Peak memory 247184 kb
Host smart-9c993e73-2ed5-43c0-a2e8-f71feaecdf4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101462382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2101462382
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.998446136
Short name T616
Test name
Test status
Simulation time 346645812 ps
CPU time 35.14 seconds
Started Jun 05 06:15:45 PM PDT 24
Finished Jun 05 06:16:20 PM PDT 24
Peak memory 248780 kb
Host smart-d3f67bcd-ddf0-4a3e-9034-651c6198c361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99844
6136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.998446136
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3325113170
Short name T438
Test name
Test status
Simulation time 1821099336 ps
CPU time 27.44 seconds
Started Jun 05 06:15:42 PM PDT 24
Finished Jun 05 06:16:10 PM PDT 24
Peak memory 255464 kb
Host smart-7fcd906d-6ea8-450c-bd4e-a7203be89d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33251
13170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3325113170
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2215050509
Short name T33
Test name
Test status
Simulation time 908792916 ps
CPU time 16.3 seconds
Started Jun 05 06:15:55 PM PDT 24
Finished Jun 05 06:16:12 PM PDT 24
Peak memory 271020 kb
Host smart-90ee04bd-19c8-4382-a199-96d087494eed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2215050509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2215050509
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2258377915
Short name T234
Test name
Test status
Simulation time 2125468772 ps
CPU time 38.69 seconds
Started Jun 05 06:15:50 PM PDT 24
Finished Jun 05 06:16:29 PM PDT 24
Peak memory 256420 kb
Host smart-668c0657-075c-4484-b6ea-84590cbfd238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22583
77915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2258377915
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2196095753
Short name T345
Test name
Test status
Simulation time 359011845 ps
CPU time 18.19 seconds
Started Jun 05 06:15:46 PM PDT 24
Finished Jun 05 06:16:05 PM PDT 24
Peak memory 256316 kb
Host smart-bf79e79f-aaeb-45cd-9fdb-c0e4cc59bd5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21960
95753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2196095753
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2856560256
Short name T237
Test name
Test status
Simulation time 14062995454 ps
CPU time 1507.48 seconds
Started Jun 05 06:15:55 PM PDT 24
Finished Jun 05 06:41:03 PM PDT 24
Peak memory 289324 kb
Host smart-0ecdc1e6-ba18-4f46-8cd3-31c6cdcf88f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856560256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2856560256
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3335980253
Short name T640
Test name
Test status
Simulation time 20254859906 ps
CPU time 1705.56 seconds
Started Jun 05 06:15:56 PM PDT 24
Finished Jun 05 06:44:22 PM PDT 24
Peak memory 281736 kb
Host smart-866d6d8f-6968-4e8b-b082-3a943ed495f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335980253 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3335980253
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.688260060
Short name T610
Test name
Test status
Simulation time 25998904390 ps
CPU time 1605.28 seconds
Started Jun 05 06:17:55 PM PDT 24
Finished Jun 05 06:44:41 PM PDT 24
Peak memory 273444 kb
Host smart-fca61b04-9e56-4d66-b118-6fdcff7b097d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688260060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.688260060
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1030327383
Short name T377
Test name
Test status
Simulation time 659251225 ps
CPU time 30.92 seconds
Started Jun 05 06:17:55 PM PDT 24
Finished Jun 05 06:18:26 PM PDT 24
Peak memory 240588 kb
Host smart-a237b0cf-6b88-43c4-84d8-04c16812107e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1030327383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1030327383
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1670666396
Short name T558
Test name
Test status
Simulation time 15899412 ps
CPU time 3.05 seconds
Started Jun 05 06:17:47 PM PDT 24
Finished Jun 05 06:17:50 PM PDT 24
Peak memory 239276 kb
Host smart-6e411daf-6089-410a-a1e6-74fe7c2b2fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16706
66396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1670666396
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.4027372311
Short name T340
Test name
Test status
Simulation time 74138630 ps
CPU time 6.16 seconds
Started Jun 05 06:17:46 PM PDT 24
Finished Jun 05 06:17:53 PM PDT 24
Peak memory 240528 kb
Host smart-5f243d56-09f9-445b-b13d-36062dc94a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40273
72311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.4027372311
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2271656247
Short name T374
Test name
Test status
Simulation time 6324830851 ps
CPU time 708.5 seconds
Started Jun 05 06:17:55 PM PDT 24
Finished Jun 05 06:29:44 PM PDT 24
Peak memory 273100 kb
Host smart-e2497358-7616-4370-81ef-c3cb3deae3e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271656247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2271656247
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.4119923954
Short name T294
Test name
Test status
Simulation time 10017071841 ps
CPU time 401.65 seconds
Started Jun 05 06:17:56 PM PDT 24
Finished Jun 05 06:24:38 PM PDT 24
Peak memory 248128 kb
Host smart-a81bcc08-387a-45e9-aef0-85b2380ad349
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119923954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.4119923954
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1974014108
Short name T451
Test name
Test status
Simulation time 231217867 ps
CPU time 13.35 seconds
Started Jun 05 06:17:46 PM PDT 24
Finished Jun 05 06:18:00 PM PDT 24
Peak memory 248776 kb
Host smart-31b0a407-82df-4aca-8faa-1fc3a3b2c74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19740
14108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1974014108
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2496916731
Short name T425
Test name
Test status
Simulation time 297606964 ps
CPU time 30.5 seconds
Started Jun 05 06:17:50 PM PDT 24
Finished Jun 05 06:18:21 PM PDT 24
Peak memory 255936 kb
Host smart-fd817ad3-60be-41a6-be5e-7c25bf5b1f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24969
16731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2496916731
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1498975311
Short name T465
Test name
Test status
Simulation time 966898280 ps
CPU time 13.9 seconds
Started Jun 05 06:17:48 PM PDT 24
Finished Jun 05 06:18:02 PM PDT 24
Peak memory 253300 kb
Host smart-c2a54342-3dbc-4aca-bce1-535236f47172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14989
75311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1498975311
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3828889767
Short name T363
Test name
Test status
Simulation time 882324016 ps
CPU time 57.37 seconds
Started Jun 05 06:17:48 PM PDT 24
Finished Jun 05 06:18:46 PM PDT 24
Peak memory 256604 kb
Host smart-6fd99a96-2107-473f-a9e0-ec0e60ef1292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38288
89767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3828889767
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2244194976
Short name T16
Test name
Test status
Simulation time 36747597 ps
CPU time 3.68 seconds
Started Jun 05 06:18:15 PM PDT 24
Finished Jun 05 06:18:19 PM PDT 24
Peak memory 248928 kb
Host smart-9fa32f1a-1523-48f8-878d-67caf6f5bd29
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2244194976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2244194976
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2020446209
Short name T412
Test name
Test status
Simulation time 48645071068 ps
CPU time 2494.95 seconds
Started Jun 05 06:18:08 PM PDT 24
Finished Jun 05 06:59:44 PM PDT 24
Peak memory 288228 kb
Host smart-836039b6-4b54-4986-9158-0822c8cf72e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020446209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2020446209
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.102165309
Short name T685
Test name
Test status
Simulation time 2256426145 ps
CPU time 34.8 seconds
Started Jun 05 06:18:09 PM PDT 24
Finished Jun 05 06:18:44 PM PDT 24
Peak memory 248844 kb
Host smart-72899b2d-de31-4224-96a1-df21eb6e019a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=102165309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.102165309
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.4213199320
Short name T258
Test name
Test status
Simulation time 1839655446 ps
CPU time 45.54 seconds
Started Jun 05 06:18:08 PM PDT 24
Finished Jun 05 06:18:54 PM PDT 24
Peak memory 256932 kb
Host smart-cbd2db0e-d305-4673-b265-39eb0f14a53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42131
99320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.4213199320
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3002348493
Short name T79
Test name
Test status
Simulation time 299122868 ps
CPU time 31.5 seconds
Started Jun 05 06:18:00 PM PDT 24
Finished Jun 05 06:18:32 PM PDT 24
Peak memory 255920 kb
Host smart-c6d28570-59d2-490a-bb4e-12e666cda7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30023
48493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3002348493
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1983802746
Short name T216
Test name
Test status
Simulation time 777993122894 ps
CPU time 3506.54 seconds
Started Jun 05 06:18:09 PM PDT 24
Finished Jun 05 07:16:37 PM PDT 24
Peak memory 289268 kb
Host smart-f2d13977-c5f8-4ed0-a2df-6e4f418a32b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983802746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1983802746
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3719866788
Short name T552
Test name
Test status
Simulation time 106635245169 ps
CPU time 1234.84 seconds
Started Jun 05 06:18:11 PM PDT 24
Finished Jun 05 06:38:47 PM PDT 24
Peak memory 281672 kb
Host smart-84e14074-d381-4ea2-9a33-6d2ecaeb820b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719866788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3719866788
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2031858775
Short name T264
Test name
Test status
Simulation time 159263146349 ps
CPU time 625.71 seconds
Started Jun 05 06:18:09 PM PDT 24
Finished Jun 05 06:28:35 PM PDT 24
Peak memory 248004 kb
Host smart-d3785c23-a532-479d-ac23-73b28ce30cfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031858775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2031858775
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.8976239
Short name T653
Test name
Test status
Simulation time 1006807149 ps
CPU time 51.67 seconds
Started Jun 05 06:17:56 PM PDT 24
Finished Jun 05 06:18:48 PM PDT 24
Peak memory 248772 kb
Host smart-4d66dca2-9025-4b74-ac51-5a479026face
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89762
39 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.8976239
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.771665396
Short name T92
Test name
Test status
Simulation time 4766638854 ps
CPU time 51.98 seconds
Started Jun 05 06:17:55 PM PDT 24
Finished Jun 05 06:18:48 PM PDT 24
Peak memory 255696 kb
Host smart-f15371df-9d1c-4883-9b0d-0a6527391464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77166
5396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.771665396
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.4210958764
Short name T466
Test name
Test status
Simulation time 328483187 ps
CPU time 22.42 seconds
Started Jun 05 06:18:09 PM PDT 24
Finished Jun 05 06:18:31 PM PDT 24
Peak memory 255092 kb
Host smart-20995c05-9de7-4b05-9640-4ae86cbf20a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42109
58764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.4210958764
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1458760781
Short name T631
Test name
Test status
Simulation time 5629594310 ps
CPU time 65.22 seconds
Started Jun 05 06:17:56 PM PDT 24
Finished Jun 05 06:19:02 PM PDT 24
Peak memory 248836 kb
Host smart-548ee353-3089-4bd7-a85b-0ed0c93a9e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14587
60781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1458760781
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2460737708
Short name T657
Test name
Test status
Simulation time 216762060029 ps
CPU time 2766.99 seconds
Started Jun 05 06:18:17 PM PDT 24
Finished Jun 05 07:04:24 PM PDT 24
Peak memory 289804 kb
Host smart-13100c07-f7cb-4672-a276-95f0d56ab4ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460737708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2460737708
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2007768384
Short name T202
Test name
Test status
Simulation time 97480943 ps
CPU time 4.35 seconds
Started Jun 05 06:18:26 PM PDT 24
Finished Jun 05 06:18:31 PM PDT 24
Peak memory 248936 kb
Host smart-f43a5239-35c9-4bb8-aa4e-df94dba97aee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2007768384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2007768384
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.655328597
Short name T362
Test name
Test status
Simulation time 44689462384 ps
CPU time 2686.66 seconds
Started Jun 05 06:18:21 PM PDT 24
Finished Jun 05 07:03:08 PM PDT 24
Peak memory 281628 kb
Host smart-c97e1b3a-db9c-4d87-a966-b83f38c26492
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655328597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.655328597
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.147073460
Short name T578
Test name
Test status
Simulation time 5318414667 ps
CPU time 160.5 seconds
Started Jun 05 06:18:17 PM PDT 24
Finished Jun 05 06:21:03 PM PDT 24
Peak memory 256832 kb
Host smart-6bed245f-cd6a-4c3a-91f2-16ffd71ce713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14707
3460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.147073460
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1480104113
Short name T692
Test name
Test status
Simulation time 2874606343 ps
CPU time 43.01 seconds
Started Jun 05 06:18:14 PM PDT 24
Finished Jun 05 06:18:57 PM PDT 24
Peak memory 248976 kb
Host smart-890d75ec-82e8-4b6e-abea-7693191a79c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14801
04113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1480104113
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1311929152
Short name T668
Test name
Test status
Simulation time 55704184067 ps
CPU time 2007.13 seconds
Started Jun 05 06:18:19 PM PDT 24
Finished Jun 05 06:51:46 PM PDT 24
Peak memory 272884 kb
Host smart-7c9af506-e91c-4114-adfb-6aee34ad63e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311929152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1311929152
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.566678883
Short name T512
Test name
Test status
Simulation time 50073134391 ps
CPU time 1233.73 seconds
Started Jun 05 06:18:23 PM PDT 24
Finished Jun 05 06:38:57 PM PDT 24
Peak memory 265252 kb
Host smart-4866d346-9776-43e7-977f-d718c97d2ab7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566678883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.566678883
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3786532649
Short name T5
Test name
Test status
Simulation time 4150315855 ps
CPU time 170.67 seconds
Started Jun 05 06:18:21 PM PDT 24
Finished Jun 05 06:21:12 PM PDT 24
Peak memory 255296 kb
Host smart-b24b102c-d782-4a4d-a1c3-bff8944d9da2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786532649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3786532649
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3697901722
Short name T398
Test name
Test status
Simulation time 1034708549 ps
CPU time 28.91 seconds
Started Jun 05 06:18:18 PM PDT 24
Finished Jun 05 06:18:47 PM PDT 24
Peak memory 248780 kb
Host smart-b74a3d34-e0cc-48a0-8214-dd2729a20457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36979
01722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3697901722
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.623027405
Short name T594
Test name
Test status
Simulation time 8075576807 ps
CPU time 52.18 seconds
Started Jun 05 06:18:14 PM PDT 24
Finished Jun 05 06:19:07 PM PDT 24
Peak memory 249132 kb
Host smart-43606dd5-3989-465b-84c5-729f127b1ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62302
7405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.623027405
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1768687518
Short name T357
Test name
Test status
Simulation time 517108158 ps
CPU time 19.91 seconds
Started Jun 05 06:18:17 PM PDT 24
Finished Jun 05 06:18:37 PM PDT 24
Peak memory 248780 kb
Host smart-86c6d24e-93a1-476c-a750-20aab7dbf3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17686
87518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1768687518
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.4071549763
Short name T620
Test name
Test status
Simulation time 36090016247 ps
CPU time 1376.31 seconds
Started Jun 05 06:18:27 PM PDT 24
Finished Jun 05 06:41:24 PM PDT 24
Peak memory 289136 kb
Host smart-a04f1365-7da6-40c8-bee8-fcf81b2c0d3d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071549763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.4071549763
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2188589663
Short name T224
Test name
Test status
Simulation time 209303080017 ps
CPU time 7440.68 seconds
Started Jun 05 06:18:32 PM PDT 24
Finished Jun 05 08:22:34 PM PDT 24
Peak memory 305896 kb
Host smart-9956d54d-b92b-4a68-af75-9fc2f86c421f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188589663 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2188589663
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2947469381
Short name T523
Test name
Test status
Simulation time 48167490807 ps
CPU time 2958.37 seconds
Started Jun 05 06:18:39 PM PDT 24
Finished Jun 05 07:07:58 PM PDT 24
Peak memory 289112 kb
Host smart-ea7b5e37-b3f6-4114-9d3c-7460b8c74767
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947469381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2947469381
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1647918104
Short name T350
Test name
Test status
Simulation time 86105168 ps
CPU time 6.73 seconds
Started Jun 05 06:18:34 PM PDT 24
Finished Jun 05 06:18:41 PM PDT 24
Peak memory 248792 kb
Host smart-1e81645a-2366-4511-a4e1-69dfb9ae68cb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1647918104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1647918104
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1079514473
Short name T475
Test name
Test status
Simulation time 313898069 ps
CPU time 31.71 seconds
Started Jun 05 06:18:25 PM PDT 24
Finished Jun 05 06:18:58 PM PDT 24
Peak memory 256716 kb
Host smart-d6a06a6c-c17d-4722-94f9-34dfcee136be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10795
14473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1079514473
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.488141575
Short name T661
Test name
Test status
Simulation time 2317180599 ps
CPU time 82 seconds
Started Jun 05 06:18:31 PM PDT 24
Finished Jun 05 06:19:53 PM PDT 24
Peak memory 256564 kb
Host smart-622c2307-ad3e-43b1-bd19-0a1a742d23e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48814
1575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.488141575
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.367298935
Short name T568
Test name
Test status
Simulation time 52533523410 ps
CPU time 1211.21 seconds
Started Jun 05 06:18:36 PM PDT 24
Finished Jun 05 06:38:47 PM PDT 24
Peak memory 281612 kb
Host smart-e4fe8473-6983-410a-9ce0-29c7a9360ffe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367298935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.367298935
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2932974676
Short name T71
Test name
Test status
Simulation time 323154364 ps
CPU time 25.38 seconds
Started Jun 05 06:18:26 PM PDT 24
Finished Jun 05 06:18:51 PM PDT 24
Peak memory 248780 kb
Host smart-520cc769-4039-4f63-8c5e-5acfafa608f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29329
74676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2932974676
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3224344780
Short name T100
Test name
Test status
Simulation time 1456278365 ps
CPU time 46.01 seconds
Started Jun 05 06:18:24 PM PDT 24
Finished Jun 05 06:19:10 PM PDT 24
Peak memory 255684 kb
Host smart-eaa8a069-1ab5-441e-a3c4-d08ece2b1180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32243
44780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3224344780
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.312299812
Short name T613
Test name
Test status
Simulation time 568547645 ps
CPU time 32.35 seconds
Started Jun 05 06:18:27 PM PDT 24
Finished Jun 05 06:18:59 PM PDT 24
Peak memory 248764 kb
Host smart-6f173233-25ac-43cb-b1e7-91a3da2b8e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31229
9812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.312299812
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.497839522
Short name T599
Test name
Test status
Simulation time 1600764087 ps
CPU time 32.29 seconds
Started Jun 05 06:18:27 PM PDT 24
Finished Jun 05 06:19:00 PM PDT 24
Peak memory 248924 kb
Host smart-309e2eb4-ac4e-458b-be91-6c879f4e055e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49783
9522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.497839522
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2164063001
Short name T508
Test name
Test status
Simulation time 54657064545 ps
CPU time 3141.78 seconds
Started Jun 05 06:18:39 PM PDT 24
Finished Jun 05 07:11:02 PM PDT 24
Peak memory 302780 kb
Host smart-168de4e6-9236-4797-a896-7fceb4930a4c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164063001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2164063001
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3605008758
Short name T449
Test name
Test status
Simulation time 162674017826 ps
CPU time 2682.43 seconds
Started Jun 05 06:18:40 PM PDT 24
Finished Jun 05 07:03:23 PM PDT 24
Peak memory 322600 kb
Host smart-e1f2d7b8-308e-4dad-9859-f872e077e77a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605008758 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3605008758
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3319691630
Short name T195
Test name
Test status
Simulation time 21692399 ps
CPU time 2.95 seconds
Started Jun 05 06:18:52 PM PDT 24
Finished Jun 05 06:18:55 PM PDT 24
Peak memory 248952 kb
Host smart-5c2c9440-e465-46ef-9cc8-32e347b2d85f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3319691630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3319691630
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.4083523570
Short name T629
Test name
Test status
Simulation time 30793430275 ps
CPU time 1948.26 seconds
Started Jun 05 06:18:47 PM PDT 24
Finished Jun 05 06:51:16 PM PDT 24
Peak memory 281628 kb
Host smart-1c99bb6a-5223-4528-83df-a6a85cf0d289
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083523570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.4083523570
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2952867466
Short name T347
Test name
Test status
Simulation time 1825040778 ps
CPU time 75.48 seconds
Started Jun 05 06:18:53 PM PDT 24
Finished Jun 05 06:20:09 PM PDT 24
Peak memory 248780 kb
Host smart-239d7c5d-f933-4dd6-9f8d-7f268882efbd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2952867466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2952867466
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3219956560
Short name T44
Test name
Test status
Simulation time 22158190962 ps
CPU time 334.92 seconds
Started Jun 05 06:18:38 PM PDT 24
Finished Jun 05 06:24:14 PM PDT 24
Peak memory 250896 kb
Host smart-60c37c98-4578-48c3-9965-135f72ae6e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32199
56560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3219956560
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3275543133
Short name T391
Test name
Test status
Simulation time 349138494 ps
CPU time 12.93 seconds
Started Jun 05 06:18:40 PM PDT 24
Finished Jun 05 06:18:54 PM PDT 24
Peak memory 255004 kb
Host smart-1b96f678-521e-4217-bb8e-0c917cfab8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32755
43133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3275543133
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3989220420
Short name T1
Test name
Test status
Simulation time 25167077675 ps
CPU time 1667.96 seconds
Started Jun 05 06:18:45 PM PDT 24
Finished Jun 05 06:46:34 PM PDT 24
Peak memory 273352 kb
Host smart-9e52e0b6-d5be-4195-b45f-3a925a455b18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989220420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3989220420
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2445157312
Short name T595
Test name
Test status
Simulation time 2284685352 ps
CPU time 34.25 seconds
Started Jun 05 06:18:40 PM PDT 24
Finished Jun 05 06:19:14 PM PDT 24
Peak memory 256068 kb
Host smart-a52b2923-ff07-4cd3-a66a-9bc2fc666cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24451
57312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2445157312
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.892369724
Short name T395
Test name
Test status
Simulation time 2996069691 ps
CPU time 66.47 seconds
Started Jun 05 06:18:39 PM PDT 24
Finished Jun 05 06:19:46 PM PDT 24
Peak memory 248820 kb
Host smart-58b6cb23-4315-4feb-b328-dda0c8f441ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89236
9724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.892369724
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3158095699
Short name T26
Test name
Test status
Simulation time 11330984646 ps
CPU time 1531.01 seconds
Started Jun 05 06:18:53 PM PDT 24
Finished Jun 05 06:44:25 PM PDT 24
Peak memory 289388 kb
Host smart-4249b6d6-4163-4b67-a683-ad5ffb28d833
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158095699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3158095699
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3835081277
Short name T187
Test name
Test status
Simulation time 33768707 ps
CPU time 2.32 seconds
Started Jun 05 06:19:13 PM PDT 24
Finished Jun 05 06:19:16 PM PDT 24
Peak memory 248932 kb
Host smart-1ec19ac4-c396-4c21-a5f5-3689862c9fe2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3835081277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3835081277
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.201812542
Short name T434
Test name
Test status
Simulation time 9148835128 ps
CPU time 499.69 seconds
Started Jun 05 06:19:04 PM PDT 24
Finished Jun 05 06:27:24 PM PDT 24
Peak memory 265472 kb
Host smart-f6a3928a-178a-4997-a148-7ae41d619091
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201812542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.201812542
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2704479254
Short name T560
Test name
Test status
Simulation time 340641117 ps
CPU time 17.72 seconds
Started Jun 05 06:19:13 PM PDT 24
Finished Jun 05 06:19:31 PM PDT 24
Peak memory 248776 kb
Host smart-2caaf076-f569-4b31-b52f-983c71ec4465
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2704479254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2704479254
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1173674564
Short name T46
Test name
Test status
Simulation time 1880441413 ps
CPU time 63.61 seconds
Started Jun 05 06:18:58 PM PDT 24
Finished Jun 05 06:20:02 PM PDT 24
Peak memory 256076 kb
Host smart-e3254e24-d63e-4ddd-811a-12a7e096f151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11736
74564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1173674564
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.889795512
Short name T18
Test name
Test status
Simulation time 239131162 ps
CPU time 14.1 seconds
Started Jun 05 06:19:00 PM PDT 24
Finished Jun 05 06:19:14 PM PDT 24
Peak memory 253752 kb
Host smart-2b889961-d6c8-4a88-9ff2-b5ed2dd96d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88979
5512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.889795512
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3361945640
Short name T292
Test name
Test status
Simulation time 55566785813 ps
CPU time 1171.4 seconds
Started Jun 05 06:19:06 PM PDT 24
Finished Jun 05 06:38:38 PM PDT 24
Peak memory 272208 kb
Host smart-9adf2d87-b10b-46ec-8221-5f40afce89a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361945640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3361945640
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3532094597
Short name T400
Test name
Test status
Simulation time 23855537099 ps
CPU time 1391.83 seconds
Started Jun 05 06:19:06 PM PDT 24
Finished Jun 05 06:42:18 PM PDT 24
Peak memory 265260 kb
Host smart-f603efb9-cb51-4f61-aea0-8facedaccc69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532094597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3532094597
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3308358240
Short name T478
Test name
Test status
Simulation time 219003551 ps
CPU time 7.71 seconds
Started Jun 05 06:18:59 PM PDT 24
Finished Jun 05 06:19:07 PM PDT 24
Peak memory 248800 kb
Host smart-04b54a73-dade-4880-980d-55b2bf446918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33083
58240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3308358240
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1855903438
Short name T623
Test name
Test status
Simulation time 660481000 ps
CPU time 28.66 seconds
Started Jun 05 06:19:00 PM PDT 24
Finished Jun 05 06:19:29 PM PDT 24
Peak memory 255908 kb
Host smart-3f08b376-0c45-4596-90cd-dd2886af2581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18559
03438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1855903438
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1419246211
Short name T659
Test name
Test status
Simulation time 2961528074 ps
CPU time 45.5 seconds
Started Jun 05 06:18:59 PM PDT 24
Finished Jun 05 06:19:45 PM PDT 24
Peak memory 248824 kb
Host smart-aecc9eb9-f1bc-4027-bb48-3193afe90171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14192
46211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1419246211
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.798761086
Short name T393
Test name
Test status
Simulation time 5414630213 ps
CPU time 252.55 seconds
Started Jun 05 06:19:11 PM PDT 24
Finished Jun 05 06:23:23 PM PDT 24
Peak memory 256988 kb
Host smart-1887e28f-31fb-47e1-b6cb-d3599e94e594
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798761086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.798761086
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3895050508
Short name T222
Test name
Test status
Simulation time 70021153401 ps
CPU time 1042.4 seconds
Started Jun 05 06:19:11 PM PDT 24
Finished Jun 05 06:36:34 PM PDT 24
Peak memory 273536 kb
Host smart-5536530e-0409-40f0-b8d0-3f66f27f931d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895050508 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3895050508
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1120722623
Short name T198
Test name
Test status
Simulation time 145522732 ps
CPU time 3.63 seconds
Started Jun 05 06:19:23 PM PDT 24
Finished Jun 05 06:19:27 PM PDT 24
Peak memory 248948 kb
Host smart-7f73b52a-ce49-4be6-a910-738ef3e15e44
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1120722623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1120722623
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1968176913
Short name T404
Test name
Test status
Simulation time 14487613388 ps
CPU time 851.14 seconds
Started Jun 05 06:19:24 PM PDT 24
Finished Jun 05 06:33:36 PM PDT 24
Peak memory 272736 kb
Host smart-c15744ae-2bcb-48c8-8c7b-2ff04a52d1dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968176913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1968176913
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3357586501
Short name T652
Test name
Test status
Simulation time 219225282 ps
CPU time 12.37 seconds
Started Jun 05 06:19:26 PM PDT 24
Finished Jun 05 06:19:39 PM PDT 24
Peak memory 248776 kb
Host smart-f61e0528-89dc-4741-8dec-0f987a53f351
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3357586501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3357586501
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2719889305
Short name T624
Test name
Test status
Simulation time 15043881143 ps
CPU time 174.87 seconds
Started Jun 05 06:19:18 PM PDT 24
Finished Jun 05 06:22:14 PM PDT 24
Peak memory 251052 kb
Host smart-fe4b1eec-302b-42c1-80be-c761d4cbe3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27198
89305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2719889305
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2229899497
Short name T643
Test name
Test status
Simulation time 920276255 ps
CPU time 62.51 seconds
Started Jun 05 06:19:20 PM PDT 24
Finished Jun 05 06:20:23 PM PDT 24
Peak memory 255960 kb
Host smart-d7b82102-d683-4ed1-be99-8a6f587e71bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22298
99497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2229899497
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.4227008008
Short name T399
Test name
Test status
Simulation time 120536485526 ps
CPU time 1909 seconds
Started Jun 05 06:19:25 PM PDT 24
Finished Jun 05 06:51:15 PM PDT 24
Peak memory 269340 kb
Host smart-4c1b4bf1-e255-4d73-9638-c0d2d81737e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227008008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.4227008008
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.28026747
Short name T670
Test name
Test status
Simulation time 35405886191 ps
CPU time 380.52 seconds
Started Jun 05 06:19:24 PM PDT 24
Finished Jun 05 06:25:45 PM PDT 24
Peak memory 248100 kb
Host smart-ac869785-4ee0-4b17-89a2-eeb425095b45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28026747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.28026747
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3338768307
Short name T686
Test name
Test status
Simulation time 1391662977 ps
CPU time 24.54 seconds
Started Jun 05 06:19:17 PM PDT 24
Finished Jun 05 06:19:42 PM PDT 24
Peak memory 248784 kb
Host smart-145f5e61-9405-42eb-b686-29afc942b520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33387
68307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3338768307
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2953000779
Short name T500
Test name
Test status
Simulation time 731784672 ps
CPU time 17.37 seconds
Started Jun 05 06:19:20 PM PDT 24
Finished Jun 05 06:19:38 PM PDT 24
Peak memory 255400 kb
Host smart-f30ebe57-64ee-4da2-8afc-59cf859070eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29530
00779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2953000779
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1953167536
Short name T515
Test name
Test status
Simulation time 785305017 ps
CPU time 12.31 seconds
Started Jun 05 06:19:10 PM PDT 24
Finished Jun 05 06:19:23 PM PDT 24
Peak memory 248792 kb
Host smart-291362a3-ea40-41c3-b8ac-9de83659749c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19531
67536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1953167536
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.843494762
Short name T368
Test name
Test status
Simulation time 8044425799 ps
CPU time 105.35 seconds
Started Jun 05 06:19:26 PM PDT 24
Finished Jun 05 06:21:11 PM PDT 24
Peak memory 256636 kb
Host smart-c2d396e7-de25-43ae-becc-dde22900f05d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843494762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.843494762
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1472412994
Short name T190
Test name
Test status
Simulation time 69928407 ps
CPU time 3.07 seconds
Started Jun 05 06:19:40 PM PDT 24
Finished Jun 05 06:19:44 PM PDT 24
Peak memory 249104 kb
Host smart-02287847-1c40-4ccf-b89d-aab34b73957f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1472412994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1472412994
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.336617617
Short name T486
Test name
Test status
Simulation time 37218719996 ps
CPU time 2200.43 seconds
Started Jun 05 06:19:31 PM PDT 24
Finished Jun 05 06:56:12 PM PDT 24
Peak memory 283000 kb
Host smart-16a71bf1-fb2d-4906-8560-0ee4217a914e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336617617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.336617617
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2394524157
Short name T392
Test name
Test status
Simulation time 259743614 ps
CPU time 13.46 seconds
Started Jun 05 06:19:39 PM PDT 24
Finished Jun 05 06:19:53 PM PDT 24
Peak memory 248796 kb
Host smart-c517e9a0-3d9f-4e53-b888-8bd5f9123406
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2394524157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2394524157
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3285589620
Short name T407
Test name
Test status
Simulation time 640310312 ps
CPU time 49.3 seconds
Started Jun 05 06:19:32 PM PDT 24
Finished Jun 05 06:20:21 PM PDT 24
Peak memory 256864 kb
Host smart-caa8481c-b224-46b4-a07c-d3a90ed9950a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32855
89620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3285589620
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2881729527
Short name T375
Test name
Test status
Simulation time 1027028242 ps
CPU time 64.18 seconds
Started Jun 05 06:19:32 PM PDT 24
Finished Jun 05 06:20:37 PM PDT 24
Peak memory 248796 kb
Host smart-6bc02bc4-62b9-4122-9a87-3e53f1d55e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28817
29527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2881729527
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3164370190
Short name T380
Test name
Test status
Simulation time 54002324405 ps
CPU time 2872.7 seconds
Started Jun 05 06:19:42 PM PDT 24
Finished Jun 05 07:07:35 PM PDT 24
Peak memory 281564 kb
Host smart-48cd2d23-8678-440e-abd8-9097e96c111c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164370190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3164370190
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3279947929
Short name T372
Test name
Test status
Simulation time 2603273664 ps
CPU time 43.01 seconds
Started Jun 05 06:19:32 PM PDT 24
Finished Jun 05 06:20:16 PM PDT 24
Peak memory 248828 kb
Host smart-dfebd821-f74a-4cca-869c-fbcef2c81c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32799
47929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3279947929
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2767841551
Short name T452
Test name
Test status
Simulation time 61067775 ps
CPU time 8.26 seconds
Started Jun 05 06:19:31 PM PDT 24
Finished Jun 05 06:19:40 PM PDT 24
Peak memory 249104 kb
Host smart-be6d1829-113f-4f14-a101-dbeb341062c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27678
41551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2767841551
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1308809531
Short name T556
Test name
Test status
Simulation time 2794569054 ps
CPU time 56.29 seconds
Started Jun 05 06:19:30 PM PDT 24
Finished Jun 05 06:20:27 PM PDT 24
Peak memory 255560 kb
Host smart-f3ba3acf-b853-4ef4-a8d9-941b8731dcbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13088
09531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1308809531
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3240400050
Short name T453
Test name
Test status
Simulation time 1328697794 ps
CPU time 39.45 seconds
Started Jun 05 06:19:30 PM PDT 24
Finished Jun 05 06:20:10 PM PDT 24
Peak memory 248796 kb
Host smart-ff5601ee-ee0e-4782-b68c-49ae7ac8e86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32404
00050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3240400050
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1850627019
Short name T520
Test name
Test status
Simulation time 39542382837 ps
CPU time 2289.96 seconds
Started Jun 05 06:19:47 PM PDT 24
Finished Jun 05 06:57:57 PM PDT 24
Peak memory 273140 kb
Host smart-3ab32e42-7ff2-4138-bd95-b267dde0236b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850627019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1850627019
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.207744583
Short name T681
Test name
Test status
Simulation time 188651088 ps
CPU time 8.38 seconds
Started Jun 05 06:19:53 PM PDT 24
Finished Jun 05 06:20:02 PM PDT 24
Peak memory 240568 kb
Host smart-3134e8d9-f394-4eed-97c6-fd9b1d7c807a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=207744583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.207744583
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.181504795
Short name T17
Test name
Test status
Simulation time 1861908727 ps
CPU time 152.9 seconds
Started Jun 05 06:19:45 PM PDT 24
Finished Jun 05 06:22:19 PM PDT 24
Peak memory 250864 kb
Host smart-f48c63f2-9755-46ca-9f05-6673a8fb4fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18150
4795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.181504795
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3221077480
Short name T433
Test name
Test status
Simulation time 297145949 ps
CPU time 30.31 seconds
Started Jun 05 06:19:47 PM PDT 24
Finished Jun 05 06:20:17 PM PDT 24
Peak memory 255832 kb
Host smart-ca356768-fa1b-46e3-afd5-3958f3619a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32210
77480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3221077480
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.846192428
Short name T698
Test name
Test status
Simulation time 90968001008 ps
CPU time 1791.12 seconds
Started Jun 05 06:19:46 PM PDT 24
Finished Jun 05 06:49:37 PM PDT 24
Peak memory 289460 kb
Host smart-33adbf02-fc83-4491-9d45-0a4e7a2b3890
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846192428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.846192428
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1878660009
Short name T590
Test name
Test status
Simulation time 53882261113 ps
CPU time 870.64 seconds
Started Jun 05 06:19:51 PM PDT 24
Finished Jun 05 06:34:22 PM PDT 24
Peak memory 272700 kb
Host smart-4946a080-3de7-4d1d-b9c9-c28123684b82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878660009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1878660009
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2190315825
Short name T206
Test name
Test status
Simulation time 12315501069 ps
CPU time 479.03 seconds
Started Jun 05 06:19:44 PM PDT 24
Finished Jun 05 06:27:44 PM PDT 24
Peak memory 248024 kb
Host smart-7dc17655-eab0-472e-8734-a40944705e8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190315825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2190315825
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2665300221
Short name T619
Test name
Test status
Simulation time 834700022 ps
CPU time 31.1 seconds
Started Jun 05 06:19:42 PM PDT 24
Finished Jun 05 06:20:14 PM PDT 24
Peak memory 248772 kb
Host smart-6bfe457b-ce30-435a-9f28-33edd695c504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26653
00221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2665300221
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1380110396
Short name T80
Test name
Test status
Simulation time 4045319173 ps
CPU time 49.97 seconds
Started Jun 05 06:19:46 PM PDT 24
Finished Jun 05 06:20:36 PM PDT 24
Peak memory 247956 kb
Host smart-c2ae231c-10ce-4aff-a31d-854d82e9e917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13801
10396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1380110396
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2280817111
Short name T250
Test name
Test status
Simulation time 1416721275 ps
CPU time 46.21 seconds
Started Jun 05 06:19:46 PM PDT 24
Finished Jun 05 06:20:33 PM PDT 24
Peak memory 255964 kb
Host smart-15d87ad5-012b-40d9-9d1a-9deb0007f6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22808
17111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2280817111
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3085712796
Short name T535
Test name
Test status
Simulation time 214924502 ps
CPU time 5.72 seconds
Started Jun 05 06:19:41 PM PDT 24
Finished Jun 05 06:19:47 PM PDT 24
Peak memory 240588 kb
Host smart-c3eb104f-0e5a-4094-ace2-d8cb2bea2c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857
12796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3085712796
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.702179916
Short name T580
Test name
Test status
Simulation time 6025458615 ps
CPU time 291.33 seconds
Started Jun 05 06:19:54 PM PDT 24
Finished Jun 05 06:24:46 PM PDT 24
Peak memory 257024 kb
Host smart-dce6d603-1d42-48f4-bc22-aeb66b3e7a6a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702179916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.702179916
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.4109534195
Short name T201
Test name
Test status
Simulation time 28095764 ps
CPU time 2.65 seconds
Started Jun 05 06:20:18 PM PDT 24
Finished Jun 05 06:20:20 PM PDT 24
Peak memory 248940 kb
Host smart-a7582f4b-5bf1-4bca-a5c8-6eb17981180e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4109534195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.4109534195
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3200672634
Short name T567
Test name
Test status
Simulation time 50371046146 ps
CPU time 2790.73 seconds
Started Jun 05 06:20:05 PM PDT 24
Finished Jun 05 07:06:37 PM PDT 24
Peak memory 288868 kb
Host smart-ae8e3867-3fcf-4fa7-a0b1-1174cefaae51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200672634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3200672634
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.178419677
Short name T354
Test name
Test status
Simulation time 5651594711 ps
CPU time 41.94 seconds
Started Jun 05 06:20:11 PM PDT 24
Finished Jun 05 06:20:53 PM PDT 24
Peak memory 248856 kb
Host smart-344369dc-18d9-4f62-b3ea-86d4dd504af8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=178419677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.178419677
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.894701523
Short name T401
Test name
Test status
Simulation time 20559534085 ps
CPU time 165.77 seconds
Started Jun 05 06:19:59 PM PDT 24
Finished Jun 05 06:22:45 PM PDT 24
Peak memory 251864 kb
Host smart-0d3a8061-1ab6-4f2e-8ea4-a5a6188940e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89470
1523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.894701523
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3399467140
Short name T85
Test name
Test status
Simulation time 333806388 ps
CPU time 37.26 seconds
Started Jun 05 06:19:59 PM PDT 24
Finished Jun 05 06:20:36 PM PDT 24
Peak memory 256756 kb
Host smart-a9f617d1-a9bf-473d-b47c-b4cd948725fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33994
67140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3399467140
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.990650587
Short name T276
Test name
Test status
Simulation time 417355722 ps
CPU time 13.61 seconds
Started Jun 05 06:19:58 PM PDT 24
Finished Jun 05 06:20:12 PM PDT 24
Peak memory 253044 kb
Host smart-ccd86833-10e7-41bb-bb7e-a64a4c5c04b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99065
0587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.990650587
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2408685849
Short name T650
Test name
Test status
Simulation time 2299377904 ps
CPU time 73.25 seconds
Started Jun 05 06:19:59 PM PDT 24
Finished Jun 05 06:21:13 PM PDT 24
Peak memory 256056 kb
Host smart-40ac0a81-8131-40e7-9575-f41a1618685f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24086
85849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2408685849
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.138221191
Short name T577
Test name
Test status
Simulation time 9263962538 ps
CPU time 804.1 seconds
Started Jun 05 06:20:17 PM PDT 24
Finished Jun 05 06:33:41 PM PDT 24
Peak memory 273156 kb
Host smart-dbf7022f-255e-4dd2-b6a3-73949a254482
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138221191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.138221191
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3560586839
Short name T655
Test name
Test status
Simulation time 474691112124 ps
CPU time 10652.3 seconds
Started Jun 05 06:20:20 PM PDT 24
Finished Jun 05 09:17:54 PM PDT 24
Peak memory 369304 kb
Host smart-3f55c677-cd85-4982-9105-ee4682ff88b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560586839 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3560586839
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.141648912
Short name T203
Test name
Test status
Simulation time 115813165 ps
CPU time 3.27 seconds
Started Jun 05 06:16:09 PM PDT 24
Finished Jun 05 06:16:13 PM PDT 24
Peak memory 248968 kb
Host smart-074ce632-53fb-4f3d-a76b-078e46e61341
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=141648912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.141648912
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3722217987
Short name T30
Test name
Test status
Simulation time 10272720847 ps
CPU time 716.84 seconds
Started Jun 05 06:16:02 PM PDT 24
Finished Jun 05 06:28:00 PM PDT 24
Peak memory 268400 kb
Host smart-189e51a7-b294-46a5-925c-f689ce881974
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722217987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3722217987
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3084456723
Short name T671
Test name
Test status
Simulation time 515778149 ps
CPU time 23.58 seconds
Started Jun 05 06:16:02 PM PDT 24
Finished Jun 05 06:16:26 PM PDT 24
Peak memory 248724 kb
Host smart-0d92f095-f75d-4c59-b375-a2551e2903e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3084456723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3084456723
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.4237195413
Short name T701
Test name
Test status
Simulation time 7967196272 ps
CPU time 259.48 seconds
Started Jun 05 06:15:55 PM PDT 24
Finished Jun 05 06:20:15 PM PDT 24
Peak memory 255560 kb
Host smart-3708daba-d91b-46b6-bf16-7ea826f8e8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42371
95413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.4237195413
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.579819333
Short name T690
Test name
Test status
Simulation time 520487152 ps
CPU time 15.16 seconds
Started Jun 05 06:15:55 PM PDT 24
Finished Jun 05 06:16:11 PM PDT 24
Peak memory 248808 kb
Host smart-ad8b287d-e573-4e4d-b75c-d6082b9d7366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57981
9333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.579819333
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2018965727
Short name T67
Test name
Test status
Simulation time 38121362656 ps
CPU time 1160.41 seconds
Started Jun 05 06:16:04 PM PDT 24
Finished Jun 05 06:35:24 PM PDT 24
Peak memory 273388 kb
Host smart-4465bf4b-1d1a-49f4-a0ff-c1ace86a98e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018965727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2018965727
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1705130389
Short name T217
Test name
Test status
Simulation time 30301754932 ps
CPU time 340.5 seconds
Started Jun 05 06:16:02 PM PDT 24
Finished Jun 05 06:21:43 PM PDT 24
Peak memory 248212 kb
Host smart-abde1113-9787-4dfc-aff1-5973b2868841
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705130389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1705130389
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.989782771
Short name T417
Test name
Test status
Simulation time 963401655 ps
CPU time 54.94 seconds
Started Jun 05 06:15:54 PM PDT 24
Finished Jun 05 06:16:50 PM PDT 24
Peak memory 248788 kb
Host smart-dbbc4847-c475-4b7d-a104-5ca9d714c88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98978
2771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.989782771
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.641455269
Short name T378
Test name
Test status
Simulation time 1279987725 ps
CPU time 33.9 seconds
Started Jun 05 06:15:55 PM PDT 24
Finished Jun 05 06:16:30 PM PDT 24
Peak memory 254864 kb
Host smart-8ecae019-f9df-4a62-9dc4-2f97924d1f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64145
5269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.641455269
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2239396986
Short name T32
Test name
Test status
Simulation time 889595888 ps
CPU time 12.17 seconds
Started Jun 05 06:16:09 PM PDT 24
Finished Jun 05 06:16:21 PM PDT 24
Peak memory 277748 kb
Host smart-23f57bcc-5308-4701-bd7f-dd24c9942577
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2239396986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2239396986
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3490227279
Short name T66
Test name
Test status
Simulation time 983591518 ps
CPU time 58.08 seconds
Started Jun 05 06:16:03 PM PDT 24
Finished Jun 05 06:17:01 PM PDT 24
Peak memory 247928 kb
Host smart-3bd586ac-3ccd-468d-a5ea-e59c15ad1f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34902
27279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3490227279
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.4217596872
Short name T492
Test name
Test status
Simulation time 602197940 ps
CPU time 26.53 seconds
Started Jun 05 06:15:55 PM PDT 24
Finished Jun 05 06:16:22 PM PDT 24
Peak memory 248880 kb
Host smart-1a9f6ac8-1a09-4782-b461-c15733ca8e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42175
96872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.4217596872
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3340945781
Short name T240
Test name
Test status
Simulation time 185304648573 ps
CPU time 2585.77 seconds
Started Jun 05 06:16:04 PM PDT 24
Finished Jun 05 06:59:10 PM PDT 24
Peak memory 281624 kb
Host smart-768ada2c-4664-4561-89cb-f1b9e8927d27
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340945781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3340945781
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2432212090
Short name T543
Test name
Test status
Simulation time 80112196189 ps
CPU time 1215.06 seconds
Started Jun 05 06:20:24 PM PDT 24
Finished Jun 05 06:40:40 PM PDT 24
Peak memory 272796 kb
Host smart-046e50ad-cc81-4cf9-8c6b-c2313e858390
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432212090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2432212090
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.286192314
Short name T102
Test name
Test status
Simulation time 5788106803 ps
CPU time 208.46 seconds
Started Jun 05 06:20:24 PM PDT 24
Finished Jun 05 06:23:52 PM PDT 24
Peak memory 250932 kb
Host smart-33bce7a7-1da8-418e-ac7c-11a6987ee386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28619
2314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.286192314
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.54757100
Short name T82
Test name
Test status
Simulation time 1133504750 ps
CPU time 59.91 seconds
Started Jun 05 06:20:23 PM PDT 24
Finished Jun 05 06:21:23 PM PDT 24
Peak memory 255952 kb
Host smart-5e035db0-31fa-4d65-ab4d-c42a4f20cd9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54757
100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.54757100
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2002151669
Short name T303
Test name
Test status
Simulation time 75281855644 ps
CPU time 1165.62 seconds
Started Jun 05 06:20:24 PM PDT 24
Finished Jun 05 06:39:50 PM PDT 24
Peak memory 272732 kb
Host smart-7a5a18fd-dfa9-4267-8178-2062923e5f74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002151669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2002151669
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2882323645
Short name T371
Test name
Test status
Simulation time 31508901210 ps
CPU time 2176.73 seconds
Started Jun 05 06:20:24 PM PDT 24
Finished Jun 05 06:56:41 PM PDT 24
Peak memory 281276 kb
Host smart-1971679f-9bff-4bb0-9d20-1bdfee47124d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882323645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2882323645
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3029445542
Short name T283
Test name
Test status
Simulation time 136704974764 ps
CPU time 617.55 seconds
Started Jun 05 06:20:24 PM PDT 24
Finished Jun 05 06:30:42 PM PDT 24
Peak memory 248040 kb
Host smart-fcd493eb-10a7-4db0-9d97-7b224402202b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029445542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3029445542
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3688546915
Short name T411
Test name
Test status
Simulation time 791298255 ps
CPU time 22.55 seconds
Started Jun 05 06:20:20 PM PDT 24
Finished Jun 05 06:20:43 PM PDT 24
Peak memory 248772 kb
Host smart-2769482b-d612-4f2d-be4d-87a6301684ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36885
46915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3688546915
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1637065749
Short name T647
Test name
Test status
Simulation time 864652819 ps
CPU time 64.52 seconds
Started Jun 05 06:20:17 PM PDT 24
Finished Jun 05 06:21:22 PM PDT 24
Peak memory 255656 kb
Host smart-34dcacfc-d027-4a66-a7c0-bab1f0dd0568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16370
65749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1637065749
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.696922607
Short name T112
Test name
Test status
Simulation time 227616446 ps
CPU time 26.06 seconds
Started Jun 05 06:20:25 PM PDT 24
Finished Jun 05 06:20:51 PM PDT 24
Peak memory 248788 kb
Host smart-0ffce3b7-fcaf-4f0f-bfae-fb69d9f697ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69692
2607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.696922607
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3118042507
Short name T468
Test name
Test status
Simulation time 2034018321 ps
CPU time 37.97 seconds
Started Jun 05 06:20:17 PM PDT 24
Finished Jun 05 06:20:56 PM PDT 24
Peak memory 248768 kb
Host smart-6cf1de78-2e7c-4bc7-a0a0-df0db111a9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31180
42507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3118042507
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1111974215
Short name T598
Test name
Test status
Simulation time 87319603759 ps
CPU time 2913.45 seconds
Started Jun 05 06:20:31 PM PDT 24
Finished Jun 05 07:09:05 PM PDT 24
Peak memory 298732 kb
Host smart-e92400aa-dac7-4cfc-a60c-420012763fa1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111974215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1111974215
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3828317562
Short name T11
Test name
Test status
Simulation time 198504682289 ps
CPU time 3114.51 seconds
Started Jun 05 06:20:37 PM PDT 24
Finished Jun 05 07:12:32 PM PDT 24
Peak memory 281768 kb
Host smart-b0756aff-787e-4e3e-bc9d-29e93bc1f512
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828317562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3828317562
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1356606698
Short name T394
Test name
Test status
Simulation time 707958069 ps
CPU time 74.31 seconds
Started Jun 05 06:20:40 PM PDT 24
Finished Jun 05 06:21:55 PM PDT 24
Peak memory 248568 kb
Host smart-cf2654db-a23f-4c68-99af-2553a13228da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13566
06698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1356606698
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3718274507
Short name T337
Test name
Test status
Simulation time 96226932 ps
CPU time 7.13 seconds
Started Jun 05 06:20:37 PM PDT 24
Finished Jun 05 06:20:44 PM PDT 24
Peak memory 252784 kb
Host smart-fc7198e1-056d-4183-8da6-1dfcd0cf3a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37182
74507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3718274507
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1330404816
Short name T309
Test name
Test status
Simulation time 102116422868 ps
CPU time 1790.05 seconds
Started Jun 05 06:20:44 PM PDT 24
Finished Jun 05 06:50:35 PM PDT 24
Peak memory 266228 kb
Host smart-e61f4637-08b4-4f3a-9425-e359c77d6017
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330404816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1330404816
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2174902672
Short name T437
Test name
Test status
Simulation time 19700436306 ps
CPU time 1806.79 seconds
Started Jun 05 06:20:45 PM PDT 24
Finished Jun 05 06:50:52 PM PDT 24
Peak memory 288348 kb
Host smart-f4a74d17-b859-45d5-9650-f5c0e07b1abb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174902672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2174902672
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1677611250
Short name T514
Test name
Test status
Simulation time 45984416354 ps
CPU time 508.35 seconds
Started Jun 05 06:20:36 PM PDT 24
Finished Jun 05 06:29:05 PM PDT 24
Peak memory 248364 kb
Host smart-211987a1-8c4a-46cf-aa91-a34ca3a79feb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677611250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1677611250
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3133298840
Short name T630
Test name
Test status
Simulation time 336929920 ps
CPU time 24.89 seconds
Started Jun 05 06:20:32 PM PDT 24
Finished Jun 05 06:20:57 PM PDT 24
Peak memory 248760 kb
Host smart-b908f414-91c3-4f57-95d7-f20db0597f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31332
98840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3133298840
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1717707637
Short name T634
Test name
Test status
Simulation time 504297594 ps
CPU time 35.46 seconds
Started Jun 05 06:20:37 PM PDT 24
Finished Jun 05 06:21:13 PM PDT 24
Peak memory 255980 kb
Host smart-8c4142b9-7ec5-408d-85c2-0c9eaba16d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17177
07637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1717707637
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.214016860
Short name T3
Test name
Test status
Simulation time 4929118662 ps
CPU time 23.52 seconds
Started Jun 05 06:20:37 PM PDT 24
Finished Jun 05 06:21:01 PM PDT 24
Peak memory 248836 kb
Host smart-27ee8fc2-b33c-4083-a8bf-ec8c810ac207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21401
6860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.214016860
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3136517090
Short name T386
Test name
Test status
Simulation time 305608890 ps
CPU time 6.62 seconds
Started Jun 05 06:20:33 PM PDT 24
Finished Jun 05 06:20:40 PM PDT 24
Peak memory 248960 kb
Host smart-0104ea63-acf2-41bd-a2d2-0617599bcd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31365
17090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3136517090
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3645436297
Short name T218
Test name
Test status
Simulation time 221799002078 ps
CPU time 1319.76 seconds
Started Jun 05 06:20:50 PM PDT 24
Finished Jun 05 06:42:51 PM PDT 24
Peak memory 281032 kb
Host smart-8ee2da77-9350-4802-bd8f-3f8e7a99a7a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645436297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3645436297
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.4149638321
Short name T109
Test name
Test status
Simulation time 5454846220 ps
CPU time 775.72 seconds
Started Jun 05 06:20:57 PM PDT 24
Finished Jun 05 06:33:53 PM PDT 24
Peak memory 273392 kb
Host smart-30799d70-22a1-492d-bf2e-d9508527f860
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149638321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.4149638321
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.280099678
Short name T207
Test name
Test status
Simulation time 13489147720 ps
CPU time 124.81 seconds
Started Jun 05 06:20:51 PM PDT 24
Finished Jun 05 06:22:57 PM PDT 24
Peak memory 257092 kb
Host smart-f50db843-1194-4ad7-ad27-40350da1a1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28009
9678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.280099678
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1964530740
Short name T547
Test name
Test status
Simulation time 448743990 ps
CPU time 21.48 seconds
Started Jun 05 06:20:50 PM PDT 24
Finished Jun 05 06:21:12 PM PDT 24
Peak memory 256052 kb
Host smart-176832e9-1ade-408c-9448-40b24c765030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19645
30740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1964530740
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3165950181
Short name T632
Test name
Test status
Simulation time 20986461007 ps
CPU time 1280.78 seconds
Started Jun 05 06:20:56 PM PDT 24
Finished Jun 05 06:42:17 PM PDT 24
Peak memory 288892 kb
Host smart-948c8e47-06bd-4339-bcb2-154ab8a06b52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165950181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3165950181
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1484490782
Short name T205
Test name
Test status
Simulation time 319622748650 ps
CPU time 741.8 seconds
Started Jun 05 06:20:56 PM PDT 24
Finished Jun 05 06:33:18 PM PDT 24
Peak memory 248124 kb
Host smart-d160a7d1-67e4-48cc-834e-3eef3584630a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484490782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1484490782
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2172402150
Short name T61
Test name
Test status
Simulation time 1599446686 ps
CPU time 29.32 seconds
Started Jun 05 06:20:54 PM PDT 24
Finished Jun 05 06:21:23 PM PDT 24
Peak memory 248780 kb
Host smart-18198b1c-04d8-470d-a0ba-ecea5b9586db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21724
02150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2172402150
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3250090971
Short name T408
Test name
Test status
Simulation time 4104867538 ps
CPU time 53.28 seconds
Started Jun 05 06:20:51 PM PDT 24
Finished Jun 05 06:21:44 PM PDT 24
Peak memory 248828 kb
Host smart-4d49949f-f5ad-477e-9af6-4384d5cc14ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32500
90971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3250090971
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2146819427
Short name T525
Test name
Test status
Simulation time 3092767975 ps
CPU time 52.29 seconds
Started Jun 05 06:20:50 PM PDT 24
Finished Jun 05 06:21:43 PM PDT 24
Peak memory 248852 kb
Host smart-0b5e8cf7-66f8-42c2-b913-44ceb80b7a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21468
19427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2146819427
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.598839287
Short name T87
Test name
Test status
Simulation time 82465043281 ps
CPU time 3517.2 seconds
Started Jun 05 06:20:58 PM PDT 24
Finished Jun 05 07:19:36 PM PDT 24
Peak memory 288736 kb
Host smart-9300d2d0-6aec-43cf-bf04-bb9ebe2b775b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598839287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.598839287
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3626828606
Short name T666
Test name
Test status
Simulation time 61693804593 ps
CPU time 2197.15 seconds
Started Jun 05 06:21:18 PM PDT 24
Finished Jun 05 06:57:57 PM PDT 24
Peak memory 289284 kb
Host smart-946972e8-95cc-41bf-af80-d6fe912aca95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626828606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3626828606
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3888104080
Short name T461
Test name
Test status
Simulation time 2046857298 ps
CPU time 23.43 seconds
Started Jun 05 06:21:05 PM PDT 24
Finished Jun 05 06:21:28 PM PDT 24
Peak memory 254076 kb
Host smart-d2e67bea-60e3-4f19-9034-e059629390af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38881
04080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3888104080
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4261351975
Short name T487
Test name
Test status
Simulation time 4701672921 ps
CPU time 46.86 seconds
Started Jun 05 06:21:05 PM PDT 24
Finished Jun 05 06:21:52 PM PDT 24
Peak memory 248816 kb
Host smart-bb5db33c-655b-4edd-b1b9-74955b38851f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42613
51975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4261351975
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2688925927
Short name T319
Test name
Test status
Simulation time 45251325747 ps
CPU time 1407.67 seconds
Started Jun 05 06:21:17 PM PDT 24
Finished Jun 05 06:44:45 PM PDT 24
Peak memory 289072 kb
Host smart-6459174c-c4db-4746-b24a-1bb1c440b660
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688925927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2688925927
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3543377048
Short name T447
Test name
Test status
Simulation time 4467956766 ps
CPU time 590.97 seconds
Started Jun 05 06:21:17 PM PDT 24
Finished Jun 05 06:31:09 PM PDT 24
Peak memory 265228 kb
Host smart-22a01725-f6a7-42fc-a77f-ef68ec8e3af4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543377048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3543377048
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1262593259
Short name T642
Test name
Test status
Simulation time 53310230 ps
CPU time 4.38 seconds
Started Jun 05 06:20:59 PM PDT 24
Finished Jun 05 06:21:04 PM PDT 24
Peak memory 248780 kb
Host smart-ea5002e8-53b4-4c85-854b-8d7d794eb9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12625
93259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1262593259
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2811546275
Short name T442
Test name
Test status
Simulation time 386773347 ps
CPU time 37.85 seconds
Started Jun 05 06:21:05 PM PDT 24
Finished Jun 05 06:21:43 PM PDT 24
Peak memory 248948 kb
Host smart-26a1c9e7-9af4-40e9-ba19-9f0093478fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28115
46275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2811546275
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2120204005
Short name T252
Test name
Test status
Simulation time 616232740 ps
CPU time 39.25 seconds
Started Jun 05 06:21:18 PM PDT 24
Finished Jun 05 06:21:58 PM PDT 24
Peak memory 255948 kb
Host smart-f1329b04-7c90-4b17-855e-3ceb251a28a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21202
04005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2120204005
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.245180646
Short name T62
Test name
Test status
Simulation time 320335036 ps
CPU time 14.5 seconds
Started Jun 05 06:20:57 PM PDT 24
Finished Jun 05 06:21:11 PM PDT 24
Peak memory 248768 kb
Host smart-7e3171b5-e492-4366-a1c5-d34add30eed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24518
0646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.245180646
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.4083660613
Short name T40
Test name
Test status
Simulation time 141824367150 ps
CPU time 1161.79 seconds
Started Jun 05 06:21:25 PM PDT 24
Finished Jun 05 06:40:47 PM PDT 24
Peak memory 285244 kb
Host smart-45936e2a-c918-4179-8b89-77646694cb1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083660613 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.4083660613
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.701074409
Short name T635
Test name
Test status
Simulation time 82096872199 ps
CPU time 1482 seconds
Started Jun 05 06:21:30 PM PDT 24
Finished Jun 05 06:46:12 PM PDT 24
Peak memory 288828 kb
Host smart-198728e9-0d05-40a3-8216-b57e1251511a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701074409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.701074409
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1139620778
Short name T498
Test name
Test status
Simulation time 725253363 ps
CPU time 8.05 seconds
Started Jun 05 06:21:23 PM PDT 24
Finished Jun 05 06:21:32 PM PDT 24
Peak memory 240576 kb
Host smart-a39002f7-1a43-414f-a9f8-8b89657ef24f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11396
20778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1139620778
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3513952880
Short name T99
Test name
Test status
Simulation time 185049492 ps
CPU time 14.17 seconds
Started Jun 05 06:21:25 PM PDT 24
Finished Jun 05 06:21:39 PM PDT 24
Peak memory 248788 kb
Host smart-74b712de-66e5-4a92-b5fe-d8f213091404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35139
52880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3513952880
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1650982206
Short name T317
Test name
Test status
Simulation time 24421690742 ps
CPU time 1235.13 seconds
Started Jun 05 06:21:31 PM PDT 24
Finished Jun 05 06:42:06 PM PDT 24
Peak memory 288644 kb
Host smart-0b853028-6b80-46ca-aa24-841d2b45f9e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650982206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1650982206
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.686207505
Short name T373
Test name
Test status
Simulation time 89141480528 ps
CPU time 1460.22 seconds
Started Jun 05 06:21:30 PM PDT 24
Finished Jun 05 06:45:51 PM PDT 24
Peak memory 271188 kb
Host smart-644b097b-86e8-4bb1-a9ef-4348c38e45a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686207505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.686207505
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1212248688
Short name T297
Test name
Test status
Simulation time 8975824641 ps
CPU time 362.09 seconds
Started Jun 05 06:21:29 PM PDT 24
Finished Jun 05 06:27:32 PM PDT 24
Peak memory 248276 kb
Host smart-9c77bab9-274b-41ed-87d7-cee1921fa318
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212248688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1212248688
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1517580512
Short name T334
Test name
Test status
Simulation time 13802454929 ps
CPU time 50.76 seconds
Started Jun 05 06:21:23 PM PDT 24
Finished Jun 05 06:22:14 PM PDT 24
Peak memory 248836 kb
Host smart-30d7ce08-1649-45f9-acdb-183cf931bc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15175
80512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1517580512
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2669620044
Short name T696
Test name
Test status
Simulation time 424067134 ps
CPU time 26.97 seconds
Started Jun 05 06:21:22 PM PDT 24
Finished Jun 05 06:21:50 PM PDT 24
Peak memory 256968 kb
Host smart-3eb9350e-e698-4e03-8f2e-9ac64a26d40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26696
20044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2669620044
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1462343878
Short name T58
Test name
Test status
Simulation time 12161167508 ps
CPU time 79.32 seconds
Started Jun 05 06:21:23 PM PDT 24
Finished Jun 05 06:22:43 PM PDT 24
Peak memory 248120 kb
Host smart-405b4a80-41c2-4913-a049-5576445d1b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14623
43878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1462343878
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.741375923
Short name T212
Test name
Test status
Simulation time 226010977 ps
CPU time 14.26 seconds
Started Jun 05 06:21:23 PM PDT 24
Finished Jun 05 06:21:38 PM PDT 24
Peak memory 248780 kb
Host smart-ed733561-6325-4143-8f0c-59e91ffb0ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74137
5923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.741375923
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1790798360
Short name T527
Test name
Test status
Simulation time 208101430475 ps
CPU time 3133.35 seconds
Started Jun 05 06:21:41 PM PDT 24
Finished Jun 05 07:13:55 PM PDT 24
Peak memory 287852 kb
Host smart-145379fd-d8fe-4581-ab5e-d65a8f93237f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790798360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1790798360
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.268521141
Short name T379
Test name
Test status
Simulation time 199296396223 ps
CPU time 1346.24 seconds
Started Jun 05 06:21:51 PM PDT 24
Finished Jun 05 06:44:18 PM PDT 24
Peak memory 273380 kb
Host smart-6ad877c5-9429-4e34-96f3-ce2a5fec9e68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268521141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.268521141
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1969143851
Short name T549
Test name
Test status
Simulation time 474541432 ps
CPU time 33.59 seconds
Started Jun 05 06:21:44 PM PDT 24
Finished Jun 05 06:22:18 PM PDT 24
Peak memory 248904 kb
Host smart-9e58a7c0-60a6-411a-ada9-a901eb254fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19691
43851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1969143851
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1452768353
Short name T358
Test name
Test status
Simulation time 844617364 ps
CPU time 52.2 seconds
Started Jun 05 06:21:45 PM PDT 24
Finished Jun 05 06:22:38 PM PDT 24
Peak memory 255564 kb
Host smart-8712eb9f-8688-449e-be88-8ede9d4dfe34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14527
68353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1452768353
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3023136954
Short name T310
Test name
Test status
Simulation time 15027238350 ps
CPU time 1462.66 seconds
Started Jun 05 06:21:51 PM PDT 24
Finished Jun 05 06:46:14 PM PDT 24
Peak memory 289164 kb
Host smart-6a031dbc-1686-4de0-a3f7-f0c376b70e66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023136954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3023136954
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2343490344
Short name T424
Test name
Test status
Simulation time 21279051336 ps
CPU time 760.05 seconds
Started Jun 05 06:21:50 PM PDT 24
Finished Jun 05 06:34:30 PM PDT 24
Peak memory 272700 kb
Host smart-d806fd23-44d5-4522-b91c-0b4331772257
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343490344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2343490344
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3564956293
Short name T564
Test name
Test status
Simulation time 11270644181 ps
CPU time 238.17 seconds
Started Jun 05 06:21:51 PM PDT 24
Finished Jun 05 06:25:49 PM PDT 24
Peak memory 247900 kb
Host smart-ffff4a45-1ca6-409c-a7fc-9b00a1eee56e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564956293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3564956293
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2173578599
Short name T526
Test name
Test status
Simulation time 19883081 ps
CPU time 4.04 seconds
Started Jun 05 06:21:40 PM PDT 24
Finished Jun 05 06:21:44 PM PDT 24
Peak memory 240584 kb
Host smart-5b4ed1a5-0557-4c6e-9afc-45076848dd2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21735
78599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2173578599
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3751754466
Short name T621
Test name
Test status
Simulation time 365443275 ps
CPU time 18.11 seconds
Started Jun 05 06:21:38 PM PDT 24
Finished Jun 05 06:21:57 PM PDT 24
Peak memory 247772 kb
Host smart-1704019a-e969-478b-9340-c9f5de45a0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37517
54466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3751754466
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.483105472
Short name T545
Test name
Test status
Simulation time 2816398956 ps
CPU time 56.24 seconds
Started Jun 05 06:21:44 PM PDT 24
Finished Jun 05 06:22:41 PM PDT 24
Peak memory 255612 kb
Host smart-ef43eac9-7219-4458-a6a6-4f8da2b8b753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48310
5472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.483105472
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3721012377
Short name T64
Test name
Test status
Simulation time 305963858 ps
CPU time 18.76 seconds
Started Jun 05 06:21:40 PM PDT 24
Finished Jun 05 06:21:59 PM PDT 24
Peak memory 248772 kb
Host smart-7b139932-c66c-4f54-82c8-8323218fa121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37210
12377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3721012377
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2711310471
Short name T230
Test name
Test status
Simulation time 60011196635 ps
CPU time 1566.66 seconds
Started Jun 05 06:21:52 PM PDT 24
Finished Jun 05 06:47:59 PM PDT 24
Peak memory 289136 kb
Host smart-bd60b725-7dcd-406c-9411-80b3e4b008b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711310471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2711310471
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1440541114
Short name T54
Test name
Test status
Simulation time 37525299858 ps
CPU time 4539.07 seconds
Started Jun 05 06:21:51 PM PDT 24
Finished Jun 05 07:37:32 PM PDT 24
Peak memory 322496 kb
Host smart-09dc5528-c1de-4c44-aba7-f3451f1825dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440541114 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1440541114
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2523334790
Short name T302
Test name
Test status
Simulation time 112345987391 ps
CPU time 1558.55 seconds
Started Jun 05 06:22:06 PM PDT 24
Finished Jun 05 06:48:05 PM PDT 24
Peak memory 273104 kb
Host smart-307ab619-e300-4218-9589-80bacb906d31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523334790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2523334790
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2534092575
Short name T699
Test name
Test status
Simulation time 2067924012 ps
CPU time 32.71 seconds
Started Jun 05 06:21:58 PM PDT 24
Finished Jun 05 06:22:31 PM PDT 24
Peak memory 254760 kb
Host smart-e9ef9363-2683-45c3-90b6-53d11f5675ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25340
92575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2534092575
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.655957102
Short name T538
Test name
Test status
Simulation time 153960434 ps
CPU time 4.21 seconds
Started Jun 05 06:21:56 PM PDT 24
Finished Jun 05 06:22:00 PM PDT 24
Peak memory 240584 kb
Host smart-435d0be6-1242-4827-8cf5-7136a8c8868c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65595
7102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.655957102
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1852126790
Short name T597
Test name
Test status
Simulation time 102042249431 ps
CPU time 1435.4 seconds
Started Jun 05 06:22:11 PM PDT 24
Finished Jun 05 06:46:07 PM PDT 24
Peak memory 265240 kb
Host smart-a06c6763-07fb-42b9-88f1-9da3f4128aac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852126790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1852126790
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2178138926
Short name T105
Test name
Test status
Simulation time 17873768987 ps
CPU time 1464.04 seconds
Started Jun 05 06:22:09 PM PDT 24
Finished Jun 05 06:46:34 PM PDT 24
Peak memory 288156 kb
Host smart-e208dce7-f650-4d3b-a2df-76eb20d40b23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178138926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2178138926
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1188451622
Short name T553
Test name
Test status
Simulation time 10906455442 ps
CPU time 469.63 seconds
Started Jun 05 06:22:12 PM PDT 24
Finished Jun 05 06:30:02 PM PDT 24
Peak memory 248116 kb
Host smart-ffad988e-acaf-445d-b89e-1f01f49b0da9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188451622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1188451622
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.469300513
Short name T344
Test name
Test status
Simulation time 742835129 ps
CPU time 41.14 seconds
Started Jun 05 06:21:57 PM PDT 24
Finished Jun 05 06:22:38 PM PDT 24
Peak memory 248764 kb
Host smart-04cb0ea5-4280-45b0-a9df-f761dc722a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46930
0513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.469300513
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3815398920
Short name T332
Test name
Test status
Simulation time 1006379609 ps
CPU time 25.42 seconds
Started Jun 05 06:21:57 PM PDT 24
Finished Jun 05 06:22:23 PM PDT 24
Peak memory 256080 kb
Host smart-dd88bf34-62d4-47f1-9a0b-ec0628a7c33e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38153
98920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3815398920
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3513732305
Short name T104
Test name
Test status
Simulation time 92235778 ps
CPU time 7.41 seconds
Started Jun 05 06:22:03 PM PDT 24
Finished Jun 05 06:22:11 PM PDT 24
Peak memory 248832 kb
Host smart-e45e3c4b-f521-4143-beb6-25fc899b9b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35137
32305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3513732305
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.299034422
Short name T592
Test name
Test status
Simulation time 91933287 ps
CPU time 13.6 seconds
Started Jun 05 06:21:53 PM PDT 24
Finished Jun 05 06:22:07 PM PDT 24
Peak memory 248784 kb
Host smart-a7809849-1d9c-4375-bbcc-f9b09d1b56cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29903
4422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.299034422
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.4046640970
Short name T641
Test name
Test status
Simulation time 33186270783 ps
CPU time 2096.11 seconds
Started Jun 05 06:22:16 PM PDT 24
Finished Jun 05 06:57:13 PM PDT 24
Peak memory 289324 kb
Host smart-20c6a13d-1165-4872-8835-da96dd1a4ecb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046640970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.4046640970
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2577935147
Short name T675
Test name
Test status
Simulation time 9282086720 ps
CPU time 218.76 seconds
Started Jun 05 06:22:25 PM PDT 24
Finished Jun 05 06:26:04 PM PDT 24
Peak memory 256976 kb
Host smart-b61d05a5-247f-4a78-8a9f-c39db5ae7387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25779
35147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2577935147
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.4059382783
Short name T559
Test name
Test status
Simulation time 783567551 ps
CPU time 43.26 seconds
Started Jun 05 06:22:25 PM PDT 24
Finished Jun 05 06:23:09 PM PDT 24
Peak memory 256296 kb
Host smart-df0887dc-5181-4925-9cb8-28f5f017efa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40593
82783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.4059382783
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3958169466
Short name T389
Test name
Test status
Simulation time 85553079589 ps
CPU time 2734.31 seconds
Started Jun 05 06:22:31 PM PDT 24
Finished Jun 05 07:08:06 PM PDT 24
Peak memory 289328 kb
Host smart-00f954a7-1aa3-491a-8484-970a236d25c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958169466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3958169466
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3032405439
Short name T286
Test name
Test status
Simulation time 5033009103 ps
CPU time 207.85 seconds
Started Jun 05 06:22:30 PM PDT 24
Finished Jun 05 06:25:58 PM PDT 24
Peak memory 248192 kb
Host smart-88e6ead4-877e-431f-8dc5-c4bc094b8a09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032405439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3032405439
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1819415799
Short name T546
Test name
Test status
Simulation time 426060939 ps
CPU time 32.34 seconds
Started Jun 05 06:22:24 PM PDT 24
Finished Jun 05 06:22:57 PM PDT 24
Peak memory 248796 kb
Host smart-dcd22db4-d822-40d4-988b-47127c33b547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18194
15799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1819415799
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.154047661
Short name T639
Test name
Test status
Simulation time 3497466292 ps
CPU time 50.56 seconds
Started Jun 05 06:22:24 PM PDT 24
Finished Jun 05 06:23:15 PM PDT 24
Peak memory 256520 kb
Host smart-ca2bc102-81c9-4e49-b6c0-0e9e742c2ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
7661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.154047661
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2269241299
Short name T581
Test name
Test status
Simulation time 478137901 ps
CPU time 15.79 seconds
Started Jun 05 06:22:25 PM PDT 24
Finished Jun 05 06:22:41 PM PDT 24
Peak memory 248784 kb
Host smart-2128dc02-c5ac-4a65-8f39-2a189aaf681c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22692
41299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2269241299
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.748613083
Short name T618
Test name
Test status
Simulation time 794466931 ps
CPU time 56.22 seconds
Started Jun 05 06:22:19 PM PDT 24
Finished Jun 05 06:23:15 PM PDT 24
Peak memory 256084 kb
Host smart-e4094df4-6294-46e9-80e0-4aff948d5aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74861
3083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.748613083
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3640836640
Short name T536
Test name
Test status
Simulation time 63574249786 ps
CPU time 241 seconds
Started Jun 05 06:22:31 PM PDT 24
Finished Jun 05 06:26:32 PM PDT 24
Peak memory 250604 kb
Host smart-c4637e4f-b489-44b7-b66e-3ae4669634af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640836640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3640836640
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.4027364445
Short name T83
Test name
Test status
Simulation time 259882006610 ps
CPU time 7277.29 seconds
Started Jun 05 06:22:37 PM PDT 24
Finished Jun 05 08:23:55 PM PDT 24
Peak memory 355512 kb
Host smart-d12d437c-86c4-4bd1-b428-d64364155972
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027364445 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.4027364445
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.636660575
Short name T673
Test name
Test status
Simulation time 47936874281 ps
CPU time 1649.83 seconds
Started Jun 05 06:22:42 PM PDT 24
Finished Jun 05 06:50:13 PM PDT 24
Peak memory 273432 kb
Host smart-25a7162e-7dc7-4af6-92aa-cd48a902ac33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636660575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.636660575
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1333371662
Short name T662
Test name
Test status
Simulation time 1093170897 ps
CPU time 66.93 seconds
Started Jun 05 06:22:37 PM PDT 24
Finished Jun 05 06:23:44 PM PDT 24
Peak memory 256588 kb
Host smart-01c6513e-5af0-4c3e-bcb9-f35dc9ba4bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13333
71662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1333371662
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1557781880
Short name T628
Test name
Test status
Simulation time 421553038 ps
CPU time 9.12 seconds
Started Jun 05 06:22:38 PM PDT 24
Finished Jun 05 06:22:47 PM PDT 24
Peak memory 249736 kb
Host smart-1b324c26-41da-44cf-9a9b-edfe2fd34bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15577
81880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1557781880
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3361889527
Short name T178
Test name
Test status
Simulation time 53137438084 ps
CPU time 2955.85 seconds
Started Jun 05 06:22:53 PM PDT 24
Finished Jun 05 07:12:10 PM PDT 24
Peak memory 288416 kb
Host smart-2ad290ba-fa61-43f4-be82-0b3d706332db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361889527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3361889527
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1571313854
Short name T69
Test name
Test status
Simulation time 12076018246 ps
CPU time 1333.69 seconds
Started Jun 05 06:22:52 PM PDT 24
Finished Jun 05 06:45:06 PM PDT 24
Peak memory 273412 kb
Host smart-5fa81255-325e-4d14-81b5-e98fbcbe9879
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571313854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1571313854
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.937440284
Short name T579
Test name
Test status
Simulation time 9204277258 ps
CPU time 381.02 seconds
Started Jun 05 06:22:55 PM PDT 24
Finished Jun 05 06:29:17 PM PDT 24
Peak memory 248232 kb
Host smart-c27d7025-ab1c-4a42-bc30-4fb7d848fab6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937440284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.937440284
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2217591130
Short name T211
Test name
Test status
Simulation time 780959384 ps
CPU time 23.99 seconds
Started Jun 05 06:22:37 PM PDT 24
Finished Jun 05 06:23:02 PM PDT 24
Peak memory 248780 kb
Host smart-202a9b0d-279d-434b-917a-41c87b6c3ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22175
91130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2217591130
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2700048815
Short name T627
Test name
Test status
Simulation time 14191887902 ps
CPU time 66.63 seconds
Started Jun 05 06:22:38 PM PDT 24
Finished Jun 05 06:23:45 PM PDT 24
Peak memory 248928 kb
Host smart-dc8c3ac1-f24e-4dfd-a198-828759e72ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27000
48815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2700048815
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.222124101
Short name T513
Test name
Test status
Simulation time 62475350 ps
CPU time 2.95 seconds
Started Jun 05 06:22:38 PM PDT 24
Finished Jun 05 06:22:41 PM PDT 24
Peak memory 240584 kb
Host smart-150fddff-5389-4b32-9a22-00bfbceca4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22212
4101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.222124101
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.376411473
Short name T431
Test name
Test status
Simulation time 170474755 ps
CPU time 22.08 seconds
Started Jun 05 06:22:36 PM PDT 24
Finished Jun 05 06:22:58 PM PDT 24
Peak memory 248772 kb
Host smart-10b328bf-8ddf-4346-a143-e83b457d98f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37641
1473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.376411473
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1159480195
Short name T184
Test name
Test status
Simulation time 267119160794 ps
CPU time 6148.23 seconds
Started Jun 05 06:22:58 PM PDT 24
Finished Jun 05 08:05:28 PM PDT 24
Peak memory 339068 kb
Host smart-ca6d86a1-7f2b-4060-840e-2bd37397e52c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159480195 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1159480195
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3732766225
Short name T110
Test name
Test status
Simulation time 193049078084 ps
CPU time 2857.67 seconds
Started Jun 05 06:23:18 PM PDT 24
Finished Jun 05 07:10:57 PM PDT 24
Peak memory 281768 kb
Host smart-765ad3d3-aa39-4840-8c51-1f41a5966f0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732766225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3732766225
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.4110947352
Short name T355
Test name
Test status
Simulation time 140970513 ps
CPU time 7.43 seconds
Started Jun 05 06:23:06 PM PDT 24
Finished Jun 05 06:23:14 PM PDT 24
Peak memory 241012 kb
Host smart-3636faf7-2466-415f-9e19-91d9e494335c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41109
47352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.4110947352
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.4222399584
Short name T531
Test name
Test status
Simulation time 235255584 ps
CPU time 25.3 seconds
Started Jun 05 06:23:05 PM PDT 24
Finished Jun 05 06:23:31 PM PDT 24
Peak memory 255960 kb
Host smart-6acf63bf-3319-418e-a4f4-7b8bc24434ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42223
99584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4222399584
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3771394574
Short name T307
Test name
Test status
Simulation time 77931127467 ps
CPU time 1648.36 seconds
Started Jun 05 06:23:17 PM PDT 24
Finished Jun 05 06:50:46 PM PDT 24
Peak memory 289316 kb
Host smart-8c3369a3-7f96-481d-962e-77a53c1613e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771394574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3771394574
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3583182646
Short name T460
Test name
Test status
Simulation time 44960359810 ps
CPU time 1116.17 seconds
Started Jun 05 06:23:20 PM PDT 24
Finished Jun 05 06:41:57 PM PDT 24
Peak memory 273264 kb
Host smart-b75c80e1-19be-435d-921d-6aad7b918284
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583182646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3583182646
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3900403875
Short name T221
Test name
Test status
Simulation time 98524432150 ps
CPU time 402.29 seconds
Started Jun 05 06:23:21 PM PDT 24
Finished Jun 05 06:30:04 PM PDT 24
Peak memory 248304 kb
Host smart-f98c230b-5161-44ab-9899-884974380531
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900403875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3900403875
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3724193388
Short name T342
Test name
Test status
Simulation time 54222963 ps
CPU time 3.1 seconds
Started Jun 05 06:22:58 PM PDT 24
Finished Jun 05 06:23:02 PM PDT 24
Peak memory 240584 kb
Host smart-ee2a6541-50d4-44f4-a8d8-21d765699309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37241
93388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3724193388
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3777453837
Short name T174
Test name
Test status
Simulation time 1045666388 ps
CPU time 37.44 seconds
Started Jun 05 06:22:58 PM PDT 24
Finished Jun 05 06:23:36 PM PDT 24
Peak memory 255636 kb
Host smart-f0b157a3-879b-45cf-a887-5fe9d15cded5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37774
53837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3777453837
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3789497598
Short name T43
Test name
Test status
Simulation time 67352252 ps
CPU time 2.95 seconds
Started Jun 05 06:23:12 PM PDT 24
Finished Jun 05 06:23:16 PM PDT 24
Peak memory 239160 kb
Host smart-0667d7af-dbe2-491a-a95c-d2eaf29be20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37894
97598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3789497598
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.4285720318
Short name T406
Test name
Test status
Simulation time 2888051186 ps
CPU time 45.13 seconds
Started Jun 05 06:22:59 PM PDT 24
Finished Jun 05 06:23:45 PM PDT 24
Peak memory 248808 kb
Host smart-7590549f-a414-4ecc-ba75-d5856fc5430d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42857
20318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.4285720318
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1989574176
Short name T255
Test name
Test status
Simulation time 23421410466 ps
CPU time 1572.2 seconds
Started Jun 05 06:23:19 PM PDT 24
Finished Jun 05 06:49:32 PM PDT 24
Peak memory 272876 kb
Host smart-0aeb3341-942a-4657-a51f-25bedcd51557
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989574176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1989574176
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1395483267
Short name T188
Test name
Test status
Simulation time 17532152 ps
CPU time 2.52 seconds
Started Jun 05 06:16:21 PM PDT 24
Finished Jun 05 06:16:24 PM PDT 24
Peak memory 248960 kb
Host smart-2a532208-9c57-4af2-befa-c41d330e9da5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1395483267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1395483267
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.861976903
Short name T464
Test name
Test status
Simulation time 39682589908 ps
CPU time 1141.21 seconds
Started Jun 05 06:16:15 PM PDT 24
Finished Jun 05 06:35:17 PM PDT 24
Peak memory 273460 kb
Host smart-f3acdc9b-c614-408d-b9f3-909e2105ddd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861976903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.861976903
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2116300846
Short name T343
Test name
Test status
Simulation time 881070081 ps
CPU time 39.27 seconds
Started Jun 05 06:16:14 PM PDT 24
Finished Jun 05 06:16:54 PM PDT 24
Peak memory 248812 kb
Host smart-c3383be4-3be0-4aa1-8859-641fcb3e98d9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2116300846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2116300846
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1112772803
Short name T506
Test name
Test status
Simulation time 1747107732 ps
CPU time 97.91 seconds
Started Jun 05 06:16:13 PM PDT 24
Finished Jun 05 06:17:52 PM PDT 24
Peak memory 256684 kb
Host smart-fae56c4c-e265-4e0a-85d5-6cdc800c6f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11127
72803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1112772803
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.4181852698
Short name T455
Test name
Test status
Simulation time 9154526291 ps
CPU time 57.14 seconds
Started Jun 05 06:16:14 PM PDT 24
Finished Jun 05 06:17:11 PM PDT 24
Peak memory 257000 kb
Host smart-4e5fe106-83fb-4686-9efb-069cfd333d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41818
52698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.4181852698
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.657806710
Short name T305
Test name
Test status
Simulation time 150808708244 ps
CPU time 2140.71 seconds
Started Jun 05 06:16:16 PM PDT 24
Finished Jun 05 06:51:57 PM PDT 24
Peak memory 272748 kb
Host smart-ba526234-2fee-46c0-ae32-fab091e52181
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657806710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.657806710
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2287447111
Short name T694
Test name
Test status
Simulation time 39709808671 ps
CPU time 1037.25 seconds
Started Jun 05 06:16:13 PM PDT 24
Finished Jun 05 06:33:31 PM PDT 24
Peak memory 273388 kb
Host smart-e7528b07-b962-4f05-b1f5-973412dbd75f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287447111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2287447111
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.4049073232
Short name T284
Test name
Test status
Simulation time 7852201419 ps
CPU time 307.86 seconds
Started Jun 05 06:16:14 PM PDT 24
Finished Jun 05 06:21:22 PM PDT 24
Peak memory 254848 kb
Host smart-5080631f-8b59-4153-bef2-b3ac3032650d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049073232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.4049073232
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1183755116
Short name T537
Test name
Test status
Simulation time 1082016213 ps
CPU time 26.24 seconds
Started Jun 05 06:16:09 PM PDT 24
Finished Jun 05 06:16:36 PM PDT 24
Peak memory 248784 kb
Host smart-feeec0e0-00da-463d-95dc-a1422ab7c4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11837
55116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1183755116
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2748846813
Short name T370
Test name
Test status
Simulation time 1575551959 ps
CPU time 9.56 seconds
Started Jun 05 06:16:15 PM PDT 24
Finished Jun 05 06:16:25 PM PDT 24
Peak memory 248772 kb
Host smart-a59284c2-7dca-4867-a5db-cd983f3f8e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27488
46813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2748846813
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.84441484
Short name T9
Test name
Test status
Simulation time 181486489 ps
CPU time 12.99 seconds
Started Jun 05 06:16:26 PM PDT 24
Finished Jun 05 06:16:40 PM PDT 24
Peak memory 266404 kb
Host smart-938c844c-7bf7-46fe-ab9e-7e7613b4e8bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=84441484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.84441484
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.166575614
Short name T436
Test name
Test status
Simulation time 260373322 ps
CPU time 28.04 seconds
Started Jun 05 06:16:13 PM PDT 24
Finished Jun 05 06:16:41 PM PDT 24
Peak memory 247716 kb
Host smart-ef2ed3d5-45c1-4daa-80cc-d8faae0ee092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16657
5614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.166575614
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2258378523
Short name T534
Test name
Test status
Simulation time 572541709 ps
CPU time 32.76 seconds
Started Jun 05 06:16:09 PM PDT 24
Finished Jun 05 06:16:42 PM PDT 24
Peak memory 248784 kb
Host smart-c671b124-9739-4f7b-8ee8-2873405b9416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22583
78523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2258378523
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.501105560
Short name T569
Test name
Test status
Simulation time 88085915113 ps
CPU time 1730.08 seconds
Started Jun 05 06:16:21 PM PDT 24
Finished Jun 05 06:45:12 PM PDT 24
Peak memory 271360 kb
Host smart-6393f0da-0484-43ba-9ee3-62199d2d60ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501105560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.501105560
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1211713919
Short name T533
Test name
Test status
Simulation time 43376673095 ps
CPU time 4118.55 seconds
Started Jun 05 06:16:21 PM PDT 24
Finished Jun 05 07:25:00 PM PDT 24
Peak memory 315852 kb
Host smart-4a1f1d0b-4ed7-4b95-a011-6301cc781fe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211713919 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1211713919
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1758441188
Short name T396
Test name
Test status
Simulation time 45127902212 ps
CPU time 2602.8 seconds
Started Jun 05 06:23:39 PM PDT 24
Finished Jun 05 07:07:03 PM PDT 24
Peak memory 289284 kb
Host smart-4f902be0-1729-4b4c-a611-01b2783b6d44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758441188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1758441188
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.28506500
Short name T542
Test name
Test status
Simulation time 6864803881 ps
CPU time 163.06 seconds
Started Jun 05 06:23:30 PM PDT 24
Finished Jun 05 06:26:14 PM PDT 24
Peak memory 249992 kb
Host smart-759e77c3-8a68-4197-bf29-510bae5d881d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28506
500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.28506500
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2689471997
Short name T63
Test name
Test status
Simulation time 981696424 ps
CPU time 34.5 seconds
Started Jun 05 06:23:29 PM PDT 24
Finished Jun 05 06:24:04 PM PDT 24
Peak memory 248792 kb
Host smart-abe17ba3-6cfe-45c3-8c4c-d4ec83f41d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26894
71997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2689471997
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1177286468
Short name T511
Test name
Test status
Simulation time 185399781123 ps
CPU time 1794.82 seconds
Started Jun 05 06:23:38 PM PDT 24
Finished Jun 05 06:53:34 PM PDT 24
Peak memory 288840 kb
Host smart-e3c19691-9967-4c75-a13a-1a89ba70c0a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177286468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1177286468
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2101660506
Short name T42
Test name
Test status
Simulation time 7764365994 ps
CPU time 968.69 seconds
Started Jun 05 06:23:39 PM PDT 24
Finished Jun 05 06:39:48 PM PDT 24
Peak memory 273048 kb
Host smart-6793be96-b99a-4096-b7df-a85043ccf370
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101660506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2101660506
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3855334179
Short name T496
Test name
Test status
Simulation time 9379952211 ps
CPU time 353.99 seconds
Started Jun 05 06:23:36 PM PDT 24
Finished Jun 05 06:29:31 PM PDT 24
Peak memory 248268 kb
Host smart-b1d0a652-ce71-460d-b203-5bbee4d5be44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855334179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3855334179
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2010353357
Short name T663
Test name
Test status
Simulation time 751639516 ps
CPU time 28.61 seconds
Started Jun 05 06:23:24 PM PDT 24
Finished Jun 05 06:23:53 PM PDT 24
Peak memory 256136 kb
Host smart-0a693504-a7bd-4147-a0e4-cae382d4229f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20103
53357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2010353357
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3029382160
Short name T381
Test name
Test status
Simulation time 517179901 ps
CPU time 22.08 seconds
Started Jun 05 06:23:24 PM PDT 24
Finished Jun 05 06:23:47 PM PDT 24
Peak memory 248832 kb
Host smart-65f7cfef-f44a-4b91-bf49-b5b9d56cdbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30293
82160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3029382160
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.620876979
Short name T541
Test name
Test status
Simulation time 679779462 ps
CPU time 53.6 seconds
Started Jun 05 06:23:39 PM PDT 24
Finished Jun 05 06:24:34 PM PDT 24
Peak memory 248772 kb
Host smart-ec8c8aad-63c6-400c-8776-58bb7448f32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62087
6979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.620876979
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1840125832
Short name T602
Test name
Test status
Simulation time 1323233407 ps
CPU time 37.27 seconds
Started Jun 05 06:23:25 PM PDT 24
Finished Jun 05 06:24:02 PM PDT 24
Peak memory 248748 kb
Host smart-6b70a0d0-cfdc-411a-82d5-c6378d4b85ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18401
25832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1840125832
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.4039484669
Short name T573
Test name
Test status
Simulation time 3983968725 ps
CPU time 65.64 seconds
Started Jun 05 06:23:38 PM PDT 24
Finished Jun 05 06:24:44 PM PDT 24
Peak memory 256400 kb
Host smart-bcee0b82-0561-4340-89c6-36dfb2609712
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039484669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.4039484669
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3321544331
Short name T245
Test name
Test status
Simulation time 405941793363 ps
CPU time 9668.66 seconds
Started Jun 05 06:23:46 PM PDT 24
Finished Jun 05 09:04:56 PM PDT 24
Peak memory 371076 kb
Host smart-89533dfe-10ec-4e54-9305-b6b82c271b3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321544331 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3321544331
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.979095549
Short name T448
Test name
Test status
Simulation time 121306415087 ps
CPU time 1896.05 seconds
Started Jun 05 06:23:51 PM PDT 24
Finished Jun 05 06:55:28 PM PDT 24
Peak memory 266256 kb
Host smart-3faf7686-abd0-473e-a898-6ea8a1dca634
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979095549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.979095549
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.260251554
Short name T615
Test name
Test status
Simulation time 126279106 ps
CPU time 8.22 seconds
Started Jun 05 06:23:47 PM PDT 24
Finished Jun 05 06:23:56 PM PDT 24
Peak memory 240336 kb
Host smart-e95438a0-e9a2-43d3-a7a1-8e3af060a6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26025
1554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.260251554
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.717055545
Short name T522
Test name
Test status
Simulation time 205479692 ps
CPU time 21.74 seconds
Started Jun 05 06:23:44 PM PDT 24
Finished Jun 05 06:24:07 PM PDT 24
Peak memory 248772 kb
Host smart-46073b35-ec5b-46eb-8d35-62a1d49097d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71705
5545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.717055545
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2989153115
Short name T322
Test name
Test status
Simulation time 27819817633 ps
CPU time 1049.18 seconds
Started Jun 05 06:23:53 PM PDT 24
Finished Jun 05 06:41:23 PM PDT 24
Peak memory 272772 kb
Host smart-9e5868db-140c-4eba-a04d-4a7942ea0879
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989153115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2989153115
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2337285768
Short name T426
Test name
Test status
Simulation time 105980429446 ps
CPU time 3162.94 seconds
Started Jun 05 06:23:51 PM PDT 24
Finished Jun 05 07:16:35 PM PDT 24
Peak memory 289580 kb
Host smart-af69641e-674b-4fb9-aaab-e5711758db22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337285768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2337285768
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.198343254
Short name T678
Test name
Test status
Simulation time 16197662896 ps
CPU time 171.21 seconds
Started Jun 05 06:23:53 PM PDT 24
Finished Jun 05 06:26:45 PM PDT 24
Peak memory 253436 kb
Host smart-bfc276bf-c9b4-44af-ab0b-6ae862880ef7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198343254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.198343254
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1037700953
Short name T418
Test name
Test status
Simulation time 606740834 ps
CPU time 47.01 seconds
Started Jun 05 06:23:47 PM PDT 24
Finished Jun 05 06:24:34 PM PDT 24
Peak memory 248796 kb
Host smart-71ce3b02-1cdc-48a2-b57b-d8636fc50ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10377
00953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1037700953
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.387248311
Short name T351
Test name
Test status
Simulation time 243303518 ps
CPU time 6.09 seconds
Started Jun 05 06:23:46 PM PDT 24
Finished Jun 05 06:23:53 PM PDT 24
Peak memory 239272 kb
Host smart-70d77fa0-665d-4aec-b374-469cb468da56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38724
8311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.387248311
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3482188366
Short name T270
Test name
Test status
Simulation time 90182231 ps
CPU time 10.88 seconds
Started Jun 05 06:23:54 PM PDT 24
Finished Jun 05 06:24:05 PM PDT 24
Peak memory 248776 kb
Host smart-0af9c125-bb26-41c7-9eea-ca85387e6e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34821
88366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3482188366
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3612433084
Short name T614
Test name
Test status
Simulation time 2900053359 ps
CPU time 48.5 seconds
Started Jun 05 06:23:44 PM PDT 24
Finished Jun 05 06:24:33 PM PDT 24
Peak memory 248912 kb
Host smart-78d9d868-1505-4346-ba46-5d3e4803ff52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36124
33084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3612433084
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2819155346
Short name T209
Test name
Test status
Simulation time 172066101383 ps
CPU time 2670.77 seconds
Started Jun 05 06:23:51 PM PDT 24
Finished Jun 05 07:08:23 PM PDT 24
Peak memory 288240 kb
Host smart-08526e46-89c7-4432-aa2c-990b51e087fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819155346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2819155346
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1175910021
Short name T267
Test name
Test status
Simulation time 140240487011 ps
CPU time 2518.39 seconds
Started Jun 05 06:23:53 PM PDT 24
Finished Jun 05 07:05:52 PM PDT 24
Peak memory 305316 kb
Host smart-879e91f3-ff86-4c18-9344-ec31c9513528
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175910021 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1175910021
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3287356970
Short name T471
Test name
Test status
Simulation time 94272589246 ps
CPU time 3085.36 seconds
Started Jun 05 06:24:19 PM PDT 24
Finished Jun 05 07:15:45 PM PDT 24
Peak memory 285156 kb
Host smart-3f43ddf4-7e39-44b4-8335-2d106ca9a783
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287356970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3287356970
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.304210834
Short name T95
Test name
Test status
Simulation time 8600691109 ps
CPU time 145.19 seconds
Started Jun 05 06:24:12 PM PDT 24
Finished Jun 05 06:26:38 PM PDT 24
Peak memory 257004 kb
Host smart-364a6e26-ab4d-404e-b1ec-108c00b4ab63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30421
0834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.304210834
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1690238024
Short name T665
Test name
Test status
Simulation time 983110580 ps
CPU time 51.82 seconds
Started Jun 05 06:24:10 PM PDT 24
Finished Jun 05 06:25:02 PM PDT 24
Peak memory 256164 kb
Host smart-d19e197a-d254-4d96-9801-e243aff6f92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16902
38024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1690238024
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3545873798
Short name T280
Test name
Test status
Simulation time 245076321045 ps
CPU time 1823.84 seconds
Started Jun 05 06:24:27 PM PDT 24
Finished Jun 05 06:54:51 PM PDT 24
Peak memory 270400 kb
Host smart-e0849a5d-8fba-42cc-8eb4-6641725c5d1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545873798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3545873798
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.939129677
Short name T41
Test name
Test status
Simulation time 30055812192 ps
CPU time 1858.51 seconds
Started Jun 05 06:24:27 PM PDT 24
Finished Jun 05 06:55:27 PM PDT 24
Peak memory 272972 kb
Host smart-34f6f3e7-3f0f-41da-9d90-3b361e6acae3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939129677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.939129677
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.17208264
Short name T285
Test name
Test status
Simulation time 35675147329 ps
CPU time 391.34 seconds
Started Jun 05 06:24:19 PM PDT 24
Finished Jun 05 06:30:51 PM PDT 24
Peak memory 248324 kb
Host smart-06d20922-0954-48bc-bc91-94198b902b5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17208264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.17208264
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.741653623
Short name T29
Test name
Test status
Simulation time 547169054 ps
CPU time 26.06 seconds
Started Jun 05 06:24:07 PM PDT 24
Finished Jun 05 06:24:34 PM PDT 24
Peak memory 248772 kb
Host smart-9502e358-a09c-4847-828c-0dafbd1eec85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74165
3623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.741653623
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.973880171
Short name T47
Test name
Test status
Simulation time 321288796 ps
CPU time 27.09 seconds
Started Jun 05 06:24:05 PM PDT 24
Finished Jun 05 06:24:33 PM PDT 24
Peak memory 249060 kb
Host smart-8bd61fdc-4ba2-4b6e-9245-ac3ac0e88ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97388
0171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.973880171
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1842019700
Short name T233
Test name
Test status
Simulation time 1194273751 ps
CPU time 20.33 seconds
Started Jun 05 06:24:12 PM PDT 24
Finished Jun 05 06:24:33 PM PDT 24
Peak memory 255948 kb
Host smart-ac04fe10-0fed-432f-956c-cfb9adefc836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18420
19700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1842019700
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2479477577
Short name T419
Test name
Test status
Simulation time 280645507 ps
CPU time 31.92 seconds
Started Jun 05 06:23:53 PM PDT 24
Finished Jun 05 06:24:25 PM PDT 24
Peak memory 248824 kb
Host smart-7f4e5570-4b62-40b2-b083-cb299594cb27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24794
77577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2479477577
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.2363482586
Short name T50
Test name
Test status
Simulation time 449020134262 ps
CPU time 7464.53 seconds
Started Jun 05 06:24:26 PM PDT 24
Finished Jun 05 08:28:52 PM PDT 24
Peak memory 338976 kb
Host smart-d9abecbb-bd8d-4fa7-8af4-c1d15d8e2a4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363482586 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.2363482586
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.999697155
Short name T493
Test name
Test status
Simulation time 36466111370 ps
CPU time 2509.32 seconds
Started Jun 05 06:24:33 PM PDT 24
Finished Jun 05 07:06:23 PM PDT 24
Peak memory 289668 kb
Host smart-75cb88a5-dac9-48f1-8b4b-da2b0e30cd32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999697155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.999697155
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.657629770
Short name T405
Test name
Test status
Simulation time 8450047296 ps
CPU time 149.26 seconds
Started Jun 05 06:24:34 PM PDT 24
Finished Jun 05 06:27:04 PM PDT 24
Peak memory 256768 kb
Host smart-e50e8d42-0882-48bd-9861-26933d9e708b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65762
9770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.657629770
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3708928928
Short name T76
Test name
Test status
Simulation time 1132819010 ps
CPU time 25.72 seconds
Started Jun 05 06:24:32 PM PDT 24
Finished Jun 05 06:24:58 PM PDT 24
Peak memory 255760 kb
Host smart-d0a8686c-0b8f-4aed-aabb-4d8d47e606ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37089
28928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3708928928
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.464909619
Short name T348
Test name
Test status
Simulation time 9072559902 ps
CPU time 858.92 seconds
Started Jun 05 06:24:42 PM PDT 24
Finished Jun 05 06:39:01 PM PDT 24
Peak memory 265560 kb
Host smart-7bd8fc59-d2ea-4a21-bd18-616c60b18c1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464909619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.464909619
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3265150309
Short name T38
Test name
Test status
Simulation time 119352437658 ps
CPU time 513.1 seconds
Started Jun 05 06:24:33 PM PDT 24
Finished Jun 05 06:33:07 PM PDT 24
Peak memory 248024 kb
Host smart-3097e08e-a540-4340-a2bf-73ab69d5be86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265150309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3265150309
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1076527463
Short name T583
Test name
Test status
Simulation time 1178876690 ps
CPU time 20.59 seconds
Started Jun 05 06:24:26 PM PDT 24
Finished Jun 05 06:24:47 PM PDT 24
Peak memory 248772 kb
Host smart-bb20f945-61c1-4298-9767-2b694ac26c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10765
27463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1076527463
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.4207374822
Short name T679
Test name
Test status
Simulation time 4990522334 ps
CPU time 69.93 seconds
Started Jun 05 06:24:33 PM PDT 24
Finished Jun 05 06:25:44 PM PDT 24
Peak memory 255520 kb
Host smart-2d331b18-88d4-4d76-9cea-633517c1f617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42073
74822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.4207374822
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3552380347
Short name T697
Test name
Test status
Simulation time 399272397 ps
CPU time 27.59 seconds
Started Jun 05 06:24:33 PM PDT 24
Finished Jun 05 06:25:01 PM PDT 24
Peak memory 248780 kb
Host smart-da70a651-2830-463a-a7bb-8417c12eda0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35523
80347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3552380347
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.28049924
Short name T587
Test name
Test status
Simulation time 626874182 ps
CPU time 46.9 seconds
Started Jun 05 06:24:27 PM PDT 24
Finished Jun 05 06:25:14 PM PDT 24
Peak memory 248776 kb
Host smart-d7e6db89-285b-4fae-b832-2302b6c6e0d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28049
924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.28049924
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3260548307
Short name T403
Test name
Test status
Simulation time 7309851900 ps
CPU time 294.92 seconds
Started Jun 05 06:24:47 PM PDT 24
Finished Jun 05 06:29:42 PM PDT 24
Peak memory 257004 kb
Host smart-82df31ae-b7cb-4ce5-94c1-386d2fa0955b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260548307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3260548307
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.4291885441
Short name T353
Test name
Test status
Simulation time 148582865098 ps
CPU time 1977.21 seconds
Started Jun 05 06:25:12 PM PDT 24
Finished Jun 05 06:58:10 PM PDT 24
Peak memory 281996 kb
Host smart-67e356f1-1b65-4647-b9a0-1f3f09eb678a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291885441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.4291885441
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3285646549
Short name T608
Test name
Test status
Simulation time 4760323777 ps
CPU time 73.34 seconds
Started Jun 05 06:25:02 PM PDT 24
Finished Jun 05 06:26:16 PM PDT 24
Peak memory 256860 kb
Host smart-227ac44c-91cd-46af-a09d-532106a80792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32856
46549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3285646549
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2806141484
Short name T607
Test name
Test status
Simulation time 90709888 ps
CPU time 14.46 seconds
Started Jun 05 06:25:00 PM PDT 24
Finished Jun 05 06:25:15 PM PDT 24
Peak memory 249016 kb
Host smart-93857504-c9f5-4d5b-9497-92c9cee3bbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28061
41484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2806141484
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.451466617
Short name T695
Test name
Test status
Simulation time 43494185450 ps
CPU time 992.54 seconds
Started Jun 05 06:25:13 PM PDT 24
Finished Jun 05 06:41:46 PM PDT 24
Peak memory 273132 kb
Host smart-76ccca6e-278b-4fae-b1a6-73d44c792d9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451466617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.451466617
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.383071986
Short name T600
Test name
Test status
Simulation time 294510724488 ps
CPU time 2419.95 seconds
Started Jun 05 06:25:14 PM PDT 24
Finished Jun 05 07:05:35 PM PDT 24
Peak memory 288076 kb
Host smart-5520f1b6-ea7c-4d48-b33d-d13fadb4edc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383071986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.383071986
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2877067363
Short name T430
Test name
Test status
Simulation time 957718857 ps
CPU time 23.24 seconds
Started Jun 05 06:25:01 PM PDT 24
Finished Jun 05 06:25:24 PM PDT 24
Peak memory 255984 kb
Host smart-708dd305-85a2-448c-863b-45af4ae3a70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28770
67363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2877067363
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.4208713037
Short name T416
Test name
Test status
Simulation time 1351331534 ps
CPU time 41.9 seconds
Started Jun 05 06:25:01 PM PDT 24
Finished Jun 05 06:25:43 PM PDT 24
Peak memory 255368 kb
Host smart-3e9864aa-5b54-4b53-bdb9-417c96afa20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42087
13037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.4208713037
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3957025845
Short name T495
Test name
Test status
Simulation time 2273803285 ps
CPU time 46.22 seconds
Started Jun 05 06:25:07 PM PDT 24
Finished Jun 05 06:25:54 PM PDT 24
Peak memory 248848 kb
Host smart-173e282c-68da-4b78-addd-0c5156c2015a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39570
25845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3957025845
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1474725624
Short name T484
Test name
Test status
Simulation time 372761184 ps
CPU time 9.96 seconds
Started Jun 05 06:24:47 PM PDT 24
Finished Jun 05 06:24:57 PM PDT 24
Peak memory 248768 kb
Host smart-11dffd12-d9a1-4901-8c5e-e1fe1a643499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14747
25624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1474725624
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.559843228
Short name T53
Test name
Test status
Simulation time 49486459493 ps
CPU time 3119.43 seconds
Started Jun 05 06:25:11 PM PDT 24
Finished Jun 05 07:17:12 PM PDT 24
Peak memory 297908 kb
Host smart-965a510e-b185-4d28-b3f5-ba43351dc149
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559843228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.559843228
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3564096179
Short name T60
Test name
Test status
Simulation time 54536081152 ps
CPU time 2225.13 seconds
Started Jun 05 06:25:12 PM PDT 24
Finished Jun 05 07:02:18 PM PDT 24
Peak memory 304940 kb
Host smart-3c768610-0fe9-44fe-9e65-499efe35f396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564096179 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3564096179
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1515910891
Short name T626
Test name
Test status
Simulation time 212977440265 ps
CPU time 2018.19 seconds
Started Jun 05 06:25:26 PM PDT 24
Finished Jun 05 06:59:04 PM PDT 24
Peak memory 273396 kb
Host smart-270f5e30-8ca5-4237-9d12-5a0cb9f5233b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515910891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1515910891
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3073856197
Short name T509
Test name
Test status
Simulation time 4774597387 ps
CPU time 145.96 seconds
Started Jun 05 06:25:27 PM PDT 24
Finished Jun 05 06:27:53 PM PDT 24
Peak memory 249852 kb
Host smart-e1ae97d7-4c58-4a25-9ae1-3f00a39c053b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30738
56197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3073856197
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.4142188828
Short name T593
Test name
Test status
Simulation time 465622405 ps
CPU time 19.78 seconds
Started Jun 05 06:25:25 PM PDT 24
Finished Jun 05 06:25:45 PM PDT 24
Peak memory 248784 kb
Host smart-83873102-f9fa-4e70-b27e-199d5c9b5151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41421
88828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.4142188828
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2339964218
Short name T34
Test name
Test status
Simulation time 23330222860 ps
CPU time 1699.73 seconds
Started Jun 05 06:25:33 PM PDT 24
Finished Jun 05 06:53:53 PM PDT 24
Peak memory 272828 kb
Host smart-da2f16e0-6e09-4e71-ac6f-c86b6cfe4ec3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339964218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2339964218
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3452319291
Short name T456
Test name
Test status
Simulation time 6335936055 ps
CPU time 669.62 seconds
Started Jun 05 06:25:40 PM PDT 24
Finished Jun 05 06:36:50 PM PDT 24
Peak memory 272448 kb
Host smart-ce59a3de-697a-47bd-8c2a-15c52871df14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452319291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3452319291
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3117681418
Short name T361
Test name
Test status
Simulation time 974459863 ps
CPU time 55.03 seconds
Started Jun 05 06:25:18 PM PDT 24
Finished Jun 05 06:26:14 PM PDT 24
Peak memory 256184 kb
Host smart-d209d566-3757-446b-8f3d-7f0e362ebdd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31176
81418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3117681418
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2560969093
Short name T521
Test name
Test status
Simulation time 917745727 ps
CPU time 57.93 seconds
Started Jun 05 06:25:18 PM PDT 24
Finished Jun 05 06:26:17 PM PDT 24
Peak memory 255800 kb
Host smart-592ab9a5-bff1-47dc-9bd3-1726920594dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25609
69093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2560969093
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.845282535
Short name T656
Test name
Test status
Simulation time 1564803363 ps
CPU time 26.58 seconds
Started Jun 05 06:25:27 PM PDT 24
Finished Jun 05 06:25:54 PM PDT 24
Peak memory 255744 kb
Host smart-f351c899-46b0-496d-b436-bd729da47666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84528
2535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.845282535
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2118555960
Short name T359
Test name
Test status
Simulation time 2687271603 ps
CPU time 41.61 seconds
Started Jun 05 06:25:11 PM PDT 24
Finished Jun 05 06:25:53 PM PDT 24
Peak memory 248824 kb
Host smart-b6823ff6-8459-4293-9b17-08a88d8a7664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21185
55960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2118555960
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.69882525
Short name T48
Test name
Test status
Simulation time 20300056168 ps
CPU time 1191 seconds
Started Jun 05 06:25:40 PM PDT 24
Finished Jun 05 06:45:31 PM PDT 24
Peak memory 282496 kb
Host smart-f73ad062-b14f-4acd-ad54-05b0b11ca9ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69882525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_hand
ler_stress_all.69882525
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2548613488
Short name T107
Test name
Test status
Simulation time 179563264201 ps
CPU time 3344.74 seconds
Started Jun 05 06:25:39 PM PDT 24
Finished Jun 05 07:21:25 PM PDT 24
Peak memory 321444 kb
Host smart-0421c008-73a4-498e-9df7-b2fafc04a63c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548613488 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2548613488
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3443405465
Short name T494
Test name
Test status
Simulation time 9939280233 ps
CPU time 1179.55 seconds
Started Jun 05 06:26:02 PM PDT 24
Finished Jun 05 06:45:42 PM PDT 24
Peak memory 285852 kb
Host smart-82302f47-5dda-4372-b957-e059b037da11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443405465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3443405465
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2461013330
Short name T336
Test name
Test status
Simulation time 6827334468 ps
CPU time 255.37 seconds
Started Jun 05 06:25:54 PM PDT 24
Finished Jun 05 06:30:10 PM PDT 24
Peak memory 256148 kb
Host smart-cefa8176-d779-4179-aebd-10ea9ba754c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24610
13330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2461013330
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2242755865
Short name T463
Test name
Test status
Simulation time 2471208313 ps
CPU time 39.65 seconds
Started Jun 05 06:25:56 PM PDT 24
Finished Jun 05 06:26:37 PM PDT 24
Peak memory 248836 kb
Host smart-b943f4f7-dd23-4265-acba-d3d3139222f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22427
55865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2242755865
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2119880061
Short name T314
Test name
Test status
Simulation time 62725733649 ps
CPU time 2131.85 seconds
Started Jun 05 06:26:02 PM PDT 24
Finished Jun 05 07:01:35 PM PDT 24
Peak memory 289228 kb
Host smart-1a669341-01b5-425c-8b1c-9b6bf6255386
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119880061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2119880061
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1085264694
Short name T427
Test name
Test status
Simulation time 34107468260 ps
CPU time 1982.9 seconds
Started Jun 05 06:26:02 PM PDT 24
Finished Jun 05 06:59:05 PM PDT 24
Peak memory 289376 kb
Host smart-a310f360-77ba-4bd7-af67-0de078429060
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085264694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1085264694
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2636371094
Short name T503
Test name
Test status
Simulation time 332660358 ps
CPU time 35.76 seconds
Started Jun 05 06:25:47 PM PDT 24
Finished Jun 05 06:26:23 PM PDT 24
Peak memory 248784 kb
Host smart-00ca477b-477f-4b61-828d-f89103c7a381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26363
71094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2636371094
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3243090938
Short name T273
Test name
Test status
Simulation time 1933153851 ps
CPU time 38 seconds
Started Jun 05 06:25:46 PM PDT 24
Finished Jun 05 06:26:25 PM PDT 24
Peak memory 255600 kb
Host smart-b4c3fb4d-66f1-4cef-85f9-d98e22754f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32430
90938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3243090938
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3003260582
Short name T366
Test name
Test status
Simulation time 656558805 ps
CPU time 41.22 seconds
Started Jun 05 06:25:56 PM PDT 24
Finished Jun 05 06:26:38 PM PDT 24
Peak memory 256092 kb
Host smart-d925d0ea-9390-40c3-a782-8b8899287ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30032
60582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3003260582
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2713551182
Short name T479
Test name
Test status
Simulation time 417541232 ps
CPU time 11.84 seconds
Started Jun 05 06:25:40 PM PDT 24
Finished Jun 05 06:25:52 PM PDT 24
Peak memory 248956 kb
Host smart-4bad919a-e78e-49c1-aac6-d9733ed36468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27135
51182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2713551182
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2636071888
Short name T88
Test name
Test status
Simulation time 2052982487 ps
CPU time 186.02 seconds
Started Jun 05 06:26:16 PM PDT 24
Finished Jun 05 06:29:23 PM PDT 24
Peak memory 256960 kb
Host smart-5143137d-30a2-49fb-bacc-048da0767dbf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636071888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2636071888
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1660207249
Short name T504
Test name
Test status
Simulation time 48222105722 ps
CPU time 2828.16 seconds
Started Jun 05 06:26:36 PM PDT 24
Finished Jun 05 07:13:45 PM PDT 24
Peak memory 285764 kb
Host smart-b7220e22-8423-4bda-9c83-e77d671c8df6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660207249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1660207249
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.4111383642
Short name T414
Test name
Test status
Simulation time 226104887 ps
CPU time 13.54 seconds
Started Jun 05 06:26:28 PM PDT 24
Finished Jun 05 06:26:42 PM PDT 24
Peak memory 248840 kb
Host smart-90b39ef8-79c0-4d76-bbdf-04053f377e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41113
83642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.4111383642
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1077526526
Short name T70
Test name
Test status
Simulation time 767857074 ps
CPU time 11.2 seconds
Started Jun 05 06:26:27 PM PDT 24
Finished Jun 05 06:26:39 PM PDT 24
Peak memory 253068 kb
Host smart-f015e2a1-02e8-4e83-99ca-a57cddbcb9c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10775
26526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1077526526
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2517646693
Short name T281
Test name
Test status
Simulation time 40581693123 ps
CPU time 2686.08 seconds
Started Jun 05 06:26:34 PM PDT 24
Finished Jun 05 07:11:21 PM PDT 24
Peak memory 286912 kb
Host smart-524d91b3-0d8d-4e09-bac7-50196ad6f9fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517646693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2517646693
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3235246257
Short name T259
Test name
Test status
Simulation time 381934858022 ps
CPU time 3223.77 seconds
Started Jun 05 06:26:32 PM PDT 24
Finished Jun 05 07:20:17 PM PDT 24
Peak memory 281644 kb
Host smart-be80fc17-4e5d-4f7c-803d-061de1c0ed5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235246257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3235246257
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.116496550
Short name T606
Test name
Test status
Simulation time 45570746245 ps
CPU time 467.41 seconds
Started Jun 05 06:26:36 PM PDT 24
Finished Jun 05 06:34:24 PM PDT 24
Peak memory 256624 kb
Host smart-1c15c91d-0da0-4dbe-ac63-02f884a7bc67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116496550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.116496550
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.542729146
Short name T582
Test name
Test status
Simulation time 3015304042 ps
CPU time 44.87 seconds
Started Jun 05 06:26:26 PM PDT 24
Finished Jun 05 06:27:11 PM PDT 24
Peak memory 248860 kb
Host smart-9ddb7bb3-eb98-48a5-b668-b9298d72b9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54272
9146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.542729146
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.4293371699
Short name T472
Test name
Test status
Simulation time 2060691453 ps
CPU time 33.13 seconds
Started Jun 05 06:26:25 PM PDT 24
Finished Jun 05 06:26:59 PM PDT 24
Peak memory 248792 kb
Host smart-7ed3f885-b3f6-454b-b0bf-66726fc68e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42933
71699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.4293371699
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.587161009
Short name T20
Test name
Test status
Simulation time 63890088 ps
CPU time 5.06 seconds
Started Jun 05 06:26:30 PM PDT 24
Finished Jun 05 06:26:35 PM PDT 24
Peak memory 240584 kb
Host smart-0a32f010-d6cc-4a79-9133-f9a9aa0a98c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58716
1009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.587161009
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3405703233
Short name T572
Test name
Test status
Simulation time 158205515 ps
CPU time 17.08 seconds
Started Jun 05 06:26:27 PM PDT 24
Finished Jun 05 06:26:45 PM PDT 24
Peak memory 248724 kb
Host smart-716626e1-adee-4c85-80f3-dce4ed200714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34057
03233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3405703233
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.521765301
Short name T21
Test name
Test status
Simulation time 101036935738 ps
CPU time 1808.51 seconds
Started Jun 05 06:26:37 PM PDT 24
Finished Jun 05 06:56:46 PM PDT 24
Peak memory 289680 kb
Host smart-6ce4f885-a8f5-4df0-bf80-bb5027d4b798
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521765301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.521765301
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.408337053
Short name T13
Test name
Test status
Simulation time 23995563474 ps
CPU time 940.29 seconds
Started Jun 05 06:27:03 PM PDT 24
Finished Jun 05 06:42:44 PM PDT 24
Peak memory 269584 kb
Host smart-1c3d300d-f653-4acd-ae88-f42c7c6d1a48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408337053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.408337053
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1042732440
Short name T96
Test name
Test status
Simulation time 61228299 ps
CPU time 8.29 seconds
Started Jun 05 06:26:56 PM PDT 24
Finished Jun 05 06:27:04 PM PDT 24
Peak memory 254332 kb
Host smart-cad93904-221c-4118-b17c-5d478531ab4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10427
32440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1042732440
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2651943047
Short name T491
Test name
Test status
Simulation time 219167087 ps
CPU time 14.65 seconds
Started Jun 05 06:26:56 PM PDT 24
Finished Jun 05 06:27:11 PM PDT 24
Peak memory 254276 kb
Host smart-fc288cbe-d597-4d74-9dde-ab16747dadfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26519
43047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2651943047
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1086419296
Short name T481
Test name
Test status
Simulation time 14277311870 ps
CPU time 712.82 seconds
Started Jun 05 06:27:01 PM PDT 24
Finished Jun 05 06:38:54 PM PDT 24
Peak memory 273024 kb
Host smart-5c98a21a-f5be-4d58-b8e6-9a5f5db3a42e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086419296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1086419296
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1950733117
Short name T288
Test name
Test status
Simulation time 5821261577 ps
CPU time 220.6 seconds
Started Jun 05 06:27:00 PM PDT 24
Finished Jun 05 06:30:41 PM PDT 24
Peak memory 248380 kb
Host smart-ba09c807-cd05-43cb-82fe-2092411f36ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950733117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1950733117
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3879627210
Short name T356
Test name
Test status
Simulation time 300947839 ps
CPU time 26.93 seconds
Started Jun 05 06:26:51 PM PDT 24
Finished Jun 05 06:27:18 PM PDT 24
Peak memory 248784 kb
Host smart-e7308bf0-6498-4226-93a4-baf62767bb97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38796
27210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3879627210
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1931786196
Short name T540
Test name
Test status
Simulation time 502232647 ps
CPU time 36.07 seconds
Started Jun 05 06:26:56 PM PDT 24
Finished Jun 05 06:27:33 PM PDT 24
Peak memory 255472 kb
Host smart-9ed449c2-abc5-4a4c-8563-2eacaff94a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19317
86196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1931786196
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.714011664
Short name T454
Test name
Test status
Simulation time 1844730090 ps
CPU time 64.81 seconds
Started Jun 05 06:26:43 PM PDT 24
Finished Jun 05 06:27:48 PM PDT 24
Peak memory 248784 kb
Host smart-4996bed8-7a92-46c8-a7d7-5fe2485ab961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71401
1664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.714011664
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1844486973
Short name T248
Test name
Test status
Simulation time 147088727488 ps
CPU time 4499.25 seconds
Started Jun 05 06:27:10 PM PDT 24
Finished Jun 05 07:42:11 PM PDT 24
Peak memory 335400 kb
Host smart-e80755d0-8c40-492c-ae6d-c215620ae302
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844486973 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1844486973
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.139765237
Short name T646
Test name
Test status
Simulation time 15626433419 ps
CPU time 1562.33 seconds
Started Jun 05 06:27:16 PM PDT 24
Finished Jun 05 06:53:19 PM PDT 24
Peak memory 289324 kb
Host smart-db002e58-4631-46be-a757-36db8ce95d56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139765237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.139765237
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1205225356
Short name T365
Test name
Test status
Simulation time 3472204093 ps
CPU time 113.41 seconds
Started Jun 05 06:27:14 PM PDT 24
Finished Jun 05 06:29:08 PM PDT 24
Peak memory 248836 kb
Host smart-6e5aadad-a53a-4c2b-aede-379312197785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12052
25356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1205225356
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2025682886
Short name T489
Test name
Test status
Simulation time 1320353726 ps
CPU time 35.7 seconds
Started Jun 05 06:27:16 PM PDT 24
Finished Jun 05 06:27:52 PM PDT 24
Peak memory 248860 kb
Host smart-65faa99e-3009-463c-811e-c8a96dbd95e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20256
82886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2025682886
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1263929610
Short name T502
Test name
Test status
Simulation time 90290538671 ps
CPU time 1344.82 seconds
Started Jun 05 06:27:22 PM PDT 24
Finished Jun 05 06:49:47 PM PDT 24
Peak memory 269320 kb
Host smart-e952ca84-6fc0-48d8-94e4-41438ac81e0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263929610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1263929610
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1452858926
Short name T287
Test name
Test status
Simulation time 2483292999 ps
CPU time 100.47 seconds
Started Jun 05 06:27:25 PM PDT 24
Finished Jun 05 06:29:06 PM PDT 24
Peak memory 247896 kb
Host smart-12b489b9-2135-464d-9046-b1ff6c9c09cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452858926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1452858926
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1372017230
Short name T335
Test name
Test status
Simulation time 498819374 ps
CPU time 8.25 seconds
Started Jun 05 06:27:14 PM PDT 24
Finished Jun 05 06:27:23 PM PDT 24
Peak memory 250880 kb
Host smart-dbe80ebd-58ba-49b6-8dda-8501aa6ba4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13720
17230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1372017230
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.24848707
Short name T555
Test name
Test status
Simulation time 144501588 ps
CPU time 5.97 seconds
Started Jun 05 06:27:16 PM PDT 24
Finished Jun 05 06:27:22 PM PDT 24
Peak memory 241180 kb
Host smart-fb05cbb9-e4df-4855-ae2b-1cb58a479b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24848
707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.24848707
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2564984545
Short name T409
Test name
Test status
Simulation time 212874170 ps
CPU time 24.96 seconds
Started Jun 05 06:27:15 PM PDT 24
Finished Jun 05 06:27:40 PM PDT 24
Peak memory 255552 kb
Host smart-30b7c03e-5b52-4a3f-a45e-9da55314efdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25649
84545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2564984545
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3556426784
Short name T548
Test name
Test status
Simulation time 153352704 ps
CPU time 5.3 seconds
Started Jun 05 06:27:13 PM PDT 24
Finished Jun 05 06:27:19 PM PDT 24
Peak memory 240576 kb
Host smart-91206fe1-ca0e-4293-bf73-01b3e926c9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35564
26784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3556426784
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2237318508
Short name T52
Test name
Test status
Simulation time 69833282387 ps
CPU time 3951.74 seconds
Started Jun 05 06:27:21 PM PDT 24
Finished Jun 05 07:33:14 PM PDT 24
Peak memory 304136 kb
Host smart-c9f8383b-771e-4c83-8da6-3272dc56ff76
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237318508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2237318508
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.905731387
Short name T223
Test name
Test status
Simulation time 55833644581 ps
CPU time 919.4 seconds
Started Jun 05 06:27:24 PM PDT 24
Finished Jun 05 06:42:44 PM PDT 24
Peak memory 272776 kb
Host smart-9271e7e4-fb95-47ed-94af-8908ee585556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905731387 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.905731387
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2198337298
Short name T197
Test name
Test status
Simulation time 238334455 ps
CPU time 3.6 seconds
Started Jun 05 06:16:32 PM PDT 24
Finished Jun 05 06:16:36 PM PDT 24
Peak memory 248944 kb
Host smart-3d382216-9e7b-407e-b4de-508d74e93730
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2198337298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2198337298
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.409754750
Short name T25
Test name
Test status
Simulation time 52696998119 ps
CPU time 1293.81 seconds
Started Jun 05 06:16:30 PM PDT 24
Finished Jun 05 06:38:05 PM PDT 24
Peak memory 289260 kb
Host smart-adad8cf0-e60c-4c59-9f66-76b7dc2b86ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409754750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.409754750
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1731314485
Short name T604
Test name
Test status
Simulation time 242749782 ps
CPU time 7.7 seconds
Started Jun 05 06:16:32 PM PDT 24
Finished Jun 05 06:16:40 PM PDT 24
Peak memory 248784 kb
Host smart-f6e8c81e-c311-433e-9304-ec6af9da9fca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1731314485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1731314485
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.4001598790
Short name T591
Test name
Test status
Simulation time 508261772 ps
CPU time 45.15 seconds
Started Jun 05 06:16:30 PM PDT 24
Finished Jun 05 06:17:16 PM PDT 24
Peak memory 256808 kb
Host smart-649d6a5a-d453-4445-adea-c0371749a5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40015
98790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.4001598790
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2331571881
Short name T75
Test name
Test status
Simulation time 146445879 ps
CPU time 10.27 seconds
Started Jun 05 06:16:28 PM PDT 24
Finished Jun 05 06:16:39 PM PDT 24
Peak memory 248792 kb
Host smart-bc02bc17-1b6a-48a3-bb15-d1ff635e86ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23315
71881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2331571881
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1723975764
Short name T316
Test name
Test status
Simulation time 44793053044 ps
CPU time 1023.31 seconds
Started Jun 05 06:16:36 PM PDT 24
Finished Jun 05 06:33:40 PM PDT 24
Peak memory 272828 kb
Host smart-eaeb5292-7824-44cb-91f5-f4142cd9c96f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723975764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1723975764
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3082811428
Short name T28
Test name
Test status
Simulation time 58010805862 ps
CPU time 1269.34 seconds
Started Jun 05 06:16:33 PM PDT 24
Finished Jun 05 06:37:43 PM PDT 24
Peak memory 289248 kb
Host smart-73207a0e-ad87-4caf-914f-10b23c70940c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082811428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3082811428
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.142312528
Short name T7
Test name
Test status
Simulation time 5623473363 ps
CPU time 227.35 seconds
Started Jun 05 06:16:33 PM PDT 24
Finished Jun 05 06:20:21 PM PDT 24
Peak memory 248232 kb
Host smart-897f23b5-05f1-4592-9a13-033202bb9ace
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142312528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.142312528
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3361775901
Short name T585
Test name
Test status
Simulation time 4712997363 ps
CPU time 70.74 seconds
Started Jun 05 06:16:29 PM PDT 24
Finished Jun 05 06:17:40 PM PDT 24
Peak memory 248824 kb
Host smart-9e08dcf0-e8f4-4dbc-98a8-8718c599c1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33617
75901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3361775901
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3647362561
Short name T244
Test name
Test status
Simulation time 448271216 ps
CPU time 14.5 seconds
Started Jun 05 06:16:28 PM PDT 24
Finished Jun 05 06:16:43 PM PDT 24
Peak memory 253036 kb
Host smart-bce0b4b6-3f61-4d47-a013-d4e65989c144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36473
62561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3647362561
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.4065008836
Short name T352
Test name
Test status
Simulation time 676777170 ps
CPU time 10.69 seconds
Started Jun 05 06:16:28 PM PDT 24
Finished Jun 05 06:16:40 PM PDT 24
Peak memory 248796 kb
Host smart-2450e501-cb51-4a86-a894-9586eed873ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40650
08836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.4065008836
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2249556464
Short name T231
Test name
Test status
Simulation time 18665137616 ps
CPU time 266.48 seconds
Started Jun 05 06:16:34 PM PDT 24
Finished Jun 05 06:21:01 PM PDT 24
Peak memory 256980 kb
Host smart-7701c5ae-bb37-45b9-9fe9-732119ab72b5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249556464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2249556464
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.786408640
Short name T261
Test name
Test status
Simulation time 22974595057 ps
CPU time 2787.13 seconds
Started Jun 05 06:16:34 PM PDT 24
Finished Jun 05 07:03:02 PM PDT 24
Peak memory 305620 kb
Host smart-1c5b48b6-f548-4a18-aab5-4169ca2a1f00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786408640 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.786408640
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2180489826
Short name T501
Test name
Test status
Simulation time 13296044216 ps
CPU time 1238.34 seconds
Started Jun 05 06:27:42 PM PDT 24
Finished Jun 05 06:48:20 PM PDT 24
Peak memory 282600 kb
Host smart-7725aa98-6bc3-432d-bcbc-d2ea8ce094a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180489826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2180489826
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.4264792572
Short name T382
Test name
Test status
Simulation time 375530754 ps
CPU time 23.43 seconds
Started Jun 05 06:27:30 PM PDT 24
Finished Jun 05 06:27:54 PM PDT 24
Peak memory 256444 kb
Host smart-a888e1a8-e7c6-47fe-a8a1-6e7d92b905fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42647
92572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.4264792572
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3767295383
Short name T477
Test name
Test status
Simulation time 346987283 ps
CPU time 21.07 seconds
Started Jun 05 06:27:28 PM PDT 24
Finished Jun 05 06:27:50 PM PDT 24
Peak memory 255364 kb
Host smart-0ecb44d0-b125-400e-8481-91db9c3def13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37672
95383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3767295383
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2957550103
Short name T570
Test name
Test status
Simulation time 85267619514 ps
CPU time 2765.92 seconds
Started Jun 05 06:27:42 PM PDT 24
Finished Jun 05 07:13:49 PM PDT 24
Peak memory 289564 kb
Host smart-d7d7e74b-5410-463c-a3ec-cb56ad1387bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957550103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2957550103
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.265399298
Short name T485
Test name
Test status
Simulation time 19006144751 ps
CPU time 400.79 seconds
Started Jun 05 06:27:44 PM PDT 24
Finished Jun 05 06:34:25 PM PDT 24
Peak memory 248376 kb
Host smart-f5fdaae9-3882-450c-9682-b1488dd9606c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265399298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.265399298
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3124975621
Short name T172
Test name
Test status
Simulation time 1398211193 ps
CPU time 37.36 seconds
Started Jun 05 06:27:31 PM PDT 24
Finished Jun 05 06:28:08 PM PDT 24
Peak memory 248780 kb
Host smart-bf943f65-8080-4052-b407-aaa909025022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31249
75621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3124975621
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3302426222
Short name T91
Test name
Test status
Simulation time 160715714 ps
CPU time 11.4 seconds
Started Jun 05 06:27:29 PM PDT 24
Finished Jun 05 06:27:41 PM PDT 24
Peak memory 247464 kb
Host smart-06149e6c-53cb-4a69-ade6-f269c893cc67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33024
26222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3302426222
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2751973979
Short name T94
Test name
Test status
Simulation time 3388955411 ps
CPU time 44.7 seconds
Started Jun 05 06:27:36 PM PDT 24
Finished Jun 05 06:28:21 PM PDT 24
Peak memory 255700 kb
Host smart-841f034c-5e40-49c3-a667-e2063b5a951f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27519
73979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2751973979
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2821782019
Short name T672
Test name
Test status
Simulation time 35938391 ps
CPU time 4.87 seconds
Started Jun 05 06:27:22 PM PDT 24
Finished Jun 05 06:27:27 PM PDT 24
Peak memory 250928 kb
Host smart-3ba5536e-269e-4854-9dc1-01a3135d1a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28217
82019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2821782019
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2140958095
Short name T106
Test name
Test status
Simulation time 18397219060 ps
CPU time 1731.78 seconds
Started Jun 05 06:27:50 PM PDT 24
Finished Jun 05 06:56:42 PM PDT 24
Peak memory 289788 kb
Host smart-86f4e2d9-0440-40fe-8d85-ae2b72ef9c42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140958095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2140958095
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2946629893
Short name T516
Test name
Test status
Simulation time 47007821326 ps
CPU time 2807.13 seconds
Started Jun 05 06:27:47 PM PDT 24
Finished Jun 05 07:14:34 PM PDT 24
Peak memory 322664 kb
Host smart-ece0a3b0-d8b0-43b1-a24e-4f394b395215
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946629893 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2946629893
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2151164785
Short name T507
Test name
Test status
Simulation time 41566270778 ps
CPU time 2683.95 seconds
Started Jun 05 06:28:03 PM PDT 24
Finished Jun 05 07:12:48 PM PDT 24
Peak memory 283436 kb
Host smart-19c3077a-3c8f-4d54-98d7-3f50c5dfcb79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151164785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2151164785
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.38408487
Short name T539
Test name
Test status
Simulation time 4032202286 ps
CPU time 153.16 seconds
Started Jun 05 06:28:06 PM PDT 24
Finished Jun 05 06:30:39 PM PDT 24
Peak memory 257020 kb
Host smart-56dcf897-fb7b-44af-bfff-67f7d4ed7d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38408
487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.38408487
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1967225370
Short name T562
Test name
Test status
Simulation time 1620436220 ps
CPU time 41.09 seconds
Started Jun 05 06:27:53 PM PDT 24
Finished Jun 05 06:28:35 PM PDT 24
Peak memory 249236 kb
Host smart-9885f8b2-e83b-4068-906a-22f243bb4f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19672
25370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1967225370
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1899970002
Short name T575
Test name
Test status
Simulation time 80242722981 ps
CPU time 869.1 seconds
Started Jun 05 06:28:08 PM PDT 24
Finished Jun 05 06:42:37 PM PDT 24
Peak memory 271900 kb
Host smart-f876e0fd-7ac9-46c4-a06e-320e35ccd572
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899970002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1899970002
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3327671635
Short name T290
Test name
Test status
Simulation time 14459795432 ps
CPU time 160.48 seconds
Started Jun 05 06:28:06 PM PDT 24
Finished Jun 05 06:30:47 PM PDT 24
Peak memory 247132 kb
Host smart-20e5a6ff-67d6-4260-b462-4f202669614f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327671635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3327671635
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3648924487
Short name T490
Test name
Test status
Simulation time 431804787 ps
CPU time 21.64 seconds
Started Jun 05 06:27:48 PM PDT 24
Finished Jun 05 06:28:11 PM PDT 24
Peak memory 248780 kb
Host smart-82018086-fb8a-483f-a54c-70a92837652e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36489
24487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3648924487
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2622551209
Short name T645
Test name
Test status
Simulation time 3910923482 ps
CPU time 64.84 seconds
Started Jun 05 06:27:54 PM PDT 24
Finished Jun 05 06:29:00 PM PDT 24
Peak memory 255312 kb
Host smart-838ea71c-5dc1-4400-99ad-2f8c2655cd93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26225
51209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2622551209
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.4195009275
Short name T519
Test name
Test status
Simulation time 166713799 ps
CPU time 3.68 seconds
Started Jun 05 06:28:03 PM PDT 24
Finished Jun 05 06:28:07 PM PDT 24
Peak memory 239272 kb
Host smart-9e366277-e3aa-4e62-800f-63d45f73b8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41950
09275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4195009275
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2336251244
Short name T339
Test name
Test status
Simulation time 489878158 ps
CPU time 34.24 seconds
Started Jun 05 06:27:47 PM PDT 24
Finished Jun 05 06:28:22 PM PDT 24
Peak memory 248788 kb
Host smart-f80b9696-f2eb-49ff-a004-d41a555d29bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23362
51244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2336251244
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2255873390
Short name T648
Test name
Test status
Simulation time 41571080863 ps
CPU time 1822.97 seconds
Started Jun 05 06:28:10 PM PDT 24
Finished Jun 05 06:58:34 PM PDT 24
Peak memory 306160 kb
Host smart-6eba289a-d2c2-4e15-8add-e7b11e86d0c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255873390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2255873390
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2363335063
Short name T683
Test name
Test status
Simulation time 55712255218 ps
CPU time 984.33 seconds
Started Jun 05 06:28:08 PM PDT 24
Finished Jun 05 06:44:33 PM PDT 24
Peak memory 283176 kb
Host smart-0b96bbfc-693e-4e55-8ee4-9b1dc4bfe15f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363335063 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2363335063
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4146339703
Short name T557
Test name
Test status
Simulation time 9490616607 ps
CPU time 576.75 seconds
Started Jun 05 06:28:33 PM PDT 24
Finished Jun 05 06:38:10 PM PDT 24
Peak memory 272256 kb
Host smart-214ab40c-bb6c-482c-8783-565108f2ede0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146339703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4146339703
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3663342017
Short name T369
Test name
Test status
Simulation time 1486961603 ps
CPU time 28.24 seconds
Started Jun 05 06:28:26 PM PDT 24
Finished Jun 05 06:28:55 PM PDT 24
Peak memory 256124 kb
Host smart-11833970-f5f1-424c-ac98-864d0a75d7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36633
42017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3663342017
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1710641507
Short name T420
Test name
Test status
Simulation time 8598170225 ps
CPU time 30.74 seconds
Started Jun 05 06:28:28 PM PDT 24
Finished Jun 05 06:28:59 PM PDT 24
Peak memory 256148 kb
Host smart-84fdbc95-904f-425f-9f35-fdb3e7ee4286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17106
41507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1710641507
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1453212791
Short name T680
Test name
Test status
Simulation time 398491025658 ps
CPU time 1585.14 seconds
Started Jun 05 06:28:32 PM PDT 24
Finished Jun 05 06:54:57 PM PDT 24
Peak memory 265216 kb
Host smart-76b49b5f-b4c3-496d-8549-b92dc051e6b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453212791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1453212791
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3616780620
Short name T644
Test name
Test status
Simulation time 26063934677 ps
CPU time 1419.07 seconds
Started Jun 05 06:28:30 PM PDT 24
Finished Jun 05 06:52:10 PM PDT 24
Peak memory 272848 kb
Host smart-25a9b60a-db04-4de0-85a7-689181558f36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616780620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3616780620
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3477443680
Short name T173
Test name
Test status
Simulation time 7050329284 ps
CPU time 157.27 seconds
Started Jun 05 06:28:33 PM PDT 24
Finished Jun 05 06:31:11 PM PDT 24
Peak memory 252860 kb
Host smart-a36bef38-7a05-4c4c-8a81-dafdfdd2d9cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477443680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3477443680
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2736349439
Short name T68
Test name
Test status
Simulation time 198736329 ps
CPU time 27.31 seconds
Started Jun 05 06:28:28 PM PDT 24
Finished Jun 05 06:28:55 PM PDT 24
Peak memory 248724 kb
Host smart-edc6e4da-1c82-498b-8e94-8dcc11e1ecf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27363
49439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2736349439
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2024420109
Short name T551
Test name
Test status
Simulation time 224705443 ps
CPU time 17.75 seconds
Started Jun 05 06:28:26 PM PDT 24
Finished Jun 05 06:28:45 PM PDT 24
Peak memory 247464 kb
Host smart-64b6851f-5e31-4591-9455-d8fe745e1ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20244
20109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2024420109
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2162514266
Short name T253
Test name
Test status
Simulation time 173803181 ps
CPU time 5.05 seconds
Started Jun 05 06:28:29 PM PDT 24
Finished Jun 05 06:28:34 PM PDT 24
Peak memory 239156 kb
Host smart-80e4763f-ac1f-42e1-b709-db219824c837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21625
14266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2162514266
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2516434736
Short name T457
Test name
Test status
Simulation time 901757792 ps
CPU time 40.88 seconds
Started Jun 05 06:28:10 PM PDT 24
Finished Jun 05 06:28:51 PM PDT 24
Peak memory 248780 kb
Host smart-d8ed340a-90ef-4bd7-829f-1720e3e3ac43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25164
34736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2516434736
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2837640994
Short name T603
Test name
Test status
Simulation time 71189990757 ps
CPU time 2180.36 seconds
Started Jun 05 06:28:50 PM PDT 24
Finished Jun 05 07:05:11 PM PDT 24
Peak memory 273432 kb
Host smart-65af7e58-b034-4028-ba7f-7a4e27ec7845
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837640994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2837640994
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2996451212
Short name T349
Test name
Test status
Simulation time 2102156889 ps
CPU time 120.47 seconds
Started Jun 05 06:28:46 PM PDT 24
Finished Jun 05 06:30:47 PM PDT 24
Peak memory 248964 kb
Host smart-13b0468f-ad17-46b9-a1b6-c837a8f60cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29964
51212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2996451212
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.308523125
Short name T654
Test name
Test status
Simulation time 2263908508 ps
CPU time 70.12 seconds
Started Jun 05 06:28:38 PM PDT 24
Finished Jun 05 06:29:48 PM PDT 24
Peak memory 248760 kb
Host smart-e113ce48-ad56-4eea-8652-13273fbe1579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30852
3125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.308523125
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.112376119
Short name T312
Test name
Test status
Simulation time 68298237401 ps
CPU time 1866.41 seconds
Started Jun 05 06:28:49 PM PDT 24
Finished Jun 05 06:59:56 PM PDT 24
Peak memory 288512 kb
Host smart-26c23e92-7945-457a-b8fe-a04a7e613e55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112376119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.112376119
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3742012849
Short name T476
Test name
Test status
Simulation time 10332113987 ps
CPU time 910.96 seconds
Started Jun 05 06:28:50 PM PDT 24
Finished Jun 05 06:44:02 PM PDT 24
Peak memory 273344 kb
Host smart-5fa16220-184b-4d23-804f-6776fcdb587f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742012849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3742012849
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1955775957
Short name T296
Test name
Test status
Simulation time 30945715812 ps
CPU time 295.86 seconds
Started Jun 05 06:28:51 PM PDT 24
Finished Jun 05 06:33:47 PM PDT 24
Peak memory 247980 kb
Host smart-89b44e6c-0ecc-46fe-94b5-1000a84eb76f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955775957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1955775957
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3995869858
Short name T35
Test name
Test status
Simulation time 3977395964 ps
CPU time 24.05 seconds
Started Jun 05 06:28:40 PM PDT 24
Finished Jun 05 06:29:05 PM PDT 24
Peak memory 248836 kb
Host smart-e1eaae9b-54b7-443d-bc68-b68ec3bac098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39958
69858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3995869858
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1852428042
Short name T529
Test name
Test status
Simulation time 946771575 ps
CPU time 55.59 seconds
Started Jun 05 06:28:37 PM PDT 24
Finished Jun 05 06:29:33 PM PDT 24
Peak memory 255644 kb
Host smart-0e7e7192-ec64-45db-b702-7aa6b64a0ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18524
28042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1852428042
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3336454252
Short name T390
Test name
Test status
Simulation time 165226547 ps
CPU time 12.27 seconds
Started Jun 05 06:28:45 PM PDT 24
Finished Jun 05 06:28:58 PM PDT 24
Peak memory 253204 kb
Host smart-5231cfab-7ed3-4f42-8b9c-0b6fa710613b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33364
54252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3336454252
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2618503517
Short name T609
Test name
Test status
Simulation time 491789245 ps
CPU time 17.19 seconds
Started Jun 05 06:28:40 PM PDT 24
Finished Jun 05 06:28:58 PM PDT 24
Peak memory 248788 kb
Host smart-05f3643f-7664-46e5-bb36-67a48f7aebb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26185
03517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2618503517
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.320490932
Short name T177
Test name
Test status
Simulation time 24018116918 ps
CPU time 132.02 seconds
Started Jun 05 06:29:04 PM PDT 24
Finished Jun 05 06:31:17 PM PDT 24
Peak memory 257004 kb
Host smart-3ab56188-35fc-4839-a68b-b16c8fbc8819
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320490932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.320490932
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2775253222
Short name T474
Test name
Test status
Simulation time 42517199825 ps
CPU time 1348.96 seconds
Started Jun 05 06:29:18 PM PDT 24
Finished Jun 05 06:51:48 PM PDT 24
Peak memory 289208 kb
Host smart-af40fa7a-4e89-4b6c-b727-2c4f364bf7e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775253222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2775253222
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.107129718
Short name T488
Test name
Test status
Simulation time 11090364099 ps
CPU time 169.8 seconds
Started Jun 05 06:29:16 PM PDT 24
Finished Jun 05 06:32:06 PM PDT 24
Peak memory 249964 kb
Host smart-42bce82c-b8c1-4b5f-a8e2-f5cbeaa31936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10712
9718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.107129718
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2545783865
Short name T528
Test name
Test status
Simulation time 631101513 ps
CPU time 30.61 seconds
Started Jun 05 06:29:17 PM PDT 24
Finished Jun 05 06:29:48 PM PDT 24
Peak memory 255964 kb
Host smart-204834f7-ba0f-4a05-a70b-7f90ea46aa97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25457
83865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2545783865
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3570264789
Short name T313
Test name
Test status
Simulation time 54141320015 ps
CPU time 1777.27 seconds
Started Jun 05 06:29:18 PM PDT 24
Finished Jun 05 06:58:56 PM PDT 24
Peak memory 271468 kb
Host smart-ae19d27e-56ce-40dc-b038-052ac2980a2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570264789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3570264789
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.41897691
Short name T432
Test name
Test status
Simulation time 6137971774 ps
CPU time 778.59 seconds
Started Jun 05 06:29:14 PM PDT 24
Finished Jun 05 06:42:13 PM PDT 24
Peak memory 272876 kb
Host smart-2f9838c6-9b8c-415a-9d32-3d1f7fe28cb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41897691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.41897691
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4161385596
Short name T532
Test name
Test status
Simulation time 58930645256 ps
CPU time 482.24 seconds
Started Jun 05 06:29:16 PM PDT 24
Finished Jun 05 06:37:19 PM PDT 24
Peak memory 248228 kb
Host smart-6e14195c-7031-466d-888f-86c7240e56dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161385596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4161385596
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.791928738
Short name T450
Test name
Test status
Simulation time 404243881 ps
CPU time 14.7 seconds
Started Jun 05 06:29:10 PM PDT 24
Finished Jun 05 06:29:25 PM PDT 24
Peak memory 248804 kb
Host smart-32d0bf7f-cd36-407d-b2df-186c21d5720e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79192
8738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.791928738
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1475857975
Short name T86
Test name
Test status
Simulation time 401105075 ps
CPU time 29.49 seconds
Started Jun 05 06:29:16 PM PDT 24
Finished Jun 05 06:29:46 PM PDT 24
Peak memory 247684 kb
Host smart-0a3cb047-3eb7-4186-ad11-b88cbccc35d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14758
57975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1475857975
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1959281643
Short name T266
Test name
Test status
Simulation time 3132655966 ps
CPU time 66.23 seconds
Started Jun 05 06:29:15 PM PDT 24
Finished Jun 05 06:30:22 PM PDT 24
Peak memory 255616 kb
Host smart-ad7b6074-5d13-4868-ad32-9ef89047f29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19592
81643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1959281643
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1261245801
Short name T469
Test name
Test status
Simulation time 770228370 ps
CPU time 52.41 seconds
Started Jun 05 06:29:04 PM PDT 24
Finished Jun 05 06:29:57 PM PDT 24
Peak memory 256968 kb
Host smart-4209a106-1d1f-43b8-8b2c-b4221a3e9e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12612
45801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1261245801
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3185281054
Short name T242
Test name
Test status
Simulation time 14327526740 ps
CPU time 436.46 seconds
Started Jun 05 06:29:22 PM PDT 24
Finished Jun 05 06:36:39 PM PDT 24
Peak memory 265208 kb
Host smart-e1f834d0-a92e-43bd-8b06-eb6fa5de3051
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185281054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3185281054
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3196217513
Short name T667
Test name
Test status
Simulation time 39163578442 ps
CPU time 2846.52 seconds
Started Jun 05 06:29:31 PM PDT 24
Finished Jun 05 07:16:58 PM PDT 24
Peak memory 298296 kb
Host smart-1fc2927a-7584-4e4e-bca0-6adfbf60cbe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196217513 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3196217513
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3428262958
Short name T84
Test name
Test status
Simulation time 272817984230 ps
CPU time 2040.05 seconds
Started Jun 05 06:29:34 PM PDT 24
Finished Jun 05 07:03:35 PM PDT 24
Peak memory 284568 kb
Host smart-113298ab-4b97-4bc9-abe3-ff64985e8890
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428262958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3428262958
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3181738576
Short name T260
Test name
Test status
Simulation time 23635592466 ps
CPU time 231.26 seconds
Started Jun 05 06:29:36 PM PDT 24
Finished Jun 05 06:33:27 PM PDT 24
Peak memory 256140 kb
Host smart-1967a9d1-7ffb-4282-9941-23c8c9853427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31817
38576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3181738576
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3840523982
Short name T596
Test name
Test status
Simulation time 711720601 ps
CPU time 41.82 seconds
Started Jun 05 06:29:37 PM PDT 24
Finished Jun 05 06:30:19 PM PDT 24
Peak memory 255872 kb
Host smart-4d469faf-5022-453a-b238-63e2922fe060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38405
23982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3840523982
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.234019608
Short name T505
Test name
Test status
Simulation time 22589036554 ps
CPU time 1364.63 seconds
Started Jun 05 06:29:38 PM PDT 24
Finished Jun 05 06:52:23 PM PDT 24
Peak memory 273480 kb
Host smart-6d6f4f2f-658c-4a91-8932-45f74c837700
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234019608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.234019608
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3936357811
Short name T215
Test name
Test status
Simulation time 13055649356 ps
CPU time 478.89 seconds
Started Jun 05 06:29:37 PM PDT 24
Finished Jun 05 06:37:36 PM PDT 24
Peak memory 248248 kb
Host smart-943309c7-0026-402e-ad6e-e64c06b9f928
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936357811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3936357811
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3353160725
Short name T633
Test name
Test status
Simulation time 2932686521 ps
CPU time 49.83 seconds
Started Jun 05 06:29:36 PM PDT 24
Finished Jun 05 06:30:26 PM PDT 24
Peak memory 256000 kb
Host smart-3847ae44-0066-4822-87e2-1bc1fa61a6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33531
60725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3353160725
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3391325163
Short name T554
Test name
Test status
Simulation time 1662425267 ps
CPU time 29.94 seconds
Started Jun 05 06:29:36 PM PDT 24
Finished Jun 05 06:30:06 PM PDT 24
Peak memory 248724 kb
Host smart-d02974e9-b2bd-4807-b567-46e9d82d56a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33913
25163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3391325163
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.918873085
Short name T246
Test name
Test status
Simulation time 1276847799 ps
CPU time 20.13 seconds
Started Jun 05 06:29:37 PM PDT 24
Finished Jun 05 06:29:57 PM PDT 24
Peak memory 248784 kb
Host smart-1b676349-c3c9-4da7-960c-dbc2a5c82ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91887
3085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.918873085
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1972569416
Short name T383
Test name
Test status
Simulation time 328033443 ps
CPU time 32.41 seconds
Started Jun 05 06:29:31 PM PDT 24
Finished Jun 05 06:30:04 PM PDT 24
Peak memory 256064 kb
Host smart-15e58673-13f3-4059-b41f-02dc6be027e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19725
69416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1972569416
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3174180751
Short name T691
Test name
Test status
Simulation time 84658419492 ps
CPU time 2228.56 seconds
Started Jun 05 06:29:43 PM PDT 24
Finished Jun 05 07:06:52 PM PDT 24
Peak memory 303876 kb
Host smart-e59805c6-25a1-4f19-ad99-57a6e7912e06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174180751 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3174180751
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2956210778
Short name T601
Test name
Test status
Simulation time 56354225928 ps
CPU time 1993.22 seconds
Started Jun 05 06:29:50 PM PDT 24
Finished Jun 05 07:03:03 PM PDT 24
Peak memory 281604 kb
Host smart-8630b5d1-717e-4d75-ac9c-675a400d371e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956210778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2956210778
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2594524938
Short name T571
Test name
Test status
Simulation time 6196394343 ps
CPU time 223.53 seconds
Started Jun 05 06:29:51 PM PDT 24
Finished Jun 05 06:33:35 PM PDT 24
Peak memory 256912 kb
Host smart-85f53687-d3b9-444d-8ef5-212f48b468cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25945
24938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2594524938
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2035092437
Short name T263
Test name
Test status
Simulation time 535424903 ps
CPU time 21.45 seconds
Started Jun 05 06:29:42 PM PDT 24
Finished Jun 05 06:30:04 PM PDT 24
Peak memory 248944 kb
Host smart-b2e7e050-d7a0-429c-b8ae-560867cc81e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20350
92437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2035092437
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.619444329
Short name T676
Test name
Test status
Simulation time 52730678902 ps
CPU time 1185.7 seconds
Started Jun 05 06:29:59 PM PDT 24
Finished Jun 05 06:49:45 PM PDT 24
Peak memory 289148 kb
Host smart-e3fbe077-c05b-454a-99b5-f7993b51ea86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619444329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.619444329
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3634187084
Short name T388
Test name
Test status
Simulation time 38857618705 ps
CPU time 2580.13 seconds
Started Jun 05 06:30:03 PM PDT 24
Finished Jun 05 07:13:03 PM PDT 24
Peak memory 288212 kb
Host smart-dcc7bed4-47b9-415f-a282-28624a709fd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634187084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3634187084
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.458751682
Short name T299
Test name
Test status
Simulation time 11705950332 ps
CPU time 119.68 seconds
Started Jun 05 06:29:59 PM PDT 24
Finished Jun 05 06:32:00 PM PDT 24
Peak memory 248040 kb
Host smart-bfd68afa-71b8-485f-9ca3-a9d6c84e4044
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458751682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.458751682
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.112146280
Short name T462
Test name
Test status
Simulation time 45925909 ps
CPU time 5.05 seconds
Started Jun 05 06:29:43 PM PDT 24
Finished Jun 05 06:29:49 PM PDT 24
Peak memory 240588 kb
Host smart-d3afd412-4b5b-4106-8d30-ac1e8e89bb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11214
6280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.112146280
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.657356586
Short name T649
Test name
Test status
Simulation time 2685055205 ps
CPU time 43.97 seconds
Started Jun 05 06:29:43 PM PDT 24
Finished Jun 05 06:30:27 PM PDT 24
Peak memory 248892 kb
Host smart-bc37cf88-bbcd-4748-a433-403997ec8d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65735
6586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.657356586
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3398492252
Short name T93
Test name
Test status
Simulation time 522360750 ps
CPU time 38.26 seconds
Started Jun 05 06:29:49 PM PDT 24
Finished Jun 05 06:30:27 PM PDT 24
Peak memory 247644 kb
Host smart-17e8666d-d271-401e-89ef-5743a2a24356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33984
92252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3398492252
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3014378032
Short name T467
Test name
Test status
Simulation time 755368386 ps
CPU time 44.4 seconds
Started Jun 05 06:29:41 PM PDT 24
Finished Jun 05 06:30:26 PM PDT 24
Peak memory 256036 kb
Host smart-f967e2ea-fcaa-4226-bca2-05b0b06fc7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30143
78032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3014378032
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4031612857
Short name T37
Test name
Test status
Simulation time 1292102526 ps
CPU time 71.78 seconds
Started Jun 05 06:30:03 PM PDT 24
Finished Jun 05 06:31:15 PM PDT 24
Peak memory 255188 kb
Host smart-56c90234-5400-410b-bd0a-d9511b21b477
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031612857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4031612857
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.689601853
Short name T510
Test name
Test status
Simulation time 28144319553 ps
CPU time 1727.76 seconds
Started Jun 05 06:30:21 PM PDT 24
Finished Jun 05 06:59:09 PM PDT 24
Peak memory 286060 kb
Host smart-9f13f8da-a078-482b-b365-44e0f56b6c7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689601853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.689601853
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3214638421
Short name T617
Test name
Test status
Simulation time 3060424923 ps
CPU time 182.77 seconds
Started Jun 05 06:30:18 PM PDT 24
Finished Jun 05 06:33:21 PM PDT 24
Peak memory 257016 kb
Host smart-c8e4f0b6-221e-4d54-8376-1f045f31e635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32146
38421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3214638421
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.4149202766
Short name T410
Test name
Test status
Simulation time 3210452234 ps
CPU time 61.25 seconds
Started Jun 05 06:30:22 PM PDT 24
Finished Jun 05 06:31:24 PM PDT 24
Peak memory 256096 kb
Host smart-c898a33c-5568-40d0-bd6e-aaaca7cd935e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41492
02766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4149202766
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.252118376
Short name T306
Test name
Test status
Simulation time 25125094103 ps
CPU time 1599.71 seconds
Started Jun 05 06:30:25 PM PDT 24
Finished Jun 05 06:57:05 PM PDT 24
Peak memory 265224 kb
Host smart-6de0cfbb-f00b-4da7-96d8-498378900021
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252118376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.252118376
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2977374929
Short name T524
Test name
Test status
Simulation time 47951874564 ps
CPU time 1799.22 seconds
Started Jun 05 06:30:25 PM PDT 24
Finished Jun 05 07:00:25 PM PDT 24
Peak memory 283572 kb
Host smart-120e3cb9-8535-4495-bc1b-523a0e027e9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977374929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2977374929
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.501803790
Short name T298
Test name
Test status
Simulation time 12435833421 ps
CPU time 514.33 seconds
Started Jun 05 06:30:23 PM PDT 24
Finished Jun 05 06:38:58 PM PDT 24
Peak memory 248208 kb
Host smart-fac438b8-e297-4719-9f3c-d516eaba082a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501803790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.501803790
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1439774233
Short name T101
Test name
Test status
Simulation time 1441019952 ps
CPU time 22.05 seconds
Started Jun 05 06:30:12 PM PDT 24
Finished Jun 05 06:30:35 PM PDT 24
Peak memory 255996 kb
Host smart-aae289dc-54f6-4069-acc1-ae47b749cbbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14397
74233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1439774233
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2268790551
Short name T262
Test name
Test status
Simulation time 1216674340 ps
CPU time 39.49 seconds
Started Jun 05 06:30:13 PM PDT 24
Finished Jun 05 06:30:53 PM PDT 24
Peak memory 255588 kb
Host smart-47f0071a-ce15-411a-9866-968c7095cefd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22687
90551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2268790551
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2457018154
Short name T687
Test name
Test status
Simulation time 238787120 ps
CPU time 13.97 seconds
Started Jun 05 06:30:19 PM PDT 24
Finished Jun 05 06:30:33 PM PDT 24
Peak memory 248804 kb
Host smart-4593d11f-80e4-4686-9cc9-0323024a3f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24570
18154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2457018154
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1751904351
Short name T441
Test name
Test status
Simulation time 163212624 ps
CPU time 7.58 seconds
Started Jun 05 06:30:12 PM PDT 24
Finished Jun 05 06:30:20 PM PDT 24
Peak memory 254232 kb
Host smart-264bc33a-f395-4f39-8a78-6f7a4c6f8251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17519
04351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1751904351
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1321243087
Short name T550
Test name
Test status
Simulation time 11349664128 ps
CPU time 1030.36 seconds
Started Jun 05 06:30:24 PM PDT 24
Finished Jun 05 06:47:35 PM PDT 24
Peak memory 284716 kb
Host smart-d8082ae9-ea55-4b8d-b394-baf5ce904d2f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321243087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1321243087
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.254199782
Short name T220
Test name
Test status
Simulation time 40282189185 ps
CPU time 2274.82 seconds
Started Jun 05 06:30:47 PM PDT 24
Finished Jun 05 07:08:43 PM PDT 24
Peak memory 281604 kb
Host smart-0aac3c02-0be3-4f78-8bc7-416434ebad1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254199782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.254199782
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1173207179
Short name T638
Test name
Test status
Simulation time 840114502 ps
CPU time 32.06 seconds
Started Jun 05 06:30:37 PM PDT 24
Finished Jun 05 06:31:10 PM PDT 24
Peak memory 256816 kb
Host smart-4c9b6cde-f7b1-4ccf-8ec5-945f6ec3e713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11732
07179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1173207179
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2104509608
Short name T497
Test name
Test status
Simulation time 380209869 ps
CPU time 11.05 seconds
Started Jun 05 06:30:37 PM PDT 24
Finished Jun 05 06:30:49 PM PDT 24
Peak memory 248880 kb
Host smart-cba4f627-ef16-4448-b7ba-8c2fc683c2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21045
09608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2104509608
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.30862415
Short name T413
Test name
Test status
Simulation time 17677622698 ps
CPU time 846.57 seconds
Started Jun 05 06:30:45 PM PDT 24
Finished Jun 05 06:44:52 PM PDT 24
Peak memory 269396 kb
Host smart-8b59437f-0f6f-45f9-bc65-f1232df43d7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30862415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.30862415
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1264307101
Short name T565
Test name
Test status
Simulation time 393366760105 ps
CPU time 1856.36 seconds
Started Jun 05 06:30:45 PM PDT 24
Finished Jun 05 07:01:42 PM PDT 24
Peak memory 281644 kb
Host smart-d6f49338-c743-4ab7-8c45-b6bb3a7bcc8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264307101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1264307101
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1574073108
Short name T674
Test name
Test status
Simulation time 12293308997 ps
CPU time 222.87 seconds
Started Jun 05 06:30:47 PM PDT 24
Finished Jun 05 06:34:30 PM PDT 24
Peak memory 248208 kb
Host smart-584ec778-5784-43a4-be4a-7d2bcb145cc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574073108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1574073108
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1525036412
Short name T473
Test name
Test status
Simulation time 100251578 ps
CPU time 8.53 seconds
Started Jun 05 06:30:24 PM PDT 24
Finished Jun 05 06:30:33 PM PDT 24
Peak memory 251416 kb
Host smart-8ec1e43b-12fc-4649-950c-3effec137ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15250
36412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1525036412
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1660814181
Short name T341
Test name
Test status
Simulation time 564074281 ps
CPU time 21.44 seconds
Started Jun 05 06:30:38 PM PDT 24
Finished Jun 05 06:31:00 PM PDT 24
Peak memory 249296 kb
Host smart-289a84bd-65dc-4298-93f6-153ec63219e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16608
14181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1660814181
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3978365534
Short name T563
Test name
Test status
Simulation time 10866713422 ps
CPU time 54.11 seconds
Started Jun 05 06:30:48 PM PDT 24
Finished Jun 05 06:31:42 PM PDT 24
Peak memory 257136 kb
Host smart-a08d1d53-8946-4d8b-a704-c02f44332f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39783
65534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3978365534
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1631027500
Short name T439
Test name
Test status
Simulation time 1570264336 ps
CPU time 60.78 seconds
Started Jun 05 06:30:23 PM PDT 24
Finished Jun 05 06:31:24 PM PDT 24
Peak memory 248980 kb
Host smart-017d7540-ca84-43ba-8afa-767e8c34c12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16310
27500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1631027500
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1041722439
Short name T636
Test name
Test status
Simulation time 33129924636 ps
CPU time 2005.73 seconds
Started Jun 05 06:30:52 PM PDT 24
Finished Jun 05 07:04:19 PM PDT 24
Peak memory 287476 kb
Host smart-6e19532b-b959-4d7e-bb85-ac0804945e0d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041722439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1041722439
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.520292535
Short name T274
Test name
Test status
Simulation time 89548055019 ps
CPU time 2834.11 seconds
Started Jun 05 06:31:07 PM PDT 24
Finished Jun 05 07:18:21 PM PDT 24
Peak memory 283816 kb
Host smart-741fd4d5-62c7-4025-b817-5108eedf453f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520292535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.520292535
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1934355108
Short name T384
Test name
Test status
Simulation time 2510512053 ps
CPU time 89.02 seconds
Started Jun 05 06:31:06 PM PDT 24
Finished Jun 05 06:32:35 PM PDT 24
Peak memory 256692 kb
Host smart-8a07bc51-162c-4c6f-ae0e-95dc3e723db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19343
55108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1934355108
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3569972988
Short name T622
Test name
Test status
Simulation time 49537870 ps
CPU time 3.47 seconds
Started Jun 05 06:31:06 PM PDT 24
Finished Jun 05 06:31:10 PM PDT 24
Peak memory 240572 kb
Host smart-f85193d2-68e7-4da8-b3d6-a815f0a8f94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35699
72988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3569972988
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2168938973
Short name T279
Test name
Test status
Simulation time 43224254858 ps
CPU time 2646.81 seconds
Started Jun 05 06:31:14 PM PDT 24
Finished Jun 05 07:15:22 PM PDT 24
Peak memory 289240 kb
Host smart-0911ef26-c52f-4ab8-a93c-f26180e70b97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168938973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2168938973
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.6848264
Short name T14
Test name
Test status
Simulation time 38597208934 ps
CPU time 2764.8 seconds
Started Jun 05 06:31:12 PM PDT 24
Finished Jun 05 07:17:18 PM PDT 24
Peak memory 289788 kb
Host smart-7c33b78d-e004-446a-9273-16ddebc0b8f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6848264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.6848264
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3419062625
Short name T291
Test name
Test status
Simulation time 14248615024 ps
CPU time 316.79 seconds
Started Jun 05 06:31:14 PM PDT 24
Finished Jun 05 06:36:31 PM PDT 24
Peak memory 248216 kb
Host smart-68c42499-9ba4-4a5d-b1f1-0bc6ecb19782
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419062625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3419062625
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.4291938344
Short name T176
Test name
Test status
Simulation time 307552091 ps
CPU time 30.47 seconds
Started Jun 05 06:30:58 PM PDT 24
Finished Jun 05 06:31:29 PM PDT 24
Peak memory 255972 kb
Host smart-91d76ae7-4e08-4436-a53a-b56d72636392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42919
38344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.4291938344
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3386324285
Short name T56
Test name
Test status
Simulation time 2374542993 ps
CPU time 37.65 seconds
Started Jun 05 06:31:08 PM PDT 24
Finished Jun 05 06:31:46 PM PDT 24
Peak memory 248928 kb
Host smart-958f4d13-e4a1-43c9-ba16-6ebf6660e7a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33863
24285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3386324285
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1522035608
Short name T77
Test name
Test status
Simulation time 903075163 ps
CPU time 13.67 seconds
Started Jun 05 06:31:06 PM PDT 24
Finished Jun 05 06:31:20 PM PDT 24
Peak memory 247364 kb
Host smart-321d0f74-103a-44b2-908c-64a5caca65b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15220
35608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1522035608
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1543354490
Short name T530
Test name
Test status
Simulation time 1186801375 ps
CPU time 19.68 seconds
Started Jun 05 06:30:58 PM PDT 24
Finished Jun 05 06:31:18 PM PDT 24
Peak memory 248780 kb
Host smart-83344e1b-c59c-43ed-b0a3-9370ce8b2c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15433
54490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1543354490
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3494417469
Short name T74
Test name
Test status
Simulation time 44260890938 ps
CPU time 929.46 seconds
Started Jun 05 06:31:18 PM PDT 24
Finished Jun 05 06:46:47 PM PDT 24
Peak memory 289384 kb
Host smart-0d6a0b26-5076-4b77-b688-6d2baab082d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494417469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3494417469
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2885137127
Short name T171
Test name
Test status
Simulation time 56172919806 ps
CPU time 3062.96 seconds
Started Jun 05 06:31:19 PM PDT 24
Finished Jun 05 07:22:23 PM PDT 24
Peak memory 322036 kb
Host smart-fe12c997-b002-4ce3-84d6-3cd7bc0cddf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885137127 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2885137127
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1505392159
Short name T194
Test name
Test status
Simulation time 90548166 ps
CPU time 2.96 seconds
Started Jun 05 06:16:46 PM PDT 24
Finished Jun 05 06:16:50 PM PDT 24
Peak memory 248976 kb
Host smart-502cd12a-c939-45bb-91cb-194cfed348a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1505392159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1505392159
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.25878552
Short name T265
Test name
Test status
Simulation time 10140530029 ps
CPU time 1156.42 seconds
Started Jun 05 06:16:43 PM PDT 24
Finished Jun 05 06:36:00 PM PDT 24
Peak memory 268532 kb
Host smart-c6838376-2af6-4987-a231-fcffb087f75e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25878552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.25878552
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2233555451
Short name T367
Test name
Test status
Simulation time 868329551 ps
CPU time 9.17 seconds
Started Jun 05 06:16:47 PM PDT 24
Finished Jun 05 06:16:57 PM PDT 24
Peak memory 240600 kb
Host smart-9ae2271a-55ca-4eb6-bf8d-2c32d4156c22
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2233555451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2233555451
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3468121811
Short name T700
Test name
Test status
Simulation time 20851633118 ps
CPU time 311.21 seconds
Started Jun 05 06:16:40 PM PDT 24
Finished Jun 05 06:21:52 PM PDT 24
Peak memory 250888 kb
Host smart-48a45ef0-2b6c-409a-b126-8aa119178047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34681
21811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3468121811
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3057975501
Short name T446
Test name
Test status
Simulation time 195170287 ps
CPU time 22.39 seconds
Started Jun 05 06:16:42 PM PDT 24
Finished Jun 05 06:17:05 PM PDT 24
Peak memory 249108 kb
Host smart-9776f8d5-c06c-4c53-99a4-527c6e12f27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30579
75501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3057975501
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2981117171
Short name T315
Test name
Test status
Simulation time 404138074647 ps
CPU time 1964.58 seconds
Started Jun 05 06:16:48 PM PDT 24
Finished Jun 05 06:49:33 PM PDT 24
Peak memory 284712 kb
Host smart-a9d2bff3-32d7-435f-9625-9e14dc0382d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981117171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2981117171
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1982309213
Short name T483
Test name
Test status
Simulation time 95847949554 ps
CPU time 2971.11 seconds
Started Jun 05 06:16:47 PM PDT 24
Finished Jun 05 07:06:19 PM PDT 24
Peak memory 285496 kb
Host smart-4142d09b-cf60-4c5a-b46c-9ba7c523e9ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982309213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1982309213
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2338196344
Short name T574
Test name
Test status
Simulation time 4729356866 ps
CPU time 184.2 seconds
Started Jun 05 06:16:47 PM PDT 24
Finished Jun 05 06:19:52 PM PDT 24
Peak memory 254268 kb
Host smart-5b2d6e38-32f6-4313-9ef2-4bc274e815e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338196344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2338196344
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.906582833
Short name T688
Test name
Test status
Simulation time 534070547 ps
CPU time 28.98 seconds
Started Jun 05 06:16:42 PM PDT 24
Finished Jun 05 06:17:11 PM PDT 24
Peak memory 248780 kb
Host smart-834bc8ca-ea0e-4d90-bcf0-b001fa2a3f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90658
2833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.906582833
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3480854549
Short name T664
Test name
Test status
Simulation time 177790556 ps
CPU time 12.01 seconds
Started Jun 05 06:16:41 PM PDT 24
Finished Jun 05 06:16:53 PM PDT 24
Peak memory 249204 kb
Host smart-9dccceaa-ad9e-4517-8d86-1b0a44089b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34808
54549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3480854549
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2286223265
Short name T421
Test name
Test status
Simulation time 261147366 ps
CPU time 29.2 seconds
Started Jun 05 06:16:42 PM PDT 24
Finished Jun 05 06:17:12 PM PDT 24
Peak memory 248784 kb
Host smart-e2b14fa6-3ab6-479e-a807-0a558b443c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
23265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2286223265
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2094262694
Short name T97
Test name
Test status
Simulation time 484243058 ps
CPU time 12.63 seconds
Started Jun 05 06:16:34 PM PDT 24
Finished Jun 05 06:16:48 PM PDT 24
Peak memory 248784 kb
Host smart-df0982a2-7397-4263-b7bc-466e58ac9a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20942
62694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2094262694
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3677907469
Short name T232
Test name
Test status
Simulation time 177059285701 ps
CPU time 1722.68 seconds
Started Jun 05 06:16:46 PM PDT 24
Finished Jun 05 06:45:29 PM PDT 24
Peak memory 289112 kb
Host smart-6f49dacd-26c9-437f-ad97-532f64b54c92
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677907469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3677907469
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3846699151
Short name T193
Test name
Test status
Simulation time 14722061 ps
CPU time 2.19 seconds
Started Jun 05 06:16:58 PM PDT 24
Finished Jun 05 06:17:01 PM PDT 24
Peak memory 248928 kb
Host smart-af7cfc52-18ea-46a6-984f-fae91ab1b5a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3846699151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3846699151
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1074256216
Short name T444
Test name
Test status
Simulation time 79665501611 ps
CPU time 2316.79 seconds
Started Jun 05 06:17:00 PM PDT 24
Finished Jun 05 06:55:38 PM PDT 24
Peak memory 288576 kb
Host smart-f854c757-d24d-4132-b0b7-99e50de75999
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074256216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1074256216
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3887555669
Short name T214
Test name
Test status
Simulation time 1896926028 ps
CPU time 13.32 seconds
Started Jun 05 06:16:58 PM PDT 24
Finished Jun 05 06:17:12 PM PDT 24
Peak memory 248812 kb
Host smart-643149ca-ee3a-4397-87aa-e367a79957f9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3887555669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3887555669
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2127586240
Short name T499
Test name
Test status
Simulation time 3864379816 ps
CPU time 232.02 seconds
Started Jun 05 06:16:51 PM PDT 24
Finished Jun 05 06:20:43 PM PDT 24
Peak memory 256996 kb
Host smart-c7b61696-be73-4cdb-a6f3-1f6cac9ab1cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21275
86240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2127586240
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3447871209
Short name T65
Test name
Test status
Simulation time 3157436362 ps
CPU time 24.7 seconds
Started Jun 05 06:16:52 PM PDT 24
Finished Jun 05 06:17:17 PM PDT 24
Peak memory 256004 kb
Host smart-87f675c6-a50f-4b9f-9472-a53e66758821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34478
71209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3447871209
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2605788958
Short name T320
Test name
Test status
Simulation time 19540376466 ps
CPU time 1395.96 seconds
Started Jun 05 06:16:59 PM PDT 24
Finished Jun 05 06:40:15 PM PDT 24
Peak memory 272452 kb
Host smart-661b7af2-bf01-455f-87e6-224c876fe4e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605788958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2605788958
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3148606347
Short name T268
Test name
Test status
Simulation time 45012593336 ps
CPU time 2620.48 seconds
Started Jun 05 06:17:00 PM PDT 24
Finished Jun 05 07:00:41 PM PDT 24
Peak memory 289188 kb
Host smart-cc8b2de3-8192-4764-b907-24a8f64fd590
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148606347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3148606347
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.973571125
Short name T625
Test name
Test status
Simulation time 3958235295 ps
CPU time 165.84 seconds
Started Jun 05 06:16:59 PM PDT 24
Finished Jun 05 06:19:45 PM PDT 24
Peak memory 247136 kb
Host smart-11ca4ff3-c97f-44bc-80aa-c34a1295d632
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973571125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.973571125
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3658792394
Short name T651
Test name
Test status
Simulation time 1714906765 ps
CPU time 53.71 seconds
Started Jun 05 06:16:46 PM PDT 24
Finished Jun 05 06:17:40 PM PDT 24
Peak memory 248944 kb
Host smart-fbec3e8f-74c0-4967-ab89-24d84f06aabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36587
92394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3658792394
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1984529490
Short name T658
Test name
Test status
Simulation time 2528011645 ps
CPU time 41.38 seconds
Started Jun 05 06:16:54 PM PDT 24
Finished Jun 05 06:17:36 PM PDT 24
Peak memory 255668 kb
Host smart-78ffd57c-62f0-4944-b7ef-6dc0ce111951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19845
29490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1984529490
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3165509522
Short name T677
Test name
Test status
Simulation time 389276728 ps
CPU time 12.87 seconds
Started Jun 05 06:16:54 PM PDT 24
Finished Jun 05 06:17:08 PM PDT 24
Peak memory 255792 kb
Host smart-0ebc89f2-ade8-465e-9b9a-f7e83e9268e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31655
09522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3165509522
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1816673399
Short name T586
Test name
Test status
Simulation time 521403863 ps
CPU time 31.98 seconds
Started Jun 05 06:16:46 PM PDT 24
Finished Jun 05 06:17:19 PM PDT 24
Peak memory 256048 kb
Host smart-03950399-a0de-4c8f-a24b-b5147d90ecd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18166
73399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1816673399
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1127913567
Short name T689
Test name
Test status
Simulation time 46045222436 ps
CPU time 765.46 seconds
Started Jun 05 06:16:59 PM PDT 24
Finished Jun 05 06:29:45 PM PDT 24
Peak memory 273316 kb
Host smart-09eebad5-7b7c-4938-b345-01438a54b5cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127913567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1127913567
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2483026616
Short name T192
Test name
Test status
Simulation time 13882563 ps
CPU time 2.53 seconds
Started Jun 05 06:17:17 PM PDT 24
Finished Jun 05 06:17:20 PM PDT 24
Peak memory 248968 kb
Host smart-221656b5-7ff6-44db-8787-3518a0dd9cd1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2483026616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2483026616
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2666147592
Short name T385
Test name
Test status
Simulation time 84189324495 ps
CPU time 1956.95 seconds
Started Jun 05 06:17:07 PM PDT 24
Finished Jun 05 06:49:44 PM PDT 24
Peak memory 281624 kb
Host smart-42197ad7-9762-49a4-862f-bf422be00733
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666147592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2666147592
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1665469293
Short name T328
Test name
Test status
Simulation time 272544200 ps
CPU time 14.32 seconds
Started Jun 05 06:17:13 PM PDT 24
Finished Jun 05 06:17:28 PM PDT 24
Peak memory 248796 kb
Host smart-cfe99e12-0b45-4e15-a888-343308ecff81
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1665469293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1665469293
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.5397399
Short name T333
Test name
Test status
Simulation time 1241040976 ps
CPU time 61.61 seconds
Started Jun 05 06:17:06 PM PDT 24
Finished Jun 05 06:18:07 PM PDT 24
Peak memory 256960 kb
Host smart-f82d8527-784f-4b46-be22-a0257e3abd25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53973
99 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.5397399
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.552975194
Short name T443
Test name
Test status
Simulation time 771267617 ps
CPU time 49.53 seconds
Started Jun 05 06:17:06 PM PDT 24
Finished Jun 05 06:17:56 PM PDT 24
Peak memory 256216 kb
Host smart-ef43646c-8790-4190-810c-588a747a40b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55297
5194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.552975194
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4215043241
Short name T318
Test name
Test status
Simulation time 10197242753 ps
CPU time 978.37 seconds
Started Jun 05 06:17:13 PM PDT 24
Finished Jun 05 06:33:32 PM PDT 24
Peak memory 271580 kb
Host smart-53d659ab-86cf-4614-96db-3b1be1c1f007
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215043241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4215043241
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.4120381048
Short name T429
Test name
Test status
Simulation time 249660525491 ps
CPU time 1492.81 seconds
Started Jun 05 06:17:15 PM PDT 24
Finished Jun 05 06:42:08 PM PDT 24
Peak memory 273416 kb
Host smart-d7cdf03d-8ba3-465a-8c5a-9e27470fcbb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120381048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.4120381048
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3091742113
Short name T22
Test name
Test status
Simulation time 216251380 ps
CPU time 24.44 seconds
Started Jun 05 06:17:06 PM PDT 24
Finished Jun 05 06:17:31 PM PDT 24
Peak memory 248800 kb
Host smart-eece75c9-d0c1-412b-bd8b-45a3b80cf421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30917
42113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3091742113
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.247647637
Short name T55
Test name
Test status
Simulation time 314803048 ps
CPU time 21.46 seconds
Started Jun 05 06:17:07 PM PDT 24
Finished Jun 05 06:17:29 PM PDT 24
Peak memory 254092 kb
Host smart-0daa7f48-eb15-421e-b997-0637589d0330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24764
7637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.247647637
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.883279552
Short name T81
Test name
Test status
Simulation time 2053533365 ps
CPU time 35.73 seconds
Started Jun 05 06:17:06 PM PDT 24
Finished Jun 05 06:17:43 PM PDT 24
Peak memory 248780 kb
Host smart-73a71fb0-32ec-4345-aac9-1f6f9991a2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88327
9552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.883279552
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.4027902805
Short name T660
Test name
Test status
Simulation time 3318761472 ps
CPU time 51.66 seconds
Started Jun 05 06:17:06 PM PDT 24
Finished Jun 05 06:17:58 PM PDT 24
Peak memory 256088 kb
Host smart-4fb2383c-867a-4fdc-8ba4-26dad36aea70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40279
02805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.4027902805
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3014152355
Short name T327
Test name
Test status
Simulation time 119893518870 ps
CPU time 1901.87 seconds
Started Jun 05 06:17:21 PM PDT 24
Finished Jun 05 06:49:03 PM PDT 24
Peak memory 284836 kb
Host smart-5217bc29-ef5a-4988-9546-7b19b0d96bcb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014152355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3014152355
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3265445896
Short name T196
Test name
Test status
Simulation time 13944632 ps
CPU time 2.84 seconds
Started Jun 05 06:17:28 PM PDT 24
Finished Jun 05 06:17:31 PM PDT 24
Peak memory 248944 kb
Host smart-bbbab300-ac19-4e23-94da-29730cd31411
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3265445896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3265445896
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2098346592
Short name T423
Test name
Test status
Simulation time 70156932603 ps
CPU time 2212.27 seconds
Started Jun 05 06:17:21 PM PDT 24
Finished Jun 05 06:54:13 PM PDT 24
Peak memory 281780 kb
Host smart-693d7ac6-1a1b-4661-94ad-1fbcb3ee37f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098346592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2098346592
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1598545671
Short name T669
Test name
Test status
Simulation time 1489092316 ps
CPU time 24.16 seconds
Started Jun 05 06:17:32 PM PDT 24
Finished Jun 05 06:17:56 PM PDT 24
Peak memory 248804 kb
Host smart-e1027060-dbf6-4490-b91c-d87e7a897576
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1598545671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1598545671
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3209535353
Short name T415
Test name
Test status
Simulation time 1799154660 ps
CPU time 97.88 seconds
Started Jun 05 06:17:19 PM PDT 24
Finished Jun 05 06:18:58 PM PDT 24
Peak memory 256968 kb
Host smart-60e61c04-9b8e-471c-998a-f8724051ccba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32095
35353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3209535353
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2190355183
Short name T470
Test name
Test status
Simulation time 337276176 ps
CPU time 20.93 seconds
Started Jun 05 06:17:23 PM PDT 24
Finished Jun 05 06:17:45 PM PDT 24
Peak memory 255556 kb
Host smart-d7e7aa58-0d59-4320-a414-fde481c129ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21903
55183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2190355183
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.4100047186
Short name T321
Test name
Test status
Simulation time 216408199440 ps
CPU time 1399.72 seconds
Started Jun 05 06:17:32 PM PDT 24
Finished Jun 05 06:40:52 PM PDT 24
Peak memory 267332 kb
Host smart-616b1838-0672-41aa-a880-c9ad3c0ff7c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100047186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.4100047186
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.4034965554
Short name T360
Test name
Test status
Simulation time 11375725383 ps
CPU time 1071.07 seconds
Started Jun 05 06:17:30 PM PDT 24
Finished Jun 05 06:35:21 PM PDT 24
Peak memory 273020 kb
Host smart-88547b26-40a5-438d-8a62-e818a008adc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034965554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.4034965554
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3506305782
Short name T684
Test name
Test status
Simulation time 7114192953 ps
CPU time 297.3 seconds
Started Jun 05 06:17:19 PM PDT 24
Finished Jun 05 06:22:17 PM PDT 24
Peak memory 248004 kb
Host smart-9753b48d-35a4-40bc-89c2-4508e99b299c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506305782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3506305782
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3218119494
Short name T544
Test name
Test status
Simulation time 229263461 ps
CPU time 24.81 seconds
Started Jun 05 06:17:19 PM PDT 24
Finished Jun 05 06:17:44 PM PDT 24
Peak memory 248792 kb
Host smart-4101338e-0257-4c24-b36c-31235be350a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32181
19494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3218119494
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3024048324
Short name T637
Test name
Test status
Simulation time 1195005242 ps
CPU time 39.14 seconds
Started Jun 05 06:17:24 PM PDT 24
Finished Jun 05 06:18:03 PM PDT 24
Peak memory 255284 kb
Host smart-256d9d24-3763-4f53-ab29-ba8f93ffc53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30240
48324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3024048324
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.4195023861
Short name T422
Test name
Test status
Simulation time 7030028119 ps
CPU time 44.19 seconds
Started Jun 05 06:17:20 PM PDT 24
Finished Jun 05 06:18:05 PM PDT 24
Peak memory 248836 kb
Host smart-ee6a2aca-c796-4b7c-9d78-39ada7b98966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41950
23861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.4195023861
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2240158887
Short name T364
Test name
Test status
Simulation time 1713124842 ps
CPU time 36.8 seconds
Started Jun 05 06:17:19 PM PDT 24
Finished Jun 05 06:17:57 PM PDT 24
Peak memory 248800 kb
Host smart-e9e62bb2-8585-4520-bb62-49be9fb2b442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22401
58887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2240158887
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.4258673683
Short name T338
Test name
Test status
Simulation time 828120294 ps
CPU time 41.62 seconds
Started Jun 05 06:17:30 PM PDT 24
Finished Jun 05 06:18:12 PM PDT 24
Peak memory 248052 kb
Host smart-a46ac201-5e2e-433b-9ab6-07c35cb45e7b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258673683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.4258673683
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1367376146
Short name T189
Test name
Test status
Simulation time 65502770 ps
CPU time 3.35 seconds
Started Jun 05 06:17:47 PM PDT 24
Finished Jun 05 06:17:51 PM PDT 24
Peak memory 248936 kb
Host smart-97422fd2-582f-40ae-98bf-5d764f854838
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1367376146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1367376146
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3792814057
Short name T682
Test name
Test status
Simulation time 9658181111 ps
CPU time 967.55 seconds
Started Jun 05 06:17:35 PM PDT 24
Finished Jun 05 06:33:44 PM PDT 24
Peak memory 272816 kb
Host smart-d6eb00a4-dd65-4044-aedf-eafd12338da6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792814057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3792814057
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3531465694
Short name T458
Test name
Test status
Simulation time 1180014162 ps
CPU time 20.79 seconds
Started Jun 05 06:17:46 PM PDT 24
Finished Jun 05 06:18:07 PM PDT 24
Peak memory 248788 kb
Host smart-c0ee3bb6-2ad2-4e55-8f0c-54ab6b5c9c8b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3531465694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3531465694
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.587852754
Short name T397
Test name
Test status
Simulation time 15053163403 ps
CPU time 190.84 seconds
Started Jun 05 06:17:35 PM PDT 24
Finished Jun 05 06:20:46 PM PDT 24
Peak memory 257032 kb
Host smart-10627b74-6cea-4e1a-bc36-a42e90de328b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58785
2754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.587852754
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1711102917
Short name T693
Test name
Test status
Simulation time 208767873 ps
CPU time 14.47 seconds
Started Jun 05 06:17:35 PM PDT 24
Finished Jun 05 06:17:50 PM PDT 24
Peak memory 248784 kb
Host smart-4e5fc57b-ffb5-49eb-8ed5-2c3f0cc2bdd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17111
02917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1711102917
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.605296314
Short name T482
Test name
Test status
Simulation time 37765558118 ps
CPU time 2477.13 seconds
Started Jun 05 06:17:45 PM PDT 24
Finished Jun 05 06:59:03 PM PDT 24
Peak memory 288868 kb
Host smart-6d28b486-5826-4a5e-8772-e5e625a8f920
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605296314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.605296314
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2679059327
Short name T6
Test name
Test status
Simulation time 5550811734 ps
CPU time 107.52 seconds
Started Jun 05 06:17:37 PM PDT 24
Finished Jun 05 06:19:25 PM PDT 24
Peak memory 248040 kb
Host smart-d23ba2b7-c93b-40f6-ad96-a19b0df29156
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679059327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2679059327
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.891728204
Short name T576
Test name
Test status
Simulation time 718041555 ps
CPU time 47.32 seconds
Started Jun 05 06:17:34 PM PDT 24
Finished Jun 05 06:18:22 PM PDT 24
Peak memory 255932 kb
Host smart-a059c49a-3866-45e5-ae95-c2109052bb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89172
8204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.891728204
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2836941555
Short name T612
Test name
Test status
Simulation time 349753499 ps
CPU time 23.24 seconds
Started Jun 05 06:17:36 PM PDT 24
Finished Jun 05 06:18:00 PM PDT 24
Peak memory 256048 kb
Host smart-7e27bc0c-4949-47c7-80ed-86a53388a45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28369
41555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2836941555
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1902198026
Short name T584
Test name
Test status
Simulation time 4304431634 ps
CPU time 24.55 seconds
Started Jun 05 06:17:36 PM PDT 24
Finished Jun 05 06:18:01 PM PDT 24
Peak memory 247384 kb
Host smart-6a6a0114-f645-4e64-94a9-99ab72b7ca52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19021
98026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1902198026
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2185101450
Short name T561
Test name
Test status
Simulation time 696962476 ps
CPU time 43.8 seconds
Started Jun 05 06:17:35 PM PDT 24
Finished Jun 05 06:18:20 PM PDT 24
Peak memory 256092 kb
Host smart-b9b31baa-b086-48a8-8537-0dc263764856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21851
01450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2185101450
Directory /workspace/9.alert_handler_smoke/latest
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