Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	78322	1			T19	2		T17	5087		T18	4
class_i[0x1]	52634	1			T3	10		T48	850		T32	13
class_i[0x2]	53990	1			T2	20		T3	3		T16	3171
class_i[0x3]	49605	1			T3	8		T5	4383		T17	169

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	60236	1			T3	3		T19	1		T5	1194
alert[0x1]	59119	1			T3	7		T5	1032		T16	834
alert[0x2]	58704	1			T2	8		T3	2		T5	1036
alert[0x3]	56492	1			T2	12		T3	9		T19	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

234251

1

T2

20

T3

21

T19

2

esc_ping_fail

300

1

T9

7

T10

10

T11

5

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	60150	1			T3	3		T19	1		T5	1194
esc_integrity_fail	alert[0x1]	59046	1			T3	7		T5	1032		T16	834
esc_integrity_fail	alert[0x2]	58625	1			T2	8		T3	2		T5	1036
esc_integrity_fail	alert[0x3]	56430	1			T2	12		T3	9		T19	1
esc_ping_fail	alert[0x0]	86	1			T9	2		T10	2		T11	2
esc_ping_fail	alert[0x1]	73	1			T9	2		T10	3		T11	1
esc_ping_fail	alert[0x2]	79	1			T9	2		T10	2		T11	1
esc_ping_fail	alert[0x3]	62	1			T9	1		T10	3		T11	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	78229	1			T19	2		T17	5087		T18	4
esc_integrity_fail	class_i[0x1]	52567	1			T3	10		T48	850		T32	13
esc_integrity_fail	class_i[0x2]	53930	1			T2	20		T3	3		T16	3171
esc_integrity_fail	class_i[0x3]	49525	1			T3	8		T5	4383		T17	169
esc_ping_fail	class_i[0x0]	93	1			T9	1		T10	9		T306	7
esc_ping_fail	class_i[0x1]	67	1			T304	7		T305	8		T316	4
esc_ping_fail	class_i[0x2]	60	1			T9	6		T11	1		T304	1
esc_ping_fail	class_i[0x3]	80	1			T10	1		T11	4		T318	7