Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	157	1			T17	2		T8	1		T25	1
index[0x1]	192	1			T1	1		T2	1		T19	1
index[0x2]	140	1			T1	1		T5	1		T17	3
index[0x3]	175	1			T2	2		T16	1		T17	4

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	223	1			T1	2		T19	1		T5	4
lens_less_than_1000[1]	137	1			T2	3		T17	7		T29	1
lens_less_than_1000[2]	106	1			T17	5		T18	1		T27	2
lens_less_than_1000[3]	57	1			T35	1		T70	1		T26	1
lens_less_than_1000[4]	50	1			T89	1		T33	1		T36	1
lens_less_than_1000[5]	29	1			T21	1		T17	1		T75	1
lens_less_than_1000[6]	29	1			T49	1		T27	1		T33	1
lens_less_than_1000[7]	11	1			T227	1		T114	1		T273	1
lens_less_than_1000[8]	9	1			T107	1		T85	1		T278	1
lens_less_than_1000[9]	6	1			T84	1		T253	1		T279	2
len_2	7	1			T9	1		T31	1		T256	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x2]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	54	1			T8	1		T25	1		T26	2
index[0x0]	lens_less_than_1000[1]	35	1			T17	2		T29	1		T77	1
index[0x0]	lens_less_than_1000[2]	27	1			T27	1		T9	1		T251	1
index[0x0]	lens_less_than_1000[3]	15	1			T70	1		T31	2		T280	1
index[0x0]	lens_less_than_1000[4]	8	1			T236	1		T112	2		T281	1
index[0x0]	lens_less_than_1000[5]	6	1			T92	2		T282	1		T283	1
index[0x0]	lens_less_than_1000[6]	5	1			T60	1		T252	1		T66	1
index[0x0]	lens_less_than_1000[7]	2	1			T114	1		T273	1		-	-
index[0x0]	lens_less_than_1000[8]	2	1			T85	1		T259	1		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T284	1		-	-		-	-
index[0x0]	len_2	2	1			T9	1		T31	1		-	-
index[0x1]	lens_less_than_1000[0]	54	1			T1	1		T19	1		T5	3
index[0x1]	lens_less_than_1000[1]	43	1			T2	1		T17	5		T75	1
index[0x1]	lens_less_than_1000[2]	31	1			T33	1		T285	1		T58	1
index[0x1]	lens_less_than_1000[3]	22	1			T26	1		T33	2		T31	1
index[0x1]	lens_less_than_1000[4]	13	1			T89	1		T58	1		T59	2
index[0x1]	lens_less_than_1000[5]	8	1			T21	1		T54	1		T56	1
index[0x1]	lens_less_than_1000[6]	9	1			T49	1		T286	1		T258	1
index[0x1]	lens_less_than_1000[7]	2	1			T287	1		T288	1		-	-
index[0x1]	lens_less_than_1000[8]	4	1			T107	1		T289	1		T290	1
index[0x1]	lens_less_than_1000[9]	4	1			T84	1		T253	1		T279	1
index[0x1]	len_2	2	1			T286	1		T291	1		-	-
index[0x2]	lens_less_than_1000[0]	53	1			T1	1		T5	1		T17	1
index[0x2]	lens_less_than_1000[1]	22	1			T53	1		T54	3		T110	1
index[0x2]	lens_less_than_1000[2]	24	1			T17	1		T31	1		T112	1
index[0x2]	lens_less_than_1000[3]	8	1			T292	1		T28	1		T46	1
index[0x2]	lens_less_than_1000[4]	12	1			T33	1		T36	1		T112	2
index[0x2]	lens_less_than_1000[5]	11	1			T17	1		T75	1		T31	1
index[0x2]	lens_less_than_1000[6]	3	1			T33	1		T61	1		T293	1
index[0x2]	lens_less_than_1000[7]	5	1			T227	1		T104	1		T66	2
index[0x2]	lens_less_than_1000[8]	1	1			T294	1		-	-		-	-
index[0x2]	len_2	1	1			T295	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	62	1			T16	1		T35	1		T70	1
index[0x3]	lens_less_than_1000[1]	37	1			T2	2		T85	1		T232	1
index[0x3]	lens_less_than_1000[2]	24	1			T17	4		T18	1		T27	1
index[0x3]	lens_less_than_1000[3]	12	1			T35	1		T60	1		T193	1
index[0x3]	lens_less_than_1000[4]	17	1			T117	1		T296	1		T297	2
index[0x3]	lens_less_than_1000[5]	4	1			T298	1		T299	1		T300	1
index[0x3]	lens_less_than_1000[6]	12	1			T27	1		T301	1		T252	1
index[0x3]	lens_less_than_1000[7]	2	1			T252	1		T302	1		-	-
index[0x3]	lens_less_than_1000[8]	2	1			T278	1		T303	1		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T279	1		-	-		-	-
index[0x3]	len_2	2	1			T256	1		T103	1		-	-