Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	50	1			T1	1		T25	1		T27	1
class_index[0x1]	68	1			T51	1		T35	1		T25	1
class_index[0x2]	55	1			T19	1		T17	2		T27	1
class_index[0x3]	48	1			T3	1		T48	1		T107	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	91	1			T1	1		T17	2		T51	1
intr_timeout_cnt[1]	39	1			T25	1		T31	4		T84	2
intr_timeout_cnt[2]	22	1			T48	1		T26	1		T88	1
intr_timeout_cnt[3]	15	1			T31	1		T54	2		T58	1
intr_timeout_cnt[4]	20	1			T3	1		T107	1		T31	2
intr_timeout_cnt[5]	3	1			T27	1		T58	1		T64	1
intr_timeout_cnt[6]	7	1			T19	1		T54	1		T58	2
intr_timeout_cnt[7]	11	1			T27	1		T85	1		T64	1
intr_timeout_cnt[8]	5	1			T58	1		T113	1		T253	1
intr_timeout_cnt[9]	8	1			T59	3		T46	2		T256	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	22	1			T1	1		T30	2		T85	4
class_index[0x0]	intr_timeout_cnt[1]	8	1			T25	1		T31	1		T28	1
class_index[0x0]	intr_timeout_cnt[2]	4	1			T88	1		T257	1		T258	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T54	1		T259	2		T260	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T54	1		T193	1		T261	2
class_index[0x0]	intr_timeout_cnt[5]	1	1			T64	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T115	1		T262	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T27	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	3	1			T58	1		T253	1		T262	1
class_index[0x0]	intr_timeout_cnt[9]	1	1			T256	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	36	1			T51	1		T35	1		T25	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T31	1		T101	1		T263	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T26	1		T46	1		T193	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T31	1		T54	1		T264	1
class_index[0x1]	intr_timeout_cnt[4]	5	1			T31	2		T103	1		T259	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T27	1		T58	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T54	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T265	1		T266	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T113	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T93	1		T262	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	17	1			T17	2		T27	1		T54	1
class_index[0x2]	intr_timeout_cnt[1]	11	1			T31	1		T84	1		T267	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T268	2		T259	3		T269	2
class_index[0x2]	intr_timeout_cnt[3]	3	1			T270	1		T271	1		T272	1
class_index[0x2]	intr_timeout_cnt[4]	5	1			T273	1		T222	1		T259	2
class_index[0x2]	intr_timeout_cnt[6]	3	1			T19	1		T58	2		-	-
class_index[0x2]	intr_timeout_cnt[7]	5	1			T85	1		T64	1		T258	1
class_index[0x2]	intr_timeout_cnt[9]	4	1			T59	2		T46	2		-	-
class_index[0x3]	intr_timeout_cnt[0]	16	1			T31	1		T47	2		T177	1
class_index[0x3]	intr_timeout_cnt[1]	8	1			T31	1		T84	1		T175	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T48	1		T274	1		T64	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T58	1		T46	1		T275	1
class_index[0x3]	intr_timeout_cnt[4]	6	1			T3	1		T107	1		T87	2
class_index[0x3]	intr_timeout_cnt[6]	1	1			T276	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	3	1			T277	1		T101	1		T260	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T258	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T59	1		-	-		-	-