Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	352027	1			T1	2408		T2	1553		T3	7
all_values[1]	352027	1			T1	2408		T2	1553		T3	7
all_values[2]	352027	1			T1	2408		T2	1553		T3	7
all_values[3]	352027	1			T1	2408		T2	1553		T3	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

700385

1

T1

4807

T2

3151

T3

13

auto[1]

707723

1

T1

4825

T2

3061

T3

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

830414

1

T1

5165

T2

3144

T3

7

auto[1]

577694

1

T1

4467

T2

3068

T3

21

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98751	1			T1	620		T2	401		T3	2
all_values[0]	auto[0]	auto[1]	75859	1			T1	582		T2	394		T3	1
all_values[0]	auto[1]	auto[0]	100705	1			T1	624		T2	383		T4	299
all_values[0]	auto[1]	auto[1]	76712	1			T1	582		T2	375		T3	4
all_values[1]	auto[0]	auto[0]	105425	1			T1	632		T2	385		T3	1
all_values[1]	auto[0]	auto[1]	69754	1			T1	540		T2	383		T3	3
all_values[1]	auto[1]	auto[0]	106867	1			T1	683		T2	394		T4	305
all_values[1]	auto[1]	auto[1]	69981	1			T1	553		T2	391		T3	3
all_values[2]	auto[0]	auto[0]	104315	1			T1	665		T2	398		T3	1
all_values[2]	auto[0]	auto[1]	71184	1			T1	562		T2	380		T3	1
all_values[2]	auto[1]	auto[0]	105428	1			T1	636		T2	396		T3	1
all_values[2]	auto[1]	auto[1]	71100	1			T1	545		T2	379		T3	4
all_values[3]	auto[0]	auto[0]	103752	1			T1	657		T2	410		T3	2
all_values[3]	auto[0]	auto[1]	71345	1			T1	549		T2	400		T3	2
all_values[3]	auto[1]	auto[0]	105171	1			T1	648		T2	377		T4	291
all_values[3]	auto[1]	auto[1]	71759	1			T1	554		T2	366		T3	3