Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	352027	1			T1	2408		T2	1553		T3	7
all_pins[1]	352027	1			T1	2408		T2	1553		T3	7
all_pins[2]	352027	1			T1	2408		T2	1553		T3	7
all_pins[3]	352027	1			T1	2408		T2	1553		T3	7

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1118556	1			T1	7398		T2	4701		T3	14
values[0x1]	289552	1			T1	2234		T2	1511		T3	14
transitions[0x0=>0x1]	192183	1			T1	1459		T2	949		T3	4
transitions[0x1=>0x0]	192442	1			T1	1460		T2	950		T3	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	275315	1			T1	1826		T2	1178		T3	3
all_pins[0]	values[0x1]	76712	1			T1	582		T2	375		T3	4
all_pins[0]	transitions[0x0=>0x1]	76040	1			T1	581		T2	374		T3	1
all_pins[0]	transitions[0x1=>0x0]	71346	1			T1	554		T2	366		T3	1
all_pins[1]	values[0x0]	282046	1			T1	1855		T2	1162		T3	4
all_pins[1]	values[0x1]	69981	1			T1	553		T2	391		T3	3
all_pins[1]	transitions[0x0=>0x1]	37266	1			T1	288		T2	201		T3	1
all_pins[1]	transitions[0x1=>0x0]	43997	1			T1	317		T2	185		T3	2
all_pins[2]	values[0x0]	280927	1			T1	1863		T2	1174		T3	3
all_pins[2]	values[0x1]	71100	1			T1	545		T2	379		T3	4
all_pins[2]	transitions[0x0=>0x1]	39152	1			T1	286		T2	190		T3	1
all_pins[2]	transitions[0x1=>0x0]	38033	1			T1	294		T2	202		T4	118
all_pins[3]	values[0x0]	280268	1			T1	1854		T2	1187		T3	4
all_pins[3]	values[0x1]	71759	1			T1	554		T2	366		T3	3
all_pins[3]	transitions[0x0=>0x1]	39725	1			T1	304		T2	184		T3	1
all_pins[3]	transitions[0x1=>0x0]	39066	1			T1	295		T2	197		T3	2