Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1			T158	7		T159	7		T160	7
all_values[1]	287	1			T158	7		T159	7		T160	7
all_values[2]	287	1			T158	7		T159	7		T160	7
all_values[3]	287	1			T158	7		T159	7		T160	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620

1

T158

14

T159

18

T160

19

auto[1]

528

1

T158

14

T159

10

T160

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

422

1

T158

16

T159

9

T160

11

auto[1]

726

1

T158

12

T159

19

T160

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

644

1

T158

18

T159

15

T160

14

auto[1]

504

1

T158

10

T159

13

T160

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

50

1

T158

2

T159

1

T160

3

all_values[0]

auto[0]

auto[0]

auto[1]

35

1

T159

1

T344

1

T249

2

all_values[0]

auto[0]

auto[1]

auto[0]

49

1

T159

1

T160

2

T344

1

all_values[0]

auto[0]

auto[1]

auto[1]

21

1

T158

1

T344

1

T345

2

all_values[0]

auto[1]

auto[0]

auto[1]

65

1

T159

1

T160

1

T344

1

all_values[0]

auto[1]

auto[1]

auto[1]

67

1

T158

4

T159

3

T160

1

all_values[1]

auto[0]

auto[0]

auto[0]

71

1

T158

5

T159

3

T344

1

all_values[1]

auto[0]

auto[0]

auto[1]

26

1

T160

1

T344

1

T345

1

all_values[1]

auto[0]

auto[1]

auto[0]

43

1

T344

3

T345

1

T346

1

all_values[1]

auto[0]

auto[1]

auto[1]

21

1

T158

1

T159

2

T345

1

all_values[1]

auto[1]

auto[0]

auto[1]

66

1

T159

1

T160

4

T344

1

all_values[1]

auto[1]

auto[1]

auto[1]

60

1

T158

1

T159

1

T160

2

all_values[2]

auto[0]

auto[0]

auto[0]

55

1

T158

2

T159

2

T160

1

all_values[2]

auto[0]

auto[0]

auto[1]

31

1

T159

1

T160

1

T344

2

all_values[2]

auto[0]

auto[1]

auto[0]

45

1

T158

2

T159

1

T160

2

all_values[2]

auto[0]

auto[1]

auto[1]

35

1

T345

1

T346

4

T249

1

all_values[2]

auto[1]

auto[0]

auto[1]

69

1

T158

1

T159

3

T160

2

all_values[2]

auto[1]

auto[1]

auto[1]

52

1

T158

2

T160

1

T344

1

all_values[3]

auto[0]

auto[0]

auto[0]

57

1

T158

2

T159

1

T160

2

all_values[3]

auto[0]

auto[0]

auto[1]

27

1

T159

1

T160

1

T344

2

all_values[3]

auto[0]

auto[1]

auto[0]

52

1

T158

3

T160

1

T345

1

all_values[3]

auto[0]

auto[1]

auto[1]

26

1

T159

1

T344

1

T345

1

all_values[3]

auto[1]

auto[0]

auto[1]

68

1

T158

2

T159

3

T160

3

all_values[3]

auto[1]

auto[1]

auto[1]

57

1

T159

1

T344

1

T345

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal