Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	90940	1			T1	528		T5	1190		T15	753
accum_cnt_1000	222088	1			T1	654		T5	1397		T21	43
accum_cnt_100	26086	1			T1	110		T5	86		T21	59
accum_cnt_50	61335	1			T1	134		T2	2332		T19	10
accum_cnt_10	181086	1			T1	1593		T2	10		T3	27
accum_cnt_0	406031	1			T1	3534		T2	2358		T3	9

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	259889	1			T1	1721		T2	1175		T3	9
class_index[0x1]	259889	1			T1	1721		T2	1175		T3	9
class_index[0x2]	259889	1			T1	1721		T2	1175		T3	9
class_index[0x3]	259889	1			T1	1721		T2	1175		T3	9

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24450	1			T5	534		T15	439		T16	268
class_index[0x0]	accum_cnt_1000	59480	1			T1	69		T5	489		T21	17
class_index[0x0]	accum_cnt_100	7201	1			T1	46		T5	29		T21	19
class_index[0x0]	accum_cnt_50	15148	1			T1	61		T5	22		T21	13
class_index[0x0]	accum_cnt_10	46102	1			T1	1461		T3	9		T19	25
class_index[0x0]	accum_cnt_0	94276	1			T1	84		T2	1175		T4	901
class_index[0x1]	accum_cnt_2000	24873	1			T17	681		T69	220		T70	592
class_index[0x1]	accum_cnt_1000	55816	1			T1	61		T17	723		T32	654
class_index[0x1]	accum_cnt_100	6313	1			T1	23		T17	120		T32	64
class_index[0x1]	accum_cnt_50	15154	1			T1	23		T2	1165		T17	113
class_index[0x1]	accum_cnt_10	40323	1			T1	19		T2	9		T4	3
class_index[0x1]	accum_cnt_0	104749	1			T1	1595		T2	1		T3	9
class_index[0x2]	accum_cnt_2000	21213	1			T5	443		T49	299		T32	172
class_index[0x2]	accum_cnt_1000	54947	1			T1	75		T5	721		T21	18
class_index[0x2]	accum_cnt_100	6617	1			T1	16		T5	44		T21	17
class_index[0x2]	accum_cnt_50	17779	1			T1	27		T2	1167		T19	10
class_index[0x2]	accum_cnt_10	51340	1			T1	18		T2	1		T3	9
class_index[0x2]	accum_cnt_0	97357	1			T1	1585		T2	7		T4	901
class_index[0x3]	accum_cnt_2000	20404	1			T1	528		T5	213		T15	314
class_index[0x3]	accum_cnt_1000	51845	1			T1	449		T5	187		T21	8
class_index[0x3]	accum_cnt_100	5955	1			T1	25		T5	13		T21	23
class_index[0x3]	accum_cnt_50	13254	1			T1	23		T5	8		T21	16
class_index[0x3]	accum_cnt_10	43321	1			T1	95		T3	9		T4	3
class_index[0x3]	accum_cnt_0	109649	1			T1	270		T2	1175		T4	898