Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	7171	1			T16	188		T32	9		T30	4
alert[0x1]	5806	1			T5	48		T32	22		T26	1
alert[0x2]	4035	1			T32	20		T10	1		T31	2
alert[0x3]	10033	1			T5	126		T16	387		T25	16
alert[0x4]	5089	1			T5	104		T17	1		T32	3
alert[0x5]	15981	1			T16	70		T7	1		T9	1
alert[0x6]	8041	1			T16	87		T32	96		T25	6
alert[0x7]	10917	1			T1	7482		T3	2		T5	160
alert[0x8]	12214	1			T16	278		T32	79		T31	8
alert[0x9]	7331	1			T69	6		T27	1		T111	34
alert[0xa]	7362	1			T1	133		T6	1		T16	599
alert[0xb]	8007	1			T17	1		T26	16		T30	1
alert[0xc]	8658	1			T5	5		T16	1		T26	1
alert[0xd]	4227	1			T5	36		T16	988		T17	1
alert[0xe]	4748	1			T1	8		T16	306		T32	505
alert[0xf]	5541	1			T5	146		T32	766		T9	1
alert[0x10]	3185	1			T1	69		T48	1		T69	18
alert[0x11]	3683	1			T16	28		T69	14		T9	1
alert[0x12]	3307	1			T1	50		T17	1		T32	76
alert[0x13]	4965	1			T3	1		T5	35		T6	1
alert[0x14]	6285	1			T16	28		T32	24		T55	372
alert[0x15]	3466	1			T16	15		T26	25		T9	1
alert[0x16]	9481	1			T1	4016		T5	15		T32	5
alert[0x17]	6206	1			T1	3662		T5	8		T32	77
alert[0x18]	10250	1			T16	106		T25	21		T31	5
alert[0x19]	4996	1			T3	5		T69	1		T10	1
alert[0x1a]	5860	1			T5	46		T16	40		T32	25
alert[0x1b]	6439	1			T5	57		T51	3		T10	1
alert[0x1c]	4004	1			T1	21		T16	357		T235	85
alert[0x1d]	9971	1			T1	39		T5	66		T32	6
alert[0x1e]	2573	1			T1	19		T31	29		T85	16
alert[0x1f]	4617	1			T1	98		T16	18		T17	7
alert[0x20]	3234	1			T32	24		T111	958		T55	592
alert[0x21]	9042	1			T1	381		T16	228		T32	1323
alert[0x22]	4589	1			T5	140		T16	397		T32	211
alert[0x23]	8500	1			T1	963		T16	705		T32	7
alert[0x24]	4667	1			T1	347		T32	60		T25	446
alert[0x25]	4595	1			T1	40		T5	20		T16	12
alert[0x26]	9026	1			T1	1024		T111	240		T117	122
alert[0x27]	6051	1			T32	803		T111	147		T55	222
alert[0x28]	8139	1			T17	3		T26	35		T117	5
alert[0x29]	15412	1			T1	127		T5	279		T32	19
alert[0x2a]	5253	1			T16	417		T8	2		T26	126
alert[0x2b]	17262	1			T1	43		T5	413		T51	2
alert[0x2c]	4306	1			T1	240		T3	6		T16	9
alert[0x2d]	9136	1			T1	27		T51	1		T25	15
alert[0x2e]	13539	1			T1	7050		T5	20		T16	1004
alert[0x2f]	12533	1			T1	1924		T25	25		T9	1
alert[0x30]	8993	1			T1	1228		T5	112		T32	11
alert[0x31]	4660	1			T5	77		T32	839		T27	2
alert[0x32]	9704	1			T1	58		T5	20		T32	51
alert[0x33]	6750	1			T5	105		T16	5		T55	30
alert[0x34]	6356	1			T111	388		T54	1		T85	2461
alert[0x35]	13977	1			T1	550		T69	2		T292	4
alert[0x36]	10753	1			T17	7		T32	59		T25	44
alert[0x37]	3721	1			T5	138		T16	282		T25	7
alert[0x38]	10791	1			T1	39		T3	2		T32	11
alert[0x39]	8193	1			T16	37		T17	3		T32	160
alert[0x3a]	8281	1			T32	573		T26	4		T235	72
alert[0x3b]	6693	1			T32	1004		T25	35		T69	6
alert[0x3c]	4462	1			T25	24		T26	1		T11	1
alert[0x3d]	4440	1			T1	42		T3	5		T16	102
alert[0x3e]	10461	1			T1	484		T5	529		T16	1463
alert[0x3f]	3680	1			T1	9		T5	38		T16	59
alert[0x40]	4178	1			T16	568		T25	6		T31	13

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	120924	1			T1	91		T3	7		T6	3
class_i[0x1]	130851	1			T51	18		T8	2		T69	32
class_i[0x2]	94617	1			T1	30059		T3	14		T16	13
class_i[0x3]	129434	1			T1	23		T5	2743		T16	8816

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

475133

1

T1

30173

T3

21

T5

2743

alert_ping_fail

693

1

T6

3

T7

3

T8

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	7160	1			T16	188		T32	9		T30	4
alert_integrity_fail	alert[0x1]	5793	1			T5	48		T32	22		T26	1
alert_integrity_fail	alert[0x2]	4022	1			T32	20		T31	2		T55	117
alert_integrity_fail	alert[0x3]	10025	1			T5	126		T16	387		T25	16
alert_integrity_fail	alert[0x4]	5076	1			T5	104		T17	1		T32	3
alert_integrity_fail	alert[0x5]	15968	1			T16	70		T30	3		T111	103
alert_integrity_fail	alert[0x6]	8026	1			T16	87		T32	96		T25	6
alert_integrity_fail	alert[0x7]	10903	1			T1	7482		T3	2		T5	160
alert_integrity_fail	alert[0x8]	12201	1			T16	278		T32	79		T31	8
alert_integrity_fail	alert[0x9]	7327	1			T69	6		T27	1		T111	34
alert_integrity_fail	alert[0xa]	7349	1			T1	133		T16	599		T25	1236
alert_integrity_fail	alert[0xb]	7996	1			T17	1		T26	16		T30	1
alert_integrity_fail	alert[0xc]	8648	1			T5	5		T16	1		T26	1
alert_integrity_fail	alert[0xd]	4221	1			T5	36		T16	988		T17	1
alert_integrity_fail	alert[0xe]	4743	1			T1	8		T16	306		T32	505
alert_integrity_fail	alert[0xf]	5532	1			T5	146		T32	766		T54	2
alert_integrity_fail	alert[0x10]	3172	1			T1	69		T48	1		T69	18
alert_integrity_fail	alert[0x11]	3675	1			T16	28		T69	14		T292	6
alert_integrity_fail	alert[0x12]	3297	1			T1	50		T17	1		T32	76
alert_integrity_fail	alert[0x13]	4946	1			T3	1		T5	35		T32	1898
alert_integrity_fail	alert[0x14]	6272	1			T16	28		T32	24		T55	372
alert_integrity_fail	alert[0x15]	3455	1			T16	15		T26	25		T117	12
alert_integrity_fail	alert[0x16]	9466	1			T1	4016		T5	15		T32	5
alert_integrity_fail	alert[0x17]	6198	1			T1	3662		T5	8		T32	77
alert_integrity_fail	alert[0x18]	10242	1			T16	106		T25	21		T31	5
alert_integrity_fail	alert[0x19]	4979	1			T3	5		T69	1		T31	1
alert_integrity_fail	alert[0x1a]	5847	1			T5	46		T16	40		T32	25
alert_integrity_fail	alert[0x1b]	6433	1			T5	57		T51	3		T117	8
alert_integrity_fail	alert[0x1c]	3997	1			T1	21		T16	357		T235	85
alert_integrity_fail	alert[0x1d]	9962	1			T1	39		T5	66		T32	6
alert_integrity_fail	alert[0x1e]	2563	1			T1	19		T31	29		T85	16
alert_integrity_fail	alert[0x1f]	4603	1			T1	98		T16	18		T17	7
alert_integrity_fail	alert[0x20]	3217	1			T32	24		T111	958		T55	592
alert_integrity_fail	alert[0x21]	9034	1			T1	381		T16	228		T32	1323
alert_integrity_fail	alert[0x22]	4575	1			T5	140		T16	397		T32	211
alert_integrity_fail	alert[0x23]	8488	1			T1	963		T16	705		T32	7
alert_integrity_fail	alert[0x24]	4661	1			T1	347		T32	60		T25	446
alert_integrity_fail	alert[0x25]	4580	1			T1	40		T5	20		T16	12
alert_integrity_fail	alert[0x26]	9018	1			T1	1024		T111	240		T117	122
alert_integrity_fail	alert[0x27]	6044	1			T32	803		T111	147		T55	222
alert_integrity_fail	alert[0x28]	8128	1			T17	3		T26	35		T117	5
alert_integrity_fail	alert[0x29]	15405	1			T1	127		T5	279		T32	19
alert_integrity_fail	alert[0x2a]	5244	1			T16	417		T26	126		T111	55
alert_integrity_fail	alert[0x2b]	17253	1			T1	43		T5	413		T51	2
alert_integrity_fail	alert[0x2c]	4289	1			T1	240		T3	6		T16	9
alert_integrity_fail	alert[0x2d]	9125	1			T1	27		T51	1		T25	15
alert_integrity_fail	alert[0x2e]	13518	1			T1	7050		T5	20		T16	1004
alert_integrity_fail	alert[0x2f]	12513	1			T1	1924		T25	25		T87	1
alert_integrity_fail	alert[0x30]	8986	1			T1	1228		T5	112		T32	11
alert_integrity_fail	alert[0x31]	4649	1			T5	77		T32	839		T27	2
alert_integrity_fail	alert[0x32]	9696	1			T1	58		T5	20		T32	51
alert_integrity_fail	alert[0x33]	6742	1			T5	105		T16	5		T55	30
alert_integrity_fail	alert[0x34]	6347	1			T111	388		T54	1		T85	2461
alert_integrity_fail	alert[0x35]	13967	1			T1	550		T69	2		T292	4
alert_integrity_fail	alert[0x36]	10740	1			T17	7		T32	59		T25	44
alert_integrity_fail	alert[0x37]	3713	1			T5	138		T16	282		T25	7
alert_integrity_fail	alert[0x38]	10779	1			T1	39		T3	2		T32	11
alert_integrity_fail	alert[0x39]	8185	1			T16	37		T17	3		T32	160
alert_integrity_fail	alert[0x3a]	8271	1			T32	573		T26	4		T235	72
alert_integrity_fail	alert[0x3b]	6683	1			T32	1004		T25	35		T69	6
alert_integrity_fail	alert[0x3c]	4453	1			T25	24		T26	1		T58	24
alert_integrity_fail	alert[0x3d]	4431	1			T1	42		T3	5		T16	102
alert_integrity_fail	alert[0x3e]	10452	1			T1	484		T5	529		T16	1463
alert_integrity_fail	alert[0x3f]	3675	1			T1	9		T5	38		T16	59
alert_integrity_fail	alert[0x40]	4175	1			T16	568		T25	6		T31	13
alert_ping_fail	alert[0x0]	11	1			T11	1		T304	1		T305	1
alert_ping_fail	alert[0x1]	13	1			T305	1		T306	1		T307	2
alert_ping_fail	alert[0x2]	13	1			T10	1		T178	1		T308	1
alert_ping_fail	alert[0x3]	8	1			T309	1		T306	1		T310	1
alert_ping_fail	alert[0x4]	13	1			T10	1		T304	1		T305	2
alert_ping_fail	alert[0x5]	13	1			T7	1		T9	1		T10	2
alert_ping_fail	alert[0x6]	15	1			T310	1		T311	1		T312	2
alert_ping_fail	alert[0x7]	14	1			T6	1		T234	1		T309	1
alert_ping_fail	alert[0x8]	13	1			T313	2		T178	1		T308	1
alert_ping_fail	alert[0x9]	4	1			T304	1		T314	1		T315	1
alert_ping_fail	alert[0xa]	13	1			T6	1		T7	1		T89	1
alert_ping_fail	alert[0xb]	11	1			T10	2		T304	1		T307	1
alert_ping_fail	alert[0xc]	10	1			T9	1		T10	1		T316	1
alert_ping_fail	alert[0xd]	6	1			T178	1		T307	1		T317	1
alert_ping_fail	alert[0xe]	5	1			T305	1		T178	1		T307	1
alert_ping_fail	alert[0xf]	9	1			T9	1		T318	1		T310	3
alert_ping_fail	alert[0x10]	13	1			T318	1		T309	1		T305	3
alert_ping_fail	alert[0x11]	8	1			T9	1		T309	2		T178	1
alert_ping_fail	alert[0x12]	10	1			T9	1		T10	1		T309	1
alert_ping_fail	alert[0x13]	19	1			T6	1		T10	1		T11	1
alert_ping_fail	alert[0x14]	13	1			T318	1		T42	1		T319	1
alert_ping_fail	alert[0x15]	11	1			T9	1		T310	2		T320	2
alert_ping_fail	alert[0x16]	15	1			T319	1		T178	1		T311	1
alert_ping_fail	alert[0x17]	8	1			T304	1		T319	1		T310	1
alert_ping_fail	alert[0x18]	8	1			T11	1		T316	1		T320	1
alert_ping_fail	alert[0x19]	17	1			T10	1		T11	1		T318	1
alert_ping_fail	alert[0x1a]	13	1			T304	1		T318	1		T309	2
alert_ping_fail	alert[0x1b]	6	1			T10	1		T304	1		T319	1
alert_ping_fail	alert[0x1c]	7	1			T309	1		T178	1		T297	1
alert_ping_fail	alert[0x1d]	9	1			T9	1		T10	1		T305	1
alert_ping_fail	alert[0x1e]	10	1			T318	1		T306	1		T319	1
alert_ping_fail	alert[0x1f]	14	1			T304	1		T97	1		T42	1
alert_ping_fail	alert[0x20]	17	1			T316	1		T297	1		T308	1
alert_ping_fail	alert[0x21]	8	1			T305	1		T306	1		T313	1
alert_ping_fail	alert[0x22]	14	1			T10	2		T11	1		T297	1
alert_ping_fail	alert[0x23]	12	1			T11	2		T306	2		T182	1
alert_ping_fail	alert[0x24]	6	1			T10	1		T297	1		T308	1
alert_ping_fail	alert[0x25]	15	1			T11	1		T305	1		T302	1
alert_ping_fail	alert[0x26]	8	1			T318	1		T321	1		T322	1
alert_ping_fail	alert[0x27]	7	1			T310	1		T308	1		T320	1
alert_ping_fail	alert[0x28]	11	1			T11	1		T318	1		T305	1
alert_ping_fail	alert[0x29]	7	1			T313	1		T314	2		T323	1
alert_ping_fail	alert[0x2a]	9	1			T8	2		T305	1		T324	1
alert_ping_fail	alert[0x2b]	9	1			T318	1		T306	2		T297	1
alert_ping_fail	alert[0x2c]	17	1			T7	1		T178	1		T311	1
alert_ping_fail	alert[0x2d]	11	1			T318	2		T182	1		T302	1
alert_ping_fail	alert[0x2e]	21	1			T304	2		T309	1		T316	1
alert_ping_fail	alert[0x2f]	20	1			T9	1		T10	1		T304	1
alert_ping_fail	alert[0x30]	7	1			T9	1		T10	1		T304	1
alert_ping_fail	alert[0x31]	11	1			T305	1		T316	1		T314	1
alert_ping_fail	alert[0x32]	8	1			T10	1		T305	1		T308	1
alert_ping_fail	alert[0x33]	8	1			T318	1		T308	1		T284	1
alert_ping_fail	alert[0x34]	9	1			T318	1		T309	1		T306	1
alert_ping_fail	alert[0x35]	10	1			T318	1		T309	1		T316	1
alert_ping_fail	alert[0x36]	13	1			T318	1		T309	1		T314	1
alert_ping_fail	alert[0x37]	8	1			T318	1		T305	1		T308	1
alert_ping_fail	alert[0x38]	12	1			T10	1		T309	1		T178	1
alert_ping_fail	alert[0x39]	8	1			T10	1		T304	1		T325	1
alert_ping_fail	alert[0x3a]	10	1			T306	1		T178	1		T297	1
alert_ping_fail	alert[0x3b]	10	1			T302	1		T307	1		T326	1
alert_ping_fail	alert[0x3c]	9	1			T11	1		T309	1		T305	1
alert_ping_fail	alert[0x3d]	9	1			T318	1		T305	1		T311	1
alert_ping_fail	alert[0x3e]	9	1			T9	1		T311	1		T327	1
alert_ping_fail	alert[0x3f]	5	1			T9	1		T308	1		T325	1
alert_ping_fail	alert[0x40]	3	1			T178	1		T297	1		T314	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	120708	1			T1	91		T3	7		T17	1
alert_integrity_fail	class_i[0x1]	130686	1			T51	18		T69	32		T26	4
alert_integrity_fail	class_i[0x2]	94488	1			T1	30059		T3	14		T16	13
alert_integrity_fail	class_i[0x3]	129251	1			T1	23		T5	2743		T16	8816
alert_ping_fail	class_i[0x0]	216	1			T6	3		T89	1		T10	5
alert_ping_fail	class_i[0x1]	165	1			T8	2		T9	1		T10	3
alert_ping_fail	class_i[0x2]	129	1			T7	3		T9	1		T10	10
alert_ping_fail	class_i[0x3]	183	1			T9	9		T10	2		T318	1