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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.75 100.00 100.00 100.00 99.38 99.60


Total test records in report: 832
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T147 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4196716314 Jun 10 06:35:32 PM PDT 24 Jun 10 06:41:24 PM PDT 24 16610699747 ps
T768 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1284510964 Jun 10 06:35:53 PM PDT 24 Jun 10 06:35:54 PM PDT 24 15329999 ps
T769 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.168341069 Jun 10 06:35:27 PM PDT 24 Jun 10 06:35:39 PM PDT 24 110700476 ps
T770 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2330102922 Jun 10 06:35:43 PM PDT 24 Jun 10 06:36:24 PM PDT 24 634323766 ps
T771 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2368941397 Jun 10 06:35:57 PM PDT 24 Jun 10 06:35:59 PM PDT 24 11887891 ps
T149 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.30785477 Jun 10 06:35:48 PM PDT 24 Jun 10 06:38:09 PM PDT 24 1877594563 ps
T772 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.184351108 Jun 10 06:35:20 PM PDT 24 Jun 10 06:36:01 PM PDT 24 1386298025 ps
T773 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2279121673 Jun 10 06:35:16 PM PDT 24 Jun 10 06:35:20 PM PDT 24 43022457 ps
T774 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.912599535 Jun 10 06:35:57 PM PDT 24 Jun 10 06:35:59 PM PDT 24 22739545 ps
T775 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.861847117 Jun 10 06:35:42 PM PDT 24 Jun 10 06:35:56 PM PDT 24 344017875 ps
T776 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1136355881 Jun 10 06:35:22 PM PDT 24 Jun 10 06:35:30 PM PDT 24 382312674 ps
T777 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.306532149 Jun 10 06:35:46 PM PDT 24 Jun 10 06:35:47 PM PDT 24 10253696 ps
T778 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1019660463 Jun 10 06:35:39 PM PDT 24 Jun 10 06:36:13 PM PDT 24 1960140170 ps
T779 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2930685394 Jun 10 06:35:48 PM PDT 24 Jun 10 06:35:50 PM PDT 24 6126236 ps
T164 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.414358660 Jun 10 06:35:32 PM PDT 24 Jun 10 06:35:37 PM PDT 24 82706139 ps
T780 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2582101694 Jun 10 06:35:53 PM PDT 24 Jun 10 06:35:54 PM PDT 24 70844323 ps
T781 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2854013928 Jun 10 06:35:35 PM PDT 24 Jun 10 06:35:55 PM PDT 24 304243875 ps
T782 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.302047366 Jun 10 06:35:26 PM PDT 24 Jun 10 06:35:36 PM PDT 24 123172228 ps
T783 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3442922121 Jun 10 06:35:23 PM PDT 24 Jun 10 06:35:31 PM PDT 24 1058595020 ps
T784 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1386978323 Jun 10 06:35:17 PM PDT 24 Jun 10 06:35:24 PM PDT 24 253910963 ps
T151 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3794779753 Jun 10 06:35:39 PM PDT 24 Jun 10 06:38:25 PM PDT 24 19201182712 ps
T785 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2160620678 Jun 10 06:35:41 PM PDT 24 Jun 10 06:35:50 PM PDT 24 554659055 ps
T786 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3676997335 Jun 10 06:35:36 PM PDT 24 Jun 10 06:35:45 PM PDT 24 500606079 ps
T787 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2053650893 Jun 10 06:35:51 PM PDT 24 Jun 10 06:35:57 PM PDT 24 95177502 ps
T788 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.18632650 Jun 10 06:35:49 PM PDT 24 Jun 10 06:35:54 PM PDT 24 54364641 ps
T125 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1986984727 Jun 10 06:35:19 PM PDT 24 Jun 10 06:38:21 PM PDT 24 7267746770 ps
T789 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1811803285 Jun 10 06:35:27 PM PDT 24 Jun 10 06:35:32 PM PDT 24 123391114 ps
T148 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3892557547 Jun 10 06:35:50 PM PDT 24 Jun 10 06:45:03 PM PDT 24 7134190743 ps
T790 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3950048073 Jun 10 06:35:32 PM PDT 24 Jun 10 06:35:37 PM PDT 24 73545968 ps
T791 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.425455683 Jun 10 06:35:23 PM PDT 24 Jun 10 06:35:33 PM PDT 24 487901855 ps
T792 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.126905483 Jun 10 06:35:10 PM PDT 24 Jun 10 06:35:15 PM PDT 24 34012131 ps
T793 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2500655417 Jun 10 06:35:18 PM PDT 24 Jun 10 06:35:20 PM PDT 24 62227680 ps
T794 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.869605673 Jun 10 06:35:54 PM PDT 24 Jun 10 06:36:01 PM PDT 24 219691049 ps
T795 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1256401682 Jun 10 06:35:54 PM PDT 24 Jun 10 06:35:56 PM PDT 24 15653960 ps
T796 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1879252624 Jun 10 06:35:16 PM PDT 24 Jun 10 06:35:18 PM PDT 24 9174082 ps
T797 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2085170765 Jun 10 06:35:46 PM PDT 24 Jun 10 06:36:10 PM PDT 24 495662381 ps
T798 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2376933413 Jun 10 06:35:49 PM PDT 24 Jun 10 06:36:03 PM PDT 24 910892045 ps
T799 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1472062225 Jun 10 06:35:45 PM PDT 24 Jun 10 06:35:47 PM PDT 24 19553415 ps
T800 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3287560751 Jun 10 06:35:48 PM PDT 24 Jun 10 06:35:50 PM PDT 24 8488673 ps
T126 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.146788112 Jun 10 06:35:48 PM PDT 24 Jun 10 06:37:15 PM PDT 24 1464971611 ps
T801 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4114804653 Jun 10 06:35:36 PM PDT 24 Jun 10 06:36:15 PM PDT 24 610810174 ps
T154 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3515785670 Jun 10 06:35:42 PM PDT 24 Jun 10 06:45:10 PM PDT 24 30957046760 ps
T802 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3358528579 Jun 10 06:35:49 PM PDT 24 Jun 10 06:36:08 PM PDT 24 599039669 ps
T803 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1409170764 Jun 10 06:35:21 PM PDT 24 Jun 10 06:39:40 PM PDT 24 4774411412 ps
T804 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1154961361 Jun 10 06:35:29 PM PDT 24 Jun 10 06:35:49 PM PDT 24 273040810 ps
T350 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2692025060 Jun 10 06:35:50 PM PDT 24 Jun 10 06:40:38 PM PDT 24 2196654042 ps
T805 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2893228691 Jun 10 06:35:24 PM PDT 24 Jun 10 06:35:46 PM PDT 24 1032525022 ps
T806 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3488366166 Jun 10 06:35:47 PM PDT 24 Jun 10 06:35:49 PM PDT 24 10053897 ps
T135 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.474270615 Jun 10 06:35:34 PM PDT 24 Jun 10 06:38:21 PM PDT 24 7360078269 ps
T807 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.240887607 Jun 10 06:35:30 PM PDT 24 Jun 10 06:35:32 PM PDT 24 10152570 ps
T170 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.423564408 Jun 10 06:35:28 PM PDT 24 Jun 10 06:36:09 PM PDT 24 1204214331 ps
T808 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1059192406 Jun 10 06:35:31 PM PDT 24 Jun 10 06:35:36 PM PDT 24 133734143 ps
T809 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3266611036 Jun 10 06:35:38 PM PDT 24 Jun 10 06:36:00 PM PDT 24 315881897 ps
T810 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.660658039 Jun 10 06:35:52 PM PDT 24 Jun 10 06:35:54 PM PDT 24 8364042 ps
T811 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.141375747 Jun 10 06:35:46 PM PDT 24 Jun 10 06:36:20 PM PDT 24 1944982018 ps
T351 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1081253241 Jun 10 06:35:39 PM PDT 24 Jun 10 06:44:53 PM PDT 24 25422102253 ps
T812 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3998996130 Jun 10 06:35:46 PM PDT 24 Jun 10 06:35:53 PM PDT 24 179694955 ps
T173 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1571609532 Jun 10 06:35:49 PM PDT 24 Jun 10 06:35:54 PM PDT 24 106823953 ps
T813 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2213164295 Jun 10 06:35:47 PM PDT 24 Jun 10 06:36:10 PM PDT 24 344023654 ps
T814 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4267672430 Jun 10 06:35:47 PM PDT 24 Jun 10 06:35:49 PM PDT 24 55732778 ps
T152 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1748407673 Jun 10 06:35:37 PM PDT 24 Jun 10 06:37:24 PM PDT 24 5710280530 ps
T815 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3596838816 Jun 10 06:35:36 PM PDT 24 Jun 10 06:35:48 PM PDT 24 450378190 ps
T167 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.681255719 Jun 10 06:35:41 PM PDT 24 Jun 10 06:35:45 PM PDT 24 54073958 ps
T816 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2506893432 Jun 10 06:35:20 PM PDT 24 Jun 10 06:38:44 PM PDT 24 20316279421 ps
T817 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.203088760 Jun 10 06:35:14 PM PDT 24 Jun 10 06:39:40 PM PDT 24 3970106921 ps
T818 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2564783445 Jun 10 06:35:39 PM PDT 24 Jun 10 06:35:53 PM PDT 24 330449185 ps
T819 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.423728560 Jun 10 06:35:21 PM PDT 24 Jun 10 06:35:29 PM PDT 24 100491459 ps
T153 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1580409070 Jun 10 06:35:16 PM PDT 24 Jun 10 06:37:28 PM PDT 24 3723980863 ps
T820 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2183989545 Jun 10 06:35:41 PM PDT 24 Jun 10 06:35:49 PM PDT 24 99256841 ps
T821 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4016366275 Jun 10 06:35:57 PM PDT 24 Jun 10 06:35:59 PM PDT 24 14735306 ps
T136 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1889717512 Jun 10 06:35:37 PM PDT 24 Jun 10 06:37:15 PM PDT 24 751073552 ps
T822 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2113047787 Jun 10 06:35:35 PM PDT 24 Jun 10 06:35:39 PM PDT 24 61152998 ps
T823 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.495842092 Jun 10 06:35:34 PM PDT 24 Jun 10 06:35:40 PM PDT 24 229092141 ps
T824 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1259815419 Jun 10 06:35:28 PM PDT 24 Jun 10 06:35:37 PM PDT 24 198208029 ps
T825 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1486503986 Jun 10 06:35:22 PM PDT 24 Jun 10 06:35:32 PM PDT 24 639193415 ps
T826 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2354028711 Jun 10 06:35:47 PM PDT 24 Jun 10 06:35:48 PM PDT 24 16598242 ps
T827 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2274649627 Jun 10 06:35:20 PM PDT 24 Jun 10 06:35:26 PM PDT 24 289329179 ps
T828 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2226074891 Jun 10 06:35:49 PM PDT 24 Jun 10 06:36:08 PM PDT 24 413003473 ps
T829 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1875177456 Jun 10 06:35:35 PM PDT 24 Jun 10 06:35:41 PM PDT 24 250803981 ps
T830 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.311388101 Jun 10 06:35:13 PM PDT 24 Jun 10 06:35:19 PM PDT 24 50163651 ps
T831 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2075298726 Jun 10 06:35:34 PM PDT 24 Jun 10 06:35:36 PM PDT 24 9853958 ps
T832 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4098418265 Jun 10 06:35:47 PM PDT 24 Jun 10 06:35:49 PM PDT 24 17280801 ps

Test location /workspace/coverage/default/38.alert_handler_stress_all.698784869
Short name T1
Test name
Test status
Simulation time 298857881472 ps
CPU time 3961.41 seconds
Started Jun 10 06:39:41 PM PDT 24
Finished Jun 10 07:45:43 PM PDT 24
Peak memory 302104 kb
Host smart-ea071734-18c2-48a6-894b-1c1d8aae0a35
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698784869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.698784869
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3215456506
Short name T32
Test name
Test status
Simulation time 13210902672 ps
CPU time 647.46 seconds
Started Jun 10 06:36:49 PM PDT 24
Finished Jun 10 06:47:37 PM PDT 24
Peak memory 272804 kb
Host smart-2f185a56-549e-4d2c-ac12-c8dcf272a001
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215456506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3215456506
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3069225105
Short name T12
Test name
Test status
Simulation time 1119935430 ps
CPU time 30.42 seconds
Started Jun 10 06:36:39 PM PDT 24
Finished Jun 10 06:37:10 PM PDT 24
Peak memory 270692 kb
Host smart-d2d466ac-24a1-450b-aa75-7f7460e678e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3069225105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3069225105
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.494637639
Short name T27
Test name
Test status
Simulation time 11389529243 ps
CPU time 1160.84 seconds
Started Jun 10 06:36:40 PM PDT 24
Finished Jun 10 06:56:01 PM PDT 24
Peak memory 271420 kb
Host smart-4075662c-5d43-4cf1-8af3-b8a5821794b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494637639 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.494637639
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3036572326
Short name T168
Test name
Test status
Simulation time 4975523012 ps
CPU time 80.78 seconds
Started Jun 10 06:35:50 PM PDT 24
Finished Jun 10 06:37:11 PM PDT 24
Peak memory 238036 kb
Host smart-53b90f72-be6b-46e7-8fa1-4f28711535fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3036572326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3036572326
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3095578251
Short name T7
Test name
Test status
Simulation time 56737221798 ps
CPU time 1690.63 seconds
Started Jun 10 06:38:00 PM PDT 24
Finished Jun 10 07:06:11 PM PDT 24
Peak memory 273300 kb
Host smart-19656512-c4b6-4c9a-8d6a-921f0ab00641
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095578251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3095578251
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2401751878
Short name T60
Test name
Test status
Simulation time 204231588193 ps
CPU time 6282.26 seconds
Started Jun 10 06:36:47 PM PDT 24
Finished Jun 10 08:21:30 PM PDT 24
Peak memory 338872 kb
Host smart-bdf6a6e5-56f4-4e93-a477-257d621e9076
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401751878 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2401751878
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3822560284
Short name T92
Test name
Test status
Simulation time 248927005098 ps
CPU time 3585.7 seconds
Started Jun 10 06:36:56 PM PDT 24
Finished Jun 10 07:36:42 PM PDT 24
Peak memory 288708 kb
Host smart-b17a3b00-8a19-487d-b455-7f70bdbcc5ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822560284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3822560284
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3132310588
Short name T33
Test name
Test status
Simulation time 4045579231 ps
CPU time 227.92 seconds
Started Jun 10 06:37:16 PM PDT 24
Finished Jun 10 06:41:05 PM PDT 24
Peak memory 256908 kb
Host smart-0ee9b7b3-97e5-4a3e-aec3-07acf0c29521
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132310588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3132310588
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2941253643
Short name T122
Test name
Test status
Simulation time 16422568263 ps
CPU time 231.87 seconds
Started Jun 10 06:35:33 PM PDT 24
Finished Jun 10 06:39:25 PM PDT 24
Peak memory 265056 kb
Host smart-62419d9a-b543-42b7-899b-637f4402ca7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2941253643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2941253643
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2346078513
Short name T131
Test name
Test status
Simulation time 250911663013 ps
CPU time 1163.53 seconds
Started Jun 10 06:35:19 PM PDT 24
Finished Jun 10 06:54:43 PM PDT 24
Peak memory 265124 kb
Host smart-e0891df9-89c1-4399-8a0c-12f94e711555
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346078513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2346078513
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3478096387
Short name T17
Test name
Test status
Simulation time 57643129313 ps
CPU time 3721.53 seconds
Started Jun 10 06:36:51 PM PDT 24
Finished Jun 10 07:38:53 PM PDT 24
Peak memory 305368 kb
Host smart-7a209da9-336c-4e8a-a47c-da89fb75a385
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478096387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3478096387
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3661653633
Short name T97
Test name
Test status
Simulation time 10053196103 ps
CPU time 847.53 seconds
Started Jun 10 06:37:16 PM PDT 24
Finished Jun 10 06:51:25 PM PDT 24
Peak memory 273316 kb
Host smart-5f2b0d2e-c758-4af4-95b6-507de71d10ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661653633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3661653633
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2294278449
Short name T141
Test name
Test status
Simulation time 6031424815 ps
CPU time 349.35 seconds
Started Jun 10 06:35:33 PM PDT 24
Finished Jun 10 06:41:23 PM PDT 24
Peak memory 266168 kb
Host smart-a2bd0a88-d5bb-44f3-ab5d-bec5b3678de5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2294278449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2294278449
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2626272482
Short name T259
Test name
Test status
Simulation time 87505782643 ps
CPU time 1869.26 seconds
Started Jun 10 06:37:13 PM PDT 24
Finished Jun 10 07:08:23 PM PDT 24
Peak memory 289748 kb
Host smart-7e2b4f1f-a21d-4704-a7d2-ec6327ac14c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626272482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2626272482
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2153182970
Short name T30
Test name
Test status
Simulation time 208980244633 ps
CPU time 1592.33 seconds
Started Jun 10 06:36:44 PM PDT 24
Finished Jun 10 07:03:17 PM PDT 24
Peak memory 273104 kb
Host smart-200d1bb9-76d5-4b40-a828-c08e9d419596
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153182970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2153182970
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3484817657
Short name T130
Test name
Test status
Simulation time 4918065197 ps
CPU time 656.66 seconds
Started Jun 10 06:35:26 PM PDT 24
Finished Jun 10 06:46:23 PM PDT 24
Peak memory 272900 kb
Host smart-781f651b-1413-45e6-9fc3-f8b67e1f8a8a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484817657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3484817657
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2446440546
Short name T345
Test name
Test status
Simulation time 47842216 ps
CPU time 1.45 seconds
Started Jun 10 06:35:23 PM PDT 24
Finished Jun 10 06:35:24 PM PDT 24
Peak memory 235724 kb
Host smart-a2379755-e907-4a59-9797-927fe9e4a17c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2446440546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2446440546
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2842265619
Short name T10
Test name
Test status
Simulation time 11669121371 ps
CPU time 473.64 seconds
Started Jun 10 06:36:50 PM PDT 24
Finished Jun 10 06:44:45 PM PDT 24
Peak memory 248388 kb
Host smart-95cc1f3b-dec3-4ffc-bbf1-f3bb7900a1c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842265619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2842265619
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.94649598
Short name T281
Test name
Test status
Simulation time 42430282503 ps
CPU time 2398.23 seconds
Started Jun 10 06:38:51 PM PDT 24
Finished Jun 10 07:18:50 PM PDT 24
Peak memory 282576 kb
Host smart-f7e95153-83b3-4d81-b355-f1d129493b0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94649598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.94649598
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.329255412
Short name T58
Test name
Test status
Simulation time 86190556757 ps
CPU time 3637.52 seconds
Started Jun 10 06:37:42 PM PDT 24
Finished Jun 10 07:38:20 PM PDT 24
Peak memory 304900 kb
Host smart-2e86bd3c-ecc9-4e38-853f-6987bb1957d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329255412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.329255412
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1879305728
Short name T140
Test name
Test status
Simulation time 1709226652 ps
CPU time 219.51 seconds
Started Jun 10 06:35:23 PM PDT 24
Finished Jun 10 06:39:03 PM PDT 24
Peak memory 265072 kb
Host smart-9d1c5aa1-c19c-4e09-bcd9-08e30fd18661
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1879305728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1879305728
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.4234813371
Short name T318
Test name
Test status
Simulation time 25892343914 ps
CPU time 527.49 seconds
Started Jun 10 06:40:13 PM PDT 24
Finished Jun 10 06:49:01 PM PDT 24
Peak memory 247932 kb
Host smart-7f90c4df-a806-4b15-b7c1-96fd0e016b1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234813371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.4234813371
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.986115352
Short name T8
Test name
Test status
Simulation time 185232888059 ps
CPU time 3124.16 seconds
Started Jun 10 06:38:02 PM PDT 24
Finished Jun 10 07:30:06 PM PDT 24
Peak memory 289696 kb
Host smart-20b2eed4-9c5c-4719-a3aa-d6db23792946
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986115352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.986115352
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4032598523
Short name T133
Test name
Test status
Simulation time 33654432462 ps
CPU time 636.87 seconds
Started Jun 10 06:35:43 PM PDT 24
Finished Jun 10 06:46:20 PM PDT 24
Peak memory 265132 kb
Host smart-16f17904-48e4-4a12-b688-be3b69a6e7ca
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032598523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4032598523
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1427493328
Short name T5
Test name
Test status
Simulation time 439677073354 ps
CPU time 2541.35 seconds
Started Jun 10 06:36:52 PM PDT 24
Finished Jun 10 07:19:15 PM PDT 24
Peak memory 287164 kb
Host smart-da55b069-2728-4af3-8aa2-a62a8311cf8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427493328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1427493328
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1986984727
Short name T125
Test name
Test status
Simulation time 7267746770 ps
CPU time 182.13 seconds
Started Jun 10 06:35:19 PM PDT 24
Finished Jun 10 06:38:21 PM PDT 24
Peak memory 264944 kb
Host smart-4dab5888-3515-49d5-8ff2-42f2022696a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1986984727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1986984727
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1498032923
Short name T31
Test name
Test status
Simulation time 47099027558 ps
CPU time 2709.53 seconds
Started Jun 10 06:36:46 PM PDT 24
Finished Jun 10 07:21:56 PM PDT 24
Peak memory 289444 kb
Host smart-2fd12249-73b8-465e-8705-cec8a95ad7ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498032923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1498032923
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1347562284
Short name T308
Test name
Test status
Simulation time 17359796483 ps
CPU time 686.29 seconds
Started Jun 10 06:36:47 PM PDT 24
Finished Jun 10 06:48:13 PM PDT 24
Peak memory 255752 kb
Host smart-cb35c333-8cbf-488f-a536-178394077684
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347562284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1347562284
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.578674033
Short name T312
Test name
Test status
Simulation time 33899793687 ps
CPU time 2230.96 seconds
Started Jun 10 06:36:46 PM PDT 24
Finished Jun 10 07:13:58 PM PDT 24
Peak memory 288816 kb
Host smart-b3eda028-b088-4f3d-a5cc-5005b1f788d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578674033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.578674033
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2237248271
Short name T134
Test name
Test status
Simulation time 15893820526 ps
CPU time 1077.29 seconds
Started Jun 10 06:35:37 PM PDT 24
Finished Jun 10 06:53:35 PM PDT 24
Peak memory 265120 kb
Host smart-68ffe11c-36ab-4cfb-9a55-2cca39a892b6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237248271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2237248271
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1897063504
Short name T317
Test name
Test status
Simulation time 44557336904 ps
CPU time 453 seconds
Started Jun 10 06:37:07 PM PDT 24
Finished Jun 10 06:44:40 PM PDT 24
Peak memory 248008 kb
Host smart-973ef748-c588-4c00-b3f3-1daed750c519
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897063504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1897063504
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.273828487
Short name T132
Test name
Test status
Simulation time 6377273882 ps
CPU time 381.92 seconds
Started Jun 10 06:35:47 PM PDT 24
Finished Jun 10 06:42:09 PM PDT 24
Peak memory 265120 kb
Host smart-a6e9e74a-30b2-431b-bfc9-fbbf83c2b6a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=273828487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.273828487
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.85864115
Short name T330
Test name
Test status
Simulation time 53625061184 ps
CPU time 1018.62 seconds
Started Jun 10 06:36:46 PM PDT 24
Finished Jun 10 06:53:45 PM PDT 24
Peak memory 265232 kb
Host smart-bdfa5fdf-b6f5-465a-af89-52e5e5d31cf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85864115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.85864115
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2321413063
Short name T46
Test name
Test status
Simulation time 303818349766 ps
CPU time 4739.67 seconds
Started Jun 10 06:39:02 PM PDT 24
Finished Jun 10 07:58:02 PM PDT 24
Peak memory 321924 kb
Host smart-74f6e563-d77c-4781-aa9a-75fd92b2931d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321413063 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2321413063
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2267932961
Short name T118
Test name
Test status
Simulation time 8252519098 ps
CPU time 471.3 seconds
Started Jun 10 06:35:15 PM PDT 24
Finished Jun 10 06:43:07 PM PDT 24
Peak memory 265208 kb
Host smart-439a89ef-beea-4fd3-8ff0-d783c6ec2e1f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267932961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2267932961
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2483720416
Short name T145
Test name
Test status
Simulation time 3322865051 ps
CPU time 354.38 seconds
Started Jun 10 06:35:22 PM PDT 24
Finished Jun 10 06:41:16 PM PDT 24
Peak memory 265128 kb
Host smart-c73188d4-3039-49d7-a2c6-f3f315561ffe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483720416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2483720416
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2565508037
Short name T494
Test name
Test status
Simulation time 12015188408 ps
CPU time 541.26 seconds
Started Jun 10 06:37:27 PM PDT 24
Finished Jun 10 06:46:29 PM PDT 24
Peak memory 248296 kb
Host smart-2637e248-3aab-4aac-963e-803715f637ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565508037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2565508037
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1046646117
Short name T302
Test name
Test status
Simulation time 7515727675 ps
CPU time 327.31 seconds
Started Jun 10 06:37:54 PM PDT 24
Finished Jun 10 06:43:21 PM PDT 24
Peak memory 248408 kb
Host smart-043fbf2d-4c4c-46b5-8743-353ef8942210
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046646117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1046646117
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1923772259
Short name T258
Test name
Test status
Simulation time 83449494689 ps
CPU time 2250.03 seconds
Started Jun 10 06:40:16 PM PDT 24
Finished Jun 10 07:17:46 PM PDT 24
Peak memory 317068 kb
Host smart-6861a2a2-4f13-4e33-b8ff-3f135292d797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923772259 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1923772259
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2563211289
Short name T54
Test name
Test status
Simulation time 16173258586 ps
CPU time 1286.18 seconds
Started Jun 10 06:37:20 PM PDT 24
Finished Jun 10 06:58:47 PM PDT 24
Peak memory 288856 kb
Host smart-08fb30e8-e49a-4e19-89fa-a88bdd2db284
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563211289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2563211289
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.414358660
Short name T164
Test name
Test status
Simulation time 82706139 ps
CPU time 4.91 seconds
Started Jun 10 06:35:32 PM PDT 24
Finished Jun 10 06:35:37 PM PDT 24
Peak memory 236672 kb
Host smart-14f87f7d-37fb-468d-aac0-2db208fc0467
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=414358660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.414358660
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1748407673
Short name T152
Test name
Test status
Simulation time 5710280530 ps
CPU time 106.96 seconds
Started Jun 10 06:35:37 PM PDT 24
Finished Jun 10 06:37:24 PM PDT 24
Peak memory 267064 kb
Host smart-0b580c7d-6d3e-4f3e-ab3c-67ef0ec2a786
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1748407673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1748407673
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.761904262
Short name T359
Test name
Test status
Simulation time 3476994836 ps
CPU time 25.65 seconds
Started Jun 10 06:37:11 PM PDT 24
Finished Jun 10 06:37:37 PM PDT 24
Peak memory 248732 kb
Host smart-5bb29221-6711-48ac-8974-3b240428c0ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=761904262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.761904262
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.640194615
Short name T711
Test name
Test status
Simulation time 11102546 ps
CPU time 1.33 seconds
Started Jun 10 06:35:59 PM PDT 24
Finished Jun 10 06:36:00 PM PDT 24
Peak memory 235692 kb
Host smart-7c8987db-e14b-48c1-81e5-adfa462d8903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=640194615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.640194615
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2808855146
Short name T216
Test name
Test status
Simulation time 99941838238 ps
CPU time 1517.92 seconds
Started Jun 10 06:37:14 PM PDT 24
Finished Jun 10 07:02:32 PM PDT 24
Peak memory 273284 kb
Host smart-96dfe556-761c-4982-91b3-f994f1e4ebe9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808855146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2808855146
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1098995360
Short name T253
Test name
Test status
Simulation time 166305024647 ps
CPU time 7317.68 seconds
Started Jun 10 06:37:23 PM PDT 24
Finished Jun 10 08:39:21 PM PDT 24
Peak memory 371296 kb
Host smart-267adf16-3b14-4f8e-8bcc-8571fd1120c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098995360 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1098995360
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.820968433
Short name T314
Test name
Test status
Simulation time 48253731369 ps
CPU time 495.51 seconds
Started Jun 10 06:36:45 PM PDT 24
Finished Jun 10 06:45:00 PM PDT 24
Peak memory 248372 kb
Host smart-cbb93811-88b8-461e-9311-b562333050d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820968433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.820968433
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4196716314
Short name T147
Test name
Test status
Simulation time 16610699747 ps
CPU time 351.67 seconds
Started Jun 10 06:35:32 PM PDT 24
Finished Jun 10 06:41:24 PM PDT 24
Peak memory 265220 kb
Host smart-124701af-4fcd-476d-9a94-9eeb09e9f40d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4196716314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.4196716314
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2308378870
Short name T129
Test name
Test status
Simulation time 60527785790 ps
CPU time 597.48 seconds
Started Jun 10 06:35:25 PM PDT 24
Finished Jun 10 06:45:22 PM PDT 24
Peak memory 270092 kb
Host smart-6f14b344-8d3c-4a95-a592-434272ed944c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308378870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2308378870
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1580409070
Short name T153
Test name
Test status
Simulation time 3723980863 ps
CPU time 131.86 seconds
Started Jun 10 06:35:16 PM PDT 24
Finished Jun 10 06:37:28 PM PDT 24
Peak memory 266112 kb
Host smart-863eb588-21d2-4e3a-8ab4-66edf7693fd7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1580409070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1580409070
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2869035267
Short name T215
Test name
Test status
Simulation time 18011437 ps
CPU time 2.83 seconds
Started Jun 10 06:36:45 PM PDT 24
Finished Jun 10 06:36:48 PM PDT 24
Peak memory 248888 kb
Host smart-e11a74fd-1cad-4039-9887-67602c2e0a16
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2869035267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2869035267
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.957635772
Short name T209
Test name
Test status
Simulation time 218490555 ps
CPU time 3.1 seconds
Started Jun 10 06:36:48 PM PDT 24
Finished Jun 10 06:36:51 PM PDT 24
Peak memory 248916 kb
Host smart-7c4924e6-4f34-43ac-bfe5-92e21e1cffe6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=957635772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.957635772
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2815048120
Short name T200
Test name
Test status
Simulation time 15792320 ps
CPU time 2.39 seconds
Started Jun 10 06:37:09 PM PDT 24
Finished Jun 10 06:37:12 PM PDT 24
Peak memory 248924 kb
Host smart-0bd6065d-f0ff-4ea2-931f-ae84f07d8f61
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2815048120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2815048120
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.277183290
Short name T213
Test name
Test status
Simulation time 85816185 ps
CPU time 3.88 seconds
Started Jun 10 06:37:21 PM PDT 24
Finished Jun 10 06:37:25 PM PDT 24
Peak memory 248856 kb
Host smart-f446d1e8-7f6e-41f1-adf1-0c016cb69538
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=277183290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.277183290
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3966535381
Short name T320
Test name
Test status
Simulation time 32389460327 ps
CPU time 331.18 seconds
Started Jun 10 06:36:45 PM PDT 24
Finished Jun 10 06:42:16 PM PDT 24
Peak memory 248232 kb
Host smart-11476af6-1000-45b5-b0d9-90d62891e3fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966535381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3966535381
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1929616005
Short name T262
Test name
Test status
Simulation time 536862739 ps
CPU time 32.24 seconds
Started Jun 10 06:36:53 PM PDT 24
Finished Jun 10 06:37:26 PM PDT 24
Peak memory 255640 kb
Host smart-9bb643b9-03d0-4a9e-b5ae-eed1f3ea8a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19296
16005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1929616005
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1528899136
Short name T100
Test name
Test status
Simulation time 210691963233 ps
CPU time 1329.75 seconds
Started Jun 10 06:37:37 PM PDT 24
Finished Jun 10 06:59:47 PM PDT 24
Peak memory 281640 kb
Host smart-dd1e0f40-dfc7-4b45-a91b-2616ddf70cbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528899136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1528899136
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2850417860
Short name T256
Test name
Test status
Simulation time 377581391 ps
CPU time 23.75 seconds
Started Jun 10 06:38:18 PM PDT 24
Finished Jun 10 06:38:42 PM PDT 24
Peak memory 248740 kb
Host smart-e5a3f079-7769-4f21-bc38-bea67cabdded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28504
17860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2850417860
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2763221759
Short name T575
Test name
Test status
Simulation time 46669846658 ps
CPU time 2756.45 seconds
Started Jun 10 06:39:33 PM PDT 24
Finished Jun 10 07:25:30 PM PDT 24
Peak memory 287860 kb
Host smart-fd3c508c-6c4a-4482-94d7-31f59a34b5ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763221759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2763221759
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2314815800
Short name T104
Test name
Test status
Simulation time 356785949611 ps
CPU time 2871.28 seconds
Started Jun 10 06:40:24 PM PDT 24
Finished Jun 10 07:28:16 PM PDT 24
Peak memory 306192 kb
Host smart-aae8fff5-66b7-49a2-a43d-693232630d01
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314815800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2314815800
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.474270615
Short name T135
Test name
Test status
Simulation time 7360078269 ps
CPU time 167.53 seconds
Started Jun 10 06:35:34 PM PDT 24
Finished Jun 10 06:38:21 PM PDT 24
Peak memory 265124 kb
Host smart-3fa1e3b4-ea27-4c94-acff-c011c64f87c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=474270615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.474270615
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.828871990
Short name T128
Test name
Test status
Simulation time 83922778679 ps
CPU time 651.32 seconds
Started Jun 10 06:35:26 PM PDT 24
Finished Jun 10 06:46:18 PM PDT 24
Peak memory 265112 kb
Host smart-60b739da-2082-48a9-9e09-bae3562d81fe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828871990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.828871990
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.233208663
Short name T273
Test name
Test status
Simulation time 192593489 ps
CPU time 23.53 seconds
Started Jun 10 06:36:46 PM PDT 24
Finished Jun 10 06:37:10 PM PDT 24
Peak memory 248488 kb
Host smart-cd5f971e-9866-4cea-932c-03d218e6b5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23320
8663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.233208663
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.4195901955
Short name T288
Test name
Test status
Simulation time 108416522616 ps
CPU time 3427.62 seconds
Started Jun 10 06:36:52 PM PDT 24
Finished Jun 10 07:34:01 PM PDT 24
Peak memory 305500 kb
Host smart-c7e3d571-16c6-4e25-b049-936c76da1b25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195901955 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.4195901955
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.4181147068
Short name T101
Test name
Test status
Simulation time 207815070770 ps
CPU time 3556.26 seconds
Started Jun 10 06:36:50 PM PDT 24
Finished Jun 10 07:36:08 PM PDT 24
Peak memory 289000 kb
Host smart-c5bed7e0-ab30-49ce-89ae-480bfeff98f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181147068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.4181147068
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.347256662
Short name T245
Test name
Test status
Simulation time 18085466805 ps
CPU time 1424.35 seconds
Started Jun 10 06:37:07 PM PDT 24
Finished Jun 10 07:00:52 PM PDT 24
Peak memory 289112 kb
Host smart-da357d23-3af1-4909-bc08-0a32c24b2443
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347256662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.347256662
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2682683501
Short name T521
Test name
Test status
Simulation time 34667297220 ps
CPU time 915.49 seconds
Started Jun 10 06:37:06 PM PDT 24
Finished Jun 10 06:52:21 PM PDT 24
Peak memory 288572 kb
Host smart-c940a8b3-99ee-4940-b8c7-8ca973d971ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682683501 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2682683501
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1745962260
Short name T291
Test name
Test status
Simulation time 8136976119 ps
CPU time 920.23 seconds
Started Jun 10 06:37:31 PM PDT 24
Finished Jun 10 06:52:52 PM PDT 24
Peak memory 273432 kb
Host smart-8bb50839-86e6-4cde-9aff-c4597fc3e668
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745962260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1745962260
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2645403468
Short name T272
Test name
Test status
Simulation time 679441659 ps
CPU time 37.72 seconds
Started Jun 10 06:37:31 PM PDT 24
Finished Jun 10 06:38:09 PM PDT 24
Peak memory 255884 kb
Host smart-4dbf441f-172d-4449-ada2-8023ecd39d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26454
03468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2645403468
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2723902739
Short name T278
Test name
Test status
Simulation time 388895854 ps
CPU time 25.92 seconds
Started Jun 10 06:37:26 PM PDT 24
Finished Jun 10 06:37:52 PM PDT 24
Peak memory 256848 kb
Host smart-b75b2329-39b8-4f9d-b70b-568283ffa2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27239
02739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2723902739
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3409273951
Short name T276
Test name
Test status
Simulation time 19704302020 ps
CPU time 1381.91 seconds
Started Jun 10 06:38:04 PM PDT 24
Finished Jun 10 07:01:06 PM PDT 24
Peak memory 283760 kb
Host smart-a10ce905-c7a4-4679-bbcd-6096467871ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409273951 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3409273951
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.4113113504
Short name T266
Test name
Test status
Simulation time 11550093521 ps
CPU time 732.84 seconds
Started Jun 10 06:36:44 PM PDT 24
Finished Jun 10 06:48:57 PM PDT 24
Peak memory 265220 kb
Host smart-9bfc4389-1669-4a34-b668-9a0966302784
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113113504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.4113113504
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2709289930
Short name T284
Test name
Test status
Simulation time 91777706286 ps
CPU time 699.33 seconds
Started Jun 10 06:38:40 PM PDT 24
Finished Jun 10 06:50:20 PM PDT 24
Peak memory 248108 kb
Host smart-c38f6d6c-6c90-46f2-b026-2cb9c095775d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709289930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2709289930
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2967765009
Short name T290
Test name
Test status
Simulation time 16962056490 ps
CPU time 1159.47 seconds
Started Jun 10 06:38:41 PM PDT 24
Finished Jun 10 06:58:01 PM PDT 24
Peak memory 282256 kb
Host smart-2572720b-624b-4164-b418-da8562611936
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967765009 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2967765009
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2954613423
Short name T294
Test name
Test status
Simulation time 832500204 ps
CPU time 39.24 seconds
Started Jun 10 06:38:46 PM PDT 24
Finished Jun 10 06:39:26 PM PDT 24
Peak memory 248864 kb
Host smart-b47546db-9685-449c-95df-674583884698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29546
13423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2954613423
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1884568410
Short name T113
Test name
Test status
Simulation time 228476006 ps
CPU time 17.92 seconds
Started Jun 10 06:38:50 PM PDT 24
Finished Jun 10 06:39:08 PM PDT 24
Peak memory 247532 kb
Host smart-0227a7e4-c1ed-45cb-a771-74f18e444b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18845
68410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1884568410
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.694715959
Short name T295
Test name
Test status
Simulation time 29822504665 ps
CPU time 2031.97 seconds
Started Jun 10 06:39:03 PM PDT 24
Finished Jun 10 07:12:56 PM PDT 24
Peak memory 289644 kb
Host smart-cf5302e0-e653-4f48-8bba-51ab8d1de47a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694715959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.694715959
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.961169035
Short name T279
Test name
Test status
Simulation time 153820844977 ps
CPU time 2273.86 seconds
Started Jun 10 06:39:58 PM PDT 24
Finished Jun 10 07:17:53 PM PDT 24
Peak memory 286896 kb
Host smart-052d8f35-3cab-4ca9-bc03-9814946652ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961169035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.961169035
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3241754936
Short name T64
Test name
Test status
Simulation time 46752536236 ps
CPU time 3789.77 seconds
Started Jun 10 06:41:17 PM PDT 24
Finished Jun 10 07:44:27 PM PDT 24
Peak memory 305696 kb
Host smart-178b50f8-e9d7-45a1-a806-b559dbfbe089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241754936 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3241754936
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.748074832
Short name T59
Test name
Test status
Simulation time 44992180063 ps
CPU time 2663.43 seconds
Started Jun 10 06:37:02 PM PDT 24
Finished Jun 10 07:21:26 PM PDT 24
Peak memory 289508 kb
Host smart-c57a0ae2-e147-4053-b4c6-e21aa21bbc3b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748074832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.748074832
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.681255719
Short name T167
Test name
Test status
Simulation time 54073958 ps
CPU time 4.1 seconds
Started Jun 10 06:35:41 PM PDT 24
Finished Jun 10 06:35:45 PM PDT 24
Peak memory 236580 kb
Host smart-24699dcf-d244-470c-af4f-f7e7d317f5d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=681255719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.681255719
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2039654007
Short name T161
Test name
Test status
Simulation time 13756855120 ps
CPU time 79.69 seconds
Started Jun 10 06:35:45 PM PDT 24
Finished Jun 10 06:37:05 PM PDT 24
Peak memory 240052 kb
Host smart-edd7145f-39be-4c45-a92e-9f71c851dc4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2039654007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2039654007
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.4156293847
Short name T137
Test name
Test status
Simulation time 15431891983 ps
CPU time 611.7 seconds
Started Jun 10 06:35:45 PM PDT 24
Finished Jun 10 06:45:57 PM PDT 24
Peak memory 272404 kb
Host smart-3006391d-a268-486b-9dea-2bedb25de968
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156293847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.4156293847
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2144299193
Short name T165
Test name
Test status
Simulation time 309819530 ps
CPU time 3.66 seconds
Started Jun 10 06:35:17 PM PDT 24
Finished Jun 10 06:35:21 PM PDT 24
Peak memory 236860 kb
Host smart-7bdc877c-272d-462b-ac9d-853cf8a4ed14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2144299193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2144299193
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3328941816
Short name T171
Test name
Test status
Simulation time 2458932278 ps
CPU time 40.18 seconds
Started Jun 10 06:35:19 PM PDT 24
Finished Jun 10 06:35:59 PM PDT 24
Peak memory 236852 kb
Host smart-068e202c-be06-4f2d-b6bb-fe7f11e232d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3328941816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3328941816
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.423564408
Short name T170
Test name
Test status
Simulation time 1204214331 ps
CPU time 40.68 seconds
Started Jun 10 06:35:28 PM PDT 24
Finished Jun 10 06:36:09 PM PDT 24
Peak memory 248280 kb
Host smart-26a41d10-2336-4621-b7cd-67a8ba6ef9d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=423564408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.423564408
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2831115524
Short name T166
Test name
Test status
Simulation time 144621314 ps
CPU time 6.93 seconds
Started Jun 10 06:35:38 PM PDT 24
Finished Jun 10 06:35:45 PM PDT 24
Peak memory 236868 kb
Host smart-14967f88-b1ff-4a70-8d7e-40a6f79dd02f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2831115524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2831115524
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2506893432
Short name T816
Test name
Test status
Simulation time 20316279421 ps
CPU time 203.88 seconds
Started Jun 10 06:35:20 PM PDT 24
Finished Jun 10 06:38:44 PM PDT 24
Peak memory 265136 kb
Host smart-82c2cf4b-7044-4eb1-8310-4f64e6935ce9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2506893432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2506893432
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4113384477
Short name T155
Test name
Test status
Simulation time 78210870 ps
CPU time 5.34 seconds
Started Jun 10 06:35:42 PM PDT 24
Finished Jun 10 06:35:47 PM PDT 24
Peak memory 236880 kb
Host smart-cc8d0c50-5422-4b5a-bfe8-f6039e8d4fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4113384477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.4113384477
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3794779753
Short name T151
Test name
Test status
Simulation time 19201182712 ps
CPU time 165.34 seconds
Started Jun 10 06:35:39 PM PDT 24
Finished Jun 10 06:38:25 PM PDT 24
Peak memory 265016 kb
Host smart-11384f78-f99d-40a2-bcff-a1edb4968100
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3794779753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3794779753
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.913602651
Short name T157
Test name
Test status
Simulation time 280835070 ps
CPU time 11.39 seconds
Started Jun 10 06:35:27 PM PDT 24
Finished Jun 10 06:35:38 PM PDT 24
Peak memory 236660 kb
Host smart-9b725b43-5a87-4eec-8eb8-edc9a46b12e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=913602651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.913602651
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3715757141
Short name T156
Test name
Test status
Simulation time 1311665328 ps
CPU time 22.67 seconds
Started Jun 10 06:35:47 PM PDT 24
Finished Jun 10 06:36:10 PM PDT 24
Peak memory 239940 kb
Host smart-0b6a6cd3-c1c3-448c-8d23-b599b7b71138
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3715757141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3715757141
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1036755589
Short name T172
Test name
Test status
Simulation time 224737865 ps
CPU time 4.28 seconds
Started Jun 10 06:35:37 PM PDT 24
Finished Jun 10 06:35:42 PM PDT 24
Peak memory 236684 kb
Host smart-7dc9886c-c2f9-4972-861b-c9c40062cb82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1036755589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1036755589
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1571609532
Short name T173
Test name
Test status
Simulation time 106823953 ps
CPU time 4.04 seconds
Started Jun 10 06:35:49 PM PDT 24
Finished Jun 10 06:35:54 PM PDT 24
Peak memory 236752 kb
Host smart-52fac49d-14c0-4413-a28e-57bf1ebd9020
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1571609532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1571609532
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.101291883
Short name T169
Test name
Test status
Simulation time 107779784 ps
CPU time 3.16 seconds
Started Jun 10 06:35:18 PM PDT 24
Finished Jun 10 06:35:22 PM PDT 24
Peak memory 236876 kb
Host smart-f48a5755-a5ed-46c5-90b3-8fe32ab91a57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=101291883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.101291883
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2571195939
Short name T162
Test name
Test status
Simulation time 1848791858 ps
CPU time 30.06 seconds
Started Jun 10 06:35:29 PM PDT 24
Finished Jun 10 06:35:59 PM PDT 24
Peak memory 236900 kb
Host smart-1f44ebc6-dcb6-42b8-9dff-ad22aa77d340
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2571195939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2571195939
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.481394095
Short name T24
Test name
Test status
Simulation time 33665983397 ps
CPU time 844.43 seconds
Started Jun 10 06:37:08 PM PDT 24
Finished Jun 10 06:51:13 PM PDT 24
Peak memory 272804 kb
Host smart-7f767ccf-a166-4a78-bd14-c4aa82f7173b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481394095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.481394095
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1490657683
Short name T28
Test name
Test status
Simulation time 222612133656 ps
CPU time 3718.36 seconds
Started Jun 10 06:39:07 PM PDT 24
Finished Jun 10 07:41:06 PM PDT 24
Peak memory 281868 kb
Host smart-3c4d014d-12eb-434f-b1d3-e63ba80e5b75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490657683 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1490657683
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1505150296
Short name T23
Test name
Test status
Simulation time 26904981548 ps
CPU time 927.24 seconds
Started Jun 10 06:41:19 PM PDT 24
Finished Jun 10 06:56:46 PM PDT 24
Peak memory 273252 kb
Host smart-06dc8f40-a4e2-4b24-af20-88841c319411
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505150296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1505150296
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.203088760
Short name T817
Test name
Test status
Simulation time 3970106921 ps
CPU time 265.38 seconds
Started Jun 10 06:35:14 PM PDT 24
Finished Jun 10 06:39:40 PM PDT 24
Peak memory 240196 kb
Host smart-e46486f9-535c-447c-a301-d48b0190cdcb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=203088760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.203088760
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.4292340624
Short name T749
Test name
Test status
Simulation time 56968224082 ps
CPU time 378.73 seconds
Started Jun 10 06:35:13 PM PDT 24
Finished Jun 10 06:41:32 PM PDT 24
Peak memory 236724 kb
Host smart-cb7d7508-c1e8-4342-9ee0-8ab60f0c8a5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4292340624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.4292340624
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2274649627
Short name T827
Test name
Test status
Simulation time 289329179 ps
CPU time 5.91 seconds
Started Jun 10 06:35:20 PM PDT 24
Finished Jun 10 06:35:26 PM PDT 24
Peak memory 240108 kb
Host smart-eb80090c-540e-46f7-ab4b-6a5a8d226219
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2274649627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2274649627
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.428240431
Short name T759
Test name
Test status
Simulation time 89881989 ps
CPU time 5.59 seconds
Started Jun 10 06:35:21 PM PDT 24
Finished Jun 10 06:35:27 PM PDT 24
Peak memory 239652 kb
Host smart-3c7c56d8-2f14-4da9-aaf9-99507563bf30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428240431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.428240431
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2579524329
Short name T248
Test name
Test status
Simulation time 68924286 ps
CPU time 5.46 seconds
Started Jun 10 06:35:16 PM PDT 24
Finished Jun 10 06:35:22 PM PDT 24
Peak memory 236680 kb
Host smart-141bde4c-05d3-4d07-8457-4578ac59a7d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2579524329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2579524329
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1879252624
Short name T796
Test name
Test status
Simulation time 9174082 ps
CPU time 1.58 seconds
Started Jun 10 06:35:16 PM PDT 24
Finished Jun 10 06:35:18 PM PDT 24
Peak memory 234748 kb
Host smart-3973e7c7-e54a-4169-be1a-ed39909468d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1879252624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1879252624
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.184351108
Short name T772
Test name
Test status
Simulation time 1386298025 ps
CPU time 41.1 seconds
Started Jun 10 06:35:20 PM PDT 24
Finished Jun 10 06:36:01 PM PDT 24
Peak memory 248308 kb
Host smart-2424babe-4ec0-4681-b2ef-64c77e483c33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=184351108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.184351108
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.126905483
Short name T792
Test name
Test status
Simulation time 34012131 ps
CPU time 4.96 seconds
Started Jun 10 06:35:10 PM PDT 24
Finished Jun 10 06:35:15 PM PDT 24
Peak memory 248240 kb
Host smart-93ee1520-d53d-4ce4-b010-33e549f8d532
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=126905483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.126905483
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3956107365
Short name T194
Test name
Test status
Simulation time 58826834 ps
CPU time 2.24 seconds
Started Jun 10 06:35:15 PM PDT 24
Finished Jun 10 06:35:18 PM PDT 24
Peak memory 236700 kb
Host smart-6aa6d9a0-9d60-496e-b55e-f3879161cd20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3956107365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3956107365
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.947095697
Short name T188
Test name
Test status
Simulation time 1116479978 ps
CPU time 165.78 seconds
Started Jun 10 06:35:18 PM PDT 24
Finished Jun 10 06:38:04 PM PDT 24
Peak memory 240060 kb
Host smart-40309f76-c130-4dae-b206-2e541086491d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=947095697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.947095697
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1409170764
Short name T803
Test name
Test status
Simulation time 4774411412 ps
CPU time 258.85 seconds
Started Jun 10 06:35:21 PM PDT 24
Finished Jun 10 06:39:40 PM PDT 24
Peak memory 236756 kb
Host smart-18130c1d-96ac-47b6-a0e8-494c5c733166
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1409170764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1409170764
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2279121673
Short name T773
Test name
Test status
Simulation time 43022457 ps
CPU time 4.02 seconds
Started Jun 10 06:35:16 PM PDT 24
Finished Jun 10 06:35:20 PM PDT 24
Peak memory 240060 kb
Host smart-84a43351-1e9e-4d7a-b3be-eaaacaf23056
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2279121673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2279121673
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3828702491
Short name T196
Test name
Test status
Simulation time 78503138 ps
CPU time 7.35 seconds
Started Jun 10 06:35:19 PM PDT 24
Finished Jun 10 06:35:26 PM PDT 24
Peak memory 239692 kb
Host smart-0097daeb-0e6d-4bca-bca1-ef2d48e4e404
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828702491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3828702491
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.311388101
Short name T830
Test name
Test status
Simulation time 50163651 ps
CPU time 5.1 seconds
Started Jun 10 06:35:13 PM PDT 24
Finished Jun 10 06:35:19 PM PDT 24
Peak memory 239416 kb
Host smart-1fad7d8c-2fac-435e-bf2e-ec902d066724
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=311388101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.311388101
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.751625813
Short name T721
Test name
Test status
Simulation time 21532716 ps
CPU time 1.37 seconds
Started Jun 10 06:35:14 PM PDT 24
Finished Jun 10 06:35:15 PM PDT 24
Peak memory 236676 kb
Host smart-d2636c70-06d2-4461-8fe3-82b052b86788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=751625813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.751625813
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1327335869
Short name T185
Test name
Test status
Simulation time 351594068 ps
CPU time 12.4 seconds
Started Jun 10 06:35:18 PM PDT 24
Finished Jun 10 06:35:31 PM PDT 24
Peak memory 244868 kb
Host smart-ebb67a1f-1148-464b-ae52-8dd2c503a6f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1327335869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1327335869
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1879520466
Short name T727
Test name
Test status
Simulation time 737063494 ps
CPU time 6.61 seconds
Started Jun 10 06:35:16 PM PDT 24
Finished Jun 10 06:35:23 PM PDT 24
Peak memory 248396 kb
Host smart-fb1aa143-d5e9-462d-8908-854a6bd848b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1879520466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1879520466
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2869845167
Short name T718
Test name
Test status
Simulation time 123271904 ps
CPU time 11.19 seconds
Started Jun 10 06:35:52 PM PDT 24
Finished Jun 10 06:36:04 PM PDT 24
Peak memory 242128 kb
Host smart-ff7e674e-169e-4959-bb3e-8f490c83b809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869845167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2869845167
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3950048073
Short name T790
Test name
Test status
Simulation time 73545968 ps
CPU time 4.46 seconds
Started Jun 10 06:35:32 PM PDT 24
Finished Jun 10 06:35:37 PM PDT 24
Peak memory 239448 kb
Host smart-818392a1-dab8-43a4-a9d6-ec93a0cc7fc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3950048073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3950048073
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.240887607
Short name T807
Test name
Test status
Simulation time 10152570 ps
CPU time 1.31 seconds
Started Jun 10 06:35:30 PM PDT 24
Finished Jun 10 06:35:32 PM PDT 24
Peak memory 235740 kb
Host smart-2270375d-0ad8-4683-95b0-85cbf129bc40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=240887607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.240887607
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2330102922
Short name T770
Test name
Test status
Simulation time 634323766 ps
CPU time 40.74 seconds
Started Jun 10 06:35:43 PM PDT 24
Finished Jun 10 06:36:24 PM PDT 24
Peak memory 243924 kb
Host smart-8bf77232-9650-4d04-91c2-2c14233cc7d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2330102922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2330102922
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2692025060
Short name T350
Test name
Test status
Simulation time 2196654042 ps
CPU time 287.13 seconds
Started Jun 10 06:35:50 PM PDT 24
Finished Jun 10 06:40:38 PM PDT 24
Peak memory 268216 kb
Host smart-53b6c9a9-184c-4c9d-9290-2468d9bb0dd4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692025060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2692025060
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2160620678
Short name T785
Test name
Test status
Simulation time 554659055 ps
CPU time 9.04 seconds
Started Jun 10 06:35:41 PM PDT 24
Finished Jun 10 06:35:50 PM PDT 24
Peak memory 248356 kb
Host smart-ede025e0-0ba5-4324-939d-114507f7a52d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2160620678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2160620678
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3125005127
Short name T723
Test name
Test status
Simulation time 55889325 ps
CPU time 4.97 seconds
Started Jun 10 06:35:34 PM PDT 24
Finished Jun 10 06:35:39 PM PDT 24
Peak memory 238684 kb
Host smart-146bd2f9-5223-4203-aa1f-67cd5821e2df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125005127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3125005127
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2183989545
Short name T820
Test name
Test status
Simulation time 99256841 ps
CPU time 8.5 seconds
Started Jun 10 06:35:41 PM PDT 24
Finished Jun 10 06:35:49 PM PDT 24
Peak memory 240064 kb
Host smart-f1af6b4a-7528-4013-952d-015709e8209d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2183989545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2183989545
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2319312750
Short name T736
Test name
Test status
Simulation time 61553756 ps
CPU time 1.39 seconds
Started Jun 10 06:35:39 PM PDT 24
Finished Jun 10 06:35:40 PM PDT 24
Peak memory 235760 kb
Host smart-fcc0360b-7d67-48f2-a9c9-903d0f5d79e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2319312750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2319312750
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3603398329
Short name T745
Test name
Test status
Simulation time 683984953 ps
CPU time 24.64 seconds
Started Jun 10 06:35:34 PM PDT 24
Finished Jun 10 06:35:59 PM PDT 24
Peak memory 244856 kb
Host smart-2867a81d-ebb6-4d8c-9ae5-2bdacb0149a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3603398329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3603398329
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2303535261
Short name T710
Test name
Test status
Simulation time 916076803 ps
CPU time 15.8 seconds
Started Jun 10 06:35:43 PM PDT 24
Finished Jun 10 06:35:59 PM PDT 24
Peak memory 247504 kb
Host smart-643bd135-e0ca-4a0c-8da8-190a36e73d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2303535261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2303535261
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3998996130
Short name T812
Test name
Test status
Simulation time 179694955 ps
CPU time 6.38 seconds
Started Jun 10 06:35:46 PM PDT 24
Finished Jun 10 06:35:53 PM PDT 24
Peak memory 249340 kb
Host smart-50a6ceb6-dc04-4169-9d7b-b08e6450b7ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998996130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3998996130
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1597312316
Short name T174
Test name
Test status
Simulation time 92435093 ps
CPU time 7.76 seconds
Started Jun 10 06:35:47 PM PDT 24
Finished Jun 10 06:35:55 PM PDT 24
Peak memory 240032 kb
Host smart-038c2210-1eb2-45b2-90ed-23d00657d772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1597312316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1597312316
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2075298726
Short name T831
Test name
Test status
Simulation time 9853958 ps
CPU time 1.39 seconds
Started Jun 10 06:35:34 PM PDT 24
Finished Jun 10 06:35:36 PM PDT 24
Peak memory 236712 kb
Host smart-470cea58-0657-4fe9-bbf3-45ba08f67540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2075298726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2075298726
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.975120352
Short name T190
Test name
Test status
Simulation time 299600169 ps
CPU time 20.07 seconds
Started Jun 10 06:35:33 PM PDT 24
Finished Jun 10 06:35:54 PM PDT 24
Peak memory 243952 kb
Host smart-d0b66a22-ccf8-427d-9717-d1f26bf0cd6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=975120352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.975120352
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2951863013
Short name T146
Test name
Test status
Simulation time 19997993706 ps
CPU time 360.78 seconds
Started Jun 10 06:35:36 PM PDT 24
Finished Jun 10 06:41:37 PM PDT 24
Peak memory 265216 kb
Host smart-ee701605-0a28-4847-be75-da884e9f1a6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2951863013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2951863013
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1081253241
Short name T351
Test name
Test status
Simulation time 25422102253 ps
CPU time 554.32 seconds
Started Jun 10 06:35:39 PM PDT 24
Finished Jun 10 06:44:53 PM PDT 24
Peak memory 265020 kb
Host smart-c67c6f45-f7b1-4ef4-be6f-90050e8a6ef7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081253241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1081253241
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3006605184
Short name T709
Test name
Test status
Simulation time 297571621 ps
CPU time 20.24 seconds
Started Jun 10 06:35:35 PM PDT 24
Finished Jun 10 06:35:55 PM PDT 24
Peak memory 248388 kb
Host smart-46b0bf80-7856-4a8b-8857-0cd922b511cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3006605184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3006605184
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3083551583
Short name T761
Test name
Test status
Simulation time 393797843 ps
CPU time 7.72 seconds
Started Jun 10 06:35:49 PM PDT 24
Finished Jun 10 06:35:57 PM PDT 24
Peak memory 240144 kb
Host smart-291b7686-9395-4f07-940b-387871639dd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083551583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3083551583
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1093230973
Short name T187
Test name
Test status
Simulation time 19654094 ps
CPU time 3.51 seconds
Started Jun 10 06:35:37 PM PDT 24
Finished Jun 10 06:35:40 PM PDT 24
Peak memory 235700 kb
Host smart-4e7de524-1aec-485d-ba7a-7683392192b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1093230973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1093230973
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.609546410
Short name T765
Test name
Test status
Simulation time 16345509 ps
CPU time 1.53 seconds
Started Jun 10 06:35:36 PM PDT 24
Finished Jun 10 06:35:37 PM PDT 24
Peak memory 236648 kb
Host smart-15606e24-f9cc-4cc9-a1a8-c0487b5daaec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=609546410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.609546410
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.141375747
Short name T811
Test name
Test status
Simulation time 1944982018 ps
CPU time 33.24 seconds
Started Jun 10 06:35:46 PM PDT 24
Finished Jun 10 06:36:20 PM PDT 24
Peak memory 248236 kb
Host smart-a45cba6b-4083-413d-8a71-ac9c451390f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=141375747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.141375747
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.146788112
Short name T126
Test name
Test status
Simulation time 1464971611 ps
CPU time 86.45 seconds
Started Jun 10 06:35:48 PM PDT 24
Finished Jun 10 06:37:15 PM PDT 24
Peak memory 256812 kb
Host smart-8f715678-2b60-43bc-9799-2b8e0a3d10c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=146788112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.146788112
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3736420477
Short name T142
Test name
Test status
Simulation time 2190685641 ps
CPU time 307.77 seconds
Started Jun 10 06:35:35 PM PDT 24
Finished Jun 10 06:40:43 PM PDT 24
Peak memory 265076 kb
Host smart-e7520aa7-1ec6-4884-b641-cc7975e7d88f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736420477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3736420477
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2647213596
Short name T742
Test name
Test status
Simulation time 1971381128 ps
CPU time 11.09 seconds
Started Jun 10 06:35:50 PM PDT 24
Finished Jun 10 06:36:01 PM PDT 24
Peak memory 247340 kb
Host smart-001fc738-f263-489d-a765-f5d80ba37f77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2647213596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2647213596
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4016834199
Short name T352
Test name
Test status
Simulation time 59680012 ps
CPU time 5.67 seconds
Started Jun 10 06:35:38 PM PDT 24
Finished Jun 10 06:35:43 PM PDT 24
Peak memory 239188 kb
Host smart-a23fcd76-53a0-48b4-a596-523f3cc7aca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016834199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.4016834199
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3676997335
Short name T786
Test name
Test status
Simulation time 500606079 ps
CPU time 9.35 seconds
Started Jun 10 06:35:36 PM PDT 24
Finished Jun 10 06:35:45 PM PDT 24
Peak memory 240052 kb
Host smart-145a208d-b720-4964-9971-8cea0dc8161b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3676997335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3676997335
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.800942057
Short name T160
Test name
Test status
Simulation time 12302348 ps
CPU time 1.34 seconds
Started Jun 10 06:35:49 PM PDT 24
Finished Jun 10 06:35:51 PM PDT 24
Peak memory 236672 kb
Host smart-be47e48b-7bd8-46fa-a531-f1d35b0ae655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=800942057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.800942057
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2376933413
Short name T798
Test name
Test status
Simulation time 910892045 ps
CPU time 13.59 seconds
Started Jun 10 06:35:49 PM PDT 24
Finished Jun 10 06:36:03 PM PDT 24
Peak memory 240064 kb
Host smart-6b714fd3-d875-4d32-95cd-d2d88395dee9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2376933413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2376933413
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1889717512
Short name T136
Test name
Test status
Simulation time 751073552 ps
CPU time 97.95 seconds
Started Jun 10 06:35:37 PM PDT 24
Finished Jun 10 06:37:15 PM PDT 24
Peak memory 256948 kb
Host smart-36e937f0-429c-43d8-b711-16d763abc7ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1889717512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1889717512
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3954649002
Short name T139
Test name
Test status
Simulation time 6385978589 ps
CPU time 455.72 seconds
Started Jun 10 06:35:35 PM PDT 24
Finished Jun 10 06:43:11 PM PDT 24
Peak memory 269200 kb
Host smart-53b917ce-003f-46ff-945b-afdf3376c727
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954649002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3954649002
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2854013928
Short name T781
Test name
Test status
Simulation time 304243875 ps
CPU time 19.23 seconds
Started Jun 10 06:35:35 PM PDT 24
Finished Jun 10 06:35:55 PM PDT 24
Peak memory 248348 kb
Host smart-e6adead2-8716-4661-9bdc-602f3ef2b14e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2854013928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2854013928
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2376931374
Short name T719
Test name
Test status
Simulation time 460716919 ps
CPU time 34.52 seconds
Started Jun 10 06:35:37 PM PDT 24
Finished Jun 10 06:36:12 PM PDT 24
Peak memory 248396 kb
Host smart-a306e61c-2ce0-47d2-b55b-80cde89875a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2376931374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2376931374
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.18632650
Short name T788
Test name
Test status
Simulation time 54364641 ps
CPU time 4.64 seconds
Started Jun 10 06:35:49 PM PDT 24
Finished Jun 10 06:35:54 PM PDT 24
Peak memory 240168 kb
Host smart-b0e6cdd5-28b0-45bb-a6b0-da219ed1d13b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18632650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.alert_handler_csr_mem_rw_with_rand_reset.18632650
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.4213459998
Short name T764
Test name
Test status
Simulation time 741466993 ps
CPU time 7.82 seconds
Started Jun 10 06:35:48 PM PDT 24
Finished Jun 10 06:35:56 PM PDT 24
Peak memory 236664 kb
Host smart-dfa362cd-548f-422e-8593-c3a171ba12d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4213459998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.4213459998
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1884701951
Short name T720
Test name
Test status
Simulation time 9680973 ps
CPU time 1.43 seconds
Started Jun 10 06:35:36 PM PDT 24
Finished Jun 10 06:35:38 PM PDT 24
Peak memory 236692 kb
Host smart-71940bbb-d300-41ee-9ec2-bf2258194a92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1884701951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1884701951
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3644855583
Short name T733
Test name
Test status
Simulation time 92822524 ps
CPU time 11.68 seconds
Started Jun 10 06:35:37 PM PDT 24
Finished Jun 10 06:35:49 PM PDT 24
Peak memory 244876 kb
Host smart-032ecfe3-2420-466d-b8d3-89433d42aa52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3644855583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3644855583
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3266611036
Short name T809
Test name
Test status
Simulation time 315881897 ps
CPU time 21.45 seconds
Started Jun 10 06:35:38 PM PDT 24
Finished Jun 10 06:36:00 PM PDT 24
Peak memory 251456 kb
Host smart-0befed40-37ba-4f92-81b1-42f77e2c5a89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3266611036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3266611036
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1507478248
Short name T163
Test name
Test status
Simulation time 111797316 ps
CPU time 2.48 seconds
Started Jun 10 06:35:49 PM PDT 24
Finished Jun 10 06:35:52 PM PDT 24
Peak memory 236680 kb
Host smart-2e2a52a6-2a06-4103-87e7-d300eeef8ac7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1507478248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1507478248
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3218859763
Short name T738
Test name
Test status
Simulation time 167687193 ps
CPU time 11.3 seconds
Started Jun 10 06:35:46 PM PDT 24
Finished Jun 10 06:35:57 PM PDT 24
Peak memory 255136 kb
Host smart-07d0c75f-3057-4eb1-b3d0-3254ff9e493c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218859763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3218859763
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3786742349
Short name T186
Test name
Test status
Simulation time 69486594 ps
CPU time 5.43 seconds
Started Jun 10 06:35:50 PM PDT 24
Finished Jun 10 06:35:56 PM PDT 24
Peak memory 236624 kb
Host smart-688d1fe9-373b-4819-b1e9-663b34124ec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3786742349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3786742349
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2582101694
Short name T780
Test name
Test status
Simulation time 70844323 ps
CPU time 1.38 seconds
Started Jun 10 06:35:53 PM PDT 24
Finished Jun 10 06:35:54 PM PDT 24
Peak memory 235648 kb
Host smart-e200ea52-3e15-4515-af89-2ff68fc004e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2582101694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2582101694
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1883334730
Short name T189
Test name
Test status
Simulation time 720915067 ps
CPU time 23.88 seconds
Started Jun 10 06:35:37 PM PDT 24
Finished Jun 10 06:36:01 PM PDT 24
Peak memory 244888 kb
Host smart-364cc3f3-89b1-4be9-b5ea-25fe1ceb2c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1883334730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1883334730
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4237821176
Short name T120
Test name
Test status
Simulation time 2219174584 ps
CPU time 321.07 seconds
Started Jun 10 06:35:50 PM PDT 24
Finished Jun 10 06:41:12 PM PDT 24
Peak memory 267648 kb
Host smart-d10decf6-a35e-4fc6-8252-0bb0befd6eb3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237821176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.4237821176
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2226074891
Short name T828
Test name
Test status
Simulation time 413003473 ps
CPU time 18.65 seconds
Started Jun 10 06:35:49 PM PDT 24
Finished Jun 10 06:36:08 PM PDT 24
Peak memory 248372 kb
Host smart-85224277-0a7b-41a9-992d-e1521456193b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2226074891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2226074891
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.498842030
Short name T715
Test name
Test status
Simulation time 78146095 ps
CPU time 4.93 seconds
Started Jun 10 06:35:38 PM PDT 24
Finished Jun 10 06:35:43 PM PDT 24
Peak memory 235748 kb
Host smart-73e87d04-637e-4ebb-9eec-4749efff202e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=498842030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.498842030
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3050758927
Short name T724
Test name
Test status
Simulation time 66254905 ps
CPU time 6.01 seconds
Started Jun 10 06:35:50 PM PDT 24
Finished Jun 10 06:35:57 PM PDT 24
Peak memory 242612 kb
Host smart-b6616c40-db6e-4f42-8087-f115a85c48f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050758927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3050758927
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2053650893
Short name T787
Test name
Test status
Simulation time 95177502 ps
CPU time 5.73 seconds
Started Jun 10 06:35:51 PM PDT 24
Finished Jun 10 06:35:57 PM PDT 24
Peak memory 239244 kb
Host smart-cc44e700-37de-4126-8df7-7e86834aaa90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2053650893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2053650893
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1891454099
Short name T249
Test name
Test status
Simulation time 14253398 ps
CPU time 1.53 seconds
Started Jun 10 06:35:48 PM PDT 24
Finished Jun 10 06:35:50 PM PDT 24
Peak memory 235704 kb
Host smart-bbbba598-64f2-408e-9b39-514aeeaf177b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1891454099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1891454099
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2564783445
Short name T818
Test name
Test status
Simulation time 330449185 ps
CPU time 13.47 seconds
Started Jun 10 06:35:39 PM PDT 24
Finished Jun 10 06:35:53 PM PDT 24
Peak memory 244832 kb
Host smart-719ac60d-3fdb-4cd2-aa67-e4e8d29a34d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2564783445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2564783445
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.252738047
Short name T138
Test name
Test status
Simulation time 66451444027 ps
CPU time 563.41 seconds
Started Jun 10 06:35:51 PM PDT 24
Finished Jun 10 06:45:15 PM PDT 24
Peak memory 265204 kb
Host smart-43f336a0-a911-4d6e-bd99-25fac114bf28
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252738047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.252738047
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.869605673
Short name T794
Test name
Test status
Simulation time 219691049 ps
CPU time 6.75 seconds
Started Jun 10 06:35:54 PM PDT 24
Finished Jun 10 06:36:01 PM PDT 24
Peak memory 253524 kb
Host smart-7ec1b201-5e0f-4cfd-958e-b6aa2791190a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=869605673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.869605673
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3477924298
Short name T347
Test name
Test status
Simulation time 83398411 ps
CPU time 8.35 seconds
Started Jun 10 06:35:50 PM PDT 24
Finished Jun 10 06:35:59 PM PDT 24
Peak memory 240388 kb
Host smart-fe110ccc-5b4b-4843-ab36-fd0bb3c83a77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477924298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3477924298
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2034340935
Short name T754
Test name
Test status
Simulation time 62317062 ps
CPU time 4.88 seconds
Started Jun 10 06:35:52 PM PDT 24
Finished Jun 10 06:35:58 PM PDT 24
Peak memory 236624 kb
Host smart-5002c62a-d117-4c7c-be8a-070dc763f180
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2034340935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2034340935
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.939585340
Short name T712
Test name
Test status
Simulation time 12338573 ps
CPU time 1.44 seconds
Started Jun 10 06:35:51 PM PDT 24
Finished Jun 10 06:35:52 PM PDT 24
Peak memory 236696 kb
Host smart-91c923c3-4390-46c0-855f-d11c4fb53651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=939585340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.939585340
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1489297935
Short name T766
Test name
Test status
Simulation time 1344458821 ps
CPU time 22.58 seconds
Started Jun 10 06:35:50 PM PDT 24
Finished Jun 10 06:36:13 PM PDT 24
Peak memory 240040 kb
Host smart-b7d3f7c6-7f22-4ecc-9bcb-e4db4bc7bad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1489297935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1489297935
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.30785477
Short name T149
Test name
Test status
Simulation time 1877594563 ps
CPU time 140.16 seconds
Started Jun 10 06:35:48 PM PDT 24
Finished Jun 10 06:38:09 PM PDT 24
Peak memory 266552 kb
Host smart-43412f92-08bc-4653-a3be-ea2266463fab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30785477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_error
s.30785477
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3063711081
Short name T124
Test name
Test status
Simulation time 3888828596 ps
CPU time 327.65 seconds
Started Jun 10 06:35:52 PM PDT 24
Finished Jun 10 06:41:20 PM PDT 24
Peak memory 269708 kb
Host smart-70adcd98-54d3-431d-91ce-086576b1200f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063711081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3063711081
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3619684761
Short name T755
Test name
Test status
Simulation time 179671913 ps
CPU time 8.03 seconds
Started Jun 10 06:35:37 PM PDT 24
Finished Jun 10 06:35:45 PM PDT 24
Peak memory 249384 kb
Host smart-1819045e-f56e-47a6-bb8f-08b8179123b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3619684761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3619684761
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2105517018
Short name T750
Test name
Test status
Simulation time 60748619 ps
CPU time 8.9 seconds
Started Jun 10 06:35:45 PM PDT 24
Finished Jun 10 06:35:54 PM PDT 24
Peak memory 251412 kb
Host smart-d2e42814-3d7d-4fad-a474-0f4207a41462
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105517018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2105517018
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2985699105
Short name T725
Test name
Test status
Simulation time 51152877 ps
CPU time 4.73 seconds
Started Jun 10 06:35:51 PM PDT 24
Finished Jun 10 06:35:56 PM PDT 24
Peak memory 236644 kb
Host smart-badea5b7-1fbb-4851-89a5-a31dd1c061cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2985699105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2985699105
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.570928655
Short name T716
Test name
Test status
Simulation time 7016498 ps
CPU time 1.39 seconds
Started Jun 10 06:35:50 PM PDT 24
Finished Jun 10 06:35:52 PM PDT 24
Peak memory 236720 kb
Host smart-29919096-de2d-46b0-92ab-d895901361a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=570928655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.570928655
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3358528579
Short name T802
Test name
Test status
Simulation time 599039669 ps
CPU time 18.44 seconds
Started Jun 10 06:35:49 PM PDT 24
Finished Jun 10 06:36:08 PM PDT 24
Peak memory 243976 kb
Host smart-c6b98fa7-7e2c-48a0-a181-fe18b64932b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3358528579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3358528579
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3509121143
Short name T144
Test name
Test status
Simulation time 19221112002 ps
CPU time 355.94 seconds
Started Jun 10 06:35:56 PM PDT 24
Finished Jun 10 06:41:52 PM PDT 24
Peak memory 265128 kb
Host smart-86709b4a-93c0-455e-9933-9887a1d4a9aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3509121143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3509121143
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3892557547
Short name T148
Test name
Test status
Simulation time 7134190743 ps
CPU time 552.34 seconds
Started Jun 10 06:35:50 PM PDT 24
Finished Jun 10 06:45:03 PM PDT 24
Peak memory 266132 kb
Host smart-c8ca0daf-e2d2-4057-b85d-6327a073cef1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892557547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3892557547
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2210996434
Short name T740
Test name
Test status
Simulation time 109647341 ps
CPU time 4.91 seconds
Started Jun 10 06:35:49 PM PDT 24
Finished Jun 10 06:35:54 PM PDT 24
Peak memory 248372 kb
Host smart-b0ebb445-d7fa-45d1-a5da-eaae34a96306
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2210996434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2210996434
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2887317261
Short name T747
Test name
Test status
Simulation time 3339707951 ps
CPU time 252.8 seconds
Started Jun 10 06:35:20 PM PDT 24
Finished Jun 10 06:39:33 PM PDT 24
Peak memory 239260 kb
Host smart-c0381bb9-a247-4097-bcb3-844927f165a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2887317261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2887317261
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2876661082
Short name T239
Test name
Test status
Simulation time 10299401700 ps
CPU time 517.65 seconds
Started Jun 10 06:35:17 PM PDT 24
Finished Jun 10 06:43:55 PM PDT 24
Peak memory 236724 kb
Host smart-e453d86f-f881-4a01-a9bc-5c0ee2360d47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2876661082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2876661082
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3391004109
Short name T753
Test name
Test status
Simulation time 451312206 ps
CPU time 9.39 seconds
Started Jun 10 06:35:24 PM PDT 24
Finished Jun 10 06:35:33 PM PDT 24
Peak memory 240248 kb
Host smart-08d9dd91-dc02-4cfb-b2cf-fbfec304286f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3391004109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3391004109
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3378155326
Short name T726
Test name
Test status
Simulation time 109198531 ps
CPU time 5.16 seconds
Started Jun 10 06:35:20 PM PDT 24
Finished Jun 10 06:35:25 PM PDT 24
Peak memory 256508 kb
Host smart-b486e98c-2c46-44dd-983b-802e8c97abce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378155326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3378155326
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1545630001
Short name T732
Test name
Test status
Simulation time 97027520 ps
CPU time 4.47 seconds
Started Jun 10 06:35:18 PM PDT 24
Finished Jun 10 06:35:23 PM PDT 24
Peak memory 235744 kb
Host smart-ae5f8e0a-0d0b-42cb-8a54-456b9294d89f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1545630001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1545630001
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2500655417
Short name T793
Test name
Test status
Simulation time 62227680 ps
CPU time 1.18 seconds
Started Jun 10 06:35:18 PM PDT 24
Finished Jun 10 06:35:20 PM PDT 24
Peak memory 234688 kb
Host smart-b7284972-437a-49ff-a41c-11dca445c1f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2500655417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2500655417
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1591057862
Short name T751
Test name
Test status
Simulation time 655566906 ps
CPU time 18.83 seconds
Started Jun 10 06:35:23 PM PDT 24
Finished Jun 10 06:35:42 PM PDT 24
Peak memory 243956 kb
Host smart-0a6961b1-b6bb-4ed0-9cd4-21b83056c0bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1591057862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1591057862
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2893228691
Short name T805
Test name
Test status
Simulation time 1032525022 ps
CPU time 21.82 seconds
Started Jun 10 06:35:24 PM PDT 24
Finished Jun 10 06:35:46 PM PDT 24
Peak memory 253784 kb
Host smart-7265d47d-184e-4580-8818-82018c0511d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2893228691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2893228691
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3083238453
Short name T729
Test name
Test status
Simulation time 21463621 ps
CPU time 1.46 seconds
Started Jun 10 06:35:44 PM PDT 24
Finished Jun 10 06:35:45 PM PDT 24
Peak memory 235728 kb
Host smart-93dbd41a-136f-4192-9166-0b8863222123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3083238453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3083238453
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2185095601
Short name T756
Test name
Test status
Simulation time 11453905 ps
CPU time 1.41 seconds
Started Jun 10 06:35:53 PM PDT 24
Finished Jun 10 06:35:55 PM PDT 24
Peak memory 234704 kb
Host smart-f4f1939e-9d69-4b80-9d0b-ae11689e75b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2185095601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2185095601
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3893065896
Short name T346
Test name
Test status
Simulation time 14765393 ps
CPU time 1.3 seconds
Started Jun 10 06:35:56 PM PDT 24
Finished Jun 10 06:35:57 PM PDT 24
Peak memory 235784 kb
Host smart-f3f3f96d-e8f5-4da1-b785-30523f708ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3893065896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3893065896
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1144772529
Short name T731
Test name
Test status
Simulation time 7231331 ps
CPU time 1.31 seconds
Started Jun 10 06:35:43 PM PDT 24
Finished Jun 10 06:35:45 PM PDT 24
Peak memory 235772 kb
Host smart-890ce8fc-05e8-4823-bedc-40eb07defbdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1144772529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1144772529
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1808717532
Short name T760
Test name
Test status
Simulation time 9793377 ps
CPU time 1.26 seconds
Started Jun 10 06:35:51 PM PDT 24
Finished Jun 10 06:35:52 PM PDT 24
Peak memory 235724 kb
Host smart-f1b913d8-0cae-45fd-9030-7e2d23b40747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1808717532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1808717532
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3465475626
Short name T730
Test name
Test status
Simulation time 8391480 ps
CPU time 1.57 seconds
Started Jun 10 06:35:45 PM PDT 24
Finished Jun 10 06:35:47 PM PDT 24
Peak memory 236656 kb
Host smart-a21e86e4-8d39-4865-ba0f-984b9633f898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3465475626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3465475626
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.660658039
Short name T810
Test name
Test status
Simulation time 8364042 ps
CPU time 1.41 seconds
Started Jun 10 06:35:52 PM PDT 24
Finished Jun 10 06:35:54 PM PDT 24
Peak memory 235728 kb
Host smart-519e4699-b3b8-453e-95a3-84d616b99916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=660658039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.660658039
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1472062225
Short name T799
Test name
Test status
Simulation time 19553415 ps
CPU time 1.4 seconds
Started Jun 10 06:35:45 PM PDT 24
Finished Jun 10 06:35:47 PM PDT 24
Peak memory 235800 kb
Host smart-96c1fd50-5f6b-4d0e-9f91-35039c201196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1472062225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1472062225
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.912599535
Short name T774
Test name
Test status
Simulation time 22739545 ps
CPU time 1.39 seconds
Started Jun 10 06:35:57 PM PDT 24
Finished Jun 10 06:35:59 PM PDT 24
Peak memory 235756 kb
Host smart-b311fbb8-a883-47fe-ae03-c50afb99272d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=912599535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.912599535
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3071657997
Short name T762
Test name
Test status
Simulation time 8868093 ps
CPU time 1.53 seconds
Started Jun 10 06:35:45 PM PDT 24
Finished Jun 10 06:35:47 PM PDT 24
Peak memory 236712 kb
Host smart-fd9bc3ee-705b-454a-8033-00a8eec25f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3071657997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3071657997
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2978898490
Short name T767
Test name
Test status
Simulation time 6956509124 ps
CPU time 142.47 seconds
Started Jun 10 06:35:21 PM PDT 24
Finished Jun 10 06:37:44 PM PDT 24
Peak memory 236728 kb
Host smart-f6915302-af6e-498c-ac8f-18bebdabc25c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2978898490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2978898490
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1219789646
Short name T763
Test name
Test status
Simulation time 4084567469 ps
CPU time 91.75 seconds
Started Jun 10 06:35:27 PM PDT 24
Finished Jun 10 06:36:59 PM PDT 24
Peak memory 240168 kb
Host smart-870e36a5-e30c-44a2-85d9-de5e12e31a9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1219789646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1219789646
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.425455683
Short name T791
Test name
Test status
Simulation time 487901855 ps
CPU time 9.84 seconds
Started Jun 10 06:35:23 PM PDT 24
Finished Jun 10 06:35:33 PM PDT 24
Peak memory 240036 kb
Host smart-2262192a-69f4-41fd-9132-4b52906582cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=425455683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.425455683
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1486503986
Short name T825
Test name
Test status
Simulation time 639193415 ps
CPU time 9.6 seconds
Started Jun 10 06:35:22 PM PDT 24
Finished Jun 10 06:35:32 PM PDT 24
Peak memory 253412 kb
Host smart-eaa52438-e377-488d-81a1-7409f8c4290c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486503986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1486503986
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.423728560
Short name T819
Test name
Test status
Simulation time 100491459 ps
CPU time 7.22 seconds
Started Jun 10 06:35:21 PM PDT 24
Finished Jun 10 06:35:29 PM PDT 24
Peak memory 235744 kb
Host smart-3ae05308-44ba-43a0-823f-78fc0ecbce23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=423728560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.423728560
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2760670502
Short name T250
Test name
Test status
Simulation time 13309881 ps
CPU time 1.72 seconds
Started Jun 10 06:35:22 PM PDT 24
Finished Jun 10 06:35:24 PM PDT 24
Peak memory 235768 kb
Host smart-44670d87-adb2-410b-8a12-51968d0f4ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2760670502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2760670502
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3596838816
Short name T815
Test name
Test status
Simulation time 450378190 ps
CPU time 12.57 seconds
Started Jun 10 06:35:36 PM PDT 24
Finished Jun 10 06:35:48 PM PDT 24
Peak memory 244876 kb
Host smart-8fb2369a-5f38-40ec-ab82-e8e3594f8110
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3596838816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3596838816
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1386978323
Short name T784
Test name
Test status
Simulation time 253910963 ps
CPU time 6.28 seconds
Started Jun 10 06:35:17 PM PDT 24
Finished Jun 10 06:35:24 PM PDT 24
Peak memory 248360 kb
Host smart-b547eec5-80b2-4361-9fa8-1599c3172bac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1386978323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1386978323
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2930685394
Short name T779
Test name
Test status
Simulation time 6126236 ps
CPU time 1.44 seconds
Started Jun 10 06:35:48 PM PDT 24
Finished Jun 10 06:35:50 PM PDT 24
Peak memory 236660 kb
Host smart-7210ad97-62c6-4e11-bbd9-9721d9286c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2930685394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2930685394
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.306532149
Short name T777
Test name
Test status
Simulation time 10253696 ps
CPU time 1.36 seconds
Started Jun 10 06:35:46 PM PDT 24
Finished Jun 10 06:35:47 PM PDT 24
Peak memory 235732 kb
Host smart-aa5c2862-9424-4b1b-822a-7051efd06f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=306532149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.306532149
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.755450123
Short name T734
Test name
Test status
Simulation time 15502020 ps
CPU time 1.32 seconds
Started Jun 10 06:35:51 PM PDT 24
Finished Jun 10 06:35:53 PM PDT 24
Peak memory 235680 kb
Host smart-ee59f0dd-36f3-4b64-9216-c56269344227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=755450123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.755450123
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1256401682
Short name T795
Test name
Test status
Simulation time 15653960 ps
CPU time 1.41 seconds
Started Jun 10 06:35:54 PM PDT 24
Finished Jun 10 06:35:56 PM PDT 24
Peak memory 235760 kb
Host smart-44b8d1aa-a130-4ec5-a090-addf66badce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1256401682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1256401682
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3615494438
Short name T741
Test name
Test status
Simulation time 20842314 ps
CPU time 1.46 seconds
Started Jun 10 06:35:45 PM PDT 24
Finished Jun 10 06:35:47 PM PDT 24
Peak memory 236712 kb
Host smart-25d94c1c-5d04-4fc1-8b22-c420e79c8c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3615494438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3615494438
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.403766414
Short name T708
Test name
Test status
Simulation time 18089575 ps
CPU time 1.23 seconds
Started Jun 10 06:35:48 PM PDT 24
Finished Jun 10 06:35:49 PM PDT 24
Peak memory 236584 kb
Host smart-6e6bff78-fde4-47ae-a651-d8c209e67943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=403766414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.403766414
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2368941397
Short name T771
Test name
Test status
Simulation time 11887891 ps
CPU time 1.57 seconds
Started Jun 10 06:35:57 PM PDT 24
Finished Jun 10 06:35:59 PM PDT 24
Peak memory 235900 kb
Host smart-36cc4d5c-62d1-4282-9ef7-24851964d752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2368941397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2368941397
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3495465459
Short name T728
Test name
Test status
Simulation time 10421428 ps
CPU time 1.64 seconds
Started Jun 10 06:35:47 PM PDT 24
Finished Jun 10 06:35:49 PM PDT 24
Peak memory 235784 kb
Host smart-e47d1711-99cf-4132-a635-0984183c70f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3495465459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3495465459
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3488366166
Short name T806
Test name
Test status
Simulation time 10053897 ps
CPU time 1.54 seconds
Started Jun 10 06:35:47 PM PDT 24
Finished Jun 10 06:35:49 PM PDT 24
Peak memory 235780 kb
Host smart-f916a363-ec16-4f46-8dae-df93e820ebe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3488366166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3488366166
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1741125427
Short name T748
Test name
Test status
Simulation time 4211353473 ps
CPU time 135.17 seconds
Started Jun 10 06:35:32 PM PDT 24
Finished Jun 10 06:37:47 PM PDT 24
Peak memory 236732 kb
Host smart-a6645b49-71a7-4a08-bde7-6f217f4fbdeb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1741125427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1741125427
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.53906845
Short name T349
Test name
Test status
Simulation time 6803831446 ps
CPU time 205.45 seconds
Started Jun 10 06:35:25 PM PDT 24
Finished Jun 10 06:38:51 PM PDT 24
Peak memory 236732 kb
Host smart-2d2249df-fa27-409a-943e-c0c0a90d982b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=53906845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.53906845
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1877773536
Short name T758
Test name
Test status
Simulation time 105397600 ps
CPU time 4.95 seconds
Started Jun 10 06:35:28 PM PDT 24
Finished Jun 10 06:35:33 PM PDT 24
Peak memory 240028 kb
Host smart-5b9e08c3-8a6b-4a13-ba5e-c209e6fd8fc4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1877773536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1877773536
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1136355881
Short name T776
Test name
Test status
Simulation time 382312674 ps
CPU time 8.17 seconds
Started Jun 10 06:35:22 PM PDT 24
Finished Jun 10 06:35:30 PM PDT 24
Peak memory 240800 kb
Host smart-3c83186e-3c25-432f-bf7e-927158883ad6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136355881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1136355881
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1875177456
Short name T829
Test name
Test status
Simulation time 250803981 ps
CPU time 6.02 seconds
Started Jun 10 06:35:35 PM PDT 24
Finished Jun 10 06:35:41 PM PDT 24
Peak memory 239280 kb
Host smart-e60c74ba-b3f7-43f2-9c37-8d8e07b47985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1875177456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1875177456
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.657459979
Short name T746
Test name
Test status
Simulation time 168299955 ps
CPU time 23.16 seconds
Started Jun 10 06:35:28 PM PDT 24
Finished Jun 10 06:35:57 PM PDT 24
Peak memory 244820 kb
Host smart-d6d19a6d-ee44-4f47-a3ff-b021f5eb8e3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=657459979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.657459979
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.442818439
Short name T121
Test name
Test status
Simulation time 1533283261 ps
CPU time 183.25 seconds
Started Jun 10 06:35:22 PM PDT 24
Finished Jun 10 06:38:26 PM PDT 24
Peak memory 265080 kb
Host smart-a7619377-a88b-4360-812b-e2c1de9c2f0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=442818439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.442818439
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3442922121
Short name T783
Test name
Test status
Simulation time 1058595020 ps
CPU time 7.54 seconds
Started Jun 10 06:35:23 PM PDT 24
Finished Jun 10 06:35:31 PM PDT 24
Peak memory 247980 kb
Host smart-fe5a8e01-6222-4171-b040-4ae0864f153f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3442922121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3442922121
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.4188024716
Short name T238
Test name
Test status
Simulation time 2512612135 ps
CPU time 42.84 seconds
Started Jun 10 06:35:31 PM PDT 24
Finished Jun 10 06:36:15 PM PDT 24
Peak memory 240024 kb
Host smart-c9e38cd4-8c78-41d6-b653-47ca3d8ee5c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4188024716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.4188024716
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3287560751
Short name T800
Test name
Test status
Simulation time 8488673 ps
CPU time 1.39 seconds
Started Jun 10 06:35:48 PM PDT 24
Finished Jun 10 06:35:50 PM PDT 24
Peak memory 236612 kb
Host smart-7e639ac6-9340-4c85-a07f-dc61b5dc941e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3287560751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3287560751
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.382582566
Short name T739
Test name
Test status
Simulation time 33162694 ps
CPU time 1.19 seconds
Started Jun 10 06:35:48 PM PDT 24
Finished Jun 10 06:35:49 PM PDT 24
Peak memory 236540 kb
Host smart-83f06330-0e2c-418b-803c-7d34ba9aa9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=382582566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.382582566
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4267672430
Short name T814
Test name
Test status
Simulation time 55732778 ps
CPU time 1.42 seconds
Started Jun 10 06:35:47 PM PDT 24
Finished Jun 10 06:35:49 PM PDT 24
Peak memory 235700 kb
Host smart-8f2eedef-e299-4d6e-92b0-1817bc8ba4e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4267672430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.4267672430
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1284510964
Short name T768
Test name
Test status
Simulation time 15329999 ps
CPU time 1.44 seconds
Started Jun 10 06:35:53 PM PDT 24
Finished Jun 10 06:35:54 PM PDT 24
Peak memory 236620 kb
Host smart-abe3f08d-b307-4748-913f-ee0acbd71700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1284510964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1284510964
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2354028711
Short name T826
Test name
Test status
Simulation time 16598242 ps
CPU time 1.33 seconds
Started Jun 10 06:35:47 PM PDT 24
Finished Jun 10 06:35:48 PM PDT 24
Peak memory 235804 kb
Host smart-728dae30-0f03-401d-9c2c-1934e29ac727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2354028711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2354028711
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2715853887
Short name T714
Test name
Test status
Simulation time 21513758 ps
CPU time 1.59 seconds
Started Jun 10 06:35:51 PM PDT 24
Finished Jun 10 06:35:53 PM PDT 24
Peak memory 235748 kb
Host smart-2fecf1d3-4d3f-4c0b-90e3-ffb7a8d5005f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2715853887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2715853887
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4098418265
Short name T832
Test name
Test status
Simulation time 17280801 ps
CPU time 1.19 seconds
Started Jun 10 06:35:47 PM PDT 24
Finished Jun 10 06:35:49 PM PDT 24
Peak memory 235764 kb
Host smart-1cb4fea9-47bd-4669-a91b-35c7b0c0e4af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4098418265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4098418265
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4016366275
Short name T821
Test name
Test status
Simulation time 14735306 ps
CPU time 1.32 seconds
Started Jun 10 06:35:57 PM PDT 24
Finished Jun 10 06:35:59 PM PDT 24
Peak memory 235652 kb
Host smart-f0d95fdc-54c4-4e56-9363-bbf62f1329d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4016366275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4016366275
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1298661761
Short name T713
Test name
Test status
Simulation time 11993189 ps
CPU time 1.28 seconds
Started Jun 10 06:35:47 PM PDT 24
Finished Jun 10 06:35:48 PM PDT 24
Peak memory 235716 kb
Host smart-78af589a-f49d-4eaf-8f37-0319e6973a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1298661761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1298661761
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2011592492
Short name T744
Test name
Test status
Simulation time 18924197 ps
CPU time 1.89 seconds
Started Jun 10 06:35:55 PM PDT 24
Finished Jun 10 06:35:58 PM PDT 24
Peak memory 236572 kb
Host smart-b0e3f52f-b336-4813-9db9-7ffe93441ca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2011592492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2011592492
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3996076365
Short name T722
Test name
Test status
Simulation time 81818931 ps
CPU time 7.7 seconds
Started Jun 10 06:35:25 PM PDT 24
Finished Jun 10 06:35:33 PM PDT 24
Peak memory 240384 kb
Host smart-26ea6d8b-72a4-4761-aea7-85bfc9ceac74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996076365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3996076365
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.495842092
Short name T823
Test name
Test status
Simulation time 229092141 ps
CPU time 5.77 seconds
Started Jun 10 06:35:34 PM PDT 24
Finished Jun 10 06:35:40 PM PDT 24
Peak memory 240016 kb
Host smart-046667c8-82f0-4a72-bf84-253d762d782d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=495842092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.495842092
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4131422274
Short name T735
Test name
Test status
Simulation time 11356549 ps
CPU time 1.29 seconds
Started Jun 10 06:35:29 PM PDT 24
Finished Jun 10 06:35:31 PM PDT 24
Peak memory 236628 kb
Host smart-03722e82-4237-4332-b598-ac815890b372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4131422274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4131422274
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4114804653
Short name T801
Test name
Test status
Simulation time 610810174 ps
CPU time 38.64 seconds
Started Jun 10 06:35:36 PM PDT 24
Finished Jun 10 06:36:15 PM PDT 24
Peak memory 248292 kb
Host smart-0cdf9e65-b945-4b17-8d7d-1823e6c452db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4114804653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.4114804653
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.124334249
Short name T123
Test name
Test status
Simulation time 4152998872 ps
CPU time 343.56 seconds
Started Jun 10 06:35:23 PM PDT 24
Finished Jun 10 06:41:07 PM PDT 24
Peak memory 273200 kb
Host smart-d08e09a9-47a4-4c3f-bc7a-46c9704fcfe4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=124334249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.124334249
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1470046084
Short name T143
Test name
Test status
Simulation time 2282779511 ps
CPU time 340 seconds
Started Jun 10 06:35:25 PM PDT 24
Finished Jun 10 06:41:05 PM PDT 24
Peak memory 265068 kb
Host smart-aaf9e485-4b55-4c1c-b45b-7561e9f0351f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470046084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1470046084
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.168341069
Short name T769
Test name
Test status
Simulation time 110700476 ps
CPU time 11.53 seconds
Started Jun 10 06:35:27 PM PDT 24
Finished Jun 10 06:35:39 PM PDT 24
Peak memory 248068 kb
Host smart-ba0d3e7b-a808-4e60-a669-85b69f4eb9fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=168341069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.168341069
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3433549065
Short name T752
Test name
Test status
Simulation time 1243622010 ps
CPU time 15.63 seconds
Started Jun 10 06:35:35 PM PDT 24
Finished Jun 10 06:35:51 PM PDT 24
Peak memory 248400 kb
Host smart-82d71790-f638-4638-919d-2e4c2be8557d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433549065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3433549065
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2014023387
Short name T348
Test name
Test status
Simulation time 62767380 ps
CPU time 3.43 seconds
Started Jun 10 06:35:26 PM PDT 24
Finished Jun 10 06:35:30 PM PDT 24
Peak memory 236680 kb
Host smart-8da0f28f-fd9b-4305-af85-9bc6ee5fa193
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2014023387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2014023387
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.130060485
Short name T158
Test name
Test status
Simulation time 9361457 ps
CPU time 1.38 seconds
Started Jun 10 06:35:30 PM PDT 24
Finished Jun 10 06:35:32 PM PDT 24
Peak memory 236704 kb
Host smart-8f37ed3a-0da3-407d-9af7-b988478f5854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=130060485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.130060485
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1154961361
Short name T804
Test name
Test status
Simulation time 273040810 ps
CPU time 19.91 seconds
Started Jun 10 06:35:29 PM PDT 24
Finished Jun 10 06:35:49 PM PDT 24
Peak memory 243928 kb
Host smart-1c9f5fe3-9827-43dd-a3b9-6efafbe32bbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1154961361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1154961361
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3515785670
Short name T154
Test name
Test status
Simulation time 30957046760 ps
CPU time 568.38 seconds
Started Jun 10 06:35:42 PM PDT 24
Finished Jun 10 06:45:10 PM PDT 24
Peak memory 265124 kb
Host smart-ef414846-2ee1-45cd-86b7-46e7fff9c7a6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515785670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3515785670
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.902568631
Short name T743
Test name
Test status
Simulation time 348874914 ps
CPU time 6.46 seconds
Started Jun 10 06:35:27 PM PDT 24
Finished Jun 10 06:35:34 PM PDT 24
Peak memory 248348 kb
Host smart-e70e9b09-300d-4a83-af02-9753dfd56221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=902568631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.902568631
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1259815419
Short name T824
Test name
Test status
Simulation time 198208029 ps
CPU time 8.1 seconds
Started Jun 10 06:35:28 PM PDT 24
Finished Jun 10 06:35:37 PM PDT 24
Peak memory 251820 kb
Host smart-ee6bf381-2d17-4bbb-9d69-1ed9ef87d0ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259815419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1259815419
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1811803285
Short name T789
Test name
Test status
Simulation time 123391114 ps
CPU time 5.15 seconds
Started Jun 10 06:35:27 PM PDT 24
Finished Jun 10 06:35:32 PM PDT 24
Peak memory 236676 kb
Host smart-2c4e83d6-4084-4544-b881-7e0105a6dad5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1811803285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1811803285
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1449608560
Short name T344
Test name
Test status
Simulation time 7578112 ps
CPU time 1.57 seconds
Started Jun 10 06:35:45 PM PDT 24
Finished Jun 10 06:35:47 PM PDT 24
Peak memory 236684 kb
Host smart-4cc0f793-02aa-47f5-9b3b-a201daeed50b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1449608560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1449608560
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.861847117
Short name T775
Test name
Test status
Simulation time 344017875 ps
CPU time 13.46 seconds
Started Jun 10 06:35:42 PM PDT 24
Finished Jun 10 06:35:56 PM PDT 24
Peak memory 244884 kb
Host smart-e3f43337-3da8-4a99-8497-0ffb49c5f8d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=861847117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.861847117
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3481590628
Short name T127
Test name
Test status
Simulation time 1703370031 ps
CPU time 103.23 seconds
Started Jun 10 06:35:47 PM PDT 24
Finished Jun 10 06:37:31 PM PDT 24
Peak memory 256816 kb
Host smart-2e9b9f6b-ae86-4e3b-a496-63c1d76c8ce8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3481590628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3481590628
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3503400669
Short name T150
Test name
Test status
Simulation time 27280410589 ps
CPU time 318.65 seconds
Started Jun 10 06:35:38 PM PDT 24
Finished Jun 10 06:40:57 PM PDT 24
Peak memory 265116 kb
Host smart-319ef072-e142-44db-8068-8b1567d5c441
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503400669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3503400669
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.302047366
Short name T782
Test name
Test status
Simulation time 123172228 ps
CPU time 10 seconds
Started Jun 10 06:35:26 PM PDT 24
Finished Jun 10 06:35:36 PM PDT 24
Peak memory 248220 kb
Host smart-9b6d25bd-7db7-469e-aa81-f5e679eb6175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=302047366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.302047366
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.536207570
Short name T737
Test name
Test status
Simulation time 42741691 ps
CPU time 5.55 seconds
Started Jun 10 06:35:37 PM PDT 24
Finished Jun 10 06:35:43 PM PDT 24
Peak memory 239576 kb
Host smart-3e7ec0fe-5b4b-4975-aee6-57bdb03517f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536207570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.536207570
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2113047787
Short name T822
Test name
Test status
Simulation time 61152998 ps
CPU time 3.28 seconds
Started Jun 10 06:35:35 PM PDT 24
Finished Jun 10 06:35:39 PM PDT 24
Peak memory 239380 kb
Host smart-99e47eaf-fc73-49c1-b4f3-53544faee461
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2113047787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2113047787
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3666263167
Short name T159
Test name
Test status
Simulation time 14761506 ps
CPU time 1.4 seconds
Started Jun 10 06:35:29 PM PDT 24
Finished Jun 10 06:35:31 PM PDT 24
Peak memory 236692 kb
Host smart-a4b7c463-3997-4a54-a242-9cee2cbd5c09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3666263167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3666263167
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2213164295
Short name T813
Test name
Test status
Simulation time 344023654 ps
CPU time 22.27 seconds
Started Jun 10 06:35:47 PM PDT 24
Finished Jun 10 06:36:10 PM PDT 24
Peak memory 244744 kb
Host smart-5a9face9-cd3e-4921-ae6a-ba197ff7ec04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2213164295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2213164295
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1019660463
Short name T778
Test name
Test status
Simulation time 1960140170 ps
CPU time 34.24 seconds
Started Jun 10 06:35:39 PM PDT 24
Finished Jun 10 06:36:13 PM PDT 24
Peak memory 247856 kb
Host smart-78a813a4-a9d1-41f7-b31c-a68eb2ab0c69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1019660463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1019660463
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.897767944
Short name T757
Test name
Test status
Simulation time 218538359 ps
CPU time 4.89 seconds
Started Jun 10 06:35:45 PM PDT 24
Finished Jun 10 06:35:51 PM PDT 24
Peak memory 239376 kb
Host smart-316bf6f6-9e4b-4a90-ac01-cfd323bc85fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897767944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.897767944
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1059192406
Short name T808
Test name
Test status
Simulation time 133734143 ps
CPU time 5.32 seconds
Started Jun 10 06:35:31 PM PDT 24
Finished Jun 10 06:35:36 PM PDT 24
Peak memory 239984 kb
Host smart-14fce9f8-22d6-49ee-ae46-6da3c3193a85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1059192406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1059192406
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.497691232
Short name T717
Test name
Test status
Simulation time 13550304 ps
CPU time 1.38 seconds
Started Jun 10 06:35:42 PM PDT 24
Finished Jun 10 06:35:44 PM PDT 24
Peak memory 236556 kb
Host smart-4e802d43-7896-4ce8-a980-c6dabf26968c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=497691232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.497691232
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2085170765
Short name T797
Test name
Test status
Simulation time 495662381 ps
CPU time 23.55 seconds
Started Jun 10 06:35:46 PM PDT 24
Finished Jun 10 06:36:10 PM PDT 24
Peak memory 244888 kb
Host smart-13e90aec-b586-4ece-becf-49c6278e46fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2085170765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2085170765
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1116075476
Short name T119
Test name
Test status
Simulation time 12412413143 ps
CPU time 141.18 seconds
Started Jun 10 06:35:50 PM PDT 24
Finished Jun 10 06:38:11 PM PDT 24
Peak memory 264916 kb
Host smart-4f643c99-3ee6-43cd-b4a0-6c037c2d3e7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1116075476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1116075476
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1198495727
Short name T247
Test name
Test status
Simulation time 296601357 ps
CPU time 18.14 seconds
Started Jun 10 06:35:30 PM PDT 24
Finished Jun 10 06:35:49 PM PDT 24
Peak memory 247800 kb
Host smart-77cbf9d5-9edd-480e-a15a-ac5c585b9e47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1198495727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1198495727
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.405086276
Short name T647
Test name
Test status
Simulation time 171348127546 ps
CPU time 1705.98 seconds
Started Jun 10 06:36:47 PM PDT 24
Finished Jun 10 07:05:13 PM PDT 24
Peak memory 273336 kb
Host smart-862a2f24-b120-4815-878f-5778452d138a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405086276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.405086276
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.4021184849
Short name T402
Test name
Test status
Simulation time 599585331 ps
CPU time 10.2 seconds
Started Jun 10 06:36:48 PM PDT 24
Finished Jun 10 06:36:59 PM PDT 24
Peak memory 240540 kb
Host smart-e598040f-1417-41c6-b0b6-3bbfe8617f2c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4021184849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.4021184849
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1499858351
Short name T557
Test name
Test status
Simulation time 4324888780 ps
CPU time 98.41 seconds
Started Jun 10 06:36:48 PM PDT 24
Finished Jun 10 06:38:27 PM PDT 24
Peak memory 256784 kb
Host smart-b9e3cc72-b751-4e0e-bdd4-de70dcba0dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14998
58351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1499858351
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.951833310
Short name T268
Test name
Test status
Simulation time 2105767668 ps
CPU time 60.18 seconds
Started Jun 10 06:36:46 PM PDT 24
Finished Jun 10 06:37:46 PM PDT 24
Peak memory 255724 kb
Host smart-13278f8f-7b4a-4b5c-bcc2-2a0653f90d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95183
3310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.951833310
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1810001277
Short name T379
Test name
Test status
Simulation time 131297469058 ps
CPU time 2126.66 seconds
Started Jun 10 06:36:48 PM PDT 24
Finished Jun 10 07:12:15 PM PDT 24
Peak memory 288748 kb
Host smart-8c1ef008-aa74-4016-b794-af4934d29667
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810001277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1810001277
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3249538301
Short name T671
Test name
Test status
Simulation time 1014233347 ps
CPU time 15.41 seconds
Started Jun 10 06:36:40 PM PDT 24
Finished Jun 10 06:36:55 PM PDT 24
Peak memory 248696 kb
Host smart-48adc092-4405-48e7-89d5-97b85be36ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32495
38301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3249538301
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2902984427
Short name T706
Test name
Test status
Simulation time 2692663680 ps
CPU time 44.51 seconds
Started Jun 10 06:36:48 PM PDT 24
Finished Jun 10 06:37:33 PM PDT 24
Peak memory 256892 kb
Host smart-517e15db-f9ee-487d-94a9-069259281614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29029
84427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2902984427
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3228179377
Short name T366
Test name
Test status
Simulation time 1687650579 ps
CPU time 32.26 seconds
Started Jun 10 06:36:47 PM PDT 24
Finished Jun 10 06:37:20 PM PDT 24
Peak memory 248728 kb
Host smart-b3634a91-e565-48ba-97c9-b8b103d95c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32281
79377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3228179377
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2736421805
Short name T456
Test name
Test status
Simulation time 136888474843 ps
CPU time 3858.82 seconds
Started Jun 10 06:36:47 PM PDT 24
Finished Jun 10 07:41:06 PM PDT 24
Peak memory 306032 kb
Host smart-a717112d-9047-4428-90ac-4fbb8e7ed4e7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736421805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2736421805
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3111584043
Short name T219
Test name
Test status
Simulation time 805668637 ps
CPU time 12.47 seconds
Started Jun 10 06:36:44 PM PDT 24
Finished Jun 10 06:36:57 PM PDT 24
Peak memory 248748 kb
Host smart-c2dd4ea6-087e-4065-8b4c-cc9977a0062b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3111584043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3111584043
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1878120556
Short name T457
Test name
Test status
Simulation time 3709627777 ps
CPU time 212.53 seconds
Started Jun 10 06:36:38 PM PDT 24
Finished Jun 10 06:40:11 PM PDT 24
Peak memory 256940 kb
Host smart-00dcef98-7534-4ff2-a643-f9d1f4f058f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18781
20556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1878120556
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2564318795
Short name T423
Test name
Test status
Simulation time 286077275 ps
CPU time 8.46 seconds
Started Jun 10 06:36:51 PM PDT 24
Finished Jun 10 06:37:01 PM PDT 24
Peak memory 251596 kb
Host smart-9f09b46f-8750-429c-b67e-283b406af6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25643
18795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2564318795
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.787474127
Short name T96
Test name
Test status
Simulation time 18124824391 ps
CPU time 860.71 seconds
Started Jun 10 06:36:50 PM PDT 24
Finished Jun 10 06:51:12 PM PDT 24
Peak memory 272308 kb
Host smart-dd933c83-25f1-4d11-a36a-e89a816a9088
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787474127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.787474127
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.195364709
Short name T645
Test name
Test status
Simulation time 8018026903 ps
CPU time 645.34 seconds
Started Jun 10 06:36:41 PM PDT 24
Finished Jun 10 06:47:27 PM PDT 24
Peak memory 265256 kb
Host smart-a92bfd18-5b8e-4fd8-99f0-98962541e07a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195364709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.195364709
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3741399080
Short name T327
Test name
Test status
Simulation time 30813367045 ps
CPU time 524.27 seconds
Started Jun 10 06:36:47 PM PDT 24
Finished Jun 10 06:45:32 PM PDT 24
Peak memory 248232 kb
Host smart-7678c0e2-c397-4449-be39-41018b9d8bbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741399080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3741399080
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3360104650
Short name T576
Test name
Test status
Simulation time 428702891 ps
CPU time 28.53 seconds
Started Jun 10 06:36:50 PM PDT 24
Finished Jun 10 06:37:20 PM PDT 24
Peak memory 255880 kb
Host smart-1204bdae-dad3-4ab2-95b5-2afd1aed65b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33601
04650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3360104650
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2130260014
Short name T591
Test name
Test status
Simulation time 158214953 ps
CPU time 4.95 seconds
Started Jun 10 06:36:49 PM PDT 24
Finished Jun 10 06:36:55 PM PDT 24
Peak memory 240320 kb
Host smart-2dd0ac2f-7dd3-4d28-9eca-b6c5d69df045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21302
60014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2130260014
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3371848876
Short name T13
Test name
Test status
Simulation time 755338198 ps
CPU time 14.09 seconds
Started Jun 10 06:36:50 PM PDT 24
Finished Jun 10 06:37:05 PM PDT 24
Peak memory 270168 kb
Host smart-5142a610-a66b-4a0f-939a-b7980aee2a3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3371848876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3371848876
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.4078792607
Short name T419
Test name
Test status
Simulation time 435447188 ps
CPU time 25.89 seconds
Started Jun 10 06:36:46 PM PDT 24
Finished Jun 10 06:37:12 PM PDT 24
Peak memory 248728 kb
Host smart-454ca9af-e412-4734-ae4f-81fe11eb791a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40787
92607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.4078792607
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1989883810
Short name T369
Test name
Test status
Simulation time 36041122524 ps
CPU time 925.76 seconds
Started Jun 10 06:37:07 PM PDT 24
Finished Jun 10 06:52:33 PM PDT 24
Peak memory 273340 kb
Host smart-047dd120-c3c2-4c44-be5e-aa774cf54e55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989883810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1989883810
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.709805466
Short name T594
Test name
Test status
Simulation time 277598542 ps
CPU time 15.13 seconds
Started Jun 10 06:37:09 PM PDT 24
Finished Jun 10 06:37:25 PM PDT 24
Peak memory 251428 kb
Host smart-8e85405a-7d0c-4ad0-b323-16230d120a81
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=709805466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.709805466
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1466269931
Short name T364
Test name
Test status
Simulation time 12791266217 ps
CPU time 185.59 seconds
Started Jun 10 06:37:08 PM PDT 24
Finished Jun 10 06:40:14 PM PDT 24
Peak memory 256988 kb
Host smart-2f20de9a-048f-4a6f-81b7-476391bca920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14662
69931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1466269931
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2519747115
Short name T607
Test name
Test status
Simulation time 2046477541 ps
CPU time 55.99 seconds
Started Jun 10 06:37:08 PM PDT 24
Finished Jun 10 06:38:05 PM PDT 24
Peak memory 255340 kb
Host smart-dbddfefc-b8f8-4b9e-a9a2-680f585cd141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25197
47115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2519747115
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3429151012
Short name T326
Test name
Test status
Simulation time 20656127648 ps
CPU time 406.77 seconds
Started Jun 10 06:37:08 PM PDT 24
Finished Jun 10 06:43:55 PM PDT 24
Peak memory 248040 kb
Host smart-2b4af7d6-75df-4038-9afa-9b1f4da0b9a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429151012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3429151012
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1576859969
Short name T470
Test name
Test status
Simulation time 19774421 ps
CPU time 2.84 seconds
Started Jun 10 06:37:08 PM PDT 24
Finished Jun 10 06:37:11 PM PDT 24
Peak memory 240536 kb
Host smart-31985880-575c-485f-b937-2c1d9c99e8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15768
59969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1576859969
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3707659920
Short name T232
Test name
Test status
Simulation time 318850258 ps
CPU time 23.93 seconds
Started Jun 10 06:37:08 PM PDT 24
Finished Jun 10 06:37:32 PM PDT 24
Peak memory 255592 kb
Host smart-0682173b-626f-4f8a-91c4-65c11f15be54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37076
59920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3707659920
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1276736614
Short name T3
Test name
Test status
Simulation time 493006648 ps
CPU time 16.05 seconds
Started Jun 10 06:37:07 PM PDT 24
Finished Jun 10 06:37:23 PM PDT 24
Peak memory 254484 kb
Host smart-c2b594b5-9662-4a93-a1f6-a4e2585d2afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12767
36614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1276736614
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.802498059
Short name T542
Test name
Test status
Simulation time 106594960 ps
CPU time 11.18 seconds
Started Jun 10 06:37:07 PM PDT 24
Finished Jun 10 06:37:19 PM PDT 24
Peak memory 248652 kb
Host smart-451ae687-cf5c-4858-8707-9bc3588ff978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80249
8059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.802498059
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3619830558
Short name T109
Test name
Test status
Simulation time 13945124271 ps
CPU time 1496.26 seconds
Started Jun 10 06:37:08 PM PDT 24
Finished Jun 10 07:02:05 PM PDT 24
Peak memory 289276 kb
Host smart-0477d159-c0ed-4001-b881-f184c37f29ad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619830558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3619830558
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2090492626
Short name T670
Test name
Test status
Simulation time 8885838877 ps
CPU time 1241.38 seconds
Started Jun 10 06:37:07 PM PDT 24
Finished Jun 10 06:57:49 PM PDT 24
Peak memory 281520 kb
Host smart-ffca340a-a776-4336-9be7-f470f2be449c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090492626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2090492626
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3273963619
Short name T674
Test name
Test status
Simulation time 1530152915 ps
CPU time 104.11 seconds
Started Jun 10 06:37:06 PM PDT 24
Finished Jun 10 06:38:50 PM PDT 24
Peak memory 249800 kb
Host smart-698ce5c4-170d-4ce3-a8f7-4a6716f7fb27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32739
63619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3273963619
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2469934620
Short name T558
Test name
Test status
Simulation time 3264625638 ps
CPU time 52.17 seconds
Started Jun 10 06:37:06 PM PDT 24
Finished Jun 10 06:37:59 PM PDT 24
Peak memory 255244 kb
Host smart-7d3c1006-b9f6-48d8-8d4a-1aab0506c558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24699
34620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2469934620
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1667389307
Short name T629
Test name
Test status
Simulation time 30555869843 ps
CPU time 1992.6 seconds
Started Jun 10 06:37:07 PM PDT 24
Finished Jun 10 07:10:20 PM PDT 24
Peak memory 273448 kb
Host smart-0a44fe2c-85cd-4495-b808-b893f76c11e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667389307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1667389307
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1981389306
Short name T75
Test name
Test status
Simulation time 7621046736 ps
CPU time 677.58 seconds
Started Jun 10 06:37:13 PM PDT 24
Finished Jun 10 06:48:31 PM PDT 24
Peak memory 265124 kb
Host smart-3bb7649a-6710-49fc-a6a0-36173f26a05f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981389306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1981389306
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3889456086
Short name T386
Test name
Test status
Simulation time 386899228 ps
CPU time 32.63 seconds
Started Jun 10 06:37:05 PM PDT 24
Finished Jun 10 06:37:38 PM PDT 24
Peak memory 248744 kb
Host smart-7e8d2408-1dac-4532-87df-840cf25e47e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38894
56086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3889456086
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3896572446
Short name T535
Test name
Test status
Simulation time 1301479620 ps
CPU time 41.76 seconds
Started Jun 10 06:37:07 PM PDT 24
Finished Jun 10 06:37:49 PM PDT 24
Peak memory 248648 kb
Host smart-ea88dfd7-7f1c-47ba-85bd-8dadb0e25244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38965
72446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3896572446
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2022790612
Short name T255
Test name
Test status
Simulation time 2114174757 ps
CPU time 27.28 seconds
Started Jun 10 06:37:09 PM PDT 24
Finished Jun 10 06:37:37 PM PDT 24
Peak memory 256464 kb
Host smart-7b3b686e-0c02-4d12-8266-12b059b33edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20227
90612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2022790612
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1046697635
Short name T429
Test name
Test status
Simulation time 253386267 ps
CPU time 22.77 seconds
Started Jun 10 06:37:07 PM PDT 24
Finished Jun 10 06:37:30 PM PDT 24
Peak memory 248752 kb
Host smart-eeb65162-6b61-486e-aafa-7d92804b149b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10466
97635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1046697635
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1172506502
Short name T25
Test name
Test status
Simulation time 33654313381 ps
CPU time 1505.55 seconds
Started Jun 10 06:37:11 PM PDT 24
Finished Jun 10 07:02:17 PM PDT 24
Peak memory 272964 kb
Host smart-7dffd80e-11fd-436b-bd85-e59798c0e7ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172506502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1172506502
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2933209784
Short name T197
Test name
Test status
Simulation time 50643058 ps
CPU time 2.12 seconds
Started Jun 10 06:37:12 PM PDT 24
Finished Jun 10 06:37:14 PM PDT 24
Peak memory 248844 kb
Host smart-3d89302c-aa53-4a50-a042-19ed84253563
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2933209784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2933209784
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.693444338
Short name T2
Test name
Test status
Simulation time 159260306590 ps
CPU time 2675.06 seconds
Started Jun 10 06:37:13 PM PDT 24
Finished Jun 10 07:21:49 PM PDT 24
Peak memory 285784 kb
Host smart-4c11e8cc-8872-46db-9ec0-8b42fab5b3b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693444338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.693444338
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3343807245
Short name T427
Test name
Test status
Simulation time 412595567 ps
CPU time 11.31 seconds
Started Jun 10 06:37:13 PM PDT 24
Finished Jun 10 06:37:24 PM PDT 24
Peak memory 248660 kb
Host smart-863cb5cf-3a2f-47b4-b81c-1d2502f60a07
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3343807245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3343807245
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2154167430
Short name T282
Test name
Test status
Simulation time 5057339365 ps
CPU time 284.7 seconds
Started Jun 10 06:37:12 PM PDT 24
Finished Jun 10 06:41:57 PM PDT 24
Peak memory 251116 kb
Host smart-dfddf9da-db06-4dd1-962b-9f8b75718c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21541
67430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2154167430
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.639885900
Short name T223
Test name
Test status
Simulation time 1717502030 ps
CPU time 34.93 seconds
Started Jun 10 06:37:10 PM PDT 24
Finished Jun 10 06:37:45 PM PDT 24
Peak memory 256080 kb
Host smart-5b821959-320b-4176-b7ab-eedccd8382af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63988
5900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.639885900
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1121374499
Short name T696
Test name
Test status
Simulation time 114937720298 ps
CPU time 1972.96 seconds
Started Jun 10 06:37:16 PM PDT 24
Finished Jun 10 07:10:10 PM PDT 24
Peak memory 273364 kb
Host smart-f5b85342-bb38-476a-ac1a-dd25196046fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121374499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1121374499
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3771416743
Short name T583
Test name
Test status
Simulation time 20165794069 ps
CPU time 1322.82 seconds
Started Jun 10 06:37:12 PM PDT 24
Finished Jun 10 06:59:15 PM PDT 24
Peak memory 281624 kb
Host smart-a9799f5b-6dcf-41a8-9f58-1857f47acf6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771416743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3771416743
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.638825844
Short name T313
Test name
Test status
Simulation time 25200050750 ps
CPU time 220.19 seconds
Started Jun 10 06:37:16 PM PDT 24
Finished Jun 10 06:40:57 PM PDT 24
Peak memory 248008 kb
Host smart-2947b3a8-1e5c-4dc8-a840-bc6edfacb4b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638825844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.638825844
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3678442633
Short name T417
Test name
Test status
Simulation time 214861163 ps
CPU time 15.8 seconds
Started Jun 10 06:37:22 PM PDT 24
Finished Jun 10 06:37:38 PM PDT 24
Peak memory 248752 kb
Host smart-004f0c1b-5df7-40bf-9f67-a29553c82793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36784
42633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3678442633
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1424592832
Short name T229
Test name
Test status
Simulation time 97614358 ps
CPU time 4.84 seconds
Started Jun 10 06:37:16 PM PDT 24
Finished Jun 10 06:37:21 PM PDT 24
Peak memory 240480 kb
Host smart-4ecc3911-1140-4ced-8223-6a35025d303b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14245
92832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1424592832
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3997900794
Short name T277
Test name
Test status
Simulation time 561728967 ps
CPU time 32.53 seconds
Started Jun 10 06:37:12 PM PDT 24
Finished Jun 10 06:37:45 PM PDT 24
Peak memory 247688 kb
Host smart-981b61a4-3915-404b-a859-95311a4ce22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39979
00794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3997900794
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1916862057
Short name T598
Test name
Test status
Simulation time 2954084192 ps
CPU time 41.16 seconds
Started Jun 10 06:37:10 PM PDT 24
Finished Jun 10 06:37:52 PM PDT 24
Peak memory 248800 kb
Host smart-8627a67c-9fba-4399-aa58-fc37588f76e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19168
62057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1916862057
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2343135344
Short name T287
Test name
Test status
Simulation time 77933373712 ps
CPU time 4279.75 seconds
Started Jun 10 06:37:13 PM PDT 24
Finished Jun 10 07:48:34 PM PDT 24
Peak memory 321976 kb
Host smart-141d797f-b1b1-4d40-8f93-78195bcac2ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343135344 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2343135344
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2022826708
Short name T198
Test name
Test status
Simulation time 220407143 ps
CPU time 2.43 seconds
Started Jun 10 06:37:25 PM PDT 24
Finished Jun 10 06:37:27 PM PDT 24
Peak memory 248908 kb
Host smart-f4355dcd-40dc-4b5c-b85e-2fb4f6854523
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2022826708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2022826708
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2045189872
Short name T680
Test name
Test status
Simulation time 15282095196 ps
CPU time 953.59 seconds
Started Jun 10 06:37:15 PM PDT 24
Finished Jun 10 06:53:09 PM PDT 24
Peak memory 273080 kb
Host smart-fbda31f1-5b48-411b-aab5-1ac1b4b9e78d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045189872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2045189872
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2312568350
Short name T642
Test name
Test status
Simulation time 1227329131 ps
CPU time 10.46 seconds
Started Jun 10 06:37:19 PM PDT 24
Finished Jun 10 06:37:30 PM PDT 24
Peak memory 248736 kb
Host smart-68c3b586-9bf4-4bd1-8ff6-c7a4cee41b8d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2312568350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2312568350
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.721773454
Short name T431
Test name
Test status
Simulation time 1475782142 ps
CPU time 60.87 seconds
Started Jun 10 06:37:12 PM PDT 24
Finished Jun 10 06:38:13 PM PDT 24
Peak memory 256912 kb
Host smart-5d687845-2e09-4318-bde1-6d15e2cd3f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72177
3454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.721773454
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1180752951
Short name T442
Test name
Test status
Simulation time 384870004 ps
CPU time 18.66 seconds
Started Jun 10 06:37:10 PM PDT 24
Finished Jun 10 06:37:29 PM PDT 24
Peak memory 255032 kb
Host smart-b4046048-b349-4747-98a2-ac40a1132afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11807
52951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1180752951
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2406060166
Short name T110
Test name
Test status
Simulation time 78538086775 ps
CPU time 2246.54 seconds
Started Jun 10 06:37:13 PM PDT 24
Finished Jun 10 07:14:40 PM PDT 24
Peak memory 286716 kb
Host smart-d0d1229c-1169-423a-8119-0e6b04667134
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406060166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2406060166
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1545370658
Short name T624
Test name
Test status
Simulation time 7118622601 ps
CPU time 281.82 seconds
Started Jun 10 06:37:16 PM PDT 24
Finished Jun 10 06:41:58 PM PDT 24
Peak memory 254568 kb
Host smart-99088bf1-edd7-44f1-ab3a-4ec8695f4997
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545370658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1545370658
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3922219367
Short name T73
Test name
Test status
Simulation time 3526551853 ps
CPU time 51.82 seconds
Started Jun 10 06:37:11 PM PDT 24
Finished Jun 10 06:38:03 PM PDT 24
Peak memory 248792 kb
Host smart-7d5ae668-be6a-46ac-9410-031972c89157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39222
19367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3922219367
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1248487691
Short name T536
Test name
Test status
Simulation time 159810053 ps
CPU time 3.69 seconds
Started Jun 10 06:37:12 PM PDT 24
Finished Jun 10 06:37:16 PM PDT 24
Peak memory 239460 kb
Host smart-c5fe9313-1d4e-4f5a-92e5-e04c932f3460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12484
87691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1248487691
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2394977546
Short name T19
Test name
Test status
Simulation time 1330725671 ps
CPU time 51.66 seconds
Started Jun 10 06:37:23 PM PDT 24
Finished Jun 10 06:38:15 PM PDT 24
Peak memory 256672 kb
Host smart-ca687fdd-3c1a-45f1-9a33-5003512b64ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23949
77546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2394977546
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.4273067412
Short name T296
Test name
Test status
Simulation time 1064823529 ps
CPU time 32.08 seconds
Started Jun 10 06:37:13 PM PDT 24
Finished Jun 10 06:37:45 PM PDT 24
Peak memory 248668 kb
Host smart-05b5cc37-470d-46ad-a022-532c6115c38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42730
67412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.4273067412
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1689845183
Short name T208
Test name
Test status
Simulation time 62043251 ps
CPU time 2.4 seconds
Started Jun 10 06:37:16 PM PDT 24
Finished Jun 10 06:37:19 PM PDT 24
Peak memory 248840 kb
Host smart-46383754-26a8-4e55-b581-b415d85d7667
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1689845183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1689845183
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1734885112
Short name T622
Test name
Test status
Simulation time 43261961728 ps
CPU time 1275.95 seconds
Started Jun 10 06:37:20 PM PDT 24
Finished Jun 10 06:58:36 PM PDT 24
Peak memory 288884 kb
Host smart-efaface1-2018-4459-9ecb-0b4cc7d4ce60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734885112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1734885112
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2178395262
Short name T641
Test name
Test status
Simulation time 6909869491 ps
CPU time 68.15 seconds
Started Jun 10 06:37:15 PM PDT 24
Finished Jun 10 06:38:24 PM PDT 24
Peak memory 248736 kb
Host smart-a88326bd-a7ec-4eb1-b947-e900991628a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2178395262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2178395262
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1326152429
Short name T179
Test name
Test status
Simulation time 13726855108 ps
CPU time 82.58 seconds
Started Jun 10 06:37:15 PM PDT 24
Finished Jun 10 06:38:38 PM PDT 24
Peak memory 248936 kb
Host smart-e52a9c6d-d295-45a6-bb33-e0b6691c5eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13261
52429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1326152429
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2541058229
Short name T492
Test name
Test status
Simulation time 772672202 ps
CPU time 49.66 seconds
Started Jun 10 06:37:16 PM PDT 24
Finished Jun 10 06:38:06 PM PDT 24
Peak memory 255824 kb
Host smart-f0719b7a-9f92-4965-b96c-240a96b4ff71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25410
58229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2541058229
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.896046767
Short name T573
Test name
Test status
Simulation time 38559137132 ps
CPU time 2262.33 seconds
Started Jun 10 06:37:23 PM PDT 24
Finished Jun 10 07:15:06 PM PDT 24
Peak memory 288768 kb
Host smart-8e95898d-1d8d-427c-811f-08b4642c36eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896046767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.896046767
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1104878827
Short name T309
Test name
Test status
Simulation time 20458020205 ps
CPU time 392.83 seconds
Started Jun 10 06:37:16 PM PDT 24
Finished Jun 10 06:43:49 PM PDT 24
Peak memory 248316 kb
Host smart-72d799fc-1eca-468d-8d4a-73066648cffe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104878827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1104878827
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3284732854
Short name T399
Test name
Test status
Simulation time 352906460 ps
CPU time 17.19 seconds
Started Jun 10 06:37:19 PM PDT 24
Finished Jun 10 06:37:36 PM PDT 24
Peak memory 256300 kb
Host smart-29b9f4c2-d122-4b64-850e-6caa76c5a52f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32847
32854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3284732854
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2696369368
Short name T547
Test name
Test status
Simulation time 552604965 ps
CPU time 25.01 seconds
Started Jun 10 06:37:17 PM PDT 24
Finished Jun 10 06:37:42 PM PDT 24
Peak memory 247568 kb
Host smart-dc2b9de7-ccdf-459d-8b76-8ff3caa37493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26963
69368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2696369368
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1632546422
Short name T659
Test name
Test status
Simulation time 6767783935 ps
CPU time 52.08 seconds
Started Jun 10 06:37:21 PM PDT 24
Finished Jun 10 06:38:13 PM PDT 24
Peak memory 248784 kb
Host smart-b34b3f59-128a-447b-9fb5-73a15b016b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16325
46422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1632546422
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.4249286315
Short name T672
Test name
Test status
Simulation time 23689984 ps
CPU time 2.98 seconds
Started Jun 10 06:37:20 PM PDT 24
Finished Jun 10 06:37:23 PM PDT 24
Peak memory 240496 kb
Host smart-2fb93774-85c6-46a6-84db-e802f84d9b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42492
86315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.4249286315
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2275799912
Short name T199
Test name
Test status
Simulation time 45359397 ps
CPU time 2.51 seconds
Started Jun 10 06:37:25 PM PDT 24
Finished Jun 10 06:37:28 PM PDT 24
Peak memory 248924 kb
Host smart-f0e5cde8-fdcd-4d26-adf0-d21e054d86b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2275799912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2275799912
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.385722185
Short name T630
Test name
Test status
Simulation time 51705154848 ps
CPU time 1390.38 seconds
Started Jun 10 06:37:25 PM PDT 24
Finished Jun 10 07:00:36 PM PDT 24
Peak memory 289508 kb
Host smart-30156914-da84-4b44-bf71-0c594451ca07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385722185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.385722185
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1711703594
Short name T83
Test name
Test status
Simulation time 1580706025 ps
CPU time 19.41 seconds
Started Jun 10 06:37:27 PM PDT 24
Finished Jun 10 06:37:47 PM PDT 24
Peak memory 248736 kb
Host smart-741576cd-c82f-4e4b-bccd-a8053b04ff00
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1711703594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1711703594
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.147083080
Short name T563
Test name
Test status
Simulation time 10519114094 ps
CPU time 148.44 seconds
Started Jun 10 06:37:19 PM PDT 24
Finished Jun 10 06:39:48 PM PDT 24
Peak memory 256956 kb
Host smart-93270fd3-2ade-482c-be64-bf94426b80cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14708
3080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.147083080
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2975446256
Short name T678
Test name
Test status
Simulation time 1598815494 ps
CPU time 23.49 seconds
Started Jun 10 06:37:27 PM PDT 24
Finished Jun 10 06:37:51 PM PDT 24
Peak memory 255392 kb
Host smart-d13969e8-893e-43f3-9479-76da1fed2775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29754
46256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2975446256
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1220076335
Short name T108
Test name
Test status
Simulation time 9223223203 ps
CPU time 789.04 seconds
Started Jun 10 06:37:25 PM PDT 24
Finished Jun 10 06:50:34 PM PDT 24
Peak memory 273172 kb
Host smart-a8f870c4-365d-4c4e-9c61-6226b1149abd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220076335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1220076335
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.483582716
Short name T62
Test name
Test status
Simulation time 1307467635 ps
CPU time 45.32 seconds
Started Jun 10 06:37:27 PM PDT 24
Finished Jun 10 06:38:13 PM PDT 24
Peak memory 248768 kb
Host smart-4d4922b6-460e-4d67-a04b-a7cc847099c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48358
2716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.483582716
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.833602380
Short name T220
Test name
Test status
Simulation time 195609392 ps
CPU time 14.56 seconds
Started Jun 10 06:37:18 PM PDT 24
Finished Jun 10 06:37:33 PM PDT 24
Peak memory 255412 kb
Host smart-e0d878da-0e18-4c3d-8a88-570d9bb445cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83360
2380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.833602380
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.4145231429
Short name T228
Test name
Test status
Simulation time 3824463818 ps
CPU time 42.65 seconds
Started Jun 10 06:37:24 PM PDT 24
Finished Jun 10 06:38:07 PM PDT 24
Peak memory 248628 kb
Host smart-cce70f7c-fe42-436a-9a3c-d57e1a7fe961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41452
31429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.4145231429
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.652723150
Short name T614
Test name
Test status
Simulation time 97170524681 ps
CPU time 1823.45 seconds
Started Jun 10 06:37:26 PM PDT 24
Finished Jun 10 07:07:50 PM PDT 24
Peak memory 301936 kb
Host smart-bbdf3545-1647-481b-8cd7-8c7376ef8c77
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652723150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.652723150
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3608070612
Short name T205
Test name
Test status
Simulation time 32798887 ps
CPU time 3.16 seconds
Started Jun 10 06:37:31 PM PDT 24
Finished Jun 10 06:37:34 PM PDT 24
Peak memory 248912 kb
Host smart-1e1ad713-e3a7-4243-9b08-427c633e6157
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3608070612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3608070612
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3703265817
Short name T475
Test name
Test status
Simulation time 15642962334 ps
CPU time 982.21 seconds
Started Jun 10 06:37:26 PM PDT 24
Finished Jun 10 06:53:49 PM PDT 24
Peak memory 271780 kb
Host smart-8ce855b5-602a-4355-be01-88928f7d421b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703265817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3703265817
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.213863030
Short name T661
Test name
Test status
Simulation time 641112480 ps
CPU time 10.35 seconds
Started Jun 10 06:37:32 PM PDT 24
Finished Jun 10 06:37:43 PM PDT 24
Peak memory 248744 kb
Host smart-2fb30c93-8fb5-42f8-a24e-416788825612
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=213863030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.213863030
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.423053642
Short name T588
Test name
Test status
Simulation time 10189063347 ps
CPU time 156.21 seconds
Started Jun 10 06:37:27 PM PDT 24
Finished Jun 10 06:40:03 PM PDT 24
Peak memory 256928 kb
Host smart-cd12f410-bde6-4dd9-9825-eabd2ac5b989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42305
3642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.423053642
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1336770431
Short name T644
Test name
Test status
Simulation time 1468184448 ps
CPU time 23.84 seconds
Started Jun 10 06:37:28 PM PDT 24
Finished Jun 10 06:37:52 PM PDT 24
Peak memory 255624 kb
Host smart-e5a03970-7f31-4926-a451-e55795960aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13367
70431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1336770431
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2001406076
Short name T234
Test name
Test status
Simulation time 24080955658 ps
CPU time 1658.02 seconds
Started Jun 10 06:37:25 PM PDT 24
Finished Jun 10 07:05:04 PM PDT 24
Peak memory 273364 kb
Host smart-5bf0419a-b897-4fcc-a5fe-22e209b666ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001406076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2001406076
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3385389152
Short name T301
Test name
Test status
Simulation time 85448289614 ps
CPU time 2722.57 seconds
Started Jun 10 06:37:33 PM PDT 24
Finished Jun 10 07:22:56 PM PDT 24
Peak memory 289244 kb
Host smart-8928acfb-9202-4498-a35b-a3481a6a40cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385389152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3385389152
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1782335356
Short name T325
Test name
Test status
Simulation time 3883041844 ps
CPU time 156.43 seconds
Started Jun 10 06:37:27 PM PDT 24
Finished Jun 10 06:40:04 PM PDT 24
Peak memory 248276 kb
Host smart-2303c8fb-49a6-4324-8aa0-f498607fb626
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782335356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1782335356
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3273315280
Short name T438
Test name
Test status
Simulation time 123747899 ps
CPU time 9.33 seconds
Started Jun 10 06:37:28 PM PDT 24
Finished Jun 10 06:37:38 PM PDT 24
Peak memory 252140 kb
Host smart-28f0a9de-c144-44fc-a433-ffc2ebf618d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32733
15280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3273315280
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3090749314
Short name T274
Test name
Test status
Simulation time 3669713406 ps
CPU time 58.93 seconds
Started Jun 10 06:37:28 PM PDT 24
Finished Jun 10 06:38:27 PM PDT 24
Peak memory 255744 kb
Host smart-ed13bfeb-d2dd-44d5-b285-5b33e611aee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30907
49314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3090749314
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1115123388
Short name T515
Test name
Test status
Simulation time 171184527 ps
CPU time 10.88 seconds
Started Jun 10 06:37:27 PM PDT 24
Finished Jun 10 06:37:38 PM PDT 24
Peak memory 254304 kb
Host smart-5abed22c-d94d-4b3f-abfa-421a68d62b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11151
23388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1115123388
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3816038489
Short name T628
Test name
Test status
Simulation time 24252653565 ps
CPU time 295.78 seconds
Started Jun 10 06:37:32 PM PDT 24
Finished Jun 10 06:42:28 PM PDT 24
Peak memory 253024 kb
Host smart-ab5473f9-6faf-45fa-aeaa-af30a68062ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816038489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3816038489
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3300333086
Short name T117
Test name
Test status
Simulation time 24223366477 ps
CPU time 2118.23 seconds
Started Jun 10 06:37:31 PM PDT 24
Finished Jun 10 07:12:49 PM PDT 24
Peak memory 289904 kb
Host smart-3e0ca7f8-5992-4cd7-add9-bf06e08c5fcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300333086 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3300333086
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3793746166
Short name T203
Test name
Test status
Simulation time 63874263 ps
CPU time 3.34 seconds
Started Jun 10 06:37:42 PM PDT 24
Finished Jun 10 06:37:46 PM PDT 24
Peak memory 248896 kb
Host smart-44258401-5e28-459f-b743-d34f6633d824
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3793746166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3793746166
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3719787571
Short name T692
Test name
Test status
Simulation time 193677048721 ps
CPU time 1788.57 seconds
Started Jun 10 06:37:39 PM PDT 24
Finished Jun 10 07:07:28 PM PDT 24
Peak memory 273420 kb
Host smart-1dd988b7-2a98-432d-9ed9-eccc3ab0dd9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719787571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3719787571
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3904618814
Short name T375
Test name
Test status
Simulation time 3544204327 ps
CPU time 41.53 seconds
Started Jun 10 06:37:40 PM PDT 24
Finished Jun 10 06:38:22 PM PDT 24
Peak memory 248804 kb
Host smart-eaa70357-e4ee-4f19-a849-a352c9f19a6c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3904618814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3904618814
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2612889804
Short name T549
Test name
Test status
Simulation time 257909273 ps
CPU time 24.69 seconds
Started Jun 10 06:37:37 PM PDT 24
Finished Jun 10 06:38:03 PM PDT 24
Peak memory 256584 kb
Host smart-5bb906a1-cc40-4d1a-8d13-097a2ab39337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26128
89804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2612889804
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.668134982
Short name T47
Test name
Test status
Simulation time 132245263 ps
CPU time 10.97 seconds
Started Jun 10 06:37:39 PM PDT 24
Finished Jun 10 06:37:51 PM PDT 24
Peak memory 253580 kb
Host smart-8ced6bdf-f941-4371-83d2-d52be11c0870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66813
4982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.668134982
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2287822501
Short name T98
Test name
Test status
Simulation time 11749625826 ps
CPU time 1167.93 seconds
Started Jun 10 06:37:35 PM PDT 24
Finished Jun 10 06:57:03 PM PDT 24
Peak memory 285004 kb
Host smart-1a42030e-702a-4b26-8ee3-e0e05a13ac0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287822501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2287822501
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2037713224
Short name T307
Test name
Test status
Simulation time 18134601885 ps
CPU time 691.43 seconds
Started Jun 10 06:37:35 PM PDT 24
Finished Jun 10 06:49:07 PM PDT 24
Peak memory 247212 kb
Host smart-c7ab7b13-f9d4-47d0-bf21-52dedf85d061
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037713224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2037713224
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2745969996
Short name T613
Test name
Test status
Simulation time 3949684654 ps
CPU time 58.61 seconds
Started Jun 10 06:37:36 PM PDT 24
Finished Jun 10 06:38:35 PM PDT 24
Peak memory 256324 kb
Host smart-4d08397f-a4c7-4491-a4a9-40685bd2f55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27459
69996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2745969996
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3147452737
Short name T638
Test name
Test status
Simulation time 532999567 ps
CPU time 39.92 seconds
Started Jun 10 06:37:37 PM PDT 24
Finished Jun 10 06:38:17 PM PDT 24
Peak memory 255396 kb
Host smart-37d6fb04-20c9-41f0-8024-6940449687b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31474
52737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3147452737
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.4213424923
Short name T191
Test name
Test status
Simulation time 180714143 ps
CPU time 18.83 seconds
Started Jun 10 06:37:33 PM PDT 24
Finished Jun 10 06:37:52 PM PDT 24
Peak memory 248756 kb
Host smart-441fd6c2-0e7e-486a-b93d-4680db972958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42134
24923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.4213424923
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2295170711
Short name T617
Test name
Test status
Simulation time 304275741 ps
CPU time 27.97 seconds
Started Jun 10 06:37:29 PM PDT 24
Finished Jun 10 06:37:57 PM PDT 24
Peak memory 248784 kb
Host smart-24b73889-0948-414d-a7ce-42659fbed3bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22951
70711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2295170711
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1022288350
Short name T406
Test name
Test status
Simulation time 147866743435 ps
CPU time 2513.03 seconds
Started Jun 10 06:37:39 PM PDT 24
Finished Jun 10 07:19:33 PM PDT 24
Peak memory 289004 kb
Host smart-50fd14ff-8b23-4450-bbf3-a7c5f25eeca7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022288350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1022288350
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2452941973
Short name T65
Test name
Test status
Simulation time 49970307116 ps
CPU time 1568.35 seconds
Started Jun 10 06:37:42 PM PDT 24
Finished Jun 10 07:03:51 PM PDT 24
Peak memory 272568 kb
Host smart-662ecc31-efeb-40ed-b8bd-f294ce00f5cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452941973 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2452941973
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4222288382
Short name T201
Test name
Test status
Simulation time 16277674 ps
CPU time 2.59 seconds
Started Jun 10 06:37:41 PM PDT 24
Finished Jun 10 06:37:44 PM PDT 24
Peak memory 248932 kb
Host smart-062b6c82-571d-4efe-9dbf-91239dfe8288
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4222288382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4222288382
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.384633572
Short name T428
Test name
Test status
Simulation time 34685858664 ps
CPU time 1067.7 seconds
Started Jun 10 06:37:38 PM PDT 24
Finished Jun 10 06:55:26 PM PDT 24
Peak memory 289116 kb
Host smart-ceac5784-b98e-4dad-ae02-ddba83ca9449
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384633572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.384633572
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.4088873513
Short name T181
Test name
Test status
Simulation time 851777258 ps
CPU time 16.97 seconds
Started Jun 10 06:37:41 PM PDT 24
Finished Jun 10 06:37:58 PM PDT 24
Peak memory 248736 kb
Host smart-8cd6d7bf-2291-440c-b6f1-c87c3f03eab9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4088873513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.4088873513
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1483928346
Short name T551
Test name
Test status
Simulation time 140283959 ps
CPU time 13.4 seconds
Started Jun 10 06:37:40 PM PDT 24
Finished Jun 10 06:37:54 PM PDT 24
Peak memory 248940 kb
Host smart-842eef67-2d6f-49aa-9210-dd50c6cb33e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14839
28346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1483928346
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.4166952178
Short name T485
Test name
Test status
Simulation time 4432770191 ps
CPU time 47.82 seconds
Started Jun 10 06:37:39 PM PDT 24
Finished Jun 10 06:38:27 PM PDT 24
Peak memory 248732 kb
Host smart-db4f80ad-330a-4728-8c75-a91bcdc8a962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41669
52178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.4166952178
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1179172251
Short name T338
Test name
Test status
Simulation time 26516547482 ps
CPU time 1428.48 seconds
Started Jun 10 06:37:42 PM PDT 24
Finished Jun 10 07:01:31 PM PDT 24
Peak memory 270360 kb
Host smart-a5e3fd0b-ffbf-4575-801b-abd1a6825e22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179172251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1179172251
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3796798139
Short name T694
Test name
Test status
Simulation time 20571860882 ps
CPU time 1282.44 seconds
Started Jun 10 06:37:44 PM PDT 24
Finished Jun 10 06:59:07 PM PDT 24
Peak memory 272616 kb
Host smart-964005ba-2a8a-49e5-bb15-29159ac2c726
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796798139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3796798139
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3527689418
Short name T305
Test name
Test status
Simulation time 48299770441 ps
CPU time 534.57 seconds
Started Jun 10 06:37:41 PM PDT 24
Finished Jun 10 06:46:36 PM PDT 24
Peak memory 248360 kb
Host smart-899b71a9-82c0-4046-bce1-5273c1c4ce31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527689418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3527689418
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1436104359
Short name T491
Test name
Test status
Simulation time 371096288 ps
CPU time 21.51 seconds
Started Jun 10 06:37:44 PM PDT 24
Finished Jun 10 06:38:05 PM PDT 24
Peak memory 256848 kb
Host smart-2a44fca3-2471-4c19-9314-77f4372b3a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14361
04359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1436104359
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.4116056498
Short name T599
Test name
Test status
Simulation time 493895773 ps
CPU time 52.09 seconds
Started Jun 10 06:37:42 PM PDT 24
Finished Jun 10 06:38:34 PM PDT 24
Peak memory 255964 kb
Host smart-f19b2fc4-76ac-4f32-b026-449c406e76e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41160
56498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4116056498
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2102586321
Short name T453
Test name
Test status
Simulation time 500806347 ps
CPU time 33.39 seconds
Started Jun 10 06:37:42 PM PDT 24
Finished Jun 10 06:38:16 PM PDT 24
Peak memory 255580 kb
Host smart-f881e6fa-abc3-4603-8e03-d27b06ed2626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21025
86321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2102586321
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3968634447
Short name T394
Test name
Test status
Simulation time 2035261127 ps
CPU time 32.04 seconds
Started Jun 10 06:37:38 PM PDT 24
Finished Jun 10 06:38:10 PM PDT 24
Peak memory 255396 kb
Host smart-1ecb9255-2b7d-4369-ab9d-ed4ec026a1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39686
34447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3968634447
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2171215772
Short name T61
Test name
Test status
Simulation time 33659733196 ps
CPU time 3620.75 seconds
Started Jun 10 06:37:42 PM PDT 24
Finished Jun 10 07:38:03 PM PDT 24
Peak memory 322472 kb
Host smart-36bd4bbe-a441-4a16-84c0-eb5efe482d8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171215772 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2171215772
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2823284565
Short name T207
Test name
Test status
Simulation time 164550599 ps
CPU time 2.23 seconds
Started Jun 10 06:37:49 PM PDT 24
Finished Jun 10 06:37:52 PM PDT 24
Peak memory 248896 kb
Host smart-a68c7176-9e8f-48a9-90d8-00554bfb76a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2823284565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2823284565
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.93186880
Short name T51
Test name
Test status
Simulation time 46195559346 ps
CPU time 1370.87 seconds
Started Jun 10 06:37:49 PM PDT 24
Finished Jun 10 07:00:40 PM PDT 24
Peak memory 272548 kb
Host smart-729bffcd-a351-4e8d-aafa-0271eafd03ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93186880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.93186880
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2892491154
Short name T373
Test name
Test status
Simulation time 893675439 ps
CPU time 36.75 seconds
Started Jun 10 06:37:50 PM PDT 24
Finished Jun 10 06:38:27 PM PDT 24
Peak memory 248760 kb
Host smart-19692764-76fb-47e3-b17f-9337631b4102
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2892491154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2892491154
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.665425633
Short name T700
Test name
Test status
Simulation time 3489909016 ps
CPU time 116.5 seconds
Started Jun 10 06:37:45 PM PDT 24
Finished Jun 10 06:39:42 PM PDT 24
Peak memory 250360 kb
Host smart-ea6d3cc9-572f-48b2-a1e4-9b3d32952c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66542
5633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.665425633
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3019737364
Short name T418
Test name
Test status
Simulation time 113262167 ps
CPU time 13.19 seconds
Started Jun 10 06:37:48 PM PDT 24
Finished Jun 10 06:38:02 PM PDT 24
Peak memory 248696 kb
Host smart-2e0512b1-5f6d-429b-ac73-13ae11bfb006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30197
37364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3019737364
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2148081864
Short name T42
Test name
Test status
Simulation time 35558832702 ps
CPU time 1976.62 seconds
Started Jun 10 06:37:46 PM PDT 24
Finished Jun 10 07:10:43 PM PDT 24
Peak memory 272988 kb
Host smart-0529a532-fa0a-4ece-8fcd-2c09070369cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148081864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2148081864
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.198416133
Short name T396
Test name
Test status
Simulation time 38054311755 ps
CPU time 2394.67 seconds
Started Jun 10 06:37:47 PM PDT 24
Finished Jun 10 07:17:42 PM PDT 24
Peak memory 282464 kb
Host smart-744e2412-9ff1-4443-8774-811f47f8afe0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198416133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.198416133
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2657842665
Short name T677
Test name
Test status
Simulation time 8490085019 ps
CPU time 311.01 seconds
Started Jun 10 06:37:46 PM PDT 24
Finished Jun 10 06:42:57 PM PDT 24
Peak memory 248004 kb
Host smart-40e2a1fd-c710-4a4b-9875-16cf6af6d989
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657842665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2657842665
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2758126853
Short name T371
Test name
Test status
Simulation time 3074190536 ps
CPU time 43.03 seconds
Started Jun 10 06:37:41 PM PDT 24
Finished Jun 10 06:38:24 PM PDT 24
Peak memory 256052 kb
Host smart-be15b527-5ec4-474a-9a61-f0e33c0716fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27581
26853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2758126853
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.416080352
Short name T582
Test name
Test status
Simulation time 2040982475 ps
CPU time 29.4 seconds
Started Jun 10 06:37:45 PM PDT 24
Finished Jun 10 06:38:15 PM PDT 24
Peak memory 255692 kb
Host smart-057bf3c6-aac4-4f31-9a33-e6a4f9c12439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41608
0352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.416080352
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2452914682
Short name T264
Test name
Test status
Simulation time 490485048 ps
CPU time 12.57 seconds
Started Jun 10 06:37:49 PM PDT 24
Finished Jun 10 06:38:02 PM PDT 24
Peak memory 255860 kb
Host smart-1c071544-3152-47c9-8117-98976d0d9a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24529
14682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2452914682
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1161085543
Short name T660
Test name
Test status
Simulation time 286358177 ps
CPU time 26.7 seconds
Started Jun 10 06:37:41 PM PDT 24
Finished Jun 10 06:38:08 PM PDT 24
Peak memory 256908 kb
Host smart-e71dd468-c354-4f4a-b126-26f73729f935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11610
85543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1161085543
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3486560489
Short name T567
Test name
Test status
Simulation time 70262191694 ps
CPU time 2362.5 seconds
Started Jun 10 06:37:49 PM PDT 24
Finished Jun 10 07:17:12 PM PDT 24
Peak memory 289600 kb
Host smart-65e80b00-b3a4-4a4d-91b1-27cc0dd90845
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486560489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3486560489
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.848754066
Short name T114
Test name
Test status
Simulation time 776093571679 ps
CPU time 4193.68 seconds
Started Jun 10 06:37:52 PM PDT 24
Finished Jun 10 07:47:46 PM PDT 24
Peak memory 334128 kb
Host smart-1278bc25-a1ac-4a3b-a9bb-05638b921d95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848754066 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.848754066
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.549548575
Short name T210
Test name
Test status
Simulation time 153129027 ps
CPU time 3.96 seconds
Started Jun 10 06:36:45 PM PDT 24
Finished Jun 10 06:36:50 PM PDT 24
Peak memory 248772 kb
Host smart-064036d4-ca50-45eb-a9ed-84291dc0ed14
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=549548575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.549548575
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2036645575
Short name T44
Test name
Test status
Simulation time 57398846168 ps
CPU time 1663.9 seconds
Started Jun 10 06:36:44 PM PDT 24
Finished Jun 10 07:04:28 PM PDT 24
Peak memory 269336 kb
Host smart-57e90d92-c1c9-4697-8e4f-c4fa2cdc59a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036645575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2036645575
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2836556846
Short name T676
Test name
Test status
Simulation time 1366042470 ps
CPU time 33.51 seconds
Started Jun 10 06:36:45 PM PDT 24
Finished Jun 10 06:37:19 PM PDT 24
Peak memory 248636 kb
Host smart-384f348b-ec64-43bb-8ad0-5ed1fdfbfd9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2836556846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2836556846
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3099845748
Short name T391
Test name
Test status
Simulation time 13597408019 ps
CPU time 177.73 seconds
Started Jun 10 06:36:46 PM PDT 24
Finished Jun 10 06:39:44 PM PDT 24
Peak memory 257040 kb
Host smart-696dcb97-2243-41e9-80f5-dd0cc064d26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30998
45748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3099845748
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1266836801
Short name T600
Test name
Test status
Simulation time 1246208012 ps
CPU time 35.29 seconds
Started Jun 10 06:36:47 PM PDT 24
Finished Jun 10 06:37:23 PM PDT 24
Peak memory 248892 kb
Host smart-cd7ec90c-bb76-4a77-a0dc-ad6de16f945c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12668
36801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1266836801
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1801238445
Short name T217
Test name
Test status
Simulation time 57975585609 ps
CPU time 1375.03 seconds
Started Jun 10 06:36:45 PM PDT 24
Finished Jun 10 06:59:41 PM PDT 24
Peak memory 289264 kb
Host smart-2707bc7b-b042-45c8-b323-64db8234160b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801238445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1801238445
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3684919067
Short name T34
Test name
Test status
Simulation time 22139493856 ps
CPU time 1455.72 seconds
Started Jun 10 06:36:50 PM PDT 24
Finished Jun 10 07:01:07 PM PDT 24
Peak memory 273352 kb
Host smart-47c291f0-9a3d-4da9-b119-c2ce412453f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684919067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3684919067
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.404843623
Short name T568
Test name
Test status
Simulation time 995671054 ps
CPU time 55.82 seconds
Started Jun 10 06:36:47 PM PDT 24
Finished Jun 10 06:37:43 PM PDT 24
Peak memory 248644 kb
Host smart-dda3e9f1-edb3-41fb-87e2-8c49c38510b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40484
3623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.404843623
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3788533968
Short name T487
Test name
Test status
Simulation time 1047168760 ps
CPU time 28.51 seconds
Started Jun 10 06:36:48 PM PDT 24
Finished Jun 10 06:37:17 PM PDT 24
Peak memory 255068 kb
Host smart-32a035c9-ec3e-43c5-97dc-0546349f077a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37885
33968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3788533968
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1276359776
Short name T38
Test name
Test status
Simulation time 1093629238 ps
CPU time 24.85 seconds
Started Jun 10 06:36:52 PM PDT 24
Finished Jun 10 06:37:17 PM PDT 24
Peak memory 277584 kb
Host smart-7a2120f1-25a9-45bb-bc5a-624ece500c25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1276359776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1276359776
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.132623682
Short name T610
Test name
Test status
Simulation time 580943513 ps
CPU time 29.34 seconds
Started Jun 10 06:36:44 PM PDT 24
Finished Jun 10 06:37:14 PM PDT 24
Peak memory 248896 kb
Host smart-c0ad8a36-1cc4-456e-8bc4-c7f78987bc59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13262
3682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.132623682
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.65642035
Short name T450
Test name
Test status
Simulation time 142452357 ps
CPU time 10.66 seconds
Started Jun 10 06:36:48 PM PDT 24
Finished Jun 10 06:37:00 PM PDT 24
Peak memory 248640 kb
Host smart-2b1c04b8-2719-44df-9d49-a06932d461d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65642
035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.65642035
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1169692843
Short name T300
Test name
Test status
Simulation time 718129855072 ps
CPU time 1971.47 seconds
Started Jun 10 06:37:51 PM PDT 24
Finished Jun 10 07:10:43 PM PDT 24
Peak memory 269284 kb
Host smart-a2ba6f80-d5ee-465e-920d-751fe9b5cc21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169692843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1169692843
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1827710619
Short name T90
Test name
Test status
Simulation time 1247823195 ps
CPU time 45.91 seconds
Started Jun 10 06:37:50 PM PDT 24
Finished Jun 10 06:38:37 PM PDT 24
Peak memory 256056 kb
Host smart-d3f37ab2-746a-477c-ac91-402332f118fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18277
10619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1827710619
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1265722995
Short name T45
Test name
Test status
Simulation time 617945502 ps
CPU time 14.65 seconds
Started Jun 10 06:37:49 PM PDT 24
Finished Jun 10 06:38:04 PM PDT 24
Peak memory 256204 kb
Host smart-d7ee347a-8538-4bbc-85b4-74cd887c4e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12657
22995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1265722995
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.4037006495
Short name T336
Test name
Test status
Simulation time 7596964789 ps
CPU time 625.53 seconds
Started Jun 10 06:37:49 PM PDT 24
Finished Jun 10 06:48:15 PM PDT 24
Peak memory 273384 kb
Host smart-8c7c13d2-f0b0-46ca-a260-e3544536f324
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037006495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.4037006495
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.762192380
Short name T435
Test name
Test status
Simulation time 33357791289 ps
CPU time 2364.14 seconds
Started Jun 10 06:37:50 PM PDT 24
Finished Jun 10 07:17:14 PM PDT 24
Peak memory 281396 kb
Host smart-41886617-4227-4a55-b69d-2d910022bd10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762192380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.762192380
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.261249628
Short name T324
Test name
Test status
Simulation time 53505743004 ps
CPU time 626.54 seconds
Started Jun 10 06:37:50 PM PDT 24
Finished Jun 10 06:48:16 PM PDT 24
Peak memory 248204 kb
Host smart-b0f431b6-7c54-467d-b92a-c1bba7c53347
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261249628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.261249628
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.733384341
Short name T571
Test name
Test status
Simulation time 185603312 ps
CPU time 4.29 seconds
Started Jun 10 06:37:51 PM PDT 24
Finished Jun 10 06:37:55 PM PDT 24
Peak memory 240564 kb
Host smart-ca091bcb-a337-4d64-9a33-fe46a4696725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73338
4341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.733384341
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.4010964749
Short name T68
Test name
Test status
Simulation time 1465818172 ps
CPU time 7.77 seconds
Started Jun 10 06:37:49 PM PDT 24
Finished Jun 10 06:37:57 PM PDT 24
Peak memory 254580 kb
Host smart-59c3dba6-380f-4a85-92bc-51a6b8c4c1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40109
64749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.4010964749
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1127006963
Short name T280
Test name
Test status
Simulation time 222215895 ps
CPU time 12.64 seconds
Started Jun 10 06:37:53 PM PDT 24
Finished Jun 10 06:38:06 PM PDT 24
Peak memory 247644 kb
Host smart-ff6300c8-3e24-4b79-8446-65c2443a3945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11270
06963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1127006963
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3692576082
Short name T72
Test name
Test status
Simulation time 1586183345 ps
CPU time 44.68 seconds
Started Jun 10 06:37:52 PM PDT 24
Finished Jun 10 06:38:37 PM PDT 24
Peak memory 248748 kb
Host smart-8aa0df37-63c0-4266-90b4-a1d80cedab2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36925
76082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3692576082
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2799318508
Short name T481
Test name
Test status
Simulation time 366216545 ps
CPU time 12.92 seconds
Started Jun 10 06:37:53 PM PDT 24
Finished Jun 10 06:38:07 PM PDT 24
Peak memory 254992 kb
Host smart-b3a7cfa6-02d1-425d-922b-7214f5fddc8f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799318508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2799318508
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.1565926282
Short name T222
Test name
Test status
Simulation time 182147514956 ps
CPU time 3126.56 seconds
Started Jun 10 06:37:54 PM PDT 24
Finished Jun 10 07:30:01 PM PDT 24
Peak memory 322580 kb
Host smart-27ea9042-60c5-47df-a762-eab9a0f70b46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565926282 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.1565926282
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3865725075
Short name T522
Test name
Test status
Simulation time 24128534721 ps
CPU time 1535.6 seconds
Started Jun 10 06:37:54 PM PDT 24
Finished Jun 10 07:03:30 PM PDT 24
Peak memory 272792 kb
Host smart-5056feb3-9841-4a72-af21-b06852358c59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865725075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3865725075
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3764618121
Short name T578
Test name
Test status
Simulation time 8031214936 ps
CPU time 243.72 seconds
Started Jun 10 06:37:56 PM PDT 24
Finished Jun 10 06:42:00 PM PDT 24
Peak memory 256564 kb
Host smart-ef40e07f-93ed-4e8d-a71c-0300de7431c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37646
18121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3764618121
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3176856159
Short name T541
Test name
Test status
Simulation time 359572804 ps
CPU time 8.23 seconds
Started Jun 10 06:37:53 PM PDT 24
Finished Jun 10 06:38:02 PM PDT 24
Peak memory 253156 kb
Host smart-4b47388c-6062-439b-81f3-eec37fbd62da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31768
56159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3176856159
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3364424067
Short name T390
Test name
Test status
Simulation time 460057465447 ps
CPU time 3091.94 seconds
Started Jun 10 06:37:57 PM PDT 24
Finished Jun 10 07:29:29 PM PDT 24
Peak memory 287960 kb
Host smart-e6900e9b-169c-43fe-a9ce-edead1f86e28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364424067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3364424067
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2609174976
Short name T77
Test name
Test status
Simulation time 405620664 ps
CPU time 18.42 seconds
Started Jun 10 06:37:56 PM PDT 24
Finished Jun 10 06:38:15 PM PDT 24
Peak memory 255520 kb
Host smart-31ce3166-3084-4ba0-96e2-19748d34a3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26091
74976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2609174976
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1982675725
Short name T41
Test name
Test status
Simulation time 400826173 ps
CPU time 45.14 seconds
Started Jun 10 06:37:54 PM PDT 24
Finished Jun 10 06:38:39 PM PDT 24
Peak memory 255876 kb
Host smart-07ec20df-c3dc-4acf-be52-89e2922a71d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19826
75725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1982675725
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3154537513
Short name T384
Test name
Test status
Simulation time 181088692 ps
CPU time 6.11 seconds
Started Jun 10 06:37:55 PM PDT 24
Finished Jun 10 06:38:01 PM PDT 24
Peak memory 253304 kb
Host smart-7e76bf79-a0a8-4167-ac74-d73be60e59f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31545
37513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3154537513
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.594523466
Short name T483
Test name
Test status
Simulation time 73867925 ps
CPU time 7.85 seconds
Started Jun 10 06:37:56 PM PDT 24
Finished Jun 10 06:38:04 PM PDT 24
Peak memory 248728 kb
Host smart-8cf9cd51-4f86-4aa0-957a-8c52af808bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59452
3466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.594523466
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1534180937
Short name T261
Test name
Test status
Simulation time 212716129579 ps
CPU time 3593.46 seconds
Started Jun 10 06:37:58 PM PDT 24
Finished Jun 10 07:37:52 PM PDT 24
Peak memory 305704 kb
Host smart-b778841c-79dd-496a-8828-16d0ad6429ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534180937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1534180937
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1545386178
Short name T532
Test name
Test status
Simulation time 9691941102 ps
CPU time 855.84 seconds
Started Jun 10 06:37:59 PM PDT 24
Finished Jun 10 06:52:16 PM PDT 24
Peak memory 269752 kb
Host smart-98766101-c75e-4f64-b025-4c4306e24503
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545386178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1545386178
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3043964869
Short name T564
Test name
Test status
Simulation time 103310657407 ps
CPU time 386.42 seconds
Started Jun 10 06:37:57 PM PDT 24
Finished Jun 10 06:44:24 PM PDT 24
Peak memory 250828 kb
Host smart-82898043-b195-43de-ab8b-add6420e0385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30439
64869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3043964869
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.454597591
Short name T84
Test name
Test status
Simulation time 750426197 ps
CPU time 48.67 seconds
Started Jun 10 06:38:02 PM PDT 24
Finished Jun 10 06:38:51 PM PDT 24
Peak memory 255540 kb
Host smart-6d6aaac5-f65c-40fd-8a37-3ca5228bb26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45459
7591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.454597591
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2460203841
Short name T95
Test name
Test status
Simulation time 77131118218 ps
CPU time 1570.05 seconds
Started Jun 10 06:38:01 PM PDT 24
Finished Jun 10 07:04:11 PM PDT 24
Peak memory 289060 kb
Host smart-1e9af334-22f6-4c54-9475-562a2f9363a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460203841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2460203841
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3245332929
Short name T9
Test name
Test status
Simulation time 22168000031 ps
CPU time 231.13 seconds
Started Jun 10 06:37:58 PM PDT 24
Finished Jun 10 06:41:49 PM PDT 24
Peak memory 247172 kb
Host smart-5060352e-c188-4514-a4e5-ecb35ec74237
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245332929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3245332929
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3106063830
Short name T681
Test name
Test status
Simulation time 1389067126 ps
CPU time 31.28 seconds
Started Jun 10 06:38:01 PM PDT 24
Finished Jun 10 06:38:33 PM PDT 24
Peak memory 248648 kb
Host smart-617fd5fb-b8f7-4060-b0f7-e6d7e6c50dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31060
63830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3106063830
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.347834953
Short name T105
Test name
Test status
Simulation time 691048107 ps
CPU time 20.6 seconds
Started Jun 10 06:37:56 PM PDT 24
Finished Jun 10 06:38:17 PM PDT 24
Peak memory 256556 kb
Host smart-471a6801-37e6-4ef1-853b-648acb030889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34783
4953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.347834953
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3472627309
Short name T625
Test name
Test status
Simulation time 249480665 ps
CPU time 29.17 seconds
Started Jun 10 06:37:59 PM PDT 24
Finished Jun 10 06:38:29 PM PDT 24
Peak memory 247972 kb
Host smart-730f2691-dbc0-40b9-ac8b-81fe4d0f6743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34726
27309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3472627309
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.238847475
Short name T446
Test name
Test status
Simulation time 2307884173 ps
CPU time 38.16 seconds
Started Jun 10 06:37:58 PM PDT 24
Finished Jun 10 06:38:36 PM PDT 24
Peak memory 257000 kb
Host smart-1cd55c25-0d91-46c3-ac2f-57e69ad7e78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23884
7475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.238847475
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.135858016
Short name T606
Test name
Test status
Simulation time 6846874797 ps
CPU time 655.93 seconds
Started Jun 10 06:38:01 PM PDT 24
Finished Jun 10 06:48:58 PM PDT 24
Peak memory 265116 kb
Host smart-9004126f-f7a5-4854-9405-7f2be6b314cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135858016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.135858016
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.894644193
Short name T112
Test name
Test status
Simulation time 7962458161 ps
CPU time 665.5 seconds
Started Jun 10 06:38:01 PM PDT 24
Finished Jun 10 06:49:07 PM PDT 24
Peak memory 272360 kb
Host smart-9bc8368b-6ad9-406a-a6f9-9b5a663d1b90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894644193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.894644193
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3100241386
Short name T452
Test name
Test status
Simulation time 4214597874 ps
CPU time 99.43 seconds
Started Jun 10 06:38:02 PM PDT 24
Finished Jun 10 06:39:41 PM PDT 24
Peak memory 249052 kb
Host smart-a7115017-4b8c-452d-ae83-660d54555608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31002
41386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3100241386
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4063877784
Short name T616
Test name
Test status
Simulation time 729980646 ps
CPU time 31.41 seconds
Started Jun 10 06:38:01 PM PDT 24
Finished Jun 10 06:38:33 PM PDT 24
Peak memory 255692 kb
Host smart-2f866969-a1b9-42fb-8dc4-014063d46ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40638
77784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4063877784
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1778442626
Short name T89
Test name
Test status
Simulation time 18760136682 ps
CPU time 1182.38 seconds
Started Jun 10 06:38:03 PM PDT 24
Finished Jun 10 06:57:46 PM PDT 24
Peak memory 273048 kb
Host smart-12c9ae9c-f62b-4376-adde-82513beccd3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778442626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1778442626
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2903313661
Short name T580
Test name
Test status
Simulation time 35019310940 ps
CPU time 1402.18 seconds
Started Jun 10 06:38:02 PM PDT 24
Finished Jun 10 07:01:25 PM PDT 24
Peak memory 272588 kb
Host smart-db7a120a-30e2-447b-9ca6-bc4ac1fc559e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903313661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2903313661
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2643076700
Short name T508
Test name
Test status
Simulation time 14792342031 ps
CPU time 313.73 seconds
Started Jun 10 06:38:02 PM PDT 24
Finished Jun 10 06:43:16 PM PDT 24
Peak memory 248348 kb
Host smart-8d35e22f-a59c-47e7-a68d-26ee37bbc8df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643076700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2643076700
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2608302254
Short name T36
Test name
Test status
Simulation time 195756424 ps
CPU time 16.05 seconds
Started Jun 10 06:38:00 PM PDT 24
Finished Jun 10 06:38:16 PM PDT 24
Peak memory 255860 kb
Host smart-f8c103d9-1aee-44ee-8405-f0a8e4234b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26083
02254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2608302254
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.919324591
Short name T533
Test name
Test status
Simulation time 1102085640 ps
CPU time 35.06 seconds
Started Jun 10 06:38:01 PM PDT 24
Finished Jun 10 06:38:37 PM PDT 24
Peak memory 256180 kb
Host smart-f040d599-6626-4df3-948d-13908398db06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91932
4591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.919324591
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3626247734
Short name T361
Test name
Test status
Simulation time 2417588196 ps
CPU time 46.94 seconds
Started Jun 10 06:37:59 PM PDT 24
Finished Jun 10 06:38:46 PM PDT 24
Peak memory 255708 kb
Host smart-f2f3bada-75f2-4676-a18a-0197a9c2cb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36262
47734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3626247734
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1295851911
Short name T432
Test name
Test status
Simulation time 4660793409 ps
CPU time 63.54 seconds
Started Jun 10 06:38:03 PM PDT 24
Finished Jun 10 06:39:07 PM PDT 24
Peak memory 256120 kb
Host smart-cd40c89f-bcfd-45fd-8005-cd9056992818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12958
51911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1295851911
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1387608444
Short name T26
Test name
Test status
Simulation time 97630980330 ps
CPU time 1720.03 seconds
Started Jun 10 06:38:06 PM PDT 24
Finished Jun 10 07:06:46 PM PDT 24
Peak memory 289648 kb
Host smart-3684d615-7304-49fd-99b3-315c24e97d3b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387608444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1387608444
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.90895686
Short name T488
Test name
Test status
Simulation time 157343462219 ps
CPU time 2093.98 seconds
Started Jun 10 06:38:07 PM PDT 24
Finished Jun 10 07:13:01 PM PDT 24
Peak memory 281712 kb
Host smart-e6ecfafe-836a-4c3c-a83e-39eec49f2498
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90895686 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.90895686
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3901426235
Short name T403
Test name
Test status
Simulation time 33825733081 ps
CPU time 1950.59 seconds
Started Jun 10 06:38:15 PM PDT 24
Finished Jun 10 07:10:46 PM PDT 24
Peak memory 273328 kb
Host smart-15424f8a-35ee-4e3d-81cd-8e7bbbec3135
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901426235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3901426235
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3937475329
Short name T397
Test name
Test status
Simulation time 5320938988 ps
CPU time 160.66 seconds
Started Jun 10 06:38:06 PM PDT 24
Finished Jun 10 06:40:47 PM PDT 24
Peak memory 251480 kb
Host smart-c8faa861-2b47-4116-9e45-9d7d9f76731f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39374
75329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3937475329
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2002547081
Short name T447
Test name
Test status
Simulation time 1337353591 ps
CPU time 68.45 seconds
Started Jun 10 06:38:07 PM PDT 24
Finished Jun 10 06:39:16 PM PDT 24
Peak memory 255028 kb
Host smart-1e3c481d-d8b9-42c0-ab11-56e1bc61b0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20025
47081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2002547081
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2020748535
Short name T331
Test name
Test status
Simulation time 31975541450 ps
CPU time 743.97 seconds
Started Jun 10 06:38:09 PM PDT 24
Finished Jun 10 06:50:33 PM PDT 24
Peak memory 265160 kb
Host smart-d554a89a-40fc-47d8-804e-563ac1ce1146
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020748535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2020748535
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2698524371
Short name T534
Test name
Test status
Simulation time 31328252895 ps
CPU time 794.76 seconds
Started Jun 10 06:38:11 PM PDT 24
Finished Jun 10 06:51:26 PM PDT 24
Peak memory 265300 kb
Host smart-c9e582a0-8622-4fa2-bd2e-dd302f2c746d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698524371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2698524371
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3250178517
Short name T297
Test name
Test status
Simulation time 16649506990 ps
CPU time 346.95 seconds
Started Jun 10 06:38:10 PM PDT 24
Finished Jun 10 06:43:57 PM PDT 24
Peak memory 248536 kb
Host smart-21da1469-d122-4615-97e4-e078cc20d7ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250178517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3250178517
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3871683163
Short name T433
Test name
Test status
Simulation time 584210182 ps
CPU time 36.69 seconds
Started Jun 10 06:38:06 PM PDT 24
Finished Jun 10 06:38:43 PM PDT 24
Peak memory 256660 kb
Host smart-a0e8330b-8c18-4b6e-a5b6-fdee555a66f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38716
83163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3871683163
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2481621829
Short name T441
Test name
Test status
Simulation time 1913056545 ps
CPU time 14.78 seconds
Started Jun 10 06:38:07 PM PDT 24
Finished Jun 10 06:38:22 PM PDT 24
Peak memory 252104 kb
Host smart-f2fa8a2d-f7c4-440c-b369-2e868a0d29af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
21829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2481621829
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3373980614
Short name T267
Test name
Test status
Simulation time 3544024666 ps
CPU time 22.8 seconds
Started Jun 10 06:38:05 PM PDT 24
Finished Jun 10 06:38:28 PM PDT 24
Peak memory 256644 kb
Host smart-a57efb9b-5cda-49cb-ae99-f45b932746ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33739
80614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3373980614
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3873997309
Short name T479
Test name
Test status
Simulation time 1064198443 ps
CPU time 62.93 seconds
Started Jun 10 06:38:04 PM PDT 24
Finished Jun 10 06:39:08 PM PDT 24
Peak memory 256892 kb
Host smart-52ce3703-52f7-4359-8afb-109c5046a7b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38739
97309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3873997309
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1009705157
Short name T224
Test name
Test status
Simulation time 62227969072 ps
CPU time 1452.77 seconds
Started Jun 10 06:38:08 PM PDT 24
Finished Jun 10 07:02:21 PM PDT 24
Peak memory 289164 kb
Host smart-68b2a84b-bee0-407c-99df-7f3f1992d2ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009705157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1009705157
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3681591901
Short name T237
Test name
Test status
Simulation time 48946299177 ps
CPU time 715.56 seconds
Started Jun 10 06:38:19 PM PDT 24
Finished Jun 10 06:50:15 PM PDT 24
Peak memory 272668 kb
Host smart-6e6a62de-850e-4f7d-b37f-982415164dbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681591901 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3681591901
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.322312209
Short name T698
Test name
Test status
Simulation time 13979212103 ps
CPU time 1312.15 seconds
Started Jun 10 06:38:12 PM PDT 24
Finished Jun 10 07:00:05 PM PDT 24
Peak memory 288236 kb
Host smart-471d8dfa-a86d-4fc9-817c-48e0c0042176
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322312209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.322312209
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3153697015
Short name T436
Test name
Test status
Simulation time 5495993618 ps
CPU time 211.53 seconds
Started Jun 10 06:38:19 PM PDT 24
Finished Jun 10 06:41:50 PM PDT 24
Peak memory 256944 kb
Host smart-c720377f-54b1-4da3-a1ed-d36a78557e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31536
97015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3153697015
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.170299598
Short name T493
Test name
Test status
Simulation time 210381716 ps
CPU time 5.43 seconds
Started Jun 10 06:38:14 PM PDT 24
Finished Jun 10 06:38:19 PM PDT 24
Peak memory 251000 kb
Host smart-e9f88c0c-97eb-4989-8b8e-1ed39f6459d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17029
9598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.170299598
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.395015518
Short name T335
Test name
Test status
Simulation time 38477459404 ps
CPU time 2264.7 seconds
Started Jun 10 06:38:12 PM PDT 24
Finished Jun 10 07:15:57 PM PDT 24
Peak memory 281580 kb
Host smart-ac5aabc0-16f3-4099-afce-2cf30b4081b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395015518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.395015518
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.909405844
Short name T621
Test name
Test status
Simulation time 79219941333 ps
CPU time 2847.09 seconds
Started Jun 10 06:38:19 PM PDT 24
Finished Jun 10 07:25:47 PM PDT 24
Peak memory 288936 kb
Host smart-a77dc790-1205-48c9-a875-b9c3fdc0523f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909405844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.909405844
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.407922652
Short name T650
Test name
Test status
Simulation time 10466191340 ps
CPU time 346.12 seconds
Started Jun 10 06:38:14 PM PDT 24
Finished Jun 10 06:44:01 PM PDT 24
Peak memory 248220 kb
Host smart-ea4a9263-88d5-4b50-89e5-5fe21c2b2de9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407922652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.407922652
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1149283981
Short name T400
Test name
Test status
Simulation time 340162087 ps
CPU time 15.68 seconds
Started Jun 10 06:38:08 PM PDT 24
Finished Jun 10 06:38:24 PM PDT 24
Peak memory 253104 kb
Host smart-58ab587e-6062-4ac8-90d0-97e10ae4df67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11492
83981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1149283981
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3021037973
Short name T298
Test name
Test status
Simulation time 353681841 ps
CPU time 35.33 seconds
Started Jun 10 06:38:11 PM PDT 24
Finished Jun 10 06:38:46 PM PDT 24
Peak memory 256900 kb
Host smart-fbed1011-d071-46ed-8fd2-ef383fe61c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30210
37973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3021037973
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1607477649
Short name T254
Test name
Test status
Simulation time 571432715 ps
CPU time 15.54 seconds
Started Jun 10 06:38:17 PM PDT 24
Finished Jun 10 06:38:33 PM PDT 24
Peak memory 248804 kb
Host smart-ffc29333-776b-49df-b480-9e4fa7c32218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16074
77649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1607477649
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3843590873
Short name T466
Test name
Test status
Simulation time 2070845428 ps
CPU time 32.1 seconds
Started Jun 10 06:38:09 PM PDT 24
Finished Jun 10 06:38:42 PM PDT 24
Peak memory 256876 kb
Host smart-d15e3677-e316-457f-a064-0481a91881a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38435
90873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3843590873
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.163322147
Short name T467
Test name
Test status
Simulation time 57966428736 ps
CPU time 3783.71 seconds
Started Jun 10 06:38:15 PM PDT 24
Finished Jun 10 07:41:19 PM PDT 24
Peak memory 305340 kb
Host smart-3541fa65-a391-437a-b44f-e81853b4fdb1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163322147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.163322147
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.4187461551
Short name T184
Test name
Test status
Simulation time 32887752495 ps
CPU time 3610.4 seconds
Started Jun 10 06:38:12 PM PDT 24
Finished Jun 10 07:38:23 PM PDT 24
Peak memory 337132 kb
Host smart-bf28b84f-9367-4a50-82f2-1385487d2407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187461551 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.4187461551
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.4288975404
Short name T554
Test name
Test status
Simulation time 9895752944 ps
CPU time 1069.02 seconds
Started Jun 10 06:38:19 PM PDT 24
Finished Jun 10 06:56:08 PM PDT 24
Peak memory 284732 kb
Host smart-5256ed0a-3b9e-4d36-bfe3-aa0b2671dae9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288975404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4288975404
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3585217170
Short name T527
Test name
Test status
Simulation time 5164684333 ps
CPU time 80.38 seconds
Started Jun 10 06:38:15 PM PDT 24
Finished Jun 10 06:39:36 PM PDT 24
Peak memory 248812 kb
Host smart-e710ca79-da7b-4db4-8f00-ff5179414450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35852
17170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3585217170
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2385109272
Short name T635
Test name
Test status
Simulation time 652771393 ps
CPU time 14.7 seconds
Started Jun 10 06:38:17 PM PDT 24
Finished Jun 10 06:38:32 PM PDT 24
Peak memory 255732 kb
Host smart-fa955420-f7c9-43ed-aebd-1cdc4e720414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23851
09272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2385109272
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3095880257
Short name T192
Test name
Test status
Simulation time 8147547615 ps
CPU time 614.39 seconds
Started Jun 10 06:38:18 PM PDT 24
Finished Jun 10 06:48:33 PM PDT 24
Peak memory 273040 kb
Host smart-e3fce3ca-edf3-4a90-b52e-6dd78b431c42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095880257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3095880257
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3914345286
Short name T667
Test name
Test status
Simulation time 51915939313 ps
CPU time 1296.05 seconds
Started Jun 10 06:38:18 PM PDT 24
Finished Jun 10 06:59:54 PM PDT 24
Peak memory 289072 kb
Host smart-a5427974-0fb7-461c-af2d-5984da2358c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914345286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3914345286
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.22006224
Short name T648
Test name
Test status
Simulation time 10110062822 ps
CPU time 403.1 seconds
Started Jun 10 06:38:17 PM PDT 24
Finished Jun 10 06:45:00 PM PDT 24
Peak memory 254592 kb
Host smart-2fd8fa95-4c6e-4076-9ae3-3301d17a3e2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22006224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.22006224
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2653259822
Short name T526
Test name
Test status
Simulation time 267075261 ps
CPU time 16.66 seconds
Started Jun 10 06:38:14 PM PDT 24
Finished Jun 10 06:38:31 PM PDT 24
Peak memory 248688 kb
Host smart-b8def2b8-bb0b-4ee9-821c-83ff4a469e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26532
59822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2653259822
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3505900007
Short name T409
Test name
Test status
Simulation time 41956256 ps
CPU time 4.17 seconds
Started Jun 10 06:38:18 PM PDT 24
Finished Jun 10 06:38:22 PM PDT 24
Peak memory 240500 kb
Host smart-05c811bb-1c8d-4c17-983c-eb1f859c1316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35059
00007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3505900007
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2399141515
Short name T413
Test name
Test status
Simulation time 34270973 ps
CPU time 3.25 seconds
Started Jun 10 06:38:14 PM PDT 24
Finished Jun 10 06:38:18 PM PDT 24
Peak memory 240540 kb
Host smart-770adf11-5777-4eb7-bece-f08173b1bc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23991
41515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2399141515
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.624116666
Short name T74
Test name
Test status
Simulation time 39015013750 ps
CPU time 678.39 seconds
Started Jun 10 06:38:17 PM PDT 24
Finished Jun 10 06:49:36 PM PDT 24
Peak memory 272632 kb
Host smart-48551a90-1dc9-4709-936b-8a7e8ea7bffd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624116666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.624116666
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1405331110
Short name T16
Test name
Test status
Simulation time 45142331262 ps
CPU time 1698.97 seconds
Started Jun 10 06:38:20 PM PDT 24
Finished Jun 10 07:06:39 PM PDT 24
Peak memory 272704 kb
Host smart-779f6909-0b94-4071-916f-b1b7f196d3bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405331110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1405331110
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3745498066
Short name T552
Test name
Test status
Simulation time 139473855 ps
CPU time 6.01 seconds
Started Jun 10 06:38:21 PM PDT 24
Finished Jun 10 06:38:27 PM PDT 24
Peak memory 254808 kb
Host smart-f1f40900-f11a-4702-aba4-274193082334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37454
98066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3745498066
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2055343450
Short name T705
Test name
Test status
Simulation time 158431588 ps
CPU time 16.42 seconds
Started Jun 10 06:38:21 PM PDT 24
Finished Jun 10 06:38:38 PM PDT 24
Peak memory 255620 kb
Host smart-fcfa67a7-ecd6-4a09-a216-52d868e5f84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20553
43450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2055343450
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3018437240
Short name T343
Test name
Test status
Simulation time 10056253933 ps
CPU time 1029.59 seconds
Started Jun 10 06:38:24 PM PDT 24
Finished Jun 10 06:55:35 PM PDT 24
Peak memory 273400 kb
Host smart-a7a0c4c6-d401-40a1-a297-962fa4c4503c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018437240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3018437240
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.205770839
Short name T688
Test name
Test status
Simulation time 176000903478 ps
CPU time 2679.71 seconds
Started Jun 10 06:38:23 PM PDT 24
Finished Jun 10 07:23:04 PM PDT 24
Peak memory 288668 kb
Host smart-2dc14a63-e7bf-41b5-bd4f-8ea94747b874
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205770839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.205770839
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.370864571
Short name T597
Test name
Test status
Simulation time 12487686331 ps
CPU time 386.79 seconds
Started Jun 10 06:38:24 PM PDT 24
Finished Jun 10 06:44:52 PM PDT 24
Peak memory 247240 kb
Host smart-3b744ca6-3257-47e5-8431-6d3ee0917444
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370864571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.370864571
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.7006479
Short name T218
Test name
Test status
Simulation time 2650450960 ps
CPU time 56.36 seconds
Started Jun 10 06:38:20 PM PDT 24
Finished Jun 10 06:39:17 PM PDT 24
Peak memory 256156 kb
Host smart-802b9665-c827-4f80-85a7-19374ff36972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70064
79 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.7006479
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2612254393
Short name T686
Test name
Test status
Simulation time 728037617 ps
CPU time 37.91 seconds
Started Jun 10 06:38:23 PM PDT 24
Finished Jun 10 06:39:01 PM PDT 24
Peak memory 248960 kb
Host smart-3cfb45a6-e706-495c-9c5a-2df8ee20583f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26122
54393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2612254393
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2273804638
Short name T374
Test name
Test status
Simulation time 2020118927 ps
CPU time 56.9 seconds
Started Jun 10 06:38:21 PM PDT 24
Finished Jun 10 06:39:18 PM PDT 24
Peak memory 256904 kb
Host smart-abef42c8-4c0a-437d-83eb-aafddf11aa23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22738
04638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2273804638
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1625234089
Short name T227
Test name
Test status
Simulation time 117242380 ps
CPU time 7.48 seconds
Started Jun 10 06:38:22 PM PDT 24
Finished Jun 10 06:38:30 PM PDT 24
Peak memory 248804 kb
Host smart-1efb8aa2-a4af-44e2-96ad-4c903b28d9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16252
34089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1625234089
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.4056800684
Short name T115
Test name
Test status
Simulation time 235605695653 ps
CPU time 2449.88 seconds
Started Jun 10 06:38:24 PM PDT 24
Finished Jun 10 07:19:14 PM PDT 24
Peak memory 289228 kb
Host smart-8fa55615-9225-4a2d-b1e9-b59ea4e78157
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056800684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.4056800684
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.93802715
Short name T416
Test name
Test status
Simulation time 11088043935 ps
CPU time 1100.91 seconds
Started Jun 10 06:38:23 PM PDT 24
Finished Jun 10 06:56:45 PM PDT 24
Peak memory 287272 kb
Host smart-1d4245cb-2fb8-4bc6-bcf3-8063e499d50f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93802715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.93802715
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.606956624
Short name T682
Test name
Test status
Simulation time 1722718338 ps
CPU time 58.79 seconds
Started Jun 10 06:38:28 PM PDT 24
Finished Jun 10 06:39:27 PM PDT 24
Peak memory 256912 kb
Host smart-1f683bc1-8b5b-497a-abd3-8b8346188711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60695
6624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.606956624
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2045242622
Short name T545
Test name
Test status
Simulation time 1254596372 ps
CPU time 25.3 seconds
Started Jun 10 06:38:28 PM PDT 24
Finished Jun 10 06:38:53 PM PDT 24
Peak memory 255580 kb
Host smart-3cc0a62a-ad9d-46b7-91f2-4f0212724f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20452
42622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2045242622
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1112774414
Short name T495
Test name
Test status
Simulation time 42179615226 ps
CPU time 1395.67 seconds
Started Jun 10 06:38:24 PM PDT 24
Finished Jun 10 07:01:41 PM PDT 24
Peak memory 273288 kb
Host smart-7afdf300-54b3-45d6-aa6b-c09c4747cc37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112774414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1112774414
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2270443907
Short name T387
Test name
Test status
Simulation time 170674151101 ps
CPU time 2421.82 seconds
Started Jun 10 06:38:29 PM PDT 24
Finished Jun 10 07:18:52 PM PDT 24
Peak memory 289004 kb
Host smart-214a39ea-a6d8-4ff6-9b73-845a5c2c70f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270443907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2270443907
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.203853534
Short name T540
Test name
Test status
Simulation time 42899458577 ps
CPU time 438.08 seconds
Started Jun 10 06:38:26 PM PDT 24
Finished Jun 10 06:45:44 PM PDT 24
Peak memory 248360 kb
Host smart-0a9e417a-48fb-4800-8734-b846a4d52e39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203853534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.203853534
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3465095102
Short name T505
Test name
Test status
Simulation time 242812235 ps
CPU time 27.31 seconds
Started Jun 10 06:38:24 PM PDT 24
Finished Jun 10 06:38:52 PM PDT 24
Peak memory 248748 kb
Host smart-764f83db-8b61-4f9c-9ea1-7e1b1d80d776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34650
95102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3465095102
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1326360816
Short name T517
Test name
Test status
Simulation time 386888091 ps
CPU time 45.69 seconds
Started Jun 10 06:38:28 PM PDT 24
Finished Jun 10 06:39:14 PM PDT 24
Peak memory 247772 kb
Host smart-41939a58-43f1-4a6a-95f8-fa7c348624f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13263
60816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1326360816
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1461383429
Short name T177
Test name
Test status
Simulation time 2375598169 ps
CPU time 39.06 seconds
Started Jun 10 06:38:25 PM PDT 24
Finished Jun 10 06:39:05 PM PDT 24
Peak memory 256348 kb
Host smart-59dbd403-85a7-470f-9495-2a22fc847113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14613
83429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1461383429
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.4265341042
Short name T22
Test name
Test status
Simulation time 752526291 ps
CPU time 41.37 seconds
Started Jun 10 06:38:21 PM PDT 24
Finished Jun 10 06:39:03 PM PDT 24
Peak memory 256828 kb
Host smart-dd45bf5a-7d12-4a5f-bdff-887bb9474ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42653
41042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.4265341042
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2873745329
Short name T85
Test name
Test status
Simulation time 12629667314 ps
CPU time 1715.97 seconds
Started Jun 10 06:38:29 PM PDT 24
Finished Jun 10 07:07:06 PM PDT 24
Peak memory 289712 kb
Host smart-9480823f-babf-4d8f-9a57-8fcb244afae3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873745329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2873745329
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.132829786
Short name T35
Test name
Test status
Simulation time 157679008953 ps
CPU time 969.64 seconds
Started Jun 10 06:38:33 PM PDT 24
Finished Jun 10 06:54:43 PM PDT 24
Peak memory 286320 kb
Host smart-27d3d7d3-be81-42c1-abd5-226eee0dfe4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132829786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.132829786
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.959783789
Short name T407
Test name
Test status
Simulation time 559761815 ps
CPU time 50.45 seconds
Started Jun 10 06:38:33 PM PDT 24
Finished Jun 10 06:39:24 PM PDT 24
Peak memory 248736 kb
Host smart-278ef4d5-4a21-4ea8-a624-e2db1cf42cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95978
3789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.959783789
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.420516964
Short name T611
Test name
Test status
Simulation time 3441476512 ps
CPU time 51.5 seconds
Started Jun 10 06:38:34 PM PDT 24
Finished Jun 10 06:39:25 PM PDT 24
Peak memory 248764 kb
Host smart-751721a0-1241-43de-ae68-075e57b7cc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42051
6964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.420516964
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2200988476
Short name T689
Test name
Test status
Simulation time 18355468100 ps
CPU time 1621.78 seconds
Started Jun 10 06:38:38 PM PDT 24
Finished Jun 10 07:05:40 PM PDT 24
Peak memory 288952 kb
Host smart-715bac1d-a6ad-485e-b13f-004db2775855
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200988476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2200988476
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3807114295
Short name T404
Test name
Test status
Simulation time 62831681543 ps
CPU time 2151.93 seconds
Started Jun 10 06:38:40 PM PDT 24
Finished Jun 10 07:14:33 PM PDT 24
Peak memory 289276 kb
Host smart-880cc271-86cd-402e-83a4-d2f725ec0442
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807114295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3807114295
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.881688288
Short name T651
Test name
Test status
Simulation time 140006405457 ps
CPU time 511.86 seconds
Started Jun 10 06:38:37 PM PDT 24
Finished Jun 10 06:47:09 PM PDT 24
Peak memory 248324 kb
Host smart-b070e681-dfb1-45e2-b378-0361d832cc0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881688288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.881688288
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2385302372
Short name T510
Test name
Test status
Simulation time 129525433 ps
CPU time 12.85 seconds
Started Jun 10 06:38:28 PM PDT 24
Finished Jun 10 06:38:41 PM PDT 24
Peak memory 248944 kb
Host smart-b7c85a38-d0ca-4360-968d-63f865b37bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23853
02372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2385302372
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.899839092
Short name T50
Test name
Test status
Simulation time 315528814 ps
CPU time 20.5 seconds
Started Jun 10 06:38:29 PM PDT 24
Finished Jun 10 06:38:50 PM PDT 24
Peak memory 254580 kb
Host smart-d670ad96-0212-45ff-80ec-01a033b9b299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89983
9092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.899839092
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3479983026
Short name T537
Test name
Test status
Simulation time 5205159866 ps
CPU time 19.68 seconds
Started Jun 10 06:38:36 PM PDT 24
Finished Jun 10 06:38:56 PM PDT 24
Peak memory 254940 kb
Host smart-f1ae6b0b-6c16-4404-81c2-880c9861fde7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34799
83026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3479983026
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.685615115
Short name T439
Test name
Test status
Simulation time 2777051049 ps
CPU time 50.01 seconds
Started Jun 10 06:38:29 PM PDT 24
Finished Jun 10 06:39:19 PM PDT 24
Peak memory 248824 kb
Host smart-924d601d-a22c-48bf-969c-3cd5d171cac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68561
5115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.685615115
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3394068898
Short name T183
Test name
Test status
Simulation time 4414359957 ps
CPU time 259.96 seconds
Started Jun 10 06:38:37 PM PDT 24
Finished Jun 10 06:42:57 PM PDT 24
Peak memory 256832 kb
Host smart-a0382228-0258-4923-ab69-1fdd44f18389
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394068898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3394068898
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.183659545
Short name T211
Test name
Test status
Simulation time 166154620 ps
CPU time 3.84 seconds
Started Jun 10 06:36:49 PM PDT 24
Finished Jun 10 06:36:54 PM PDT 24
Peak memory 248912 kb
Host smart-7f7a5a90-425b-46a8-8f44-c947b5a9adc8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=183659545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.183659545
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.4022633023
Short name T39
Test name
Test status
Simulation time 870963360028 ps
CPU time 2629.08 seconds
Started Jun 10 06:36:43 PM PDT 24
Finished Jun 10 07:20:33 PM PDT 24
Peak memory 288088 kb
Host smart-2affdd3e-c17c-4db3-a0f2-ec954239c96c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022633023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.4022633023
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.805474500
Short name T430
Test name
Test status
Simulation time 3818843410 ps
CPU time 32.23 seconds
Started Jun 10 06:36:43 PM PDT 24
Finished Jun 10 06:37:16 PM PDT 24
Peak memory 248736 kb
Host smart-4e4e60cd-521c-45c8-a147-6b0ece42a6ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=805474500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.805474500
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1745040242
Short name T231
Test name
Test status
Simulation time 8067936073 ps
CPU time 150.88 seconds
Started Jun 10 06:36:50 PM PDT 24
Finished Jun 10 06:39:22 PM PDT 24
Peak memory 256920 kb
Host smart-2c1faef5-59e8-4c69-a7f4-4be0920316eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17450
40242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1745040242
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3096881353
Short name T410
Test name
Test status
Simulation time 267800190 ps
CPU time 26.63 seconds
Started Jun 10 06:36:49 PM PDT 24
Finished Jun 10 06:37:16 PM PDT 24
Peak memory 248652 kb
Host smart-a3ca488f-5650-4bfd-9a02-4e6a36f1ab0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30968
81353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3096881353
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3518247675
Short name T176
Test name
Test status
Simulation time 64542050652 ps
CPU time 2203.55 seconds
Started Jun 10 06:36:48 PM PDT 24
Finished Jun 10 07:13:32 PM PDT 24
Peak memory 285772 kb
Host smart-1c6292e9-90eb-421f-b226-357029518b73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518247675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3518247675
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2334108476
Short name T577
Test name
Test status
Simulation time 105789018585 ps
CPU time 1681.31 seconds
Started Jun 10 06:36:47 PM PDT 24
Finished Jun 10 07:04:49 PM PDT 24
Peak memory 272904 kb
Host smart-d22af451-55e9-4845-b151-ea2664f0d16c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334108476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2334108476
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1513334971
Short name T586
Test name
Test status
Simulation time 1889138710 ps
CPU time 14.2 seconds
Started Jun 10 06:36:43 PM PDT 24
Finished Jun 10 06:36:58 PM PDT 24
Peak memory 252576 kb
Host smart-b69bf11a-03dd-43e6-8121-336fbce16ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15133
34971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1513334971
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.624297877
Short name T99
Test name
Test status
Simulation time 246405354 ps
CPU time 10.57 seconds
Started Jun 10 06:36:44 PM PDT 24
Finished Jun 10 06:36:55 PM PDT 24
Peak memory 248796 kb
Host smart-5bc2f9fc-89b7-4e1d-8939-4d3936cdfa19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62429
7877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.624297877
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1280206187
Short name T14
Test name
Test status
Simulation time 1688396997 ps
CPU time 42.01 seconds
Started Jun 10 06:36:48 PM PDT 24
Finished Jun 10 06:37:30 PM PDT 24
Peak memory 270156 kb
Host smart-f6f1cd2f-8540-45dd-a090-4178b1d0bdd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1280206187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1280206187
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2229986554
Short name T620
Test name
Test status
Simulation time 539885149 ps
CPU time 12.05 seconds
Started Jun 10 06:36:47 PM PDT 24
Finished Jun 10 06:37:00 PM PDT 24
Peak memory 249200 kb
Host smart-245f5936-dbc9-4d25-a7fb-0480dd506ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22299
86554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2229986554
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2449111893
Short name T490
Test name
Test status
Simulation time 1634144201 ps
CPU time 19.37 seconds
Started Jun 10 06:36:51 PM PDT 24
Finished Jun 10 06:37:11 PM PDT 24
Peak memory 255052 kb
Host smart-11ebee22-f549-42bd-bec4-7e4cb9b07c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24491
11893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2449111893
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3794623690
Short name T40
Test name
Test status
Simulation time 84360211699 ps
CPU time 2380.88 seconds
Started Jun 10 06:36:49 PM PDT 24
Finished Jun 10 07:16:31 PM PDT 24
Peak memory 306180 kb
Host smart-306c8631-c923-4b98-9e76-92a2e11772b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794623690 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3794623690
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3580461516
Short name T632
Test name
Test status
Simulation time 11968879577 ps
CPU time 1120.1 seconds
Started Jun 10 06:38:41 PM PDT 24
Finished Jun 10 06:57:22 PM PDT 24
Peak memory 273216 kb
Host smart-f16b88eb-538b-4e03-85a0-e716da988d86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580461516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3580461516
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1141440356
Short name T478
Test name
Test status
Simulation time 6334565462 ps
CPU time 144.11 seconds
Started Jun 10 06:38:36 PM PDT 24
Finished Jun 10 06:41:01 PM PDT 24
Peak memory 256928 kb
Host smart-bb3a1519-9c5c-4736-b926-5639d55c1e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11414
40356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1141440356
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3393821791
Short name T86
Test name
Test status
Simulation time 1192481641 ps
CPU time 45.01 seconds
Started Jun 10 06:38:39 PM PDT 24
Finished Jun 10 06:39:24 PM PDT 24
Peak memory 249068 kb
Host smart-a3e286ab-6836-4b84-84c3-461ec74859f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33938
21791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3393821791
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.626805632
Short name T230
Test name
Test status
Simulation time 17871536299 ps
CPU time 1187.52 seconds
Started Jun 10 06:38:40 PM PDT 24
Finished Jun 10 06:58:28 PM PDT 24
Peak memory 271248 kb
Host smart-6d5ac3fa-693d-4cb9-9bd8-a15c7747f357
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626805632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.626805632
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.864150034
Short name T49
Test name
Test status
Simulation time 12493867753 ps
CPU time 1276.15 seconds
Started Jun 10 06:38:41 PM PDT 24
Finished Jun 10 06:59:58 PM PDT 24
Peak memory 284480 kb
Host smart-6380e963-1c3c-4344-8f10-234e3f50cb31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864150034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.864150034
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1110446233
Short name T523
Test name
Test status
Simulation time 6322524754 ps
CPU time 35.75 seconds
Started Jun 10 06:38:39 PM PDT 24
Finished Jun 10 06:39:15 PM PDT 24
Peak memory 256988 kb
Host smart-523f7467-cf1a-42c2-9137-c7dfefcb85fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11104
46233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1110446233
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3309563449
Short name T592
Test name
Test status
Simulation time 3901198831 ps
CPU time 28.71 seconds
Started Jun 10 06:38:37 PM PDT 24
Finished Jun 10 06:39:06 PM PDT 24
Peak memory 256352 kb
Host smart-620b7c5d-02dd-475e-b9fe-656b9794b740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33095
63449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3309563449
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3403291107
Short name T664
Test name
Test status
Simulation time 551691599 ps
CPU time 14.76 seconds
Started Jun 10 06:38:37 PM PDT 24
Finished Jun 10 06:38:53 PM PDT 24
Peak memory 247664 kb
Host smart-c75d1859-31f4-40f1-a6a5-89947b337903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34032
91107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3403291107
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2889306328
Short name T704
Test name
Test status
Simulation time 16972852276 ps
CPU time 52.01 seconds
Started Jun 10 06:38:36 PM PDT 24
Finished Jun 10 06:39:28 PM PDT 24
Peak memory 256704 kb
Host smart-eafc470c-ffc5-4580-9035-f91eb8f8764a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28893
06328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2889306328
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.505729583
Short name T502
Test name
Test status
Simulation time 878054678 ps
CPU time 76.82 seconds
Started Jun 10 06:38:41 PM PDT 24
Finished Jun 10 06:39:58 PM PDT 24
Peak memory 256916 kb
Host smart-5e024342-e24a-4798-9f66-d5f83bebc4c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505729583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.505729583
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.4062399536
Short name T18
Test name
Test status
Simulation time 11330636098 ps
CPU time 1386.66 seconds
Started Jun 10 06:38:45 PM PDT 24
Finished Jun 10 07:01:52 PM PDT 24
Peak memory 281420 kb
Host smart-bf5b938a-f515-4581-afef-4972ac1610f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062399536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.4062399536
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.943670459
Short name T251
Test name
Test status
Simulation time 29364704869 ps
CPU time 113.17 seconds
Started Jun 10 06:38:45 PM PDT 24
Finished Jun 10 06:40:38 PM PDT 24
Peak memory 256884 kb
Host smart-96face5a-f8ae-4e53-b28b-fdcc39a6d06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94367
0459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.943670459
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3154401459
Short name T372
Test name
Test status
Simulation time 2262527463 ps
CPU time 31.57 seconds
Started Jun 10 06:38:45 PM PDT 24
Finished Jun 10 06:39:16 PM PDT 24
Peak memory 254660 kb
Host smart-0f74f17b-1471-4ec4-ae8c-a10cf7402979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31544
01459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3154401459
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.894700840
Short name T643
Test name
Test status
Simulation time 34906420295 ps
CPU time 2200.85 seconds
Started Jun 10 06:38:51 PM PDT 24
Finished Jun 10 07:15:32 PM PDT 24
Peak memory 286660 kb
Host smart-22dc11cc-fe76-4d3d-8859-3676a9b62ff4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894700840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.894700840
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.909339020
Short name T319
Test name
Test status
Simulation time 30712715230 ps
CPU time 314.66 seconds
Started Jun 10 06:38:51 PM PDT 24
Finished Jun 10 06:44:06 PM PDT 24
Peak memory 253848 kb
Host smart-5a4f68a4-896a-4f89-81b6-794dbb91567b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909339020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.909339020
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1042060961
Short name T362
Test name
Test status
Simulation time 477715029 ps
CPU time 33.9 seconds
Started Jun 10 06:38:44 PM PDT 24
Finished Jun 10 06:39:19 PM PDT 24
Peak memory 255648 kb
Host smart-d6ecfecc-a233-4393-b3fe-e276890c2404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10420
60961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1042060961
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.653674193
Short name T463
Test name
Test status
Simulation time 645937283 ps
CPU time 40.64 seconds
Started Jun 10 06:38:46 PM PDT 24
Finished Jun 10 06:39:27 PM PDT 24
Peak memory 248672 kb
Host smart-c9b17f31-387c-450c-9644-9111de515dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65367
4193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.653674193
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.231771981
Short name T507
Test name
Test status
Simulation time 1102993518 ps
CPU time 11.95 seconds
Started Jun 10 06:38:41 PM PDT 24
Finished Jun 10 06:38:53 PM PDT 24
Peak memory 248692 kb
Host smart-778ad758-c368-4929-9ae2-dae4f1b3ac81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23177
1981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.231771981
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.425568168
Short name T656
Test name
Test status
Simulation time 80215427378 ps
CPU time 2776.99 seconds
Started Jun 10 06:38:50 PM PDT 24
Finished Jun 10 07:25:08 PM PDT 24
Peak memory 289764 kb
Host smart-c4e5b766-a01c-4403-9853-0796bedbcd13
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425568168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.425568168
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3285079526
Short name T265
Test name
Test status
Simulation time 280120059218 ps
CPU time 1384.63 seconds
Started Jun 10 06:38:52 PM PDT 24
Finished Jun 10 07:01:57 PM PDT 24
Peak memory 284888 kb
Host smart-a9679265-5556-4a10-aa20-fc9239401157
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285079526 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3285079526
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2819852166
Short name T486
Test name
Test status
Simulation time 10194473696 ps
CPU time 1064.57 seconds
Started Jun 10 06:38:54 PM PDT 24
Finished Jun 10 06:56:39 PM PDT 24
Peak memory 270700 kb
Host smart-5b3cd8d3-a5f2-4091-9944-6320b41cf742
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819852166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2819852166
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2373211279
Short name T378
Test name
Test status
Simulation time 29304329407 ps
CPU time 165.83 seconds
Started Jun 10 06:38:48 PM PDT 24
Finished Jun 10 06:41:34 PM PDT 24
Peak memory 256932 kb
Host smart-181fd3a1-017b-4aec-a436-801b0d30f661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23732
11279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2373211279
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3249449522
Short name T501
Test name
Test status
Simulation time 818194886 ps
CPU time 23.89 seconds
Started Jun 10 06:38:50 PM PDT 24
Finished Jun 10 06:39:14 PM PDT 24
Peak memory 248784 kb
Host smart-ff6906fa-8882-4c1a-be6d-2f326877aa6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32494
49522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3249449522
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3003056316
Short name T637
Test name
Test status
Simulation time 26127924059 ps
CPU time 1424.85 seconds
Started Jun 10 06:38:52 PM PDT 24
Finished Jun 10 07:02:37 PM PDT 24
Peak memory 265252 kb
Host smart-a1e00b16-1637-437b-bf37-891d97847972
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003056316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3003056316
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2069357454
Short name T560
Test name
Test status
Simulation time 6458190939 ps
CPU time 608.68 seconds
Started Jun 10 06:38:58 PM PDT 24
Finished Jun 10 06:49:07 PM PDT 24
Peak memory 265092 kb
Host smart-2e93dc5e-3001-4720-bccf-02aa4d48abb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069357454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2069357454
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3289441554
Short name T480
Test name
Test status
Simulation time 2121461291 ps
CPU time 94.75 seconds
Started Jun 10 06:38:53 PM PDT 24
Finished Jun 10 06:40:29 PM PDT 24
Peak memory 247116 kb
Host smart-26deacb4-8aec-43f9-899f-3eb8d7985855
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289441554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3289441554
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2798711625
Short name T520
Test name
Test status
Simulation time 2950368885 ps
CPU time 50.5 seconds
Started Jun 10 06:38:50 PM PDT 24
Finished Jun 10 06:39:40 PM PDT 24
Peak memory 256528 kb
Host smart-2ceae105-8dc7-4c5d-b520-7d274a942f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27987
11625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2798711625
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2349217577
Short name T52
Test name
Test status
Simulation time 1566406399 ps
CPU time 43.24 seconds
Started Jun 10 06:38:49 PM PDT 24
Finished Jun 10 06:39:33 PM PDT 24
Peak memory 256852 kb
Host smart-589a48aa-cd49-475c-87fd-cf9c9e32c54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23492
17577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2349217577
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.892210094
Short name T626
Test name
Test status
Simulation time 3317341501 ps
CPU time 51.65 seconds
Started Jun 10 06:38:51 PM PDT 24
Finished Jun 10 06:39:43 PM PDT 24
Peak memory 257004 kb
Host smart-93d92b0a-2c2e-4ca8-8f51-48c51b7aafd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89221
0094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.892210094
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2383352933
Short name T581
Test name
Test status
Simulation time 682069647 ps
CPU time 49.69 seconds
Started Jun 10 06:39:00 PM PDT 24
Finished Jun 10 06:39:50 PM PDT 24
Peak memory 256732 kb
Host smart-6b755f8b-a325-4bca-9868-3d3326cf371a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383352933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2383352933
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1210053715
Short name T401
Test name
Test status
Simulation time 15651246897 ps
CPU time 1590.45 seconds
Started Jun 10 06:39:00 PM PDT 24
Finished Jun 10 07:05:31 PM PDT 24
Peak memory 289228 kb
Host smart-aadf2d9c-5248-4eb3-9d17-4370f9e9667a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210053715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1210053715
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1052628758
Short name T530
Test name
Test status
Simulation time 103989445835 ps
CPU time 318.46 seconds
Started Jun 10 06:39:00 PM PDT 24
Finished Jun 10 06:44:19 PM PDT 24
Peak memory 250796 kb
Host smart-66b6bb34-b1e5-4b37-a6d9-8a9ac6bb6bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10526
28758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1052628758
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2659239682
Short name T589
Test name
Test status
Simulation time 195800728 ps
CPU time 18.26 seconds
Started Jun 10 06:39:00 PM PDT 24
Finished Jun 10 06:39:19 PM PDT 24
Peak memory 254540 kb
Host smart-714fd1d9-51ba-4be0-a2d3-e98fbedcb28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26592
39682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2659239682
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.4032346441
Short name T496
Test name
Test status
Simulation time 15853660185 ps
CPU time 1440.5 seconds
Started Jun 10 06:39:03 PM PDT 24
Finished Jun 10 07:03:03 PM PDT 24
Peak memory 286112 kb
Host smart-fd0438ec-da01-4ff8-a71f-4f49488c4370
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032346441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.4032346441
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2689231808
Short name T462
Test name
Test status
Simulation time 217484469658 ps
CPU time 3288.99 seconds
Started Jun 10 06:39:01 PM PDT 24
Finished Jun 10 07:33:50 PM PDT 24
Peak memory 289788 kb
Host smart-45ef8b36-0764-4871-8296-5aab0c9e1393
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689231808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2689231808
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1296042535
Short name T182
Test name
Test status
Simulation time 3218461988 ps
CPU time 138.25 seconds
Started Jun 10 06:38:59 PM PDT 24
Finished Jun 10 06:41:17 PM PDT 24
Peak memory 254920 kb
Host smart-596f6c97-e420-4141-8200-399a2520746c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296042535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1296042535
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2598749632
Short name T353
Test name
Test status
Simulation time 468055526 ps
CPU time 16.64 seconds
Started Jun 10 06:38:58 PM PDT 24
Finished Jun 10 06:39:15 PM PDT 24
Peak memory 256860 kb
Host smart-78a3c45e-13f1-4fee-9ef7-d2116274de9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25987
49632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2598749632
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.206270865
Short name T476
Test name
Test status
Simulation time 3778899939 ps
CPU time 54.37 seconds
Started Jun 10 06:38:59 PM PDT 24
Finished Jun 10 06:39:53 PM PDT 24
Peak memory 254844 kb
Host smart-a1df991c-8c2e-4abf-a05c-69167fe9d703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20627
0865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.206270865
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.71369486
Short name T461
Test name
Test status
Simulation time 542440175 ps
CPU time 5.42 seconds
Started Jun 10 06:38:58 PM PDT 24
Finished Jun 10 06:39:03 PM PDT 24
Peak memory 239112 kb
Host smart-fc2b6f9a-4923-4b64-a8d7-279a8418029f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71369
486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.71369486
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1829484974
Short name T412
Test name
Test status
Simulation time 961298676 ps
CPU time 49.38 seconds
Started Jun 10 06:38:58 PM PDT 24
Finished Jun 10 06:39:47 PM PDT 24
Peak memory 255640 kb
Host smart-92472ed4-7cf5-478d-a51d-22edc84858a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18294
84974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1829484974
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3570076964
Short name T662
Test name
Test status
Simulation time 85427931467 ps
CPU time 460.18 seconds
Started Jun 10 06:39:00 PM PDT 24
Finished Jun 10 06:46:40 PM PDT 24
Peak memory 257008 kb
Host smart-ea37feeb-fe6e-4472-aab5-463f32e1d6fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570076964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3570076964
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1985839012
Short name T240
Test name
Test status
Simulation time 8445756292 ps
CPU time 196.46 seconds
Started Jun 10 06:39:01 PM PDT 24
Finished Jun 10 06:42:18 PM PDT 24
Peak memory 257020 kb
Host smart-aa2cc127-89dc-4a13-82ef-589436ccdf2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19858
39012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1985839012
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1461453526
Short name T368
Test name
Test status
Simulation time 528702764 ps
CPU time 18.46 seconds
Started Jun 10 06:38:59 PM PDT 24
Finished Jun 10 06:39:18 PM PDT 24
Peak memory 255032 kb
Host smart-88ecad6c-b2b8-4794-9d7c-faad19d2e656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14614
53526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1461453526
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3252867215
Short name T584
Test name
Test status
Simulation time 120238707012 ps
CPU time 1377.72 seconds
Started Jun 10 06:39:05 PM PDT 24
Finished Jun 10 07:02:03 PM PDT 24
Peak memory 265156 kb
Host smart-66050729-7db2-4cfb-bc20-0a7143758f18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252867215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3252867215
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1190467114
Short name T385
Test name
Test status
Simulation time 12723923359 ps
CPU time 1432.43 seconds
Started Jun 10 06:39:05 PM PDT 24
Finished Jun 10 07:02:58 PM PDT 24
Peak memory 289444 kb
Host smart-9f1d63c8-a7ae-48fb-b148-8899707eb575
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190467114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1190467114
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2810021023
Short name T636
Test name
Test status
Simulation time 16419170258 ps
CPU time 194.64 seconds
Started Jun 10 06:39:04 PM PDT 24
Finished Jun 10 06:42:19 PM PDT 24
Peak memory 248252 kb
Host smart-8cef26b0-d19c-46ee-ac0a-fe5e4ec7e203
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810021023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2810021023
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.191218611
Short name T666
Test name
Test status
Simulation time 1081729452 ps
CPU time 25.9 seconds
Started Jun 10 06:39:00 PM PDT 24
Finished Jun 10 06:39:26 PM PDT 24
Peak memory 256252 kb
Host smart-07a754a3-c0e4-4498-bbb6-2a8a402ca498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19121
8611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.191218611
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1452241862
Short name T675
Test name
Test status
Simulation time 457499379 ps
CPU time 13.76 seconds
Started Jun 10 06:39:01 PM PDT 24
Finished Jun 10 06:39:15 PM PDT 24
Peak memory 253532 kb
Host smart-bf197562-6ea7-49e5-8334-9d6ae817373c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14522
41862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1452241862
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2089576691
Short name T246
Test name
Test status
Simulation time 219787730 ps
CPU time 17.89 seconds
Started Jun 10 06:39:01 PM PDT 24
Finished Jun 10 06:39:19 PM PDT 24
Peak memory 254680 kb
Host smart-9e14c56d-2d81-40b5-aef1-2f0583916689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20895
76691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2089576691
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2720258385
Short name T458
Test name
Test status
Simulation time 529966921 ps
CPU time 10.19 seconds
Started Jun 10 06:39:01 PM PDT 24
Finished Jun 10 06:39:11 PM PDT 24
Peak memory 248672 kb
Host smart-1f403c07-74ab-4d32-9d93-76122c82c12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202
58385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2720258385
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3703450109
Short name T57
Test name
Test status
Simulation time 51292727169 ps
CPU time 1518.76 seconds
Started Jun 10 06:39:05 PM PDT 24
Finished Jun 10 07:04:24 PM PDT 24
Peak memory 289444 kb
Host smart-e778283d-6acd-435c-8eb3-7e66cb8d0164
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703450109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3703450109
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.872460340
Short name T623
Test name
Test status
Simulation time 12793963547 ps
CPU time 1012.97 seconds
Started Jun 10 06:39:12 PM PDT 24
Finished Jun 10 06:56:06 PM PDT 24
Peak memory 282336 kb
Host smart-e5e4dc93-3575-46e3-840c-f668689a2442
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872460340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.872460340
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2830447617
Short name T574
Test name
Test status
Simulation time 15573595444 ps
CPU time 266.47 seconds
Started Jun 10 06:39:07 PM PDT 24
Finished Jun 10 06:43:34 PM PDT 24
Peak memory 257000 kb
Host smart-65469525-00c7-47ca-aece-4649a6c7db3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28304
47617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2830447617
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.763343722
Short name T398
Test name
Test status
Simulation time 831661998 ps
CPU time 52.05 seconds
Started Jun 10 06:39:08 PM PDT 24
Finished Jun 10 06:40:00 PM PDT 24
Peak memory 256176 kb
Host smart-98d889f9-f386-4e60-8e10-dbd7e56d8718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76334
3722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.763343722
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.614421789
Short name T601
Test name
Test status
Simulation time 200670678353 ps
CPU time 2826.34 seconds
Started Jun 10 06:39:12 PM PDT 24
Finished Jun 10 07:26:19 PM PDT 24
Peak memory 289136 kb
Host smart-9dfb3485-5709-4ebe-9549-014dbd512af7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614421789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.614421789
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3329541478
Short name T525
Test name
Test status
Simulation time 102156041178 ps
CPU time 1370.66 seconds
Started Jun 10 06:39:14 PM PDT 24
Finished Jun 10 07:02:05 PM PDT 24
Peak memory 286288 kb
Host smart-c0567743-dea3-4ba9-91d1-b455a0abd302
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329541478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3329541478
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3369636619
Short name T474
Test name
Test status
Simulation time 33964046158 ps
CPU time 399.1 seconds
Started Jun 10 06:39:13 PM PDT 24
Finished Jun 10 06:45:53 PM PDT 24
Peak memory 248232 kb
Host smart-4b387e82-8495-48d0-b5a3-5203f99979dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369636619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3369636619
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.648227295
Short name T244
Test name
Test status
Simulation time 359024680 ps
CPU time 13.83 seconds
Started Jun 10 06:39:09 PM PDT 24
Finished Jun 10 06:39:23 PM PDT 24
Peak memory 252764 kb
Host smart-f16342bb-fb6d-4ea8-8c66-ac2bf605cb40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64822
7295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.648227295
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.418925642
Short name T29
Test name
Test status
Simulation time 955165685 ps
CPU time 47.91 seconds
Started Jun 10 06:39:07 PM PDT 24
Finished Jun 10 06:39:55 PM PDT 24
Peak memory 256032 kb
Host smart-4f225304-ca94-45c9-b071-dad76e548448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41892
5642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.418925642
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3337443610
Short name T283
Test name
Test status
Simulation time 652694796 ps
CPU time 51.55 seconds
Started Jun 10 06:39:12 PM PDT 24
Finished Jun 10 06:40:04 PM PDT 24
Peak memory 256780 kb
Host smart-b7cee63d-07ec-4079-974c-c0ffac1f0a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33374
43610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3337443610
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.251279189
Short name T550
Test name
Test status
Simulation time 230403014 ps
CPU time 13.88 seconds
Started Jun 10 06:39:09 PM PDT 24
Finished Jun 10 06:39:23 PM PDT 24
Peak memory 256864 kb
Host smart-148776f9-d8ce-494a-a75a-aea4221f9059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25127
9189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.251279189
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3943547617
Short name T269
Test name
Test status
Simulation time 228485274440 ps
CPU time 2005.51 seconds
Started Jun 10 06:39:11 PM PDT 24
Finished Jun 10 07:12:37 PM PDT 24
Peak memory 273240 kb
Host smart-9d2d0111-9126-4900-9315-6122d1d6d0d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943547617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3943547617
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.897515265
Short name T175
Test name
Test status
Simulation time 69089810795 ps
CPU time 5134.05 seconds
Started Jun 10 06:39:12 PM PDT 24
Finished Jun 10 08:04:47 PM PDT 24
Peak memory 319540 kb
Host smart-39784f9a-5d9b-41bf-88d3-2b58c09b7d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897515265 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.897515265
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1680272678
Short name T697
Test name
Test status
Simulation time 29245667108 ps
CPU time 1211.29 seconds
Started Jun 10 06:39:18 PM PDT 24
Finished Jun 10 06:59:30 PM PDT 24
Peak memory 282884 kb
Host smart-d67f03cc-51d5-4d2a-87ee-6498aeaa87ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680272678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1680272678
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.4151208517
Short name T484
Test name
Test status
Simulation time 4120625966 ps
CPU time 202.93 seconds
Started Jun 10 06:39:15 PM PDT 24
Finished Jun 10 06:42:38 PM PDT 24
Peak memory 250024 kb
Host smart-33b4ddfd-fefd-4d5d-9733-b7ea7065749e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41512
08517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4151208517
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2945283249
Short name T440
Test name
Test status
Simulation time 1536680681 ps
CPU time 54.93 seconds
Started Jun 10 06:39:17 PM PDT 24
Finished Jun 10 06:40:12 PM PDT 24
Peak memory 248768 kb
Host smart-caa28abe-226c-40cb-baf7-5a45e1e54f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29452
83249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2945283249
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1810682015
Short name T683
Test name
Test status
Simulation time 90328681443 ps
CPU time 2679.22 seconds
Started Jun 10 06:39:18 PM PDT 24
Finished Jun 10 07:23:58 PM PDT 24
Peak memory 288916 kb
Host smart-4a4590a1-91fd-40da-9639-aaba677ef871
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810682015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1810682015
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2822865273
Short name T543
Test name
Test status
Simulation time 49936348468 ps
CPU time 1652.09 seconds
Started Jun 10 06:39:19 PM PDT 24
Finished Jun 10 07:06:52 PM PDT 24
Peak memory 272616 kb
Host smart-788c768f-77a8-446b-9792-1cd6f736a39b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822865273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2822865273
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3277573082
Short name T304
Test name
Test status
Simulation time 9873551197 ps
CPU time 416.45 seconds
Started Jun 10 06:39:19 PM PDT 24
Finished Jun 10 06:46:16 PM PDT 24
Peak memory 248144 kb
Host smart-76d4abc2-7c2f-41bc-bdf1-7a01563c2bc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277573082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3277573082
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2013059688
Short name T566
Test name
Test status
Simulation time 388316940 ps
CPU time 9.92 seconds
Started Jun 10 06:39:10 PM PDT 24
Finished Jun 10 06:39:20 PM PDT 24
Peak memory 254472 kb
Host smart-029e5c7f-e401-405b-bd0a-506b350111fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20130
59688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2013059688
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3976059767
Short name T91
Test name
Test status
Simulation time 1286716963 ps
CPU time 33.73 seconds
Started Jun 10 06:39:16 PM PDT 24
Finished Jun 10 06:39:49 PM PDT 24
Peak memory 256452 kb
Host smart-84896121-5742-411b-a5b9-05ebe4c0d882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39760
59767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3976059767
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3665051569
Short name T618
Test name
Test status
Simulation time 180676619 ps
CPU time 11.24 seconds
Started Jun 10 06:39:16 PM PDT 24
Finished Jun 10 06:39:28 PM PDT 24
Peak memory 256048 kb
Host smart-2f4cf550-a469-4bff-af7c-be582e93e487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36650
51569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3665051569
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.478774335
Short name T303
Test name
Test status
Simulation time 1720843343 ps
CPU time 44.97 seconds
Started Jun 10 06:39:12 PM PDT 24
Finished Jun 10 06:39:58 PM PDT 24
Peak memory 248748 kb
Host smart-a84d1bbf-fba8-4601-92e8-9109650cb26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47877
4335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.478774335
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.4131934049
Short name T668
Test name
Test status
Simulation time 2395799240 ps
CPU time 146.26 seconds
Started Jun 10 06:39:23 PM PDT 24
Finished Jun 10 06:41:50 PM PDT 24
Peak memory 256996 kb
Host smart-a51a31b2-a2dc-461f-8e58-42879a08ceb7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131934049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.4131934049
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2610845304
Short name T649
Test name
Test status
Simulation time 32057835797 ps
CPU time 2207.6 seconds
Started Jun 10 06:39:26 PM PDT 24
Finished Jun 10 07:16:14 PM PDT 24
Peak memory 285176 kb
Host smart-6d362a9d-4a56-4663-9b86-50b7b179427e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610845304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2610845304
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2927576449
Short name T531
Test name
Test status
Simulation time 5654563879 ps
CPU time 54.33 seconds
Started Jun 10 06:39:27 PM PDT 24
Finished Jun 10 06:40:21 PM PDT 24
Peak memory 249052 kb
Host smart-8c76e451-29bd-4832-8fdb-4a95682faea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29275
76449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2927576449
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2460196863
Short name T519
Test name
Test status
Simulation time 2286104319 ps
CPU time 31.68 seconds
Started Jun 10 06:39:27 PM PDT 24
Finished Jun 10 06:39:59 PM PDT 24
Peak memory 256276 kb
Host smart-e51a5e46-11c0-4f75-bbbf-6ad6c8b10830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24601
96863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2460196863
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2391140680
Short name T595
Test name
Test status
Simulation time 8291421725 ps
CPU time 722.44 seconds
Started Jun 10 06:39:34 PM PDT 24
Finished Jun 10 06:51:37 PM PDT 24
Peak memory 272504 kb
Host smart-5a048f0a-4a50-4852-a70e-8e53147c3fd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391140680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2391140680
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2425472035
Short name T603
Test name
Test status
Simulation time 3049777969 ps
CPU time 117.43 seconds
Started Jun 10 06:39:28 PM PDT 24
Finished Jun 10 06:41:26 PM PDT 24
Peak memory 247212 kb
Host smart-78ab9896-ae1c-4059-a019-93a6221774cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425472035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2425472035
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.352304669
Short name T687
Test name
Test status
Simulation time 41162206 ps
CPU time 5.95 seconds
Started Jun 10 06:39:23 PM PDT 24
Finished Jun 10 06:39:29 PM PDT 24
Peak memory 240552 kb
Host smart-4355d414-cfb1-4415-b72a-6f1e36bfed9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35230
4669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.352304669
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1496396371
Short name T116
Test name
Test status
Simulation time 4715638832 ps
CPU time 34.12 seconds
Started Jun 10 06:39:28 PM PDT 24
Finished Jun 10 06:40:03 PM PDT 24
Peak memory 256716 kb
Host smart-c8f53062-3faa-4af7-b24c-9b982e407ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14963
96371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1496396371
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1636969140
Short name T707
Test name
Test status
Simulation time 391533827 ps
CPU time 15.71 seconds
Started Jun 10 06:39:29 PM PDT 24
Finished Jun 10 06:39:45 PM PDT 24
Peak memory 255968 kb
Host smart-613e20a4-bdfc-4da0-8e6b-2edd4e072ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16369
69140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1636969140
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1149254909
Short name T43
Test name
Test status
Simulation time 544279369 ps
CPU time 31.51 seconds
Started Jun 10 06:39:24 PM PDT 24
Finished Jun 10 06:39:55 PM PDT 24
Peak memory 248728 kb
Host smart-06fdfec4-2762-497c-a51d-ce2c70dcc6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11492
54909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1149254909
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.964676622
Short name T518
Test name
Test status
Simulation time 8974240364 ps
CPU time 858.41 seconds
Started Jun 10 06:39:34 PM PDT 24
Finished Jun 10 06:53:53 PM PDT 24
Peak memory 273484 kb
Host smart-9cc4584f-ab3e-4e69-bb40-1de54fc40bc5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964676622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.964676622
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2396084208
Short name T653
Test name
Test status
Simulation time 17751624415 ps
CPU time 2118.37 seconds
Started Jun 10 06:39:35 PM PDT 24
Finished Jun 10 07:14:54 PM PDT 24
Peak memory 305592 kb
Host smart-2825c754-3336-4ce2-8555-a9b49264837a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396084208 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2396084208
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2134607914
Short name T596
Test name
Test status
Simulation time 22113254768 ps
CPU time 937.01 seconds
Started Jun 10 06:39:37 PM PDT 24
Finished Jun 10 06:55:15 PM PDT 24
Peak memory 286996 kb
Host smart-dea4f5fb-8cc8-4b5b-9572-513c6c5e0937
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134607914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2134607914
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.302459244
Short name T546
Test name
Test status
Simulation time 9245481327 ps
CPU time 165.54 seconds
Started Jun 10 06:39:37 PM PDT 24
Finished Jun 10 06:42:23 PM PDT 24
Peak memory 256880 kb
Host smart-e4c0e563-3007-4812-b391-8c87a516fede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30245
9244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.302459244
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.518295067
Short name T652
Test name
Test status
Simulation time 971680833 ps
CPU time 60.91 seconds
Started Jun 10 06:39:39 PM PDT 24
Finished Jun 10 06:40:40 PM PDT 24
Peak memory 255548 kb
Host smart-93e933f8-b30b-42fd-bdf1-dc7cdf78d1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51829
5067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.518295067
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.967892209
Short name T334
Test name
Test status
Simulation time 18792650998 ps
CPU time 1678.5 seconds
Started Jun 10 06:39:43 PM PDT 24
Finished Jun 10 07:07:42 PM PDT 24
Peak memory 289636 kb
Host smart-35a88a79-6d00-4bed-8b6d-3ed5447f5ce8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967892209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.967892209
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.682765602
Short name T15
Test name
Test status
Simulation time 103508624226 ps
CPU time 1815.48 seconds
Started Jun 10 06:39:43 PM PDT 24
Finished Jun 10 07:09:59 PM PDT 24
Peak memory 283416 kb
Host smart-4fce2ede-c538-47bc-964e-576018e97cfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682765602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.682765602
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.73501972
Short name T315
Test name
Test status
Simulation time 11626032528 ps
CPU time 481.17 seconds
Started Jun 10 06:39:43 PM PDT 24
Finished Jun 10 06:47:45 PM PDT 24
Peak memory 247284 kb
Host smart-f397e7ed-d5d6-4178-a727-9d0ccfbd9afc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73501972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.73501972
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3530768394
Short name T426
Test name
Test status
Simulation time 1175043335 ps
CPU time 43.82 seconds
Started Jun 10 06:39:41 PM PDT 24
Finished Jun 10 06:40:25 PM PDT 24
Peak memory 255900 kb
Host smart-b2dd8b02-485c-4059-b2f8-ef29282ef8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35307
68394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3530768394
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3061520044
Short name T565
Test name
Test status
Simulation time 113472363 ps
CPU time 11.12 seconds
Started Jun 10 06:39:40 PM PDT 24
Finished Jun 10 06:39:51 PM PDT 24
Peak memory 255856 kb
Host smart-78edbd04-a8e7-4c34-be32-4caec3f142a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30615
20044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3061520044
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1839981749
Short name T473
Test name
Test status
Simulation time 1287684928 ps
CPU time 11.85 seconds
Started Jun 10 06:39:40 PM PDT 24
Finished Jun 10 06:39:52 PM PDT 24
Peak memory 251324 kb
Host smart-75eeb2c0-a549-48a5-b0aa-172298f95a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18399
81749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1839981749
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2642688599
Short name T679
Test name
Test status
Simulation time 49218348 ps
CPU time 4.62 seconds
Started Jun 10 06:39:38 PM PDT 24
Finished Jun 10 06:39:43 PM PDT 24
Peak memory 240532 kb
Host smart-add65a04-ac38-4d14-9953-938af2a2ed29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26426
88599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2642688599
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1616708950
Short name T612
Test name
Test status
Simulation time 18431608518 ps
CPU time 847.64 seconds
Started Jun 10 06:39:54 PM PDT 24
Finished Jun 10 06:54:02 PM PDT 24
Peak memory 265184 kb
Host smart-6b2fecef-a83f-49dc-8f34-3f6eedee095d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616708950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1616708950
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2129816563
Short name T78
Test name
Test status
Simulation time 16936272028 ps
CPU time 135.44 seconds
Started Jun 10 06:39:51 PM PDT 24
Finished Jun 10 06:42:07 PM PDT 24
Peak memory 249952 kb
Host smart-2f10b8cc-f2c4-44e2-9b37-3ff26bbda0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21298
16563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2129816563
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1505593086
Short name T88
Test name
Test status
Simulation time 1161524737 ps
CPU time 17.27 seconds
Started Jun 10 06:39:52 PM PDT 24
Finished Jun 10 06:40:09 PM PDT 24
Peak memory 255316 kb
Host smart-7ab5bb3e-2908-4eb6-a222-30a87a45f7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15055
93086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1505593086
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1781376677
Short name T339
Test name
Test status
Simulation time 149068094662 ps
CPU time 1845.69 seconds
Started Jun 10 06:39:50 PM PDT 24
Finished Jun 10 07:10:36 PM PDT 24
Peak memory 273156 kb
Host smart-f158b3dc-9296-404b-a559-4ef738c71292
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781376677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1781376677
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3898050323
Short name T377
Test name
Test status
Simulation time 31522121569 ps
CPU time 1742.89 seconds
Started Jun 10 06:39:50 PM PDT 24
Finished Jun 10 07:08:54 PM PDT 24
Peak memory 273000 kb
Host smart-35a714b4-e914-4990-8a19-15a81af726c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898050323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3898050323
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3917499677
Short name T633
Test name
Test status
Simulation time 27700481514 ps
CPU time 311.45 seconds
Started Jun 10 06:39:52 PM PDT 24
Finished Jun 10 06:45:04 PM PDT 24
Peak memory 248464 kb
Host smart-df31d2b5-8041-4483-8427-b65958aa4541
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917499677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3917499677
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1138391863
Short name T482
Test name
Test status
Simulation time 398151447 ps
CPU time 12.5 seconds
Started Jun 10 06:39:46 PM PDT 24
Finished Jun 10 06:39:59 PM PDT 24
Peak memory 248732 kb
Host smart-26ff1eab-ff88-4628-a650-6278789ed9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11383
91863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1138391863
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1874264570
Short name T354
Test name
Test status
Simulation time 395030544 ps
CPU time 9.15 seconds
Started Jun 10 06:39:53 PM PDT 24
Finished Jun 10 06:40:03 PM PDT 24
Peak memory 250696 kb
Host smart-00eac190-65a6-476a-a012-d4c35c02b37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18742
64570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1874264570
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1964836769
Short name T420
Test name
Test status
Simulation time 615274903 ps
CPU time 41.24 seconds
Started Jun 10 06:39:49 PM PDT 24
Finished Jun 10 06:40:30 PM PDT 24
Peak memory 247472 kb
Host smart-651e454a-338a-44f6-bda4-b939313a2ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19648
36769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1964836769
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.980088609
Short name T380
Test name
Test status
Simulation time 545702950 ps
CPU time 4.89 seconds
Started Jun 10 06:39:50 PM PDT 24
Finished Jun 10 06:39:55 PM PDT 24
Peak memory 248752 kb
Host smart-2e715e9b-3602-43ee-a4b3-9e3c3b1ef596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98008
8609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.980088609
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3881230373
Short name T94
Test name
Test status
Simulation time 43086670490 ps
CPU time 1881.85 seconds
Started Jun 10 06:39:49 PM PDT 24
Finished Jun 10 07:11:12 PM PDT 24
Peak memory 299728 kb
Host smart-04ca53c1-8531-4872-a86f-b2bb05926a81
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881230373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3881230373
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.368241849
Short name T193
Test name
Test status
Simulation time 206106071187 ps
CPU time 5853.28 seconds
Started Jun 10 06:39:50 PM PDT 24
Finished Jun 10 08:17:24 PM PDT 24
Peak memory 371304 kb
Host smart-88e073c2-361f-416c-ad1d-d13544157129
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368241849 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.368241849
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3503177979
Short name T212
Test name
Test status
Simulation time 44429361 ps
CPU time 4.05 seconds
Started Jun 10 06:36:46 PM PDT 24
Finished Jun 10 06:36:51 PM PDT 24
Peak memory 248932 kb
Host smart-ea2f6c97-09bf-4cb0-8a6e-287d6121846f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3503177979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3503177979
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.683283192
Short name T263
Test name
Test status
Simulation time 370137755382 ps
CPU time 3214.79 seconds
Started Jun 10 06:36:51 PM PDT 24
Finished Jun 10 07:30:27 PM PDT 24
Peak memory 289432 kb
Host smart-8e6c855d-2c74-4000-a36e-eeb62c9bfc79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683283192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.683283192
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1449851772
Short name T468
Test name
Test status
Simulation time 766257044 ps
CPU time 18.62 seconds
Started Jun 10 06:36:49 PM PDT 24
Finished Jun 10 06:37:08 PM PDT 24
Peak memory 248764 kb
Host smart-cae6c8f1-30e7-4d6f-8225-7ee79fa1210c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1449851772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1449851772
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3982453043
Short name T529
Test name
Test status
Simulation time 1682033894 ps
CPU time 62.33 seconds
Started Jun 10 06:36:51 PM PDT 24
Finished Jun 10 06:37:54 PM PDT 24
Peak memory 256800 kb
Host smart-bee61e72-6b31-4e97-9f6e-29643654de82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39824
53043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3982453043
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1632441403
Short name T631
Test name
Test status
Simulation time 451845239 ps
CPU time 13.08 seconds
Started Jun 10 06:36:50 PM PDT 24
Finished Jun 10 06:37:03 PM PDT 24
Peak memory 248696 kb
Host smart-bdea61b8-6eee-4343-b177-5932b4313c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16324
41403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1632441403
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1730622555
Short name T425
Test name
Test status
Simulation time 62979050455 ps
CPU time 1293.23 seconds
Started Jun 10 06:36:50 PM PDT 24
Finished Jun 10 06:58:23 PM PDT 24
Peak memory 285364 kb
Host smart-d7146b02-f262-4921-9aba-4cc7908c932b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730622555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1730622555
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3945644142
Short name T445
Test name
Test status
Simulation time 1816244341 ps
CPU time 30.07 seconds
Started Jun 10 06:36:47 PM PDT 24
Finished Jun 10 06:37:18 PM PDT 24
Peak memory 248804 kb
Host smart-0e22f673-ce26-425a-abd7-dc60b20e2765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39456
44142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3945644142
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1303979264
Short name T609
Test name
Test status
Simulation time 853070084 ps
CPU time 53.77 seconds
Started Jun 10 06:36:49 PM PDT 24
Finished Jun 10 06:37:44 PM PDT 24
Peak memory 255032 kb
Host smart-e48be6e9-c0f5-435f-b74e-dfc6221f07ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13039
79264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1303979264
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3371941915
Short name T37
Test name
Test status
Simulation time 1337100183 ps
CPU time 42.12 seconds
Started Jun 10 06:36:52 PM PDT 24
Finished Jun 10 06:37:35 PM PDT 24
Peak memory 271200 kb
Host smart-4922cd56-801d-47db-82a6-f2bdfaa94226
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3371941915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3371941915
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1564796792
Short name T449
Test name
Test status
Simulation time 894570070 ps
CPU time 28.23 seconds
Started Jun 10 06:36:49 PM PDT 24
Finished Jun 10 06:37:18 PM PDT 24
Peak memory 255636 kb
Host smart-5500dce6-c156-46a5-b474-1d91d7baf959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15647
96792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1564796792
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.965546330
Short name T669
Test name
Test status
Simulation time 579350359 ps
CPU time 30.68 seconds
Started Jun 10 06:36:47 PM PDT 24
Finished Jun 10 06:37:18 PM PDT 24
Peak memory 248768 kb
Host smart-c20972a0-7866-4245-a399-c15f702ceec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96554
6330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.965546330
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3771237527
Short name T512
Test name
Test status
Simulation time 149253856202 ps
CPU time 1631.32 seconds
Started Jun 10 06:39:54 PM PDT 24
Finished Jun 10 07:07:06 PM PDT 24
Peak memory 266180 kb
Host smart-cbd2ed8d-341b-4c55-9f66-e4efd6dd19ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771237527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3771237527
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3713886828
Short name T684
Test name
Test status
Simulation time 3865067294 ps
CPU time 203.04 seconds
Started Jun 10 06:39:57 PM PDT 24
Finished Jun 10 06:43:20 PM PDT 24
Peak memory 256980 kb
Host smart-91f5b501-efc3-4085-8b2f-3693697cf78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37138
86828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3713886828
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3955467010
Short name T587
Test name
Test status
Simulation time 621665541 ps
CPU time 22.24 seconds
Started Jun 10 06:39:56 PM PDT 24
Finished Jun 10 06:40:18 PM PDT 24
Peak memory 248672 kb
Host smart-624bcde6-c558-4233-9501-b77f68a0727a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39554
67010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3955467010
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1375295402
Short name T328
Test name
Test status
Simulation time 10827843211 ps
CPU time 1028.9 seconds
Started Jun 10 06:39:58 PM PDT 24
Finished Jun 10 06:57:07 PM PDT 24
Peak memory 281624 kb
Host smart-54ed6373-f68d-4640-90d2-2bf918d8ad0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375295402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1375295402
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2339916304
Short name T178
Test name
Test status
Simulation time 8543944375 ps
CPU time 338.06 seconds
Started Jun 10 06:39:57 PM PDT 24
Finished Jun 10 06:45:35 PM PDT 24
Peak memory 247440 kb
Host smart-10bcdaa1-4242-476f-9168-c1583a0f891d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339916304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2339916304
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1610020724
Short name T500
Test name
Test status
Simulation time 3438168727 ps
CPU time 45.14 seconds
Started Jun 10 06:39:55 PM PDT 24
Finished Jun 10 06:40:40 PM PDT 24
Peak memory 248820 kb
Host smart-56040ff0-8e42-4b6d-86ab-fa922f19bd97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16100
20724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1610020724
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2041204941
Short name T455
Test name
Test status
Simulation time 630133213 ps
CPU time 25.76 seconds
Started Jun 10 06:39:55 PM PDT 24
Finished Jun 10 06:40:21 PM PDT 24
Peak memory 248928 kb
Host smart-e3b40644-5f4a-426e-baa2-f0876ec56274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20412
04941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2041204941
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.875048781
Short name T87
Test name
Test status
Simulation time 789230958 ps
CPU time 29.95 seconds
Started Jun 10 06:39:53 PM PDT 24
Finished Jun 10 06:40:24 PM PDT 24
Peak memory 255836 kb
Host smart-b9c1fe15-dc34-4bea-8e90-d41d0711e774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87504
8781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.875048781
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3487754865
Short name T415
Test name
Test status
Simulation time 145901555 ps
CPU time 15.69 seconds
Started Jun 10 06:39:52 PM PDT 24
Finished Jun 10 06:40:08 PM PDT 24
Peak memory 248872 kb
Host smart-6903fc3a-9eb9-4522-836c-170996d73a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34877
54865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3487754865
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2250604728
Short name T93
Test name
Test status
Simulation time 3540824898 ps
CPU time 115.5 seconds
Started Jun 10 06:39:57 PM PDT 24
Finished Jun 10 06:41:52 PM PDT 24
Peak memory 256920 kb
Host smart-be5db701-6dbe-4fd7-ae8f-ae9eb5bfb5a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250604728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2250604728
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1116510779
Short name T111
Test name
Test status
Simulation time 10980791975 ps
CPU time 1122.81 seconds
Started Jun 10 06:40:02 PM PDT 24
Finished Jun 10 06:58:45 PM PDT 24
Peak memory 272768 kb
Host smart-a65da32c-314d-4eb8-bb4f-5aeba93f11de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116510779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1116510779
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2954087223
Short name T556
Test name
Test status
Simulation time 354871421 ps
CPU time 42.04 seconds
Started Jun 10 06:40:04 PM PDT 24
Finished Jun 10 06:40:46 PM PDT 24
Peak memory 248912 kb
Host smart-556f28a6-3352-4e46-941c-1cff428f1ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29540
87223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2954087223
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2554367035
Short name T619
Test name
Test status
Simulation time 4448323183 ps
CPU time 50.7 seconds
Started Jun 10 06:39:57 PM PDT 24
Finished Jun 10 06:40:48 PM PDT 24
Peak memory 255792 kb
Host smart-27e50699-de13-48f4-8e03-ef66b261b052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25543
67035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2554367035
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3498781057
Short name T340
Test name
Test status
Simulation time 53041809374 ps
CPU time 1429.85 seconds
Started Jun 10 06:40:04 PM PDT 24
Finished Jun 10 07:03:54 PM PDT 24
Peak memory 283224 kb
Host smart-d1674194-ca1c-4295-bd00-dc1dd0f9b55f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498781057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3498781057
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1578652966
Short name T70
Test name
Test status
Simulation time 24225584810 ps
CPU time 1301.59 seconds
Started Jun 10 06:40:05 PM PDT 24
Finished Jun 10 07:01:47 PM PDT 24
Peak memory 289144 kb
Host smart-6861603c-cfc2-4fef-b1f9-7509117679da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578652966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1578652966
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.674559266
Short name T322
Test name
Test status
Simulation time 8480753320 ps
CPU time 164.23 seconds
Started Jun 10 06:40:00 PM PDT 24
Finished Jun 10 06:42:45 PM PDT 24
Peak memory 248252 kb
Host smart-d9914b74-9035-4df7-b74f-368bbf75db38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674559266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.674559266
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3917701980
Short name T528
Test name
Test status
Simulation time 1136333340 ps
CPU time 28.89 seconds
Started Jun 10 06:39:57 PM PDT 24
Finished Jun 10 06:40:26 PM PDT 24
Peak memory 248740 kb
Host smart-4fe6ce04-6070-49e8-95e0-519c9cd51575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39177
01980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3917701980
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.83908414
Short name T663
Test name
Test status
Simulation time 1847451026 ps
CPU time 14.51 seconds
Started Jun 10 06:39:57 PM PDT 24
Finished Jun 10 06:40:12 PM PDT 24
Peak memory 255164 kb
Host smart-b6fc03ba-ad92-497a-929b-f242d38eabc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83908
414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.83908414
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2470519634
Short name T242
Test name
Test status
Simulation time 236213569 ps
CPU time 32.18 seconds
Started Jun 10 06:40:03 PM PDT 24
Finished Jun 10 06:40:35 PM PDT 24
Peak memory 247904 kb
Host smart-7b0a4b31-bfc1-402d-b2fc-6899bfe181ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24705
19634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2470519634
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.597867954
Short name T285
Test name
Test status
Simulation time 259349013 ps
CPU time 28 seconds
Started Jun 10 06:39:58 PM PDT 24
Finished Jun 10 06:40:26 PM PDT 24
Peak memory 248680 kb
Host smart-9dec4c12-8fb1-4249-8eee-ce132c5a34f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59786
7954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.597867954
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1088286450
Short name T553
Test name
Test status
Simulation time 163545493525 ps
CPU time 2754.31 seconds
Started Jun 10 06:40:07 PM PDT 24
Finished Jun 10 07:26:02 PM PDT 24
Peak memory 289068 kb
Host smart-5a17eb6d-2aea-4bd2-9d2d-56114fc7a885
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088286450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1088286450
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2221069739
Short name T703
Test name
Test status
Simulation time 2634424906 ps
CPU time 212.77 seconds
Started Jun 10 06:40:07 PM PDT 24
Finished Jun 10 06:43:40 PM PDT 24
Peak memory 265296 kb
Host smart-acf891e4-1229-47d2-bd1f-6bef7527cd56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221069739 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2221069739
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.705781177
Short name T55
Test name
Test status
Simulation time 47256740258 ps
CPU time 1666.09 seconds
Started Jun 10 06:40:13 PM PDT 24
Finished Jun 10 07:07:59 PM PDT 24
Peak memory 273312 kb
Host smart-5a533cab-cc7b-49bb-94c1-6cc4e18bc1e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705781177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.705781177
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2695068335
Short name T499
Test name
Test status
Simulation time 2245837296 ps
CPU time 95.8 seconds
Started Jun 10 06:40:09 PM PDT 24
Finished Jun 10 06:41:45 PM PDT 24
Peak memory 249848 kb
Host smart-0bfd3c90-6a87-4f6d-95a6-ab33d64e5b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26950
68335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2695068335
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2552475176
Short name T489
Test name
Test status
Simulation time 10357381957 ps
CPU time 59.21 seconds
Started Jun 10 06:40:11 PM PDT 24
Finished Jun 10 06:41:10 PM PDT 24
Peak memory 255564 kb
Host smart-7d4fbcf7-5268-4659-98de-731adb88ad30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25524
75176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2552475176
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3522711335
Short name T6
Test name
Test status
Simulation time 166554826923 ps
CPU time 2642.66 seconds
Started Jun 10 06:40:15 PM PDT 24
Finished Jun 10 07:24:18 PM PDT 24
Peak memory 281560 kb
Host smart-79141406-427a-4458-a8b6-8737722c9321
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522711335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3522711335
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3203671043
Short name T503
Test name
Test status
Simulation time 38387955243 ps
CPU time 1137 seconds
Started Jun 10 06:40:13 PM PDT 24
Finished Jun 10 06:59:10 PM PDT 24
Peak memory 272680 kb
Host smart-d173fdc9-315d-45ee-a054-ce91a0917246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203671043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3203671043
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1102850268
Short name T471
Test name
Test status
Simulation time 4302787685 ps
CPU time 62.52 seconds
Started Jun 10 06:40:07 PM PDT 24
Finished Jun 10 06:41:10 PM PDT 24
Peak memory 257004 kb
Host smart-6aac8f7c-b5b1-456e-8974-00d6fb107755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11028
50268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1102850268
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2032215851
Short name T572
Test name
Test status
Simulation time 188646334 ps
CPU time 26.42 seconds
Started Jun 10 06:40:06 PM PDT 24
Finished Jun 10 06:40:33 PM PDT 24
Peak memory 256832 kb
Host smart-ba5d7931-9b33-47d7-8368-5038578e49f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20322
15851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2032215851
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.4145062342
Short name T627
Test name
Test status
Simulation time 1217240970 ps
CPU time 19.98 seconds
Started Jun 10 06:40:14 PM PDT 24
Finished Jun 10 06:40:34 PM PDT 24
Peak memory 248616 kb
Host smart-e69051bb-e814-4fbe-9b83-6d42628ba131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41450
62342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.4145062342
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2409331511
Short name T654
Test name
Test status
Simulation time 1020383466 ps
CPU time 19.09 seconds
Started Jun 10 06:40:06 PM PDT 24
Finished Jun 10 06:40:25 PM PDT 24
Peak memory 248764 kb
Host smart-0c351751-b33e-4eb8-8890-fcbec0b934d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24093
31511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2409331511
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2515425995
Short name T701
Test name
Test status
Simulation time 127875359 ps
CPU time 15.3 seconds
Started Jun 10 06:40:14 PM PDT 24
Finished Jun 10 06:40:30 PM PDT 24
Peak memory 255888 kb
Host smart-694ef3b5-f3d8-49b9-ad7c-29e26f19f514
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515425995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2515425995
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2021651321
Short name T69
Test name
Test status
Simulation time 70375543701 ps
CPU time 1633.1 seconds
Started Jun 10 06:40:26 PM PDT 24
Finished Jun 10 07:07:40 PM PDT 24
Peak memory 289104 kb
Host smart-beb680d7-7a9b-4a4b-9c59-a2f21a074cc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021651321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2021651321
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2099801719
Short name T236
Test name
Test status
Simulation time 3441317632 ps
CPU time 186.67 seconds
Started Jun 10 06:40:23 PM PDT 24
Finished Jun 10 06:43:30 PM PDT 24
Peak memory 250044 kb
Host smart-847eeea2-e870-41b5-bf02-1de2222f48ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20998
01719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2099801719
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2576245010
Short name T382
Test name
Test status
Simulation time 2558435581 ps
CPU time 34.97 seconds
Started Jun 10 06:40:22 PM PDT 24
Finished Jun 10 06:40:57 PM PDT 24
Peak memory 255772 kb
Host smart-7e9cd72c-8ede-4504-a48e-bc77192aa4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25762
45010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2576245010
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3228109962
Short name T693
Test name
Test status
Simulation time 38114953578 ps
CPU time 2013.63 seconds
Started Jun 10 06:40:27 PM PDT 24
Finished Jun 10 07:14:01 PM PDT 24
Peak memory 281516 kb
Host smart-2bb6672f-abe2-4b69-80aa-4378e4aa1b80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228109962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3228109962
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1216142496
Short name T538
Test name
Test status
Simulation time 43208581141 ps
CPU time 1947.99 seconds
Started Jun 10 06:40:27 PM PDT 24
Finished Jun 10 07:12:55 PM PDT 24
Peak memory 283596 kb
Host smart-8eb865ab-0a0c-4052-8e7e-46b5f23f2b47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216142496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1216142496
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.4104225003
Short name T602
Test name
Test status
Simulation time 24476103403 ps
CPU time 252.82 seconds
Started Jun 10 06:40:27 PM PDT 24
Finished Jun 10 06:44:40 PM PDT 24
Peak memory 248324 kb
Host smart-3277cc65-39ea-492f-a1cf-388611863d50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104225003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.4104225003
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.397850091
Short name T421
Test name
Test status
Simulation time 2036422900 ps
CPU time 39.8 seconds
Started Jun 10 06:40:18 PM PDT 24
Finished Jun 10 06:40:58 PM PDT 24
Peak memory 248760 kb
Host smart-c4f8f055-e60f-48d3-9e64-c80a9b946c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39785
0091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.397850091
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3042280588
Short name T76
Test name
Test status
Simulation time 362208312 ps
CPU time 30.74 seconds
Started Jun 10 06:40:16 PM PDT 24
Finished Jun 10 06:40:47 PM PDT 24
Peak memory 248080 kb
Host smart-25a27505-889b-4004-95d9-1ce793d6141f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30422
80588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3042280588
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3261140572
Short name T107
Test name
Test status
Simulation time 304447545 ps
CPU time 26.26 seconds
Started Jun 10 06:40:22 PM PDT 24
Finished Jun 10 06:40:49 PM PDT 24
Peak memory 247556 kb
Host smart-a5983926-d83c-4b40-b06b-1f856d1d967a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32611
40572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3261140572
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3525329508
Short name T464
Test name
Test status
Simulation time 1368604190 ps
CPU time 92.1 seconds
Started Jun 10 06:40:17 PM PDT 24
Finished Jun 10 06:41:49 PM PDT 24
Peak memory 248776 kb
Host smart-24ef1e2f-c9a4-4964-95ef-f7d537dfde43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35253
29508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3525329508
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.4107243184
Short name T655
Test name
Test status
Simulation time 61000457316 ps
CPU time 5418.14 seconds
Started Jun 10 06:40:31 PM PDT 24
Finished Jun 10 08:10:50 PM PDT 24
Peak memory 338536 kb
Host smart-7704a86f-f81d-40f2-9a48-cffa7d39dcfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107243184 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.4107243184
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.362390403
Short name T604
Test name
Test status
Simulation time 144510140325 ps
CPU time 1095.92 seconds
Started Jun 10 06:40:38 PM PDT 24
Finished Jun 10 06:58:55 PM PDT 24
Peak memory 272608 kb
Host smart-2c1e6284-d91a-4c16-8cfa-c1a1da3ab6b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362390403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.362390403
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.137053427
Short name T539
Test name
Test status
Simulation time 220607910 ps
CPU time 20.69 seconds
Started Jun 10 06:40:31 PM PDT 24
Finished Jun 10 06:40:52 PM PDT 24
Peak memory 256388 kb
Host smart-b444f114-7a63-4cfc-8ee5-50157e377394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13705
3427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.137053427
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3843044239
Short name T257
Test name
Test status
Simulation time 596601228 ps
CPU time 31.58 seconds
Started Jun 10 06:40:39 PM PDT 24
Finished Jun 10 06:41:11 PM PDT 24
Peak memory 256892 kb
Host smart-07070e29-8170-49dc-bf7e-5783dced76d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38430
44239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3843044239
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2465003421
Short name T562
Test name
Test status
Simulation time 6912393044 ps
CPU time 783.9 seconds
Started Jun 10 06:40:39 PM PDT 24
Finished Jun 10 06:53:44 PM PDT 24
Peak memory 273272 kb
Host smart-bc4a3a61-0229-4061-ab67-9c0617adb329
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465003421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2465003421
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3936638662
Short name T504
Test name
Test status
Simulation time 13646355141 ps
CPU time 988.17 seconds
Started Jun 10 06:40:41 PM PDT 24
Finished Jun 10 06:57:10 PM PDT 24
Peak memory 273324 kb
Host smart-2beb6996-79b7-4d45-a934-36da8c15d213
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936638662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3936638662
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2492592224
Short name T321
Test name
Test status
Simulation time 33488101444 ps
CPU time 288.91 seconds
Started Jun 10 06:40:40 PM PDT 24
Finished Jun 10 06:45:29 PM PDT 24
Peak memory 248372 kb
Host smart-ceea5274-ce30-4d73-bd07-014c56ff0ab6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492592224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2492592224
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1047231381
Short name T498
Test name
Test status
Simulation time 130555940 ps
CPU time 9.41 seconds
Started Jun 10 06:40:31 PM PDT 24
Finished Jun 10 06:40:41 PM PDT 24
Peak memory 256868 kb
Host smart-9eb0a13d-7b81-4285-aaed-740eaa021857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10472
31381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1047231381
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.655319350
Short name T357
Test name
Test status
Simulation time 582724188 ps
CPU time 35.01 seconds
Started Jun 10 06:40:30 PM PDT 24
Finished Jun 10 06:41:06 PM PDT 24
Peak memory 255676 kb
Host smart-2b1a5115-e1cb-4d97-83a7-619ca3575aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65531
9350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.655319350
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2682851284
Short name T395
Test name
Test status
Simulation time 4043685261 ps
CPU time 68.46 seconds
Started Jun 10 06:40:40 PM PDT 24
Finished Jun 10 06:41:49 PM PDT 24
Peak memory 255908 kb
Host smart-cfeda8c5-b384-462f-abaf-5b61424a8dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26828
51284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2682851284
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1768245082
Short name T241
Test name
Test status
Simulation time 125528758 ps
CPU time 9.24 seconds
Started Jun 10 06:40:29 PM PDT 24
Finished Jun 10 06:40:38 PM PDT 24
Peak memory 248736 kb
Host smart-c6915cc1-4f53-44e2-9975-8bb69d8e1c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17682
45082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1768245082
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3310089210
Short name T79
Test name
Test status
Simulation time 18422861236 ps
CPU time 1560.83 seconds
Started Jun 10 06:40:37 PM PDT 24
Finished Jun 10 07:06:38 PM PDT 24
Peak memory 289756 kb
Host smart-009d104f-9ede-45c0-ae64-b5cdacefea13
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310089210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3310089210
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3317807140
Short name T544
Test name
Test status
Simulation time 35327000623 ps
CPU time 3563.53 seconds
Started Jun 10 06:40:37 PM PDT 24
Finished Jun 10 07:40:02 PM PDT 24
Peak memory 322720 kb
Host smart-0ba78bcd-c77d-47c3-87ba-8b7b0657cc42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317807140 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3317807140
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2261170879
Short name T516
Test name
Test status
Simulation time 10990814674 ps
CPU time 658.19 seconds
Started Jun 10 06:40:41 PM PDT 24
Finished Jun 10 06:51:40 PM PDT 24
Peak memory 266292 kb
Host smart-d25d5477-62a8-4219-aa25-3f439b75d560
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261170879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2261170879
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1411335760
Short name T460
Test name
Test status
Simulation time 3199637113 ps
CPU time 76.35 seconds
Started Jun 10 06:40:43 PM PDT 24
Finished Jun 10 06:42:00 PM PDT 24
Peak memory 256896 kb
Host smart-8bf69314-593a-4f11-9d80-c5078d5c1024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14113
35760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1411335760
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.797960693
Short name T514
Test name
Test status
Simulation time 183367553 ps
CPU time 22.74 seconds
Started Jun 10 06:40:36 PM PDT 24
Finished Jun 10 06:41:00 PM PDT 24
Peak memory 255084 kb
Host smart-d2b83fae-8ae9-432f-896d-7e31beb48fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79796
0693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.797960693
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.150371249
Short name T332
Test name
Test status
Simulation time 49783341637 ps
CPU time 1067.39 seconds
Started Jun 10 06:40:45 PM PDT 24
Finished Jun 10 06:58:33 PM PDT 24
Peak memory 289052 kb
Host smart-6fe0163e-9527-4bc2-898c-14a30642272a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150371249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.150371249
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1555156218
Short name T389
Test name
Test status
Simulation time 17549943396 ps
CPU time 1616.53 seconds
Started Jun 10 06:40:46 PM PDT 24
Finished Jun 10 07:07:43 PM PDT 24
Peak memory 289672 kb
Host smart-010fcae3-06b7-4006-bf68-0fc76bb63756
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555156218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1555156218
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1428651949
Short name T306
Test name
Test status
Simulation time 83256146227 ps
CPU time 373.39 seconds
Started Jun 10 06:40:44 PM PDT 24
Finished Jun 10 06:46:58 PM PDT 24
Peak memory 248440 kb
Host smart-82581f3c-1f98-46ff-9ed5-f62551b7e62b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428651949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1428651949
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.4208617866
Short name T434
Test name
Test status
Simulation time 506781588 ps
CPU time 14.67 seconds
Started Jun 10 06:40:37 PM PDT 24
Finished Jun 10 06:40:52 PM PDT 24
Peak memory 254980 kb
Host smart-694730fb-7177-42b1-b663-a2ddff011e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42086
17866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.4208617866
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2131950698
Short name T106
Test name
Test status
Simulation time 2476020701 ps
CPU time 80.67 seconds
Started Jun 10 06:40:37 PM PDT 24
Finished Jun 10 06:41:58 PM PDT 24
Peak memory 256872 kb
Host smart-d39aabec-cc93-4c01-b9c7-722b1818d04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21319
50698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2131950698
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3415760512
Short name T48
Test name
Test status
Simulation time 734821688 ps
CPU time 14 seconds
Started Jun 10 06:40:41 PM PDT 24
Finished Jun 10 06:40:56 PM PDT 24
Peak memory 247200 kb
Host smart-5a283ed2-36f2-4420-9c57-ed6a28e6a20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34157
60512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3415760512
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.201503126
Short name T356
Test name
Test status
Simulation time 4273161223 ps
CPU time 42.38 seconds
Started Jun 10 06:40:37 PM PDT 24
Finished Jun 10 06:41:20 PM PDT 24
Peak memory 256992 kb
Host smart-5adc137a-d90a-4661-862a-f5b2e85f9045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20150
3126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.201503126
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3371784034
Short name T252
Test name
Test status
Simulation time 70634430359 ps
CPU time 3963.91 seconds
Started Jun 10 06:40:44 PM PDT 24
Finished Jun 10 07:46:49 PM PDT 24
Peak memory 297868 kb
Host smart-ad3f0a13-10d9-4752-94ac-99b805d75343
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371784034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3371784034
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1624632651
Short name T691
Test name
Test status
Simulation time 25755039699 ps
CPU time 1629.04 seconds
Started Jun 10 06:40:53 PM PDT 24
Finished Jun 10 07:08:03 PM PDT 24
Peak memory 273344 kb
Host smart-a7643fb6-cba1-4d95-91fd-f6e9d7c965cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624632651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1624632651
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.414641862
Short name T695
Test name
Test status
Simulation time 6477677011 ps
CPU time 170.81 seconds
Started Jun 10 06:40:54 PM PDT 24
Finished Jun 10 06:43:45 PM PDT 24
Peak memory 250432 kb
Host smart-129d4cc8-2fac-49de-bf83-16cee7953a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41464
1862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.414641862
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2908511636
Short name T570
Test name
Test status
Simulation time 184750424 ps
CPU time 14.03 seconds
Started Jun 10 06:40:47 PM PDT 24
Finished Jun 10 06:41:01 PM PDT 24
Peak memory 248832 kb
Host smart-14a46bf6-5bdf-44d7-a081-ec7fd7fd3c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29085
11636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2908511636
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1997681184
Short name T341
Test name
Test status
Simulation time 57990001281 ps
CPU time 3055.64 seconds
Started Jun 10 06:40:58 PM PDT 24
Finished Jun 10 07:31:54 PM PDT 24
Peak memory 288304 kb
Host smart-f579d83a-9507-4bd7-911d-47649650495c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997681184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1997681184
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.797861476
Short name T221
Test name
Test status
Simulation time 28746323405 ps
CPU time 1582.73 seconds
Started Jun 10 06:40:57 PM PDT 24
Finished Jun 10 07:07:20 PM PDT 24
Peak memory 267084 kb
Host smart-c96e4f6d-edb4-4ad4-830b-7905712481ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797861476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.797861476
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3152939831
Short name T548
Test name
Test status
Simulation time 14875965733 ps
CPU time 556.59 seconds
Started Jun 10 06:40:56 PM PDT 24
Finished Jun 10 06:50:13 PM PDT 24
Peak memory 248396 kb
Host smart-fd997c4e-0443-4e7c-9059-3bb5606a1e1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152939831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3152939831
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.544303452
Short name T365
Test name
Test status
Simulation time 146945675 ps
CPU time 9.96 seconds
Started Jun 10 06:40:45 PM PDT 24
Finished Jun 10 06:40:56 PM PDT 24
Peak memory 240564 kb
Host smart-a6289b03-661e-4abb-ae16-de2ba6d6c675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54430
3452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.544303452
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1187122468
Short name T53
Test name
Test status
Simulation time 1119688281 ps
CPU time 24.62 seconds
Started Jun 10 06:40:49 PM PDT 24
Finished Jun 10 06:41:14 PM PDT 24
Peak memory 248416 kb
Host smart-116950e6-0ea9-460e-bd89-bdf602f7213f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11871
22468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1187122468
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.223871184
Short name T292
Test name
Test status
Simulation time 7079845923 ps
CPU time 53.48 seconds
Started Jun 10 06:40:54 PM PDT 24
Finished Jun 10 06:41:48 PM PDT 24
Peak memory 248920 kb
Host smart-dd7845d6-8e9f-4b0b-9bba-a25c352a073b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22387
1184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.223871184
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3113782140
Short name T80
Test name
Test status
Simulation time 4359958225 ps
CPU time 62.64 seconds
Started Jun 10 06:40:44 PM PDT 24
Finished Jun 10 06:41:47 PM PDT 24
Peak memory 248752 kb
Host smart-9e14e111-70e8-42d8-a8fa-de598cb75104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31137
82140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3113782140
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3552301312
Short name T286
Test name
Test status
Simulation time 62657341982 ps
CPU time 1214.86 seconds
Started Jun 10 06:40:58 PM PDT 24
Finished Jun 10 07:01:13 PM PDT 24
Peak memory 285528 kb
Host smart-a59082e8-fe45-4961-90e0-a3732da7ab9b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552301312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3552301312
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.508703439
Short name T63
Test name
Test status
Simulation time 116616805740 ps
CPU time 1842.91 seconds
Started Jun 10 06:41:03 PM PDT 24
Finished Jun 10 07:11:47 PM PDT 24
Peak memory 288948 kb
Host smart-79fd784a-48e8-4237-807d-cceab968f86c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508703439 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.508703439
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2935886500
Short name T590
Test name
Test status
Simulation time 50323958252 ps
CPU time 1295.78 seconds
Started Jun 10 06:41:03 PM PDT 24
Finished Jun 10 07:02:40 PM PDT 24
Peak memory 289196 kb
Host smart-73b93bb0-4005-451f-8d84-3b769e31af89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935886500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2935886500
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.539324560
Short name T459
Test name
Test status
Simulation time 2403415219 ps
CPU time 74.01 seconds
Started Jun 10 06:41:01 PM PDT 24
Finished Jun 10 06:42:15 PM PDT 24
Peak memory 256728 kb
Host smart-971c84d8-11fa-4256-be33-7f7e4be9113f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53932
4560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.539324560
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2176532951
Short name T405
Test name
Test status
Simulation time 1662148789 ps
CPU time 39.32 seconds
Started Jun 10 06:40:58 PM PDT 24
Finished Jun 10 06:41:37 PM PDT 24
Peak memory 248680 kb
Host smart-0485dc96-d747-41ce-9502-790dec8e64d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21765
32951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2176532951
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2762261497
Short name T342
Test name
Test status
Simulation time 10445183918 ps
CPU time 1049.02 seconds
Started Jun 10 06:41:02 PM PDT 24
Finished Jun 10 06:58:31 PM PDT 24
Peak memory 282404 kb
Host smart-b11efe54-bb08-435d-9eaf-d747eb7d9759
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762261497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2762261497
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.4086355851
Short name T593
Test name
Test status
Simulation time 39374755921 ps
CPU time 2305.16 seconds
Started Jun 10 06:41:05 PM PDT 24
Finished Jun 10 07:19:30 PM PDT 24
Peak memory 289084 kb
Host smart-dd17f201-d56c-4e13-bf29-bd6420119eb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086355851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.4086355851
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2125062376
Short name T699
Test name
Test status
Simulation time 18891486169 ps
CPU time 401.13 seconds
Started Jun 10 06:41:00 PM PDT 24
Finished Jun 10 06:47:41 PM PDT 24
Peak memory 248820 kb
Host smart-cbba5647-fb7a-4a96-bec5-6d93745be4cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125062376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2125062376
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2668270577
Short name T451
Test name
Test status
Simulation time 114144029 ps
CPU time 7.75 seconds
Started Jun 10 06:41:03 PM PDT 24
Finished Jun 10 06:41:11 PM PDT 24
Peak memory 248764 kb
Host smart-296968a8-cd57-4f42-8ef5-dd7ffefb13d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26682
70577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2668270577
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2547922088
Short name T422
Test name
Test status
Simulation time 203500419 ps
CPU time 21.05 seconds
Started Jun 10 06:40:58 PM PDT 24
Finished Jun 10 06:41:19 PM PDT 24
Peak memory 254956 kb
Host smart-1a263ff1-d949-48a0-a107-5cf0bc1cc5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25479
22088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2547922088
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3087174894
Short name T408
Test name
Test status
Simulation time 455055720 ps
CPU time 37.37 seconds
Started Jun 10 06:41:03 PM PDT 24
Finished Jun 10 06:41:41 PM PDT 24
Peak memory 256200 kb
Host smart-67b813c8-6b00-4457-8552-e2fccae26916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30871
74894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3087174894
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3830238785
Short name T360
Test name
Test status
Simulation time 807634260 ps
CPU time 55.6 seconds
Started Jun 10 06:40:59 PM PDT 24
Finished Jun 10 06:41:55 PM PDT 24
Peak memory 248792 kb
Host smart-a8281e52-4974-43b2-8206-0afdc967c9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38302
38785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3830238785
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3463854855
Short name T472
Test name
Test status
Simulation time 7080051256 ps
CPU time 319.62 seconds
Started Jun 10 06:41:05 PM PDT 24
Finished Jun 10 06:46:24 PM PDT 24
Peak memory 256924 kb
Host smart-c39b8bcc-9371-4947-bff0-264509345aa9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463854855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3463854855
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.581323024
Short name T67
Test name
Test status
Simulation time 123243874433 ps
CPU time 3323.18 seconds
Started Jun 10 06:41:18 PM PDT 24
Finished Jun 10 07:36:42 PM PDT 24
Peak memory 289000 kb
Host smart-16ffeebc-0086-4810-b878-9d0e3a770eeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581323024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.581323024
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2103821058
Short name T469
Test name
Test status
Simulation time 2625368092 ps
CPU time 178.24 seconds
Started Jun 10 06:41:12 PM PDT 24
Finished Jun 10 06:44:11 PM PDT 24
Peak memory 249048 kb
Host smart-d91f65fe-82e8-4ef5-8902-35048945bbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21038
21058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2103821058
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.4095214858
Short name T634
Test name
Test status
Simulation time 4329645286 ps
CPU time 36.6 seconds
Started Jun 10 06:41:08 PM PDT 24
Finished Jun 10 06:41:45 PM PDT 24
Peak memory 255160 kb
Host smart-08549713-62cd-4d7f-9d5b-46e45f32c3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40952
14858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.4095214858
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1299921090
Short name T640
Test name
Test status
Simulation time 22902588152 ps
CPU time 1540.6 seconds
Started Jun 10 06:41:20 PM PDT 24
Finished Jun 10 07:07:01 PM PDT 24
Peak memory 273448 kb
Host smart-a86fc118-fd69-4a5e-b6a3-48db271eb55b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299921090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1299921090
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1255175689
Short name T310
Test name
Test status
Simulation time 18338472811 ps
CPU time 401.2 seconds
Started Jun 10 06:41:13 PM PDT 24
Finished Jun 10 06:47:54 PM PDT 24
Peak memory 248168 kb
Host smart-5c72e57e-83d2-4c21-a907-c8ea6a5ffa23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255175689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1255175689
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3221833025
Short name T444
Test name
Test status
Simulation time 1293886880 ps
CPU time 18.5 seconds
Started Jun 10 06:41:09 PM PDT 24
Finished Jun 10 06:41:28 PM PDT 24
Peak memory 254124 kb
Host smart-6fa2f740-8782-43d6-98d8-de539f50e5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32218
33025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3221833025
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.4072128103
Short name T685
Test name
Test status
Simulation time 37410477 ps
CPU time 5.9 seconds
Started Jun 10 06:41:10 PM PDT 24
Finished Jun 10 06:41:16 PM PDT 24
Peak memory 251752 kb
Host smart-4e8d7f0f-4bd7-4b4a-a9ed-ec99ad7aa28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40721
28103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.4072128103
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1760955
Short name T270
Test name
Test status
Simulation time 131467665 ps
CPU time 5.65 seconds
Started Jun 10 06:41:12 PM PDT 24
Finished Jun 10 06:41:18 PM PDT 24
Peak memory 239124 kb
Host smart-9de91e93-1e97-43eb-9e15-3e8405a3349b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17609
55 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1760955
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.4080346394
Short name T454
Test name
Test status
Simulation time 239068002 ps
CPU time 20.71 seconds
Started Jun 10 06:41:09 PM PDT 24
Finished Jun 10 06:41:30 PM PDT 24
Peak memory 248720 kb
Host smart-cd9e08ae-546c-4a32-a1e8-58f2aa852356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40803
46394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4080346394
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2595104331
Short name T524
Test name
Test status
Simulation time 62865233579 ps
CPU time 1497.36 seconds
Started Jun 10 06:41:13 PM PDT 24
Finished Jun 10 07:06:11 PM PDT 24
Peak memory 288668 kb
Host smart-d4835938-a52d-4cbe-80a8-aed787640d2d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595104331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2595104331
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1496729441
Short name T392
Test name
Test status
Simulation time 61781034206 ps
CPU time 2944.14 seconds
Started Jun 10 06:41:22 PM PDT 24
Finished Jun 10 07:30:27 PM PDT 24
Peak memory 287060 kb
Host smart-2bc00c94-9e82-43aa-b264-c9ca3986212e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496729441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1496729441
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2416237490
Short name T21
Test name
Test status
Simulation time 3643727410 ps
CPU time 142.81 seconds
Started Jun 10 06:41:22 PM PDT 24
Finished Jun 10 06:43:45 PM PDT 24
Peak memory 256940 kb
Host smart-ce0b0c3b-fa13-4331-98be-d5fc373e4f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24162
37490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2416237490
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1540322337
Short name T81
Test name
Test status
Simulation time 630779816 ps
CPU time 37.15 seconds
Started Jun 10 06:41:21 PM PDT 24
Finished Jun 10 06:41:58 PM PDT 24
Peak memory 248872 kb
Host smart-58f2de95-ef27-46c5-a623-0e5fedd9927d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15403
22337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1540322337
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2492974728
Short name T180
Test name
Test status
Simulation time 43494053518 ps
CPU time 1685.28 seconds
Started Jun 10 06:41:25 PM PDT 24
Finished Jun 10 07:09:31 PM PDT 24
Peak memory 281608 kb
Host smart-bcfd4a49-970f-464d-a118-b8f8f1f9e9c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492974728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2492974728
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2257669035
Short name T4
Test name
Test status
Simulation time 22021690734 ps
CPU time 1084.97 seconds
Started Jun 10 06:41:25 PM PDT 24
Finished Jun 10 06:59:30 PM PDT 24
Peak memory 270344 kb
Host smart-63ce1869-61d9-4089-87f5-9e731cf88a16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257669035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2257669035
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1681770142
Short name T646
Test name
Test status
Simulation time 9290142623 ps
CPU time 100.87 seconds
Started Jun 10 06:41:21 PM PDT 24
Finished Jun 10 06:43:03 PM PDT 24
Peak memory 247300 kb
Host smart-60fd75be-4c0a-4e40-949d-5b2c00d2105c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681770142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1681770142
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.272486723
Short name T424
Test name
Test status
Simulation time 4677415351 ps
CPU time 53 seconds
Started Jun 10 06:41:16 PM PDT 24
Finished Jun 10 06:42:09 PM PDT 24
Peak memory 256252 kb
Host smart-bd38434d-1bac-4a2f-883d-17db795d9044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27248
6723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.272486723
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2903331231
Short name T363
Test name
Test status
Simulation time 184486753 ps
CPU time 4.23 seconds
Started Jun 10 06:41:21 PM PDT 24
Finished Jun 10 06:41:26 PM PDT 24
Peak memory 239404 kb
Host smart-cbc66223-0255-4bc1-9e31-41c7eca0495e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29033
31231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2903331231
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2496224254
Short name T271
Test name
Test status
Simulation time 1170698215 ps
CPU time 41.35 seconds
Started Jun 10 06:41:20 PM PDT 24
Finished Jun 10 06:42:02 PM PDT 24
Peak memory 248592 kb
Host smart-1bf8d7fa-8b76-4dac-be9e-a82e0af939d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24962
24254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2496224254
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.158147306
Short name T358
Test name
Test status
Simulation time 900529879 ps
CPU time 17.07 seconds
Started Jun 10 06:41:19 PM PDT 24
Finished Jun 10 06:41:36 PM PDT 24
Peak memory 255176 kb
Host smart-723ad6ad-a5b8-4fb7-9ead-007faec6b1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15814
7306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.158147306
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3129900297
Short name T605
Test name
Test status
Simulation time 148852758599 ps
CPU time 2782.4 seconds
Started Jun 10 06:41:23 PM PDT 24
Finished Jun 10 07:27:46 PM PDT 24
Peak memory 289156 kb
Host smart-083639f2-d56c-4175-8d09-ee9962569440
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129900297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3129900297
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1382895202
Short name T103
Test name
Test status
Simulation time 16490254992 ps
CPU time 1999.15 seconds
Started Jun 10 06:41:25 PM PDT 24
Finished Jun 10 07:14:45 PM PDT 24
Peak memory 289376 kb
Host smart-e44e06ab-499f-4027-ab9c-53b529e959af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382895202 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1382895202
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2315200379
Short name T206
Test name
Test status
Simulation time 914074909 ps
CPU time 4.27 seconds
Started Jun 10 06:36:52 PM PDT 24
Finished Jun 10 06:36:57 PM PDT 24
Peak memory 248776 kb
Host smart-cb9aa4a2-902b-4bd4-86f1-26a50b23674b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2315200379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2315200379
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2200388265
Short name T226
Test name
Test status
Simulation time 511911591 ps
CPU time 7.74 seconds
Started Jun 10 06:36:56 PM PDT 24
Finished Jun 10 06:37:05 PM PDT 24
Peak memory 248652 kb
Host smart-858a1db5-4539-429b-92d5-ef5c80e19c04
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2200388265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2200388265
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.834837695
Short name T506
Test name
Test status
Simulation time 4996954437 ps
CPU time 269.44 seconds
Started Jun 10 06:36:50 PM PDT 24
Finished Jun 10 06:41:20 PM PDT 24
Peak memory 256924 kb
Host smart-c6eb8746-e7bc-453a-af5f-698d1887b34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83483
7695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.834837695
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3532141718
Short name T569
Test name
Test status
Simulation time 2345129885 ps
CPU time 15.09 seconds
Started Jun 10 06:36:52 PM PDT 24
Finished Jun 10 06:37:08 PM PDT 24
Peak memory 254060 kb
Host smart-5611f11a-39d9-47bf-8177-2a114cf8528d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35321
41718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3532141718
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2861454139
Short name T329
Test name
Test status
Simulation time 24945712378 ps
CPU time 715.11 seconds
Started Jun 10 06:36:52 PM PDT 24
Finished Jun 10 06:48:47 PM PDT 24
Peak memory 271984 kb
Host smart-97600815-a59c-49da-be4e-4707b746e048
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861454139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2861454139
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.608990122
Short name T414
Test name
Test status
Simulation time 32872494565 ps
CPU time 1549.3 seconds
Started Jun 10 06:36:51 PM PDT 24
Finished Jun 10 07:02:41 PM PDT 24
Peak memory 289460 kb
Host smart-93a66e12-2e1c-45d1-8727-6ce42073c274
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608990122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.608990122
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3571385115
Short name T11
Test name
Test status
Simulation time 6716746886 ps
CPU time 245.85 seconds
Started Jun 10 06:36:50 PM PDT 24
Finished Jun 10 06:40:57 PM PDT 24
Peak memory 248352 kb
Host smart-6197db34-3ff6-4dde-b000-a4edb2f02c3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571385115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3571385115
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3909950795
Short name T702
Test name
Test status
Simulation time 992988548 ps
CPU time 54.72 seconds
Started Jun 10 06:36:50 PM PDT 24
Finished Jun 10 06:37:46 PM PDT 24
Peak memory 256196 kb
Host smart-2004c90d-9ae3-46ef-b3fb-9c1323e7a93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39099
50795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3909950795
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2112788112
Short name T690
Test name
Test status
Simulation time 842434503 ps
CPU time 33.68 seconds
Started Jun 10 06:36:48 PM PDT 24
Finished Jun 10 06:37:22 PM PDT 24
Peak memory 255936 kb
Host smart-7665be95-16ef-4ee2-ab40-e09160613f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21127
88112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2112788112
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2866347074
Short name T561
Test name
Test status
Simulation time 1322689119 ps
CPU time 46.44 seconds
Started Jun 10 06:36:52 PM PDT 24
Finished Jun 10 06:37:39 PM PDT 24
Peak memory 248708 kb
Host smart-63a76980-676c-4725-9524-acb3bce3f3b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28663
47074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2866347074
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2138130721
Short name T82
Test name
Test status
Simulation time 352457342 ps
CPU time 11.86 seconds
Started Jun 10 06:36:51 PM PDT 24
Finished Jun 10 06:37:03 PM PDT 24
Peak memory 256828 kb
Host smart-1ea9d767-39a0-496d-8165-740ac953ee9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21381
30721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2138130721
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3758818858
Short name T66
Test name
Test status
Simulation time 122958349034 ps
CPU time 1906.88 seconds
Started Jun 10 06:36:51 PM PDT 24
Finished Jun 10 07:08:39 PM PDT 24
Peak memory 302112 kb
Host smart-7723fa80-d8f6-4f83-aae9-4cb35385cb06
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758818858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3758818858
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.4095730356
Short name T202
Test name
Test status
Simulation time 27014951 ps
CPU time 2.56 seconds
Started Jun 10 06:36:58 PM PDT 24
Finished Jun 10 06:37:01 PM PDT 24
Peak memory 248872 kb
Host smart-8615a4d8-2bea-4201-86b3-9d7f45f3cf12
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4095730356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.4095730356
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2899207900
Short name T233
Test name
Test status
Simulation time 1215077167 ps
CPU time 51.79 seconds
Started Jun 10 06:36:55 PM PDT 24
Finished Jun 10 06:37:47 PM PDT 24
Peak memory 248604 kb
Host smart-8be24f23-458d-49b4-848c-e32c09ffc30c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2899207900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2899207900
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.172181976
Short name T497
Test name
Test status
Simulation time 720729260 ps
CPU time 38.09 seconds
Started Jun 10 06:36:52 PM PDT 24
Finished Jun 10 06:37:31 PM PDT 24
Peak memory 255732 kb
Host smart-65bb52ae-d79b-4c12-b31e-74adbe6f136c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17218
1976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.172181976
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.4193159312
Short name T443
Test name
Test status
Simulation time 513304946 ps
CPU time 37.99 seconds
Started Jun 10 06:36:51 PM PDT 24
Finished Jun 10 06:37:29 PM PDT 24
Peak memory 255080 kb
Host smart-b3a33331-84fc-4e96-933d-b174cd54b535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41931
59312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.4193159312
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1481568912
Short name T513
Test name
Test status
Simulation time 41165956258 ps
CPU time 1087.7 seconds
Started Jun 10 06:36:57 PM PDT 24
Finished Jun 10 06:55:05 PM PDT 24
Peak memory 283284 kb
Host smart-4d2695c9-5d88-41a0-a285-f2f0d8965c03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481568912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1481568912
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.792728359
Short name T311
Test name
Test status
Simulation time 32004439575 ps
CPU time 353.1 seconds
Started Jun 10 06:36:56 PM PDT 24
Finished Jun 10 06:42:50 PM PDT 24
Peak memory 248324 kb
Host smart-26c5e0f6-6a62-4995-b93e-5887a5b79371
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792728359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.792728359
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.505577195
Short name T293
Test name
Test status
Simulation time 266956699 ps
CPU time 5.7 seconds
Started Jun 10 06:36:51 PM PDT 24
Finished Jun 10 06:36:57 PM PDT 24
Peak memory 240564 kb
Host smart-249a01b8-36a2-4acb-85a8-3a4528cb7878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50557
7195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.505577195
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1647620748
Short name T555
Test name
Test status
Simulation time 1815142013 ps
CPU time 33.32 seconds
Started Jun 10 06:36:51 PM PDT 24
Finished Jun 10 06:37:25 PM PDT 24
Peak memory 256328 kb
Host smart-9310537b-d9a5-4189-846b-2069a9693e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16476
20748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1647620748
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2501304489
Short name T260
Test name
Test status
Simulation time 3788051517 ps
CPU time 30.86 seconds
Started Jun 10 06:36:57 PM PDT 24
Finished Jun 10 06:37:28 PM PDT 24
Peak memory 255140 kb
Host smart-de818394-046b-4049-a6e7-9cc28672531d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25013
04489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2501304489
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.39665296
Short name T225
Test name
Test status
Simulation time 33072102 ps
CPU time 2.63 seconds
Started Jun 10 06:36:52 PM PDT 24
Finished Jun 10 06:36:55 PM PDT 24
Peak memory 240544 kb
Host smart-033e5817-2524-4aad-9fd8-71e78e9481e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39665
296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.39665296
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1650069668
Short name T639
Test name
Test status
Simulation time 1934878588 ps
CPU time 128.68 seconds
Started Jun 10 06:36:57 PM PDT 24
Finished Jun 10 06:39:06 PM PDT 24
Peak memory 255620 kb
Host smart-3dc8ae9d-e144-4c52-834f-bd74fc0a19ab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650069668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1650069668
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3198659799
Short name T477
Test name
Test status
Simulation time 19768001170 ps
CPU time 1157.91 seconds
Started Jun 10 06:36:54 PM PDT 24
Finished Jun 10 06:56:12 PM PDT 24
Peak memory 273120 kb
Host smart-b22a934e-c0d2-467e-af7f-00e8b70802e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198659799 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3198659799
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3489892689
Short name T20
Test name
Test status
Simulation time 155493534 ps
CPU time 3.31 seconds
Started Jun 10 06:37:07 PM PDT 24
Finished Jun 10 06:37:10 PM PDT 24
Peak memory 248932 kb
Host smart-de970945-4a27-4eed-b418-179364555b2c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3489892689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3489892689
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.364949924
Short name T509
Test name
Test status
Simulation time 38388137046 ps
CPU time 1006.38 seconds
Started Jun 10 06:37:01 PM PDT 24
Finished Jun 10 06:53:48 PM PDT 24
Peak memory 273284 kb
Host smart-e420e837-80ee-4d2e-9c47-b7e21bc49da1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364949924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.364949924
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2714130985
Short name T448
Test name
Test status
Simulation time 731304007 ps
CPU time 25.13 seconds
Started Jun 10 06:36:59 PM PDT 24
Finished Jun 10 06:37:24 PM PDT 24
Peak memory 248676 kb
Host smart-c8eba8d5-ca4a-491d-9171-80fbe927170f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2714130985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2714130985
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2720589763
Short name T615
Test name
Test status
Simulation time 3916324672 ps
CPU time 258.39 seconds
Started Jun 10 06:37:00 PM PDT 24
Finished Jun 10 06:41:19 PM PDT 24
Peak memory 257004 kb
Host smart-0489118f-5bd0-4afc-b039-66d27dd5ba8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27205
89763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2720589763
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.959954895
Short name T383
Test name
Test status
Simulation time 120680890 ps
CPU time 9.05 seconds
Started Jun 10 06:36:55 PM PDT 24
Finished Jun 10 06:37:05 PM PDT 24
Peak memory 251164 kb
Host smart-0c6ec598-a453-4fbf-94e1-a7bffceeadfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95995
4895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.959954895
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2633574927
Short name T243
Test name
Test status
Simulation time 200790117512 ps
CPU time 1535.76 seconds
Started Jun 10 06:36:59 PM PDT 24
Finished Jun 10 07:02:35 PM PDT 24
Peak memory 289200 kb
Host smart-7deaceda-8cf5-43ad-a52d-61f184b7529d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633574927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2633574927
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3776908170
Short name T465
Test name
Test status
Simulation time 28201886628 ps
CPU time 1238.27 seconds
Started Jun 10 06:37:00 PM PDT 24
Finished Jun 10 06:57:38 PM PDT 24
Peak memory 283164 kb
Host smart-4f62438d-a9d1-4e2a-a591-7e9852a5db45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776908170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3776908170
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.4258855491
Short name T316
Test name
Test status
Simulation time 5925352038 ps
CPU time 247.49 seconds
Started Jun 10 06:37:00 PM PDT 24
Finished Jun 10 06:41:08 PM PDT 24
Peak memory 247196 kb
Host smart-d0127140-2b88-4589-a20b-9899f6323a44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258855491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.4258855491
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.4108509922
Short name T658
Test name
Test status
Simulation time 1646453857 ps
CPU time 27.58 seconds
Started Jun 10 06:36:55 PM PDT 24
Finished Jun 10 06:37:23 PM PDT 24
Peak memory 255924 kb
Host smart-35e232b9-6c92-4823-9eed-84b2f763dc08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41085
09922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.4108509922
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.226683287
Short name T56
Test name
Test status
Simulation time 610508041 ps
CPU time 36.18 seconds
Started Jun 10 06:36:58 PM PDT 24
Finished Jun 10 06:37:34 PM PDT 24
Peak memory 254088 kb
Host smart-2ba3dbc7-1810-4c75-9939-f63c0e89ad46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22668
3287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.226683287
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3430637551
Short name T437
Test name
Test status
Simulation time 215439204 ps
CPU time 6.96 seconds
Started Jun 10 06:36:59 PM PDT 24
Finished Jun 10 06:37:07 PM PDT 24
Peak memory 239372 kb
Host smart-c11d5e59-45f3-4395-b1e2-b7f7c85cc68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34306
37551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3430637551
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.865894876
Short name T367
Test name
Test status
Simulation time 12813758271 ps
CPU time 49.8 seconds
Started Jun 10 06:36:55 PM PDT 24
Finished Jun 10 06:37:45 PM PDT 24
Peak memory 248784 kb
Host smart-869ac4dd-b048-4495-b15b-91c486e7c21f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86589
4876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.865894876
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2268059637
Short name T559
Test name
Test status
Simulation time 16868433725 ps
CPU time 1571.8 seconds
Started Jun 10 06:37:03 PM PDT 24
Finished Jun 10 07:03:15 PM PDT 24
Peak memory 289760 kb
Host smart-d193d326-9741-4439-8e46-ef67d2323f94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268059637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2268059637
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.667884054
Short name T102
Test name
Test status
Simulation time 42058656835 ps
CPU time 3684.2 seconds
Started Jun 10 06:37:01 PM PDT 24
Finished Jun 10 07:38:26 PM PDT 24
Peak memory 338840 kb
Host smart-6204ec42-1e97-4e5e-be59-b52b50722123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667884054 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.667884054
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3647857821
Short name T204
Test name
Test status
Simulation time 212027846 ps
CPU time 3.22 seconds
Started Jun 10 06:37:05 PM PDT 24
Finished Jun 10 06:37:08 PM PDT 24
Peak memory 248904 kb
Host smart-a33cbb55-ac78-4edb-9d3c-728841501a36
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3647857821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3647857821
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2512609296
Short name T235
Test name
Test status
Simulation time 14669608091 ps
CPU time 674.06 seconds
Started Jun 10 06:36:59 PM PDT 24
Finished Jun 10 06:48:14 PM PDT 24
Peak memory 272676 kb
Host smart-72ea3734-ac3e-4aad-9e11-2e62f2d8dd5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512609296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2512609296
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2914503940
Short name T195
Test name
Test status
Simulation time 2050133041 ps
CPU time 26.01 seconds
Started Jun 10 06:37:04 PM PDT 24
Finished Jun 10 06:37:30 PM PDT 24
Peak memory 248708 kb
Host smart-c182d9b8-a2db-4fa0-b431-18e839a30cb9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2914503940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2914503940
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.79814825
Short name T579
Test name
Test status
Simulation time 10030785614 ps
CPU time 133.76 seconds
Started Jun 10 06:36:59 PM PDT 24
Finished Jun 10 06:39:13 PM PDT 24
Peak memory 249924 kb
Host smart-532a69a3-15fd-4f03-80ec-19a892339cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79814
825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.79814825
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.325887697
Short name T370
Test name
Test status
Simulation time 923129099 ps
CPU time 20.01 seconds
Started Jun 10 06:36:59 PM PDT 24
Finished Jun 10 06:37:19 PM PDT 24
Peak memory 248892 kb
Host smart-17ec35dc-41f6-4b2e-b978-e85d9073acbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32588
7697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.325887697
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1080535737
Short name T333
Test name
Test status
Simulation time 29968752161 ps
CPU time 1898.1 seconds
Started Jun 10 06:37:06 PM PDT 24
Finished Jun 10 07:08:45 PM PDT 24
Peak memory 273108 kb
Host smart-f0455fed-24b0-45ea-b887-7d3f28058437
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080535737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1080535737
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2823244948
Short name T299
Test name
Test status
Simulation time 14121120643 ps
CPU time 1259.09 seconds
Started Jun 10 06:37:01 PM PDT 24
Finished Jun 10 06:58:00 PM PDT 24
Peak memory 281096 kb
Host smart-1f92471d-6195-4a64-8c80-dae578186b0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823244948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2823244948
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.782851405
Short name T323
Test name
Test status
Simulation time 26809412864 ps
CPU time 309.39 seconds
Started Jun 10 06:36:59 PM PDT 24
Finished Jun 10 06:42:08 PM PDT 24
Peak memory 248200 kb
Host smart-c47917e2-cb77-4070-bcf9-3528ce8ad539
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782851405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.782851405
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3001552590
Short name T355
Test name
Test status
Simulation time 170417635 ps
CPU time 18.25 seconds
Started Jun 10 06:37:07 PM PDT 24
Finished Jun 10 06:37:26 PM PDT 24
Peak memory 255272 kb
Host smart-3032f42e-f1fb-4e7f-a97c-195c18f86ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30015
52590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3001552590
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2395815397
Short name T289
Test name
Test status
Simulation time 2197034011 ps
CPU time 39.73 seconds
Started Jun 10 06:36:58 PM PDT 24
Finished Jun 10 06:37:38 PM PDT 24
Peak memory 256884 kb
Host smart-1514c78d-5fce-40e8-8bf3-9b79a8211a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23958
15397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2395815397
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3405875940
Short name T376
Test name
Test status
Simulation time 1035595173 ps
CPU time 17.38 seconds
Started Jun 10 06:36:59 PM PDT 24
Finished Jun 10 06:37:17 PM PDT 24
Peak memory 255996 kb
Host smart-d4969edd-1040-4cc0-b856-68ea7beabd2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34058
75940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3405875940
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2800583818
Short name T393
Test name
Test status
Simulation time 714955916 ps
CPU time 24.13 seconds
Started Jun 10 06:36:58 PM PDT 24
Finished Jun 10 06:37:23 PM PDT 24
Peak memory 255920 kb
Host smart-3a8e4dbe-b7ae-427c-947b-547ff97790e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28005
83818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2800583818
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3915800642
Short name T275
Test name
Test status
Simulation time 268248109462 ps
CPU time 3896.07 seconds
Started Jun 10 06:37:02 PM PDT 24
Finished Jun 10 07:41:59 PM PDT 24
Peak memory 303232 kb
Host smart-219f5917-8c4d-433f-a872-ddafc1b70c49
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915800642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3915800642
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.306873772
Short name T214
Test name
Test status
Simulation time 74985622 ps
CPU time 3.8 seconds
Started Jun 10 06:37:05 PM PDT 24
Finished Jun 10 06:37:09 PM PDT 24
Peak memory 248848 kb
Host smart-451c66ba-a39c-4ab1-8039-cd523d64ce3f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=306873772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.306873772
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.594843906
Short name T381
Test name
Test status
Simulation time 7042578437 ps
CPU time 994.41 seconds
Started Jun 10 06:37:05 PM PDT 24
Finished Jun 10 06:53:40 PM PDT 24
Peak memory 269556 kb
Host smart-79d91ae2-51d1-44dc-9f35-8aea0264d5fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594843906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.594843906
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2440055161
Short name T388
Test name
Test status
Simulation time 743480808 ps
CPU time 32.52 seconds
Started Jun 10 06:37:05 PM PDT 24
Finished Jun 10 06:37:38 PM PDT 24
Peak memory 248660 kb
Host smart-361fd2c7-a4e4-4743-a19a-989c145f3fca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2440055161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2440055161
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1981223553
Short name T411
Test name
Test status
Simulation time 2602241806 ps
CPU time 41.45 seconds
Started Jun 10 06:37:03 PM PDT 24
Finished Jun 10 06:37:44 PM PDT 24
Peak memory 249116 kb
Host smart-fb99f263-61b8-496b-a0f4-c0ff3cf67f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19812
23553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1981223553
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2740955792
Short name T665
Test name
Test status
Simulation time 3131119691 ps
CPU time 52.09 seconds
Started Jun 10 06:37:02 PM PDT 24
Finished Jun 10 06:37:55 PM PDT 24
Peak memory 255240 kb
Host smart-e23e8818-993f-48fe-a070-62c0200978b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27409
55792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2740955792
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.681987781
Short name T337
Test name
Test status
Simulation time 29302012597 ps
CPU time 1667.82 seconds
Started Jun 10 06:37:01 PM PDT 24
Finished Jun 10 07:04:49 PM PDT 24
Peak memory 273372 kb
Host smart-9fae62a6-3860-4245-b72b-b590baf4dffe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681987781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.681987781
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.478048903
Short name T511
Test name
Test status
Simulation time 77010389993 ps
CPU time 2386.52 seconds
Started Jun 10 06:37:05 PM PDT 24
Finished Jun 10 07:16:52 PM PDT 24
Peak memory 289232 kb
Host smart-5330b22c-c2bc-47af-b5ba-6e25a77ab459
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478048903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.478048903
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1655688213
Short name T673
Test name
Test status
Simulation time 19858611399 ps
CPU time 137.38 seconds
Started Jun 10 06:37:03 PM PDT 24
Finished Jun 10 06:39:21 PM PDT 24
Peak memory 248452 kb
Host smart-9d64431b-3c7e-44a4-9d55-66aecb044b5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655688213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1655688213
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3509612069
Short name T71
Test name
Test status
Simulation time 378233942 ps
CPU time 25.78 seconds
Started Jun 10 06:37:02 PM PDT 24
Finished Jun 10 06:37:28 PM PDT 24
Peak memory 254668 kb
Host smart-89c08d55-db40-4156-bab0-3e900b51798d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35096
12069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3509612069
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2088721183
Short name T608
Test name
Test status
Simulation time 890119702 ps
CPU time 38.58 seconds
Started Jun 10 06:37:02 PM PDT 24
Finished Jun 10 06:37:40 PM PDT 24
Peak memory 248852 kb
Host smart-50933fe4-befd-40e7-9614-98daabf5ce70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20887
21183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2088721183
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2871506411
Short name T585
Test name
Test status
Simulation time 416598031 ps
CPU time 25.85 seconds
Started Jun 10 06:37:06 PM PDT 24
Finished Jun 10 06:37:32 PM PDT 24
Peak memory 253840 kb
Host smart-aff0b428-b483-49fc-b1fb-a14d132b613b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28715
06411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2871506411
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.226074831
Short name T657
Test name
Test status
Simulation time 132010118 ps
CPU time 4.17 seconds
Started Jun 10 06:37:05 PM PDT 24
Finished Jun 10 06:37:09 PM PDT 24
Peak memory 256884 kb
Host smart-504300b1-8905-436e-8884-842b944ba35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22607
4831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.226074831
Directory /workspace/9.alert_handler_smoke/latest
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