Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	90188	1			T5	7		T15	37		T16	12
class_i[0x1]	62638	1			T2	51		T3	39		T6	13
class_i[0x2]	34066	1			T2	8		T6	379		T15	23
class_i[0x3]	49841	1			T6	163		T7	9		T15	4515

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	59147	1			T2	7		T3	12		T5	1
alert[0x1]	57092	1			T2	10		T3	4		T5	2
alert[0x2]	56048	1			T2	15		T3	13		T5	2
alert[0x3]	64446	1			T2	27		T3	10		T5	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

236464

1

T2

59

T3

27

T6

555

esc_ping_fail

269

1

T3

12

T5

7

T59

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	59074	1			T2	7		T3	9		T6	55
esc_integrity_fail	alert[0x1]	57020	1			T2	10		T3	2		T6	365
esc_integrity_fail	alert[0x2]	55982	1			T2	15		T3	9		T6	47
esc_integrity_fail	alert[0x3]	64388	1			T2	27		T3	7		T6	88
esc_ping_fail	alert[0x0]	73	1			T3	3		T5	1		T59	1
esc_ping_fail	alert[0x1]	72	1			T3	2		T5	2		T59	1
esc_ping_fail	alert[0x2]	66	1			T3	4		T5	2		T61	1
esc_ping_fail	alert[0x3]	58	1			T3	3		T5	2		T61	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	90127	1			T15	37		T16	12		T45	2004
esc_integrity_fail	class_i[0x1]	62536	1			T2	51		T3	27		T6	13
esc_integrity_fail	class_i[0x2]	33997	1			T2	8		T6	379		T15	23
esc_integrity_fail	class_i[0x3]	49804	1			T6	163		T7	9		T15	4515
esc_ping_fail	class_i[0x0]	61	1			T5	7		T61	2		T62	6
esc_ping_fail	class_i[0x1]	102	1			T3	12		T61	8		T64	1
esc_ping_fail	class_i[0x2]	69	1			T59	1		T76	2		T303	2
esc_ping_fail	class_i[0x3]	37	1			T59	1		T115	1		T76	1