Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	61	1			T16	1		T67	1		T27	1
class_index[0x1]	47	1			T6	1		T15	1		T80	1
class_index[0x2]	53	1			T6	1		T27	2		T39	1
class_index[0x3]	73	1			T6	2		T17	1		T16	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	78	1			T6	2		T16	1		T48	2
intr_timeout_cnt[1]	66	1			T15	1		T17	1		T16	1
intr_timeout_cnt[2]	21	1			T27	1		T29	2		T91	1
intr_timeout_cnt[3]	16	1			T27	1		T51	1		T86	1
intr_timeout_cnt[4]	16	1			T6	2		T39	1		T91	1
intr_timeout_cnt[5]	11	1			T50	1		T39	2		T55	1
intr_timeout_cnt[6]	10	1			T67	1		T100	1		T108	1
intr_timeout_cnt[7]	7	1			T83	1		T85	1		T277	1
intr_timeout_cnt[8]	6	1			T67	1		T48	1		T278	1
intr_timeout_cnt[9]	3	1			T279	1		T274	1		T280	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	22	1			T48	1		T51	1		T118	1
class_index[0x0]	intr_timeout_cnt[1]	12	1			T16	1		T100	1		T88	1
class_index[0x0]	intr_timeout_cnt[2]	3	1			T29	2		T281	1		-	-
class_index[0x0]	intr_timeout_cnt[3]	3	1			T27	1		T86	1		T282	1
class_index[0x0]	intr_timeout_cnt[4]	7	1			T283	1		T284	1		T265	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T39	2		T285	2		-	-
class_index[0x0]	intr_timeout_cnt[6]	4	1			T67	1		T272	1		T286	1
class_index[0x0]	intr_timeout_cnt[7]	4	1			T83	1		T85	1		T287	2
class_index[0x0]	intr_timeout_cnt[8]	2	1			T287	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	12	1			T6	1		T84	1		T51	1
class_index[0x1]	intr_timeout_cnt[1]	20	1			T15	1		T80	1		T37	2
class_index[0x1]	intr_timeout_cnt[2]	6	1			T54	1		T185	1		T56	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T287	1		T288	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	2	1			T91	1		T289	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T259	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T290	1		T95	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T277	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T274	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	18	1			T6	1		T29	1		T88	1
class_index[0x2]	intr_timeout_cnt[1]	15	1			T27	1		T117	1		T261	1
class_index[0x2]	intr_timeout_cnt[2]	6	1			T27	1		T91	1		T120	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T51	1		T87	1		T103	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T39	1		T291	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T292	1		T280	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	3	1			T108	1		T248	1		T293	1
class_index[0x2]	intr_timeout_cnt[8]	1	1			T277	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T279	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	26	1			T16	1		T48	1		T37	1
class_index[0x3]	intr_timeout_cnt[1]	19	1			T17	1		T63	7		T67	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T108	1		T285	2		T294	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T103	1		T108	2		T295	1
class_index[0x3]	intr_timeout_cnt[4]	5	1			T6	2		T284	1		T56	2
class_index[0x3]	intr_timeout_cnt[5]	4	1			T50	1		T55	1		T274	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T100	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T293	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	3	1			T67	1		T48	1		T278	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T280	1		-	-		-	-