Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	358034	1			T1	231		T2	1769		T3	57
all_values[1]	358034	1			T1	231		T2	1769		T3	57
all_values[2]	358034	1			T1	231		T2	1769		T3	57
all_values[3]	358034	1			T1	231		T2	1769		T3	57

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

712670

1

T1

447

T2

3491

T4

3167

auto[1]

719466

1

T1

477

T2

3585

T3

228

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

850574

1

T1

477

T2

3605

T3

199

auto[1]

581562

1

T1

447

T2

3471

T3

29

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	101986	1			T1	54		T2	450		T4	468
all_values[0]	auto[0]	auto[1]	76169	1			T1	57		T2	434		T4	284
all_values[0]	auto[1]	auto[0]	103291	1			T1	60		T2	451		T3	57
all_values[0]	auto[1]	auto[1]	76588	1			T1	60		T2	434		T4	321
all_values[1]	auto[0]	auto[0]	106342	1			T1	67		T2	453		T4	516
all_values[1]	auto[0]	auto[1]	71795	1			T1	51		T2	448		T4	319
all_values[1]	auto[1]	auto[0]	107629	1			T1	60		T2	434		T3	45
all_values[1]	auto[1]	auto[1]	72268	1			T1	53		T2	434		T3	12
all_values[2]	auto[0]	auto[0]	107837	1			T1	61		T2	444		T4	800
all_values[2]	auto[0]	auto[1]	70556	1			T1	61		T2	415		T4	1
all_values[2]	auto[1]	auto[0]	109236	1			T1	58		T2	469		T3	57
all_values[2]	auto[1]	auto[1]	70405	1			T1	51		T2	441		T4	1
all_values[3]	auto[0]	auto[0]	106238	1			T1	49		T2	432		T4	577
all_values[3]	auto[0]	auto[1]	71747	1			T1	47		T2	415		T4	202
all_values[3]	auto[1]	auto[0]	108015	1			T1	68		T2	472		T3	40
all_values[3]	auto[1]	auto[1]	72034	1			T1	67		T2	450		T3	17