Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	358034	1			T1	231		T2	1769		T3	57
all_pins[1]	358034	1			T1	231		T2	1769		T3	57
all_pins[2]	358034	1			T1	231		T2	1769		T3	57
all_pins[3]	358034	1			T1	231		T2	1769		T3	57

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1140841	1			T1	693		T2	5317		T3	199
values[0x1]	291295	1			T1	231		T2	1759		T3	29
transitions[0x0=>0x1]	193074	1			T1	148		T2	1084		T3	29
transitions[0x1=>0x0]	193330	1			T1	148		T2	1084		T3	29

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	281446	1			T1	171		T2	1335		T3	57
all_pins[0]	values[0x1]	76588	1			T1	60		T2	434		T4	321
all_pins[0]	transitions[0x0=>0x1]	75912	1			T1	57		T2	434		T4	320
all_pins[0]	transitions[0x1=>0x0]	71614	1			T1	64		T2	450		T3	17
all_pins[1]	values[0x0]	285766	1			T1	178		T2	1335		T3	45
all_pins[1]	values[0x1]	72268	1			T1	53		T2	434		T3	12
all_pins[1]	transitions[0x0=>0x1]	39449	1			T1	29		T2	212		T3	12
all_pins[1]	transitions[0x1=>0x0]	43769	1			T1	36		T2	212		T4	197
all_pins[2]	values[0x0]	287629	1			T1	180		T2	1328		T3	57
all_pins[2]	values[0x1]	70405	1			T1	51		T2	441		T4	1
all_pins[2]	transitions[0x0=>0x1]	38038	1			T1	23		T2	213		T4	1
all_pins[2]	transitions[0x1=>0x0]	39901	1			T1	25		T2	206		T3	12
all_pins[3]	values[0x0]	286000	1			T1	164		T2	1319		T3	40
all_pins[3]	values[0x1]	72034	1			T1	67		T2	450		T3	17
all_pins[3]	transitions[0x0=>0x1]	39675	1			T1	39		T2	225		T3	17
all_pins[3]	transitions[0x1=>0x0]	38046	1			T1	23		T2	216		T4	1