Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	257	1			T163	4		T164	4		T240	4
all_values[1]	257	1			T163	4		T164	4		T240	4
all_values[2]	257	1			T163	4		T164	4		T240	4
all_values[3]	257	1			T163	4		T164	4		T240	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

551

1

T163

8

T164

10

T240

11

auto[1]

477

1

T163

8

T164

6

T240

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

412

1

T163

7

T164

4

T240

1

auto[1]

616

1

T163

9

T164

12

T240

15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

611

1

T163

9

T164

9

T240

7

auto[1]

417

1

T163

7

T164

7

T240

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

62

1

T163

1

T240

1

T344

1

all_values[0]

auto[0]

auto[0]

auto[1]

24

1

T164

1

T240

1

T345

1

all_values[0]

auto[0]

auto[1]

auto[0]

56

1

T163

1

T164

1

T344

2

all_values[0]

auto[0]

auto[1]

auto[1]

20

1

T346

1

T347

2

T345

1

all_values[0]

auto[1]

auto[0]

auto[1]

54

1

T164

1

T240

2

T346

1

all_values[0]

auto[1]

auto[1]

auto[1]

41

1

T163

2

T164

1

T344

1

all_values[1]

auto[0]

auto[0]

auto[0]

58

1

T348

2

T346

2

T349

1

all_values[1]

auto[0]

auto[0]

auto[1]

25

1

T163

1

T240

1

T348

1

all_values[1]

auto[0]

auto[1]

auto[0]

42

1

T163

1

T344

3

T346

1

all_values[1]

auto[0]

auto[1]

auto[1]

24

1

T164

1

T240

1

T346

1

all_values[1]

auto[1]

auto[0]

auto[1]

53

1

T163

1

T164

1

T240

1

all_values[1]

auto[1]

auto[1]

auto[1]

55

1

T163

1

T164

2

T240

1

all_values[2]

auto[0]

auto[0]

auto[0]

67

1

T163

2

T164

1

T348

1

all_values[2]

auto[0]

auto[0]

auto[1]

21

1

T164

1

T240

1

T345

1

all_values[2]

auto[0]

auto[1]

auto[0]

43

1

T163

2

T164

1

T348

1

all_values[2]

auto[0]

auto[1]

auto[1]

28

1

T240

1

T344

2

T350

1

all_values[2]

auto[1]

auto[0]

auto[1]

59

1

T164

1

T240

2

T344

1

all_values[2]

auto[1]

auto[1]

auto[1]

39

1

T344

1

T348

2

T346

2

all_values[3]

auto[0]

auto[0]

auto[0]

44

1

T164

1

T351

2

T352

1

all_values[3]

auto[0]

auto[0]

auto[1]

25

1

T164

2

T240

1

T352

1

all_values[3]

auto[0]

auto[1]

auto[0]

40

1

T344

2

T346

1

T352

2

all_values[3]

auto[0]

auto[1]

auto[1]

32

1

T163

1

T348

1

T346

2

all_values[3]

auto[1]

auto[0]

auto[1]

59

1

T163

3

T164

1

T240

1

all_values[3]

auto[1]

auto[1]

auto[1]

57

1

T240

2

T344

1

T348

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal