Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	82606	1			T2	2331		T7	715		T24	536
accum_cnt_1000	218501	1			T1	26		T2	2313		T4	1025
accum_cnt_100	27074	1			T1	54		T2	137		T4	89
accum_cnt_50	76633	1			T1	126		T2	101		T3	3
accum_cnt_10	181076	1			T1	170		T2	31		T3	30
accum_cnt_0	432797	1			T1	236		T2	4		T3	151

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	264165	1			T1	153		T2	1337		T3	46
class_index[0x1]	264165	1			T1	153		T2	1337		T3	46
class_index[0x2]	264165	1			T1	153		T2	1337		T3	46
class_index[0x3]	264165	1			T1	153		T2	1337		T3	46

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23856	1			T2	665		T42	101		T16	115
class_index[0x0]	accum_cnt_1000	54871	1			T1	19		T2	593		T6	74
class_index[0x0]	accum_cnt_100	6566	1			T1	20		T2	35		T6	69
class_index[0x0]	accum_cnt_50	19146	1			T1	27		T2	33		T6	52
class_index[0x0]	accum_cnt_10	55706	1			T1	6		T2	6		T6	40
class_index[0x0]	accum_cnt_0	90721	1			T1	81		T3	46		T4	1204
class_index[0x1]	accum_cnt_2000	19833	1			T2	514		T7	149		T24	536
class_index[0x1]	accum_cnt_1000	56553	1			T2	440		T4	1025		T7	101
class_index[0x1]	accum_cnt_100	8610	1			T2	23		T4	89		T7	6
class_index[0x1]	accum_cnt_50	16122	1			T2	10		T4	68		T6	8
class_index[0x1]	accum_cnt_10	45037	1			T1	79		T2	9		T3	1
class_index[0x1]	accum_cnt_0	109120	1			T1	74		T3	45		T4	5
class_index[0x2]	accum_cnt_2000	18657	1			T2	516		T42	144		T25	631
class_index[0x2]	accum_cnt_1000	49778	1			T1	7		T2	736		T6	3
class_index[0x2]	accum_cnt_100	5797	1			T1	34		T2	46		T6	30
class_index[0x2]	accum_cnt_50	20014	1			T1	28		T2	33		T6	51
class_index[0x2]	accum_cnt_10	41290	1			T1	8		T2	6		T4	1191
class_index[0x2]	accum_cnt_0	118705	1			T1	76		T3	46		T4	13
class_index[0x3]	accum_cnt_2000	20260	1			T2	636		T7	566		T45	113
class_index[0x3]	accum_cnt_1000	57299	1			T2	544		T7	481		T15	136
class_index[0x3]	accum_cnt_100	6101	1			T2	33		T6	25		T7	30
class_index[0x3]	accum_cnt_50	21351	1			T1	71		T2	25		T3	3
class_index[0x3]	accum_cnt_10	39043	1			T1	77		T2	10		T3	29
class_index[0x3]	accum_cnt_0	114251	1			T1	5		T2	4		T3	14