Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4539	1			T5	1		T6	36		T62	1
alert[0x1]	8674	1			T3	1		T25	14		T46	28
alert[0x2]	4167	1			T5	1		T7	489		T16	21
alert[0x3]	2721	1			T1	9		T3	1		T7	96
alert[0x4]	4100	1			T15	41		T17	216		T26	6
alert[0x5]	4356	1			T15	323		T16	51		T44	1
alert[0x6]	13123	1			T3	1		T15	94		T17	7
alert[0x7]	5909	1			T3	1		T15	17		T17	195
alert[0x8]	3599	1			T6	1		T7	25		T16	11
alert[0x9]	9261	1			T3	1		T7	99		T15	210
alert[0xa]	2226	1			T6	5		T15	36		T16	40
alert[0xb]	5493	1			T6	2		T15	332		T16	242
alert[0xc]	11543	1			T6	207		T15	508		T16	129
alert[0xd]	7681	1			T5	1		T61	1		T48	215
alert[0xe]	12919	1			T7	34		T16	1753		T61	2
alert[0xf]	5263	1			T6	2		T7	99		T15	227
alert[0x10]	5016	1			T6	7		T7	67		T16	50
alert[0x11]	4451	1			T1	1		T5	1		T15	40
alert[0x12]	6311	1			T6	8		T16	20		T115	1
alert[0x13]	5131	1			T3	1		T16	1032		T25	1
alert[0x14]	3436	1			T7	64		T17	3		T16	272
alert[0x15]	8669	1			T7	80		T15	12		T45	29
alert[0x16]	7385	1			T6	8		T17	71		T238	3
alert[0x17]	10287	1			T7	202		T15	96		T25	1
alert[0x18]	10036	1			T1	2		T7	300		T15	301
alert[0x19]	17495	1			T6	5		T7	300		T15	132
alert[0x1a]	5752	1			T6	3		T17	1		T45	22
alert[0x1b]	2222	1			T16	6		T45	6		T46	74
alert[0x1c]	13127	1			T7	266		T16	1080		T73	19
alert[0x1d]	12721	1			T7	125		T16	87		T45	65
alert[0x1e]	15394	1			T6	1		T15	59		T16	1418
alert[0x1f]	9016	1			T5	1		T15	87		T238	1
alert[0x20]	6425	1			T1	1		T3	1		T6	1
alert[0x21]	3996	1			T5	1		T15	46		T16	61
alert[0x22]	9288	1			T3	1		T4	2		T6	3
alert[0x23]	12242	1			T5	1		T15	142		T17	6
alert[0x24]	3867	1			T5	1		T6	4		T7	277
alert[0x25]	8806	1			T3	1		T15	24		T45	30
alert[0x26]	2513	1			T3	1		T16	69		T62	1
alert[0x27]	12621	1			T7	1195		T16	1		T45	208
alert[0x28]	9320	1			T7	529		T16	422		T45	12
alert[0x29]	6482	1			T3	1		T25	1		T61	1
alert[0x2a]	1828	1			T3	1		T6	24		T7	65
alert[0x2b]	11310	1			T3	1		T15	26		T16	1
alert[0x2c]	4146	1			T3	1		T6	5		T7	453
alert[0x2d]	7535	1			T6	3		T7	371		T15	269
alert[0x2e]	12981	1			T3	1		T4	1		T5	1
alert[0x2f]	2537	1			T6	3		T17	1		T16	41
alert[0x30]	5009	1			T3	1		T6	7		T16	10
alert[0x31]	14300	1			T5	1		T7	4363		T15	15
alert[0x32]	11143	1			T5	1		T7	2037		T15	63
alert[0x33]	6498	1			T45	219		T85	5		T301	396
alert[0x34]	7261	1			T6	3		T15	304		T17	8
alert[0x35]	5154	1			T6	15		T15	377		T16	8
alert[0x36]	10054	1			T7	69		T15	749		T16	633
alert[0x37]	4143	1			T15	5		T59	1		T61	2
alert[0x38]	5600	1			T15	417		T16	39		T62	2
alert[0x39]	9018	1			T7	748		T15	17		T17	3
alert[0x3a]	8959	1			T5	1		T16	158		T45	42
alert[0x3b]	13023	1			T6	90		T15	11		T62	1
alert[0x3c]	5877	1			T3	1		T15	5		T25	3
alert[0x3d]	5560	1			T5	1		T6	3		T16	114
alert[0x3e]	4592	1			T15	144		T16	51		T61	2
alert[0x3f]	2539	1			T6	10		T7	2		T15	18
alert[0x40]	7540	1			T15	308		T16	402		T45	30

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	170987	1			T1	10		T5	10		T6	170
class_i[0x1]	110817	1			T1	3		T6	8		T7	12443
class_i[0x2]	124077	1			T6	30		T17	9		T59	1
class_i[0x3]	78309	1			T3	17		T4	3		T5	3

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

483565

1

T1

13

T6

456

T7

12499

alert_ping_fail

625

1

T3

17

T4

3

T5

13

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4522	1			T6	36		T46	1		T28	40
alert_integrity_fail	alert[0x1]	8662	1			T25	14		T46	28		T73	334
alert_integrity_fail	alert[0x2]	4156	1			T7	489		T16	21		T25	11
alert_integrity_fail	alert[0x3]	2708	1			T1	9		T7	96		T15	89
alert_integrity_fail	alert[0x4]	4093	1			T15	41		T17	216		T26	6
alert_integrity_fail	alert[0x5]	4349	1			T15	323		T16	51		T45	25
alert_integrity_fail	alert[0x6]	13114	1			T15	94		T17	7		T25	18
alert_integrity_fail	alert[0x7]	5899	1			T15	17		T17	195		T16	40
alert_integrity_fail	alert[0x8]	3589	1			T6	1		T7	25		T16	11
alert_integrity_fail	alert[0x9]	9251	1			T7	99		T15	210		T16	35
alert_integrity_fail	alert[0xa]	2218	1			T6	5		T15	36		T16	40
alert_integrity_fail	alert[0xb]	5477	1			T6	2		T15	332		T16	242
alert_integrity_fail	alert[0xc]	11535	1			T6	207		T15	508		T16	129
alert_integrity_fail	alert[0xd]	7672	1			T48	215		T50	15		T276	36
alert_integrity_fail	alert[0xe]	12911	1			T7	34		T16	1753		T45	35
alert_integrity_fail	alert[0xf]	5257	1			T6	2		T7	99		T15	227
alert_integrity_fail	alert[0x10]	5007	1			T6	7		T7	67		T16	50
alert_integrity_fail	alert[0x11]	4436	1			T1	1		T15	40		T45	1268
alert_integrity_fail	alert[0x12]	6308	1			T6	8		T16	20		T73	1964
alert_integrity_fail	alert[0x13]	5119	1			T16	1032		T25	1		T48	12
alert_integrity_fail	alert[0x14]	3428	1			T7	64		T17	3		T16	272
alert_integrity_fail	alert[0x15]	8655	1			T7	80		T15	12		T45	29
alert_integrity_fail	alert[0x16]	7370	1			T6	8		T17	71		T26	4
alert_integrity_fail	alert[0x17]	10277	1			T7	202		T15	96		T25	1
alert_integrity_fail	alert[0x18]	10029	1			T1	2		T7	300		T15	301
alert_integrity_fail	alert[0x19]	17482	1			T6	5		T7	300		T15	132
alert_integrity_fail	alert[0x1a]	5744	1			T6	3		T17	1		T45	22
alert_integrity_fail	alert[0x1b]	2216	1			T16	6		T45	6		T46	74
alert_integrity_fail	alert[0x1c]	13120	1			T7	266		T16	1080		T73	19
alert_integrity_fail	alert[0x1d]	12713	1			T7	125		T16	87		T45	65
alert_integrity_fail	alert[0x1e]	15380	1			T6	1		T15	59		T16	1418
alert_integrity_fail	alert[0x1f]	9001	1			T15	87		T28	122		T301	99
alert_integrity_fail	alert[0x20]	6420	1			T1	1		T6	1		T15	360
alert_integrity_fail	alert[0x21]	3986	1			T15	46		T16	61		T45	69
alert_integrity_fail	alert[0x22]	9272	1			T6	3		T7	144		T17	6
alert_integrity_fail	alert[0x23]	12235	1			T15	142		T17	6		T16	182
alert_integrity_fail	alert[0x24]	3861	1			T6	4		T7	277		T15	177
alert_integrity_fail	alert[0x25]	8799	1			T15	24		T45	30		T122	2
alert_integrity_fail	alert[0x26]	2507	1			T16	69		T28	303		T276	141
alert_integrity_fail	alert[0x27]	12611	1			T7	1195		T16	1		T45	208
alert_integrity_fail	alert[0x28]	9307	1			T7	529		T16	422		T45	12
alert_integrity_fail	alert[0x29]	6477	1			T25	1		T46	49		T27	448
alert_integrity_fail	alert[0x2a]	1818	1			T6	24		T7	65		T17	2
alert_integrity_fail	alert[0x2b]	11296	1			T15	26		T16	1		T27	6
alert_integrity_fail	alert[0x2c]	4134	1			T6	5		T7	453		T45	169
alert_integrity_fail	alert[0x2d]	7524	1			T6	3		T7	371		T15	269
alert_integrity_fail	alert[0x2e]	12968	1			T15	6470		T17	56		T45	112
alert_integrity_fail	alert[0x2f]	2524	1			T6	3		T17	1		T16	41
alert_integrity_fail	alert[0x30]	4999	1			T6	7		T16	10		T25	1
alert_integrity_fail	alert[0x31]	14296	1			T7	4363		T15	15		T45	777
alert_integrity_fail	alert[0x32]	11130	1			T7	2037		T15	63		T16	3
alert_integrity_fail	alert[0x33]	6488	1			T45	219		T85	5		T301	396
alert_integrity_fail	alert[0x34]	7251	1			T6	3		T15	304		T17	8
alert_integrity_fail	alert[0x35]	5149	1			T6	15		T15	377		T16	8
alert_integrity_fail	alert[0x36]	10051	1			T7	69		T15	749		T16	633
alert_integrity_fail	alert[0x37]	4130	1			T15	5		T26	5		T48	1
alert_integrity_fail	alert[0x38]	5592	1			T15	417		T16	39		T45	61
alert_integrity_fail	alert[0x39]	9012	1			T7	748		T15	17		T17	3
alert_integrity_fail	alert[0x3a]	8950	1			T16	158		T45	42		T27	29
alert_integrity_fail	alert[0x3b]	13011	1			T6	90		T15	11		T45	13
alert_integrity_fail	alert[0x3c]	5869	1			T15	5		T25	3		T27	771
alert_integrity_fail	alert[0x3d]	5548	1			T6	3		T16	114		T28	1089
alert_integrity_fail	alert[0x3e]	4584	1			T15	144		T16	51		T45	1118
alert_integrity_fail	alert[0x3f]	2533	1			T6	10		T7	2		T15	18
alert_integrity_fail	alert[0x40]	7535	1			T15	308		T16	402		T45	30
alert_ping_fail	alert[0x0]	17	1			T5	1		T62	1		T115	1
alert_ping_fail	alert[0x1]	12	1			T3	1		T115	1		T302	1
alert_ping_fail	alert[0x2]	11	1			T5	1		T59	1		T303	2
alert_ping_fail	alert[0x3]	13	1			T3	1		T61	1		T115	1
alert_ping_fail	alert[0x4]	7	1			T115	1		T304	2		T305	1
alert_ping_fail	alert[0x5]	7	1			T44	1		T76	1		T298	1
alert_ping_fail	alert[0x6]	9	1			T3	1		T187	1		T306	1
alert_ping_fail	alert[0x7]	10	1			T3	1		T61	1		T115	1
alert_ping_fail	alert[0x8]	10	1			T44	1		T64	1		T76	1
alert_ping_fail	alert[0x9]	10	1			T3	1		T187	1		T307	1
alert_ping_fail	alert[0xa]	8	1			T61	1		T303	1		T308	1
alert_ping_fail	alert[0xb]	16	1			T304	1		T187	1		T307	1
alert_ping_fail	alert[0xc]	8	1			T115	1		T305	1		T236	1
alert_ping_fail	alert[0xd]	9	1			T5	1		T61	1		T303	1
alert_ping_fail	alert[0xe]	8	1			T61	2		T64	1		T303	1
alert_ping_fail	alert[0xf]	6	1			T61	1		T307	1		T309	1
alert_ping_fail	alert[0x10]	9	1			T304	1		T308	1		T236	2
alert_ping_fail	alert[0x11]	15	1			T5	1		T115	1		T307	1
alert_ping_fail	alert[0x12]	3	1			T115	1		T310	1		T311	1
alert_ping_fail	alert[0x13]	12	1			T3	1		T297	2		T187	1
alert_ping_fail	alert[0x14]	8	1			T44	1		T61	1		T187	1
alert_ping_fail	alert[0x15]	14	1			T40	2		T303	1		T310	1
alert_ping_fail	alert[0x16]	15	1			T238	3		T115	1		T303	1
alert_ping_fail	alert[0x17]	10	1			T304	1		T76	1		T310	1
alert_ping_fail	alert[0x18]	7	1			T115	1		T309	1		T312	2
alert_ping_fail	alert[0x19]	13	1			T61	1		T303	1		T305	1
alert_ping_fail	alert[0x1a]	8	1			T64	1		T115	1		T310	1
alert_ping_fail	alert[0x1b]	6	1			T304	1		T313	1		T232	1
alert_ping_fail	alert[0x1c]	7	1			T312	1		T314	1		T315	1
alert_ping_fail	alert[0x1d]	8	1			T187	1		T227	1		T316	1
alert_ping_fail	alert[0x1e]	14	1			T76	1		T307	2		T317	1
alert_ping_fail	alert[0x1f]	15	1			T5	1		T238	1		T115	1
alert_ping_fail	alert[0x20]	5	1			T3	1		T302	1		T314	1
alert_ping_fail	alert[0x21]	10	1			T5	1		T44	1		T61	1
alert_ping_fail	alert[0x22]	16	1			T3	1		T4	2		T238	1
alert_ping_fail	alert[0x23]	7	1			T5	1		T62	1		T187	1
alert_ping_fail	alert[0x24]	6	1			T5	1		T187	1		T310	1
alert_ping_fail	alert[0x25]	7	1			T3	1		T187	1		T310	1
alert_ping_fail	alert[0x26]	6	1			T3	1		T62	1		T303	1
alert_ping_fail	alert[0x27]	10	1			T304	1		T307	1		T232	1
alert_ping_fail	alert[0x28]	13	1			T64	1		T115	2		T297	1
alert_ping_fail	alert[0x29]	5	1			T3	1		T61	1		T62	1
alert_ping_fail	alert[0x2a]	10	1			T3	1		T318	1		T307	2
alert_ping_fail	alert[0x2b]	14	1			T3	1		T61	1		T238	1
alert_ping_fail	alert[0x2c]	12	1			T3	1		T59	1		T61	1
alert_ping_fail	alert[0x2d]	11	1			T319	1		T236	1		T320	2
alert_ping_fail	alert[0x2e]	13	1			T3	1		T4	1		T5	1
alert_ping_fail	alert[0x2f]	13	1			T61	1		T64	1		T298	2
alert_ping_fail	alert[0x30]	10	1			T3	1		T303	1		T187	1
alert_ping_fail	alert[0x31]	4	1			T5	1		T76	1		T307	1
alert_ping_fail	alert[0x32]	13	1			T5	1		T59	1		T304	1
alert_ping_fail	alert[0x33]	10	1			T307	1		T309	1		T232	1
alert_ping_fail	alert[0x34]	10	1			T61	1		T303	1		T310	1
alert_ping_fail	alert[0x35]	5	1			T64	1		T313	1		T309	1
alert_ping_fail	alert[0x36]	3	1			T309	1		T236	1		T321	1
alert_ping_fail	alert[0x37]	13	1			T59	1		T61	2		T62	1
alert_ping_fail	alert[0x38]	8	1			T62	2		T76	1		T305	1
alert_ping_fail	alert[0x39]	6	1			T307	1		T236	1		T322	1
alert_ping_fail	alert[0x3a]	9	1			T5	1		T115	1		T187	1
alert_ping_fail	alert[0x3b]	12	1			T62	1		T115	1		T307	1
alert_ping_fail	alert[0x3c]	8	1			T3	1		T115	1		T323	1
alert_ping_fail	alert[0x3d]	12	1			T5	1		T115	1		T303	1
alert_ping_fail	alert[0x3e]	8	1			T61	2		T62	1		T324	2
alert_ping_fail	alert[0x3f]	6	1			T303	1		T308	1		T309	2
alert_ping_fail	alert[0x40]	5	1			T312	1		T325	2		T326	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	170824	1			T1	10		T6	170		T7	56
alert_integrity_fail	class_i[0x1]	110631	1			T1	3		T6	8		T7	12443
alert_integrity_fail	class_i[0x2]	123945	1			T6	30		T17	9		T46	2408
alert_integrity_fail	class_i[0x3]	78165	1			T6	248		T15	60		T16	9
alert_ping_fail	class_i[0x0]	163	1			T5	10		T62	4		T64	4
alert_ping_fail	class_i[0x1]	186	1			T59	3		T44	4		T61	19
alert_ping_fail	class_i[0x2]	132	1			T59	1		T62	2		T238	6
alert_ping_fail	class_i[0x3]	144	1			T3	17		T4	3		T5	3