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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.76 100.00 100.00 100.00 99.38 99.40


Total test records in report: 832
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T773 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3855811305 Jun 11 02:23:19 PM PDT 24 Jun 11 02:23:25 PM PDT 24 491271309 ps
T774 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3164808236 Jun 11 02:23:00 PM PDT 24 Jun 11 02:25:44 PM PDT 24 2674209145 ps
T775 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2174334440 Jun 11 02:23:20 PM PDT 24 Jun 11 02:23:40 PM PDT 24 1072150268 ps
T776 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2183397311 Jun 11 02:23:22 PM PDT 24 Jun 11 02:23:35 PM PDT 24 164958160 ps
T777 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3504646650 Jun 11 02:23:04 PM PDT 24 Jun 11 02:23:09 PM PDT 24 63758406 ps
T778 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1764619133 Jun 11 02:23:15 PM PDT 24 Jun 11 02:23:18 PM PDT 24 22961239 ps
T779 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2935433237 Jun 11 02:23:22 PM PDT 24 Jun 11 02:23:29 PM PDT 24 111918365 ps
T139 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.688367599 Jun 11 02:23:21 PM PDT 24 Jun 11 02:29:02 PM PDT 24 4074701831 ps
T780 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2846840538 Jun 11 02:23:21 PM PDT 24 Jun 11 02:23:48 PM PDT 24 442545911 ps
T781 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.475214799 Jun 11 02:23:11 PM PDT 24 Jun 11 02:23:17 PM PDT 24 91168146 ps
T168 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2221935241 Jun 11 02:22:59 PM PDT 24 Jun 11 02:23:04 PM PDT 24 206779354 ps
T782 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1931189976 Jun 11 02:23:01 PM PDT 24 Jun 11 02:25:01 PM PDT 24 1651686309 ps
T783 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2237682452 Jun 11 02:23:04 PM PDT 24 Jun 11 02:23:16 PM PDT 24 266995188 ps
T174 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3438415320 Jun 11 02:23:02 PM PDT 24 Jun 11 02:23:24 PM PDT 24 1266918828 ps
T151 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1768112494 Jun 11 02:23:11 PM PDT 24 Jun 11 02:25:16 PM PDT 24 1174684819 ps
T149 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3904191307 Jun 11 02:23:18 PM PDT 24 Jun 11 02:30:56 PM PDT 24 24602920647 ps
T784 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4033561637 Jun 11 02:23:02 PM PDT 24 Jun 11 02:23:04 PM PDT 24 14973275 ps
T785 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3842669432 Jun 11 02:23:22 PM PDT 24 Jun 11 02:23:30 PM PDT 24 156437031 ps
T786 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1763699145 Jun 11 02:23:31 PM PDT 24 Jun 11 02:23:34 PM PDT 24 12777598 ps
T787 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3480796242 Jun 11 02:23:19 PM PDT 24 Jun 11 02:23:28 PM PDT 24 262398905 ps
T788 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2655342443 Jun 11 02:23:15 PM PDT 24 Jun 11 02:23:18 PM PDT 24 10631788 ps
T789 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1235820123 Jun 11 02:22:57 PM PDT 24 Jun 11 02:23:06 PM PDT 24 96262146 ps
T790 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.696617640 Jun 11 02:23:32 PM PDT 24 Jun 11 02:23:35 PM PDT 24 11314536 ps
T158 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.4283005676 Jun 11 02:23:03 PM PDT 24 Jun 11 02:40:56 PM PDT 24 54794839309 ps
T147 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2182077011 Jun 11 02:23:12 PM PDT 24 Jun 11 02:26:51 PM PDT 24 3158035759 ps
T152 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2645192207 Jun 11 02:23:02 PM PDT 24 Jun 11 02:26:29 PM PDT 24 10359218759 ps
T791 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3789274681 Jun 11 02:23:01 PM PDT 24 Jun 11 02:25:09 PM PDT 24 3144366191 ps
T792 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.167658201 Jun 11 02:23:32 PM PDT 24 Jun 11 02:23:34 PM PDT 24 15338991 ps
T793 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3092367169 Jun 11 02:23:19 PM PDT 24 Jun 11 02:23:27 PM PDT 24 195393060 ps
T794 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3075268244 Jun 11 02:23:33 PM PDT 24 Jun 11 02:23:36 PM PDT 24 9331875 ps
T795 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2598713545 Jun 11 02:22:59 PM PDT 24 Jun 11 02:23:09 PM PDT 24 341734978 ps
T796 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3850245982 Jun 11 02:23:02 PM PDT 24 Jun 11 02:23:11 PM PDT 24 408757173 ps
T797 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4011296170 Jun 11 02:23:00 PM PDT 24 Jun 11 02:23:05 PM PDT 24 22054982 ps
T172 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.145052545 Jun 11 02:23:06 PM PDT 24 Jun 11 02:23:50 PM PDT 24 654296874 ps
T798 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2879530761 Jun 11 02:23:04 PM PDT 24 Jun 11 02:23:31 PM PDT 24 1553468684 ps
T153 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2506277842 Jun 11 02:23:02 PM PDT 24 Jun 11 02:26:35 PM PDT 24 20900114136 ps
T799 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.509179357 Jun 11 02:23:05 PM PDT 24 Jun 11 02:23:13 PM PDT 24 374708195 ps
T800 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1513442140 Jun 11 02:23:23 PM PDT 24 Jun 11 02:23:26 PM PDT 24 21435712 ps
T801 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.985945491 Jun 11 02:23:33 PM PDT 24 Jun 11 02:23:35 PM PDT 24 24745812 ps
T178 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.606396822 Jun 11 02:23:19 PM PDT 24 Jun 11 02:24:04 PM PDT 24 326717423 ps
T155 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.238356847 Jun 11 02:23:10 PM PDT 24 Jun 11 02:29:38 PM PDT 24 3236979379 ps
T802 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1588169374 Jun 11 02:23:35 PM PDT 24 Jun 11 02:23:37 PM PDT 24 7986271 ps
T803 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2846979884 Jun 11 02:23:22 PM PDT 24 Jun 11 02:23:25 PM PDT 24 14342103 ps
T353 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.509956556 Jun 11 02:23:13 PM PDT 24 Jun 11 02:30:57 PM PDT 24 11911418081 ps
T181 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2425672429 Jun 11 02:23:10 PM PDT 24 Jun 11 02:23:15 PM PDT 24 106228128 ps
T804 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3974211729 Jun 11 02:23:10 PM PDT 24 Jun 11 02:23:22 PM PDT 24 598774575 ps
T805 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1930963630 Jun 11 02:23:04 PM PDT 24 Jun 11 02:23:07 PM PDT 24 35738120 ps
T806 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.4100583079 Jun 11 02:23:15 PM PDT 24 Jun 11 02:23:22 PM PDT 24 127172275 ps
T143 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2500887441 Jun 11 02:23:21 PM PDT 24 Jun 11 02:29:02 PM PDT 24 17844999034 ps
T807 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.248842584 Jun 11 02:23:15 PM PDT 24 Jun 11 02:23:34 PM PDT 24 916744000 ps
T808 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2096549507 Jun 11 02:23:21 PM PDT 24 Jun 11 02:23:50 PM PDT 24 347271746 ps
T809 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.47680196 Jun 11 02:23:18 PM PDT 24 Jun 11 02:23:21 PM PDT 24 12658657 ps
T176 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1863563107 Jun 11 02:23:17 PM PDT 24 Jun 11 02:23:22 PM PDT 24 157659464 ps
T810 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1144513341 Jun 11 02:23:01 PM PDT 24 Jun 11 02:23:11 PM PDT 24 160746337 ps
T811 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4034606795 Jun 11 02:23:22 PM PDT 24 Jun 11 02:23:34 PM PDT 24 126387725 ps
T812 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2217810086 Jun 11 02:23:22 PM PDT 24 Jun 11 02:23:31 PM PDT 24 80830456 ps
T813 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2459325957 Jun 11 02:23:22 PM PDT 24 Jun 11 02:26:22 PM PDT 24 6323029797 ps
T814 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.742065390 Jun 11 02:23:04 PM PDT 24 Jun 11 02:23:07 PM PDT 24 23092664 ps
T815 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3871537830 Jun 11 02:22:58 PM PDT 24 Jun 11 02:23:05 PM PDT 24 260785882 ps
T816 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3104094112 Jun 11 02:23:22 PM PDT 24 Jun 11 02:23:36 PM PDT 24 148720905 ps
T817 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2810146907 Jun 11 02:23:10 PM PDT 24 Jun 11 02:23:50 PM PDT 24 2013617699 ps
T818 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2258299112 Jun 11 02:23:06 PM PDT 24 Jun 11 02:23:53 PM PDT 24 1677484443 ps
T819 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3613253996 Jun 11 02:23:21 PM PDT 24 Jun 11 02:23:26 PM PDT 24 23452446 ps
T820 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3970126277 Jun 11 02:22:58 PM PDT 24 Jun 11 02:30:55 PM PDT 24 34222515553 ps
T157 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2189562568 Jun 11 02:23:23 PM PDT 24 Jun 11 02:25:12 PM PDT 24 781216462 ps
T821 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.907952204 Jun 11 02:23:23 PM PDT 24 Jun 11 02:24:06 PM PDT 24 530371713 ps
T354 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4224656009 Jun 11 02:23:12 PM PDT 24 Jun 11 02:28:45 PM PDT 24 4345784449 ps
T175 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.189176239 Jun 11 02:23:04 PM PDT 24 Jun 11 02:23:09 PM PDT 24 120539180 ps
T822 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4095081318 Jun 11 02:23:27 PM PDT 24 Jun 11 02:23:30 PM PDT 24 10615121 ps
T823 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1568593676 Jun 11 02:23:21 PM PDT 24 Jun 11 02:23:31 PM PDT 24 346748284 ps
T824 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1069885642 Jun 11 02:23:00 PM PDT 24 Jun 11 02:39:58 PM PDT 24 14017335262 ps
T825 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2846826665 Jun 11 02:23:21 PM PDT 24 Jun 11 02:23:34 PM PDT 24 248451777 ps
T156 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3407185283 Jun 11 02:23:02 PM PDT 24 Jun 11 02:39:30 PM PDT 24 13528260501 ps
T826 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.572801415 Jun 11 02:23:12 PM PDT 24 Jun 11 02:25:26 PM PDT 24 1952626383 ps
T827 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3469110142 Jun 11 02:23:05 PM PDT 24 Jun 11 02:23:11 PM PDT 24 433550244 ps
T150 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2454680528 Jun 11 02:23:21 PM PDT 24 Jun 11 02:29:26 PM PDT 24 4624336054 ps
T171 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3513474215 Jun 11 02:23:15 PM PDT 24 Jun 11 02:24:18 PM PDT 24 3562666317 ps
T828 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1355056442 Jun 11 02:23:33 PM PDT 24 Jun 11 02:23:35 PM PDT 24 13748855 ps
T829 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2280145093 Jun 11 02:23:02 PM PDT 24 Jun 11 02:23:26 PM PDT 24 299969489 ps
T830 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3759042333 Jun 11 02:23:33 PM PDT 24 Jun 11 02:23:35 PM PDT 24 10054731 ps
T831 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.4021140082 Jun 11 02:23:20 PM PDT 24 Jun 11 02:23:23 PM PDT 24 10439915 ps
T832 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2409017156 Jun 11 02:23:27 PM PDT 24 Jun 11 02:23:30 PM PDT 24 15199757 ps

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2166256522
Short name T6
Test name
Test status
Simulation time 31213427529 ps
CPU time 1800.55 seconds
Started Jun 11 02:24:41 PM PDT 24
Finished Jun 11 02:54:44 PM PDT 24
Peak memory 272328 kb
Host smart-6edd2c34-d4a4-49bc-8b12-aedd71b6b20f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166256522 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2166256522
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.4109346119
Short name T15
Test name
Test status
Simulation time 135903271557 ps
CPU time 4198.11 seconds
Started Jun 11 02:28:11 PM PDT 24
Finished Jun 11 03:38:11 PM PDT 24
Peak memory 298008 kb
Host smart-f9463192-6d38-4a65-9d24-0d600882d4eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109346119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.4109346119
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2116533471
Short name T11
Test name
Test status
Simulation time 3805045459 ps
CPU time 23.09 seconds
Started Jun 11 02:24:35 PM PDT 24
Finished Jun 11 02:25:00 PM PDT 24
Peak memory 277900 kb
Host smart-6bb2194d-c857-4bfa-a56c-a600bba64855
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2116533471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2116533471
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2576123886
Short name T160
Test name
Test status
Simulation time 189583620 ps
CPU time 25.38 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:49 PM PDT 24
Peak memory 236780 kb
Host smart-644f48b0-501b-47fe-84b7-54738f31f317
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2576123886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2576123886
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3621684551
Short name T27
Test name
Test status
Simulation time 118148487595 ps
CPU time 2056.97 seconds
Started Jun 11 02:25:19 PM PDT 24
Finished Jun 11 02:59:37 PM PDT 24
Peak memory 287424 kb
Host smart-7f5da4dd-b3be-4851-9ee5-506c0c793d70
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621684551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3621684551
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1050570692
Short name T24
Test name
Test status
Simulation time 47561364289 ps
CPU time 2471.4 seconds
Started Jun 11 02:25:29 PM PDT 24
Finished Jun 11 03:06:42 PM PDT 24
Peak memory 289732 kb
Host smart-cd98f388-abb8-4e28-b7f0-ae6c3b0fc67e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050570692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1050570692
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3905426394
Short name T133
Test name
Test status
Simulation time 3935967690 ps
CPU time 289.49 seconds
Started Jun 11 02:23:20 PM PDT 24
Finished Jun 11 02:28:11 PM PDT 24
Peak memory 273132 kb
Host smart-326598cf-43cc-4cc5-9373-3be463cc4ec7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3905426394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3905426394
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.4073250303
Short name T108
Test name
Test status
Simulation time 167033541689 ps
CPU time 5354.76 seconds
Started Jun 11 02:26:00 PM PDT 24
Finished Jun 11 03:55:17 PM PDT 24
Peak memory 306280 kb
Host smart-b353c742-30f1-4b92-9449-97d41c32e283
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073250303 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.4073250303
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.709356747
Short name T238
Test name
Test status
Simulation time 219649677555 ps
CPU time 2725.35 seconds
Started Jun 11 02:26:36 PM PDT 24
Finished Jun 11 03:12:02 PM PDT 24
Peak memory 273600 kb
Host smart-243e282b-5d0c-4e1c-a76c-aec8830ebf3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709356747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.709356747
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.1178406818
Short name T17
Test name
Test status
Simulation time 55457685312 ps
CPU time 968.45 seconds
Started Jun 11 02:26:48 PM PDT 24
Finished Jun 11 02:42:57 PM PDT 24
Peak memory 273560 kb
Host smart-a8bb83aa-7fe3-4184-abd9-9d84794938bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178406818 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.1178406818
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1573695671
Short name T128
Test name
Test status
Simulation time 64621409663 ps
CPU time 1059.78 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:41:04 PM PDT 24
Peak memory 265112 kb
Host smart-0ac70c43-2462-4066-9dda-6c2877f1cb5d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573695671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1573695671
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.625817444
Short name T112
Test name
Test status
Simulation time 152071888844 ps
CPU time 1533.86 seconds
Started Jun 11 02:27:07 PM PDT 24
Finished Jun 11 02:52:42 PM PDT 24
Peak memory 265352 kb
Host smart-4a39cad5-f3d4-40cf-9485-2639ff1f9998
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625817444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.625817444
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2511824942
Short name T134
Test name
Test status
Simulation time 7357654610 ps
CPU time 283.4 seconds
Started Jun 11 02:23:01 PM PDT 24
Finished Jun 11 02:27:45 PM PDT 24
Peak memory 265128 kb
Host smart-04b98e11-ede8-4c19-ab08-b49eeaf551c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2511824942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2511824942
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.328557493
Short name T7
Test name
Test status
Simulation time 170715134651 ps
CPU time 2690.14 seconds
Started Jun 11 02:26:44 PM PDT 24
Finished Jun 11 03:11:35 PM PDT 24
Peak memory 289792 kb
Host smart-ec900850-b47f-441d-82e2-91a8879ab661
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328557493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.328557493
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.4076874091
Short name T29
Test name
Test status
Simulation time 54224777310 ps
CPU time 1342.87 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 02:46:51 PM PDT 24
Peak memory 288924 kb
Host smart-9a61c777-d9d7-49c6-b11b-16a24bb5f125
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076874091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.4076874091
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2314535349
Short name T95
Test name
Test status
Simulation time 481885735 ps
CPU time 10.5 seconds
Started Jun 11 02:25:16 PM PDT 24
Finished Jun 11 02:25:28 PM PDT 24
Peak memory 254140 kb
Host smart-a2a92a99-6d77-4502-ba17-da05429d653f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23145
35349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2314535349
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3157526386
Short name T140
Test name
Test status
Simulation time 4782094311 ps
CPU time 759.3 seconds
Started Jun 11 02:23:20 PM PDT 24
Finished Jun 11 02:36:01 PM PDT 24
Peak memory 265040 kb
Host smart-71530b8f-bdbf-4f45-8cf9-722b3e68e361
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157526386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3157526386
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1244642955
Short name T44
Test name
Test status
Simulation time 42935664631 ps
CPU time 2507.32 seconds
Started Jun 11 02:24:24 PM PDT 24
Finished Jun 11 03:06:13 PM PDT 24
Peak memory 289268 kb
Host smart-a9915556-5859-4fd2-9105-b50581330e6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244642955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1244642955
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.160136715
Short name T346
Test name
Test status
Simulation time 6848878 ps
CPU time 1.55 seconds
Started Jun 11 02:23:05 PM PDT 24
Finished Jun 11 02:23:08 PM PDT 24
Peak memory 235644 kb
Host smart-6477dad1-96c7-4eba-b774-46dd73f72362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=160136715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.160136715
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3387297691
Short name T148
Test name
Test status
Simulation time 12613662204 ps
CPU time 1043.59 seconds
Started Jun 11 02:23:04 PM PDT 24
Finished Jun 11 02:40:29 PM PDT 24
Peak memory 265068 kb
Host smart-5163c01d-cf89-495e-be6a-34378ab7b71f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387297691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3387297691
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3478614891
Short name T3
Test name
Test status
Simulation time 11213653863 ps
CPU time 472.66 seconds
Started Jun 11 02:27:50 PM PDT 24
Finished Jun 11 02:35:44 PM PDT 24
Peak memory 248884 kb
Host smart-37a4890a-bfa9-4630-9546-1d51301fbc98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478614891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3478614891
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.4281235988
Short name T331
Test name
Test status
Simulation time 35644196412 ps
CPU time 1832.4 seconds
Started Jun 11 02:27:50 PM PDT 24
Finished Jun 11 02:58:24 PM PDT 24
Peak memory 288924 kb
Host smart-1350d056-7da0-412c-b626-5d9be53a2cd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281235988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.4281235988
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1711885982
Short name T48
Test name
Test status
Simulation time 24946158890 ps
CPU time 1205.52 seconds
Started Jun 11 02:26:58 PM PDT 24
Finished Jun 11 02:47:05 PM PDT 24
Peak memory 286912 kb
Host smart-7c3bea64-475c-41bf-81cc-f23f8dc8b757
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711885982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1711885982
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2141255247
Short name T315
Test name
Test status
Simulation time 55910749631 ps
CPU time 667.66 seconds
Started Jun 11 02:28:01 PM PDT 24
Finished Jun 11 02:39:09 PM PDT 24
Peak memory 248528 kb
Host smart-384f781a-4e8c-4091-971d-e603b56b9a89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141255247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2141255247
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1285698223
Short name T203
Test name
Test status
Simulation time 5894236549 ps
CPU time 379.84 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:29:23 PM PDT 24
Peak memory 236636 kb
Host smart-cd57f0c0-3e05-4625-9b3f-b185667601c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1285698223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1285698223
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.55102648
Short name T131
Test name
Test status
Simulation time 12454916746 ps
CPU time 196.45 seconds
Started Jun 11 02:23:03 PM PDT 24
Finished Jun 11 02:26:21 PM PDT 24
Peak memory 265100 kb
Host smart-f96f7e89-17d6-4391-a55e-7099b6394771
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55102648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors
.55102648
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1069885642
Short name T824
Test name
Test status
Simulation time 14017335262 ps
CPU time 1016.45 seconds
Started Jun 11 02:23:00 PM PDT 24
Finished Jun 11 02:39:58 PM PDT 24
Peak memory 265176 kb
Host smart-a21e3005-6645-4076-90e2-f0c404697dff
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069885642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1069885642
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3710657589
Short name T299
Test name
Test status
Simulation time 84680145926 ps
CPU time 2584.69 seconds
Started Jun 11 02:26:00 PM PDT 24
Finished Jun 11 03:09:06 PM PDT 24
Peak memory 281808 kb
Host smart-40b96454-9670-45de-8c84-7540b8a74f9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710657589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3710657589
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3175632109
Short name T115
Test name
Test status
Simulation time 87896687911 ps
CPU time 577.03 seconds
Started Jun 11 02:25:50 PM PDT 24
Finished Jun 11 02:35:28 PM PDT 24
Peak memory 255584 kb
Host smart-26798e8e-f184-45f3-add2-ecd17d1c4ca7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175632109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3175632109
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.993624798
Short name T339
Test name
Test status
Simulation time 197313176697 ps
CPU time 2672.6 seconds
Started Jun 11 02:24:44 PM PDT 24
Finished Jun 11 03:09:18 PM PDT 24
Peak memory 281760 kb
Host smart-60a0931f-541a-4cab-9a8e-e2af5ddbbac0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993624798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.993624798
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1204391118
Short name T46
Test name
Test status
Simulation time 66582944108 ps
CPU time 1190.35 seconds
Started Jun 11 02:24:51 PM PDT 24
Finished Jun 11 02:44:43 PM PDT 24
Peak memory 289544 kb
Host smart-89c69140-d580-494d-959d-d4d83a6d3a63
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204391118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1204391118
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2658194268
Short name T274
Test name
Test status
Simulation time 1963231635 ps
CPU time 38.09 seconds
Started Jun 11 02:24:31 PM PDT 24
Finished Jun 11 02:25:10 PM PDT 24
Peak memory 248992 kb
Host smart-577713b6-11ce-4121-a8e3-8efa8ea25679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26581
94268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2658194268
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1700293198
Short name T316
Test name
Test status
Simulation time 44991317689 ps
CPU time 453.2 seconds
Started Jun 11 02:24:43 PM PDT 24
Finished Jun 11 02:32:17 PM PDT 24
Peak memory 248064 kb
Host smart-eeb6ce94-66e4-4d41-88ac-dab88733b06c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700293198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1700293198
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2506277842
Short name T153
Test name
Test status
Simulation time 20900114136 ps
CPU time 210.75 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:26:35 PM PDT 24
Peak memory 265112 kb
Host smart-ecba6f3f-ecac-45df-b35f-513e9210b366
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2506277842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2506277842
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2440966339
Short name T129
Test name
Test status
Simulation time 12180390622 ps
CPU time 962.61 seconds
Started Jun 11 02:23:20 PM PDT 24
Finished Jun 11 02:39:24 PM PDT 24
Peak memory 265072 kb
Host smart-409ed438-3a3d-4c7b-ab9c-ad1a38162385
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440966339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2440966339
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3413130065
Short name T240
Test name
Test status
Simulation time 14627006 ps
CPU time 1.41 seconds
Started Jun 11 02:23:20 PM PDT 24
Finished Jun 11 02:23:23 PM PDT 24
Peak memory 236712 kb
Host smart-c8bb4c1a-4872-4da8-8b9c-042813edd1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3413130065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3413130065
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3065504932
Short name T16
Test name
Test status
Simulation time 48009682411 ps
CPU time 2744.14 seconds
Started Jun 11 02:24:32 PM PDT 24
Finished Jun 11 03:10:17 PM PDT 24
Peak memory 288544 kb
Host smart-d0fbdd8f-0cf4-4bb5-9ad9-72b77add4ffc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065504932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3065504932
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2029672337
Short name T327
Test name
Test status
Simulation time 103862336658 ps
CPU time 1932.34 seconds
Started Jun 11 02:25:38 PM PDT 24
Finished Jun 11 02:57:52 PM PDT 24
Peak memory 273536 kb
Host smart-6a0aeb05-f7b0-4339-adc9-b5bb1794561f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029672337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2029672337
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2864569621
Short name T307
Test name
Test status
Simulation time 11243046823 ps
CPU time 430.2 seconds
Started Jun 11 02:26:38 PM PDT 24
Finished Jun 11 02:33:49 PM PDT 24
Peak memory 248104 kb
Host smart-086def3a-c621-4b1c-90b5-5097d5593197
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864569621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2864569621
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.4241561418
Short name T272
Test name
Test status
Simulation time 64604860049 ps
CPU time 3180 seconds
Started Jun 11 02:25:35 PM PDT 24
Finished Jun 11 03:18:37 PM PDT 24
Peak memory 306220 kb
Host smart-35b5a26c-ae33-4f00-ae8a-500540cf794c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241561418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.4241561418
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2980708807
Short name T287
Test name
Test status
Simulation time 106581571352 ps
CPU time 2912.5 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 03:14:10 PM PDT 24
Peak memory 289316 kb
Host smart-9a6c99d8-726c-4151-a77a-c28714d175cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980708807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2980708807
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.68154775
Short name T136
Test name
Test status
Simulation time 8915699519 ps
CPU time 198.93 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:26:23 PM PDT 24
Peak memory 265108 kb
Host smart-46c2e25b-7ff5-4f65-a55f-18814d88863e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=68154775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors
.68154775
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3556593832
Short name T236
Test name
Test status
Simulation time 59622779031 ps
CPU time 337.87 seconds
Started Jun 11 02:24:24 PM PDT 24
Finished Jun 11 02:30:04 PM PDT 24
Peak memory 248356 kb
Host smart-23b6edd5-08d6-4563-972f-929cda28157f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556593832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3556593832
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1251320212
Short name T39
Test name
Test status
Simulation time 1074644535 ps
CPU time 62.25 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 02:25:30 PM PDT 24
Peak memory 255728 kb
Host smart-cedb5731-109a-4d84-a4d1-beff98e3fba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12513
20212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1251320212
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2193125998
Short name T342
Test name
Test status
Simulation time 117464715124 ps
CPU time 2025.79 seconds
Started Jun 11 02:25:38 PM PDT 24
Finished Jun 11 02:59:25 PM PDT 24
Peak memory 271728 kb
Host smart-8a9fee34-6d37-4129-8890-d3a21c0db77b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193125998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2193125998
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.154727825
Short name T61
Test name
Test status
Simulation time 22770361575 ps
CPU time 463.52 seconds
Started Jun 11 02:25:49 PM PDT 24
Finished Jun 11 02:33:33 PM PDT 24
Peak memory 248644 kb
Host smart-ffb14620-0573-42eb-a77e-20d8da8652a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154727825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.154727825
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2164606543
Short name T99
Test name
Test status
Simulation time 39472236133 ps
CPU time 2347.44 seconds
Started Jun 11 02:25:48 PM PDT 24
Finished Jun 11 03:04:56 PM PDT 24
Peak memory 283924 kb
Host smart-15a18e29-10c7-40c1-967a-2ea11537bb2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164606543 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2164606543
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2645287897
Short name T256
Test name
Test status
Simulation time 196408110499 ps
CPU time 4938.32 seconds
Started Jun 11 02:28:00 PM PDT 24
Finished Jun 11 03:50:20 PM PDT 24
Peak memory 355596 kb
Host smart-a5495eb1-dcef-4cc5-b91a-18782aa01d5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645287897 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2645287897
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.852094908
Short name T170
Test name
Test status
Simulation time 117850727 ps
CPU time 4.41 seconds
Started Jun 11 02:23:19 PM PDT 24
Finished Jun 11 02:23:25 PM PDT 24
Peak memory 236860 kb
Host smart-c6a4c005-ab33-4af6-9351-9e7df5e299d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=852094908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.852094908
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2454680528
Short name T150
Test name
Test status
Simulation time 4624336054 ps
CPU time 363.34 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:29:26 PM PDT 24
Peak memory 272256 kb
Host smart-d094f4b3-0a7b-447a-9f9d-f58a6de8c1be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2454680528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2454680528
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2382280558
Short name T144
Test name
Test status
Simulation time 23690743495 ps
CPU time 985.21 seconds
Started Jun 11 02:23:06 PM PDT 24
Finished Jun 11 02:39:33 PM PDT 24
Peak memory 265232 kb
Host smart-88c58408-dc4d-4aa3-b0e8-e79c9409c496
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382280558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2382280558
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2366583510
Short name T221
Test name
Test status
Simulation time 39716303 ps
CPU time 3.81 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:24:29 PM PDT 24
Peak memory 249112 kb
Host smart-c087c31c-9bb6-4187-b366-0bcbd6e3a906
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2366583510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2366583510
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.89148130
Short name T218
Test name
Test status
Simulation time 60195796 ps
CPU time 3.49 seconds
Started Jun 11 02:24:27 PM PDT 24
Finished Jun 11 02:24:32 PM PDT 24
Peak memory 249192 kb
Host smart-1ab5089a-80bc-443c-abc0-21c1b4b3b67c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=89148130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.89148130
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2916711579
Short name T207
Test name
Test status
Simulation time 14200007 ps
CPU time 2.94 seconds
Started Jun 11 02:25:14 PM PDT 24
Finished Jun 11 02:25:18 PM PDT 24
Peak memory 249200 kb
Host smart-f864a450-3037-44c3-a05a-6324e60865d7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2916711579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2916711579
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2654367814
Short name T217
Test name
Test status
Simulation time 68113443 ps
CPU time 3.65 seconds
Started Jun 11 02:25:15 PM PDT 24
Finished Jun 11 02:25:20 PM PDT 24
Peak memory 249016 kb
Host smart-4269a5d0-eb7a-45fc-a12f-e5559a19124a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2654367814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2654367814
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3883245154
Short name T619
Test name
Test status
Simulation time 636850020076 ps
CPU time 2684.57 seconds
Started Jun 11 02:25:49 PM PDT 24
Finished Jun 11 03:10:35 PM PDT 24
Peak memory 289412 kb
Host smart-effa1117-238f-4e30-9f28-5882562d2a82
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883245154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3883245154
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.735538657
Short name T277
Test name
Test status
Simulation time 2202595740 ps
CPU time 16.3 seconds
Started Jun 11 02:26:29 PM PDT 24
Finished Jun 11 02:26:46 PM PDT 24
Peak memory 248960 kb
Host smart-0929e72b-59ee-41c7-a0e3-e32276e0003c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73553
8657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.735538657
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1892409823
Short name T259
Test name
Test status
Simulation time 32336709199 ps
CPU time 2222.74 seconds
Started Jun 11 02:26:35 PM PDT 24
Finished Jun 11 03:03:39 PM PDT 24
Peak memory 289572 kb
Host smart-b96b08df-9b4d-437f-a5f5-469088d1a944
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892409823 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1892409823
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3303232837
Short name T250
Test name
Test status
Simulation time 32969083670 ps
CPU time 1855.24 seconds
Started Jun 11 02:27:09 PM PDT 24
Finished Jun 11 02:58:05 PM PDT 24
Peak memory 282340 kb
Host smart-ee72d9d6-d6f8-4ddd-a283-75148b722c8a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303232837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3303232837
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.146137418
Short name T704
Test name
Test status
Simulation time 88175909939 ps
CPU time 511.66 seconds
Started Jun 11 02:27:17 PM PDT 24
Finished Jun 11 02:35:50 PM PDT 24
Peak memory 248376 kb
Host smart-93a97775-57b0-4017-b5e9-2819e4278b5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146137418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.146137418
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.660672764
Short name T280
Test name
Test status
Simulation time 149096152136 ps
CPU time 1921.19 seconds
Started Jun 11 02:28:11 PM PDT 24
Finished Jun 11 03:00:14 PM PDT 24
Peak memory 288852 kb
Host smart-1d237c16-7bfc-4035-912d-e02ee76c5100
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660672764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.660672764
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.259851599
Short name T113
Test name
Test status
Simulation time 43800477569 ps
CPU time 1312.86 seconds
Started Jun 11 02:25:30 PM PDT 24
Finished Jun 11 02:47:25 PM PDT 24
Peak memory 289560 kb
Host smart-bf3228dc-15c8-4f9f-a5fd-970edb06140c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259851599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.259851599
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3509718462
Short name T100
Test name
Test status
Simulation time 506663037 ps
CPU time 10.97 seconds
Started Jun 11 02:25:47 PM PDT 24
Finished Jun 11 02:25:59 PM PDT 24
Peak memory 256156 kb
Host smart-47d0f4b9-61ca-4a8e-9af1-2d7fbba4da46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35097
18462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3509718462
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2089081550
Short name T137
Test name
Test status
Simulation time 4446840199 ps
CPU time 684.43 seconds
Started Jun 11 02:23:20 PM PDT 24
Finished Jun 11 02:34:46 PM PDT 24
Peak memory 265256 kb
Host smart-6fd2d3b0-11c9-4667-a4e5-437d47bcd388
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089081550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2089081550
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2948947618
Short name T349
Test name
Test status
Simulation time 25822444 ps
CPU time 1.58 seconds
Started Jun 11 02:23:01 PM PDT 24
Finished Jun 11 02:23:04 PM PDT 24
Peak memory 236664 kb
Host smart-7f60e036-70a9-4100-999d-66a0c422c3ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2948947618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2948947618
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1609292660
Short name T251
Test name
Test status
Simulation time 164183247770 ps
CPU time 1122.09 seconds
Started Jun 11 02:24:24 PM PDT 24
Finished Jun 11 02:43:08 PM PDT 24
Peak memory 288912 kb
Host smart-fc90c88b-459f-419f-80de-9768477c650d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609292660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1609292660
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.950028993
Short name T328
Test name
Test status
Simulation time 57813933970 ps
CPU time 2924.58 seconds
Started Jun 11 02:25:27 PM PDT 24
Finished Jun 11 03:14:14 PM PDT 24
Peak memory 287368 kb
Host smart-afedc28c-d765-4e7a-83dd-0d5f692a1f9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950028993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.950028993
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.829473316
Short name T253
Test name
Test status
Simulation time 7126736776 ps
CPU time 221.54 seconds
Started Jun 11 02:25:25 PM PDT 24
Finished Jun 11 02:29:08 PM PDT 24
Peak memory 248584 kb
Host smart-c0a803d0-b1d3-49a9-aeeb-75e4d19a4430
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829473316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.829473316
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1078957157
Short name T682
Test name
Test status
Simulation time 43189380267 ps
CPU time 1144.9 seconds
Started Jun 11 02:26:01 PM PDT 24
Finished Jun 11 02:45:08 PM PDT 24
Peak memory 283472 kb
Host smart-0c9eb6dc-3e5f-419c-a158-de6bf9f580a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078957157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1078957157
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3653300369
Short name T91
Test name
Test status
Simulation time 1565740137 ps
CPU time 26.79 seconds
Started Jun 11 02:26:00 PM PDT 24
Finished Jun 11 02:26:28 PM PDT 24
Peak memory 247980 kb
Host smart-52c758c0-cc29-4c9d-9e7d-3c8a1c36c48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36533
00369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3653300369
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3882012231
Short name T279
Test name
Test status
Simulation time 4438658328 ps
CPU time 45.69 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 02:27:13 PM PDT 24
Peak memory 256088 kb
Host smart-3f45280a-e31d-4d90-8728-ace1fc47ec41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38820
12231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3882012231
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1766669244
Short name T705
Test name
Test status
Simulation time 12308221364 ps
CPU time 131.74 seconds
Started Jun 11 02:26:46 PM PDT 24
Finished Jun 11 02:28:59 PM PDT 24
Peak memory 248576 kb
Host smart-9e49f3d0-f9be-4854-89c0-839ba94f9454
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766669244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1766669244
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.220181858
Short name T293
Test name
Test status
Simulation time 3134143272 ps
CPU time 54.36 seconds
Started Jun 11 02:27:48 PM PDT 24
Finished Jun 11 02:28:44 PM PDT 24
Peak memory 247824 kb
Host smart-d08326ab-d930-4505-8b91-0ec7b47fe3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22018
1858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.220181858
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3129428515
Short name T271
Test name
Test status
Simulation time 4380986420 ps
CPU time 54.76 seconds
Started Jun 11 02:28:12 PM PDT 24
Finished Jun 11 02:29:08 PM PDT 24
Peak memory 249100 kb
Host smart-58bf1784-5c25-4564-99a8-34115705fdf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31294
28515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3129428515
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1936686111
Short name T398
Test name
Test status
Simulation time 1966901216 ps
CPU time 61.25 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:25:26 PM PDT 24
Peak memory 248928 kb
Host smart-8fac4ee5-8f10-482c-8995-bb977111829f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19366
86111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1936686111
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.572801415
Short name T826
Test name
Test status
Simulation time 1952626383 ps
CPU time 133.37 seconds
Started Jun 11 02:23:12 PM PDT 24
Finished Jun 11 02:25:26 PM PDT 24
Peak memory 256856 kb
Host smart-ee665f97-4421-4cde-b17f-82c480261c76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=572801415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.572801415
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2221935241
Short name T168
Test name
Test status
Simulation time 206779354 ps
CPU time 4.21 seconds
Started Jun 11 02:22:59 PM PDT 24
Finished Jun 11 02:23:04 PM PDT 24
Peak memory 236728 kb
Host smart-548c3f91-db91-4342-8cf4-e4e00df4d28e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2221935241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2221935241
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1863563107
Short name T176
Test name
Test status
Simulation time 157659464 ps
CPU time 3.68 seconds
Started Jun 11 02:23:17 PM PDT 24
Finished Jun 11 02:23:22 PM PDT 24
Peak memory 236756 kb
Host smart-981915a5-52b4-466b-a1d8-9be63dfd4220
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1863563107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1863563107
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2601590261
Short name T167
Test name
Test status
Simulation time 79987999 ps
CPU time 4.94 seconds
Started Jun 11 02:23:20 PM PDT 24
Finished Jun 11 02:23:27 PM PDT 24
Peak memory 236672 kb
Host smart-eb3829d5-ba87-455a-9c50-1133d7a646f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2601590261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2601590261
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3438415320
Short name T174
Test name
Test status
Simulation time 1266918828 ps
CPU time 20.39 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:23:24 PM PDT 24
Peak memory 239536 kb
Host smart-9029a683-b980-4b36-9b1a-b8c50604f320
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3438415320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3438415320
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1696226277
Short name T173
Test name
Test status
Simulation time 598364007 ps
CPU time 43.32 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:24:06 PM PDT 24
Peak memory 236824 kb
Host smart-3fc8a5db-e78f-480b-b4ea-8184fbdfad19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1696226277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1696226277
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3240691023
Short name T165
Test name
Test status
Simulation time 66788338 ps
CPU time 4.61 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:28 PM PDT 24
Peak memory 236744 kb
Host smart-856c73a5-e9d5-4897-b9f6-bc648340a702
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3240691023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3240691023
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.145052545
Short name T172
Test name
Test status
Simulation time 654296874 ps
CPU time 43.43 seconds
Started Jun 11 02:23:06 PM PDT 24
Finished Jun 11 02:23:50 PM PDT 24
Peak memory 236788 kb
Host smart-d422afc7-69c0-47b6-9337-2443be7a4831
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=145052545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.145052545
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3866001351
Short name T166
Test name
Test status
Simulation time 2575518458 ps
CPU time 90.76 seconds
Started Jun 11 02:23:04 PM PDT 24
Finished Jun 11 02:24:36 PM PDT 24
Peak memory 240172 kb
Host smart-8e18b4b9-08b6-4f89-9225-0c106456543e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3866001351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3866001351
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.183875177
Short name T177
Test name
Test status
Simulation time 1849059471 ps
CPU time 33.77 seconds
Started Jun 11 02:23:18 PM PDT 24
Finished Jun 11 02:23:53 PM PDT 24
Peak memory 236920 kb
Host smart-bf982ef2-12c0-4c8c-bfa1-122a5f6a6ba0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=183875177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.183875177
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.606396822
Short name T178
Test name
Test status
Simulation time 326717423 ps
CPU time 43.97 seconds
Started Jun 11 02:23:19 PM PDT 24
Finished Jun 11 02:24:04 PM PDT 24
Peak memory 240032 kb
Host smart-454d6a9b-8230-43e6-ae41-0b29c7cc27da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=606396822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.606396822
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.189176239
Short name T175
Test name
Test status
Simulation time 120539180 ps
CPU time 3.18 seconds
Started Jun 11 02:23:04 PM PDT 24
Finished Jun 11 02:23:09 PM PDT 24
Peak memory 236772 kb
Host smart-a0955e85-9b45-4006-af07-69b984030615
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=189176239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.189176239
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3796836184
Short name T169
Test name
Test status
Simulation time 321085905 ps
CPU time 25.83 seconds
Started Jun 11 02:23:18 PM PDT 24
Finished Jun 11 02:23:46 PM PDT 24
Peak memory 240108 kb
Host smart-dbe658e2-d9b6-4f56-820a-43f58d065260
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3796836184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3796836184
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.4292169676
Short name T159
Test name
Test status
Simulation time 1809539113 ps
CPU time 38.02 seconds
Started Jun 11 02:23:24 PM PDT 24
Finished Jun 11 02:24:04 PM PDT 24
Peak memory 240056 kb
Host smart-2d046670-33bc-453a-9c42-7d97cfec9214
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4292169676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.4292169676
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3356941899
Short name T180
Test name
Test status
Simulation time 457684146 ps
CPU time 45.23 seconds
Started Jun 11 02:23:03 PM PDT 24
Finished Jun 11 02:23:50 PM PDT 24
Peak memory 236852 kb
Host smart-0f76b49e-7cf5-41d7-8a2f-f773d91af213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3356941899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3356941899
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2425672429
Short name T181
Test name
Test status
Simulation time 106228128 ps
CPU time 3.21 seconds
Started Jun 11 02:23:10 PM PDT 24
Finished Jun 11 02:23:15 PM PDT 24
Peak memory 236652 kb
Host smart-579e97b1-0430-4487-8994-5fcce2f03f17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2425672429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2425672429
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2733088580
Short name T179
Test name
Test status
Simulation time 84765849 ps
CPU time 4.96 seconds
Started Jun 11 02:23:16 PM PDT 24
Finished Jun 11 02:23:22 PM PDT 24
Peak memory 236676 kb
Host smart-303fe401-5fcb-4f8a-9e13-32259552be6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2733088580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2733088580
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.450766543
Short name T14
Test name
Test status
Simulation time 123567466561 ps
CPU time 1775.27 seconds
Started Jun 11 02:25:35 PM PDT 24
Finished Jun 11 02:55:11 PM PDT 24
Peak memory 273148 kb
Host smart-1ae8817c-ff82-422a-b63e-88c51d5926e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450766543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.450766543
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2971941728
Short name T18
Test name
Test status
Simulation time 752502086 ps
CPU time 50.9 seconds
Started Jun 11 02:26:49 PM PDT 24
Finished Jun 11 02:27:40 PM PDT 24
Peak memory 248980 kb
Host smart-7982f8bc-a936-442e-88ba-479264056f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29719
41728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2971941728
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2228060223
Short name T19
Test name
Test status
Simulation time 20479514917 ps
CPU time 679.72 seconds
Started Jun 11 02:24:41 PM PDT 24
Finished Jun 11 02:36:02 PM PDT 24
Peak memory 266612 kb
Host smart-6bb83516-ae0b-41d0-aeb2-a6b509f0f88a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228060223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2228060223
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3654484223
Short name T200
Test name
Test status
Simulation time 24820553682 ps
CPU time 272.29 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:27:36 PM PDT 24
Peak memory 238236 kb
Host smart-7d484810-1924-4392-892f-64e8f5600c49
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3654484223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3654484223
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2949404990
Short name T723
Test name
Test status
Simulation time 3291150303 ps
CPU time 198.32 seconds
Started Jun 11 02:23:03 PM PDT 24
Finished Jun 11 02:26:23 PM PDT 24
Peak memory 240120 kb
Host smart-01863655-108d-464d-9a5c-95cec57b6c08
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2949404990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2949404990
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2177878819
Short name T204
Test name
Test status
Simulation time 68103747 ps
CPU time 5.72 seconds
Started Jun 11 02:23:06 PM PDT 24
Finished Jun 11 02:23:13 PM PDT 24
Peak memory 240040 kb
Host smart-acd554ac-0be7-4407-a48b-ad9b2f54cc48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2177878819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2177878819
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3871537830
Short name T815
Test name
Test status
Simulation time 260785882 ps
CPU time 5.77 seconds
Started Jun 11 02:22:58 PM PDT 24
Finished Jun 11 02:23:05 PM PDT 24
Peak memory 236700 kb
Host smart-b467f579-de97-47ba-ad2b-838b72d24009
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871537830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3871537830
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1144513341
Short name T810
Test name
Test status
Simulation time 160746337 ps
CPU time 8.05 seconds
Started Jun 11 02:23:01 PM PDT 24
Finished Jun 11 02:23:11 PM PDT 24
Peak memory 236680 kb
Host smart-f4c17ad5-87a1-4d67-9cb3-1ac3717406eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1144513341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1144513341
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3662992317
Short name T748
Test name
Test status
Simulation time 503319774 ps
CPU time 20.56 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:23:24 PM PDT 24
Peak memory 244876 kb
Host smart-98ed5f37-43d7-485d-af73-792e80ee6d6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3662992317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3662992317
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2510673555
Short name T753
Test name
Test status
Simulation time 274376479 ps
CPU time 10.86 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:23:15 PM PDT 24
Peak memory 247796 kb
Host smart-d8e597e6-e3b9-41eb-beff-e8e8061111ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2510673555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2510673555
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1931189976
Short name T782
Test name
Test status
Simulation time 1651686309 ps
CPU time 119.29 seconds
Started Jun 11 02:23:01 PM PDT 24
Finished Jun 11 02:25:01 PM PDT 24
Peak memory 240032 kb
Host smart-3ad0a4c4-4d79-4689-a848-e990fe4ea8bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1931189976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1931189976
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3789274681
Short name T791
Test name
Test status
Simulation time 3144366191 ps
CPU time 126.71 seconds
Started Jun 11 02:23:01 PM PDT 24
Finished Jun 11 02:25:09 PM PDT 24
Peak memory 240168 kb
Host smart-25f7e837-271e-401f-a224-13986a411fbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3789274681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3789274681
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2218920952
Short name T742
Test name
Test status
Simulation time 103839606 ps
CPU time 10.8 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:23:15 PM PDT 24
Peak memory 240104 kb
Host smart-c29e4758-775d-44dc-bce9-7bd393f9b395
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2218920952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2218920952
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3850245982
Short name T796
Test name
Test status
Simulation time 408757173 ps
CPU time 7.82 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:23:11 PM PDT 24
Peak memory 239244 kb
Host smart-9a762c3e-011a-4302-b7f4-32fd132905e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850245982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3850245982
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3469110142
Short name T827
Test name
Test status
Simulation time 433550244 ps
CPU time 4.66 seconds
Started Jun 11 02:23:05 PM PDT 24
Finished Jun 11 02:23:11 PM PDT 24
Peak memory 235560 kb
Host smart-831b2474-e304-47a8-8710-6d28c703aef3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3469110142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3469110142
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4033561637
Short name T784
Test name
Test status
Simulation time 14973275 ps
CPU time 1.41 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:23:04 PM PDT 24
Peak memory 235740 kb
Host smart-55482420-d452-4415-b87b-9fbfefef7e91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4033561637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.4033561637
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3869923989
Short name T763
Test name
Test status
Simulation time 598902367 ps
CPU time 19.68 seconds
Started Jun 11 02:22:58 PM PDT 24
Finished Jun 11 02:23:18 PM PDT 24
Peak memory 243940 kb
Host smart-c2dd055d-8463-4a96-bfc4-3e0f47d5c086
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3869923989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3869923989
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3869921656
Short name T138
Test name
Test status
Simulation time 9185226914 ps
CPU time 278.65 seconds
Started Jun 11 02:22:58 PM PDT 24
Finished Jun 11 02:27:37 PM PDT 24
Peak memory 265048 kb
Host smart-bbdd9d5e-3bd5-4a54-857e-8fdae50e1e94
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869921656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3869921656
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3195520137
Short name T747
Test name
Test status
Simulation time 470736630 ps
CPU time 7.32 seconds
Started Jun 11 02:23:06 PM PDT 24
Finished Jun 11 02:23:14 PM PDT 24
Peak memory 248156 kb
Host smart-9f3ac553-bacd-4ea7-86ed-2cf1040e1f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3195520137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3195520137
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2432907721
Short name T720
Test name
Test status
Simulation time 80339919 ps
CPU time 6.59 seconds
Started Jun 11 02:23:13 PM PDT 24
Finished Jun 11 02:23:20 PM PDT 24
Peak memory 240176 kb
Host smart-a715a1fc-4cd0-4e1f-9b15-c24bab07fd52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432907721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2432907721
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2942047454
Short name T765
Test name
Test status
Simulation time 182591089 ps
CPU time 5.2 seconds
Started Jun 11 02:23:18 PM PDT 24
Finished Jun 11 02:23:24 PM PDT 24
Peak memory 236680 kb
Host smart-9993873a-43d9-41d3-9aff-bb608ca5d4f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2942047454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2942047454
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2655342443
Short name T788
Test name
Test status
Simulation time 10631788 ps
CPU time 1.28 seconds
Started Jun 11 02:23:15 PM PDT 24
Finished Jun 11 02:23:18 PM PDT 24
Peak memory 236640 kb
Host smart-50dcdae8-34fd-4774-bd56-6400c54214fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2655342443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2655342443
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3903197040
Short name T756
Test name
Test status
Simulation time 1881252154 ps
CPU time 41.83 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:24:06 PM PDT 24
Peak memory 244840 kb
Host smart-fcf1e9d0-5a9d-4407-8abd-15ec2dcadab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3903197040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3903197040
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3904191307
Short name T149
Test name
Test status
Simulation time 24602920647 ps
CPU time 456.4 seconds
Started Jun 11 02:23:18 PM PDT 24
Finished Jun 11 02:30:56 PM PDT 24
Peak memory 265116 kb
Host smart-723bddd6-e661-402d-b05e-d23847df4818
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904191307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3904191307
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1738743180
Short name T715
Test name
Test status
Simulation time 261429607 ps
CPU time 11.78 seconds
Started Jun 11 02:23:16 PM PDT 24
Finished Jun 11 02:23:29 PM PDT 24
Peak memory 247056 kb
Host smart-9743557e-6f80-470f-9303-a9e9b06efd5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1738743180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1738743180
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.4139130020
Short name T755
Test name
Test status
Simulation time 49203597 ps
CPU time 6.24 seconds
Started Jun 11 02:23:18 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 248372 kb
Host smart-fefe9a58-638c-408f-beaf-b827dc473ce6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139130020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.4139130020
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.165138320
Short name T721
Test name
Test status
Simulation time 148334513 ps
CPU time 8.89 seconds
Started Jun 11 02:23:11 PM PDT 24
Finished Jun 11 02:23:21 PM PDT 24
Peak memory 240092 kb
Host smart-1ab03c9d-ff0b-48bb-a8ee-ab57c1a81855
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=165138320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.165138320
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.47680196
Short name T809
Test name
Test status
Simulation time 12658657 ps
CPU time 1.5 seconds
Started Jun 11 02:23:18 PM PDT 24
Finished Jun 11 02:23:21 PM PDT 24
Peak memory 235756 kb
Host smart-4fa342b2-6a80-41a4-bffc-85a0d6092bdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=47680196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.47680196
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2584088690
Short name T196
Test name
Test status
Simulation time 498504589 ps
CPU time 20.24 seconds
Started Jun 11 02:23:10 PM PDT 24
Finished Jun 11 02:23:32 PM PDT 24
Peak memory 244868 kb
Host smart-c4d4c19c-876c-40ed-b69f-cd590ae1bcba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2584088690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2584088690
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.674159664
Short name T124
Test name
Test status
Simulation time 6501953927 ps
CPU time 182.67 seconds
Started Jun 11 02:23:19 PM PDT 24
Finished Jun 11 02:26:23 PM PDT 24
Peak memory 269552 kb
Host smart-ab5c36af-5f8d-485d-a39c-b7848c8c4c79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=674159664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.674159664
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4224656009
Short name T354
Test name
Test status
Simulation time 4345784449 ps
CPU time 331.9 seconds
Started Jun 11 02:23:12 PM PDT 24
Finished Jun 11 02:28:45 PM PDT 24
Peak memory 265200 kb
Host smart-a2b12e46-ea45-4314-a860-e6e3da6dc1b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224656009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.4224656009
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.4127586841
Short name T718
Test name
Test status
Simulation time 35542795 ps
CPU time 4.81 seconds
Started Jun 11 02:23:15 PM PDT 24
Finished Jun 11 02:23:21 PM PDT 24
Peak memory 248968 kb
Host smart-ab3baece-6333-44c5-846d-17c250e36308
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4127586841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.4127586841
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1833214590
Short name T182
Test name
Test status
Simulation time 770665562 ps
CPU time 14.88 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:38 PM PDT 24
Peak memory 249600 kb
Host smart-bfd8e589-a16c-4983-b5f8-e7f4e00d6a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833214590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1833214590
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.4100583079
Short name T806
Test name
Test status
Simulation time 127172275 ps
CPU time 5.78 seconds
Started Jun 11 02:23:15 PM PDT 24
Finished Jun 11 02:23:22 PM PDT 24
Peak memory 236664 kb
Host smart-adf0d403-379f-4043-aadc-df38bdec2c27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4100583079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.4100583079
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1981083948
Short name T767
Test name
Test status
Simulation time 8032808 ps
CPU time 1.44 seconds
Started Jun 11 02:23:16 PM PDT 24
Finished Jun 11 02:23:18 PM PDT 24
Peak memory 234700 kb
Host smart-e1bc84a1-0a51-4b6a-b3ad-ebbe639c0bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1981083948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1981083948
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1058740641
Short name T744
Test name
Test status
Simulation time 83237270 ps
CPU time 12.94 seconds
Started Jun 11 02:23:15 PM PDT 24
Finished Jun 11 02:23:29 PM PDT 24
Peak memory 248300 kb
Host smart-422446b9-ce74-4ffc-8874-ee587256460b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1058740641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1058740641
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2182077011
Short name T147
Test name
Test status
Simulation time 3158035759 ps
CPU time 217.83 seconds
Started Jun 11 02:23:12 PM PDT 24
Finished Jun 11 02:26:51 PM PDT 24
Peak memory 265212 kb
Host smart-5241be06-fc66-4075-a939-d95b22510e8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2182077011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2182077011
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.603065584
Short name T154
Test name
Test status
Simulation time 11638239039 ps
CPU time 727.12 seconds
Started Jun 11 02:23:16 PM PDT 24
Finished Jun 11 02:35:25 PM PDT 24
Peak memory 265280 kb
Host smart-8ccd9001-84fb-418c-bdf0-296704a33b14
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603065584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.603065584
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3092367169
Short name T793
Test name
Test status
Simulation time 195393060 ps
CPU time 6.27 seconds
Started Jun 11 02:23:19 PM PDT 24
Finished Jun 11 02:23:27 PM PDT 24
Peak memory 248308 kb
Host smart-e975e53e-d61b-4ef7-9345-ddc74fa1fa75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3092367169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3092367169
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1093986246
Short name T719
Test name
Test status
Simulation time 161696516 ps
CPU time 7.96 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:23:32 PM PDT 24
Peak memory 238772 kb
Host smart-6305c188-4dae-4ce0-abc8-e25a0b147551
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093986246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1093986246
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.4039648697
Short name T743
Test name
Test status
Simulation time 34302743 ps
CPU time 6 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:28 PM PDT 24
Peak memory 236680 kb
Host smart-1b9a98ed-4afe-45f1-9cfe-23816e75b598
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4039648697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.4039648697
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2846979884
Short name T803
Test name
Test status
Simulation time 14342103 ps
CPU time 1.37 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:25 PM PDT 24
Peak memory 236672 kb
Host smart-f411dd82-22a6-4665-b70b-d114b23ef17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2846979884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2846979884
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2174334440
Short name T775
Test name
Test status
Simulation time 1072150268 ps
CPU time 18.5 seconds
Started Jun 11 02:23:20 PM PDT 24
Finished Jun 11 02:23:40 PM PDT 24
Peak memory 240012 kb
Host smart-903acf5b-8538-4033-95ee-0c6dd18a5315
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2174334440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2174334440
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3712502596
Short name T125
Test name
Test status
Simulation time 28844160325 ps
CPU time 515.74 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:31:58 PM PDT 24
Peak memory 270412 kb
Host smart-81c8ef89-a979-4e9e-8e3c-1159e54072e5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712502596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3712502596
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2846826665
Short name T825
Test name
Test status
Simulation time 248451777 ps
CPU time 11.32 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:34 PM PDT 24
Peak memory 247472 kb
Host smart-81d70043-3296-4c1e-aeb8-5c9b4dab8aad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2846826665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2846826665
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2183397311
Short name T776
Test name
Test status
Simulation time 164958160 ps
CPU time 10.93 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:35 PM PDT 24
Peak memory 250672 kb
Host smart-81981242-c027-4267-916b-fc49ee578642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183397311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2183397311
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1008112972
Short name T198
Test name
Test status
Simulation time 130401989 ps
CPU time 10.55 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:34 PM PDT 24
Peak memory 240076 kb
Host smart-e64d8af4-f5cb-47ec-9767-93a8c0b88a5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1008112972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1008112972
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1247792754
Short name T724
Test name
Test status
Simulation time 373921638 ps
CPU time 18.43 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:23:43 PM PDT 24
Peak memory 244844 kb
Host smart-b8cf7649-fed3-40c7-89d6-b9f880af1c57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1247792754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1247792754
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4184817282
Short name T126
Test name
Test status
Simulation time 3139698344 ps
CPU time 89.83 seconds
Started Jun 11 02:23:27 PM PDT 24
Finished Jun 11 02:24:58 PM PDT 24
Peak memory 256916 kb
Host smart-eec5b73f-6b57-438c-9684-2a4e925e2928
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4184817282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.4184817282
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2502317269
Short name T135
Test name
Test status
Simulation time 12229837833 ps
CPU time 547.14 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:32:30 PM PDT 24
Peak memory 267176 kb
Host smart-c7c40c07-4e6a-4141-8a78-2f6ee7219c54
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502317269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2502317269
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2846840538
Short name T780
Test name
Test status
Simulation time 442545911 ps
CPU time 25.48 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:48 PM PDT 24
Peak memory 249376 kb
Host smart-d5d8a327-e1d3-4ac4-9233-1098f1bdc788
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2846840538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2846840538
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2536159648
Short name T161
Test name
Test status
Simulation time 2274230798 ps
CPU time 37.47 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:24:02 PM PDT 24
Peak memory 236760 kb
Host smart-a3af8b64-f581-4baf-ae92-d6d0488fa0ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2536159648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2536159648
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2451538660
Short name T745
Test name
Test status
Simulation time 34596414 ps
CPU time 4.88 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:23:30 PM PDT 24
Peak memory 240416 kb
Host smart-267d1258-6f81-4075-8167-04b50fb92fdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451538660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2451538660
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.4134303082
Short name T730
Test name
Test status
Simulation time 183070909 ps
CPU time 7.05 seconds
Started Jun 11 02:23:20 PM PDT 24
Finished Jun 11 02:23:28 PM PDT 24
Peak memory 235748 kb
Host smart-8fc5f399-7785-4f85-aeba-8377b0236e56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4134303082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.4134303082
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3595637498
Short name T729
Test name
Test status
Simulation time 9374718 ps
CPU time 1.46 seconds
Started Jun 11 02:23:19 PM PDT 24
Finished Jun 11 02:23:22 PM PDT 24
Peak memory 236692 kb
Host smart-8dffa145-36be-463c-9a21-bf79d26c5a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3595637498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3595637498
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3793957981
Short name T201
Test name
Test status
Simulation time 364835707 ps
CPU time 28.84 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:52 PM PDT 24
Peak memory 248480 kb
Host smart-2b27a3a4-ec47-49d8-8228-d4cec1db771c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3793957981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3793957981
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.117493664
Short name T145
Test name
Test status
Simulation time 4977424790 ps
CPU time 371.95 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:29:37 PM PDT 24
Peak memory 265004 kb
Host smart-771a0cb3-53c3-40a8-a8f1-d89d35d78f0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=117493664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.117493664
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2217810086
Short name T812
Test name
Test status
Simulation time 80830456 ps
CPU time 6.95 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:31 PM PDT 24
Peak memory 248352 kb
Host smart-bc825f97-4522-41f6-a546-53fba8162f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2217810086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2217810086
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4034606795
Short name T811
Test name
Test status
Simulation time 126387725 ps
CPU time 9.89 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:34 PM PDT 24
Peak memory 250432 kb
Host smart-a0a569da-c4b3-4994-9b8c-5693cd7ce5aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034606795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4034606795
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1660647212
Short name T764
Test name
Test status
Simulation time 62591162 ps
CPU time 3.39 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 238500 kb
Host smart-5813b728-aa9c-4308-a67d-fee6fdb244c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1660647212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1660647212
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1429795201
Short name T750
Test name
Test status
Simulation time 8596348 ps
CPU time 1.6 seconds
Started Jun 11 02:23:24 PM PDT 24
Finished Jun 11 02:23:27 PM PDT 24
Peak memory 236692 kb
Host smart-f6da0cdd-bc39-433b-9a21-a69b8f369249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1429795201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1429795201
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.907952204
Short name T821
Test name
Test status
Simulation time 530371713 ps
CPU time 40.9 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:24:06 PM PDT 24
Peak memory 244840 kb
Host smart-fb7b6812-75b4-41ec-9871-aefdda1e577d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=907952204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.907952204
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2500887441
Short name T143
Test name
Test status
Simulation time 17844999034 ps
CPU time 339.54 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:29:02 PM PDT 24
Peak memory 265020 kb
Host smart-f9489eb1-bc96-4d0e-a5c2-9de4fc4d601c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2500887441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2500887441
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1974613870
Short name T146
Test name
Test status
Simulation time 27761507728 ps
CPU time 507.26 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:31:52 PM PDT 24
Peak memory 272464 kb
Host smart-56413585-6ff6-4d32-a3e4-03cf5e39d098
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974613870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1974613870
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3104094112
Short name T816
Test name
Test status
Simulation time 148720905 ps
CPU time 11.11 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:36 PM PDT 24
Peak memory 248372 kb
Host smart-e93fa583-02e9-4fa4-b348-436d406ba6c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3104094112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3104094112
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3855811305
Short name T773
Test name
Test status
Simulation time 491271309 ps
CPU time 5.15 seconds
Started Jun 11 02:23:19 PM PDT 24
Finished Jun 11 02:23:25 PM PDT 24
Peak memory 239772 kb
Host smart-f97141fb-c11f-4797-b9af-7206ed75c8e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855811305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3855811305
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1964854437
Short name T762
Test name
Test status
Simulation time 59527770 ps
CPU time 4.63 seconds
Started Jun 11 02:23:27 PM PDT 24
Finished Jun 11 02:23:33 PM PDT 24
Peak memory 238484 kb
Host smart-ccd00123-8543-4e34-b543-654c904a6191
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1964854437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1964854437
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2409017156
Short name T832
Test name
Test status
Simulation time 15199757 ps
CPU time 1.51 seconds
Started Jun 11 02:23:27 PM PDT 24
Finished Jun 11 02:23:30 PM PDT 24
Peak memory 236712 kb
Host smart-e35c2699-d138-499c-8e14-27f2250aeea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2409017156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2409017156
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2511165900
Short name T195
Test name
Test status
Simulation time 752859053 ps
CPU time 21.94 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:45 PM PDT 24
Peak memory 244888 kb
Host smart-aea5c1a9-1ea3-4905-a30f-b0e1ae579611
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2511165900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2511165900
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1721765706
Short name T734
Test name
Test status
Simulation time 123248818 ps
CPU time 9.09 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:33 PM PDT 24
Peak memory 248148 kb
Host smart-f189ea3e-1825-4eeb-887e-e975d62e80a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1721765706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1721765706
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4064374732
Short name T740
Test name
Test status
Simulation time 135548270 ps
CPU time 11 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:23:36 PM PDT 24
Peak memory 242480 kb
Host smart-e3882d04-8655-4b8b-a5fd-e30697398586
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064374732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4064374732
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2394507864
Short name T197
Test name
Test status
Simulation time 112194491 ps
CPU time 5.64 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:28 PM PDT 24
Peak memory 236616 kb
Host smart-e32bfdbf-d72f-4244-9b9a-bcfb63174316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2394507864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2394507864
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2501166584
Short name T345
Test name
Test status
Simulation time 11144284 ps
CPU time 1.39 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:25 PM PDT 24
Peak memory 235752 kb
Host smart-a519598c-039f-4410-8833-e3359cab1e81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2501166584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2501166584
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2096549507
Short name T808
Test name
Test status
Simulation time 347271746 ps
CPU time 27.07 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:50 PM PDT 24
Peak memory 248224 kb
Host smart-fda76d93-6980-4da1-9d65-dfca143bb244
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2096549507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2096549507
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.688367599
Short name T139
Test name
Test status
Simulation time 4074701831 ps
CPU time 338.24 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:29:02 PM PDT 24
Peak memory 266148 kb
Host smart-75427eec-e076-4e66-b0e9-89baed98e73d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=688367599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.688367599
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1971411688
Short name T713
Test name
Test status
Simulation time 194855364 ps
CPU time 13.19 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:37 PM PDT 24
Peak memory 248356 kb
Host smart-b9a37ea5-bfdf-431a-813c-29a6db2633ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1971411688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1971411688
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1568593676
Short name T823
Test name
Test status
Simulation time 346748284 ps
CPU time 7.78 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:31 PM PDT 24
Peak memory 240132 kb
Host smart-7297e015-ef74-453c-b1c2-1dcf995e0695
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568593676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1568593676
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2923100097
Short name T768
Test name
Test status
Simulation time 38809730 ps
CPU time 5.47 seconds
Started Jun 11 02:23:24 PM PDT 24
Finished Jun 11 02:23:31 PM PDT 24
Peak memory 235720 kb
Host smart-4b19f9bf-1f64-4cf1-bb79-75a58e7d3f6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2923100097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2923100097
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3419589741
Short name T737
Test name
Test status
Simulation time 8929303 ps
CPU time 1.46 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:25 PM PDT 24
Peak memory 235724 kb
Host smart-c57f8468-de28-4e74-b401-acb4388f311d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3419589741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3419589741
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.863078746
Short name T746
Test name
Test status
Simulation time 184060898 ps
CPU time 25.01 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:47 PM PDT 24
Peak memory 244872 kb
Host smart-b6f5402d-ecc9-4218-90fa-ecc9276dee62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=863078746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.863078746
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2189562568
Short name T157
Test name
Test status
Simulation time 781216462 ps
CPU time 107.72 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:25:12 PM PDT 24
Peak memory 266008 kb
Host smart-c514336b-1aa9-42ac-bfbe-3eb07b6dc8bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2189562568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2189562568
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3613253996
Short name T819
Test name
Test status
Simulation time 23452446 ps
CPU time 3.24 seconds
Started Jun 11 02:23:21 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 239924 kb
Host smart-79a5c289-f024-4628-b7b9-bf77962c77bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3613253996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3613253996
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3164808236
Short name T774
Test name
Test status
Simulation time 2674209145 ps
CPU time 163.81 seconds
Started Jun 11 02:23:00 PM PDT 24
Finished Jun 11 02:25:44 PM PDT 24
Peak memory 241176 kb
Host smart-70c8825d-5741-447f-92c4-fb0e21011301
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3164808236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3164808236
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3970126277
Short name T820
Test name
Test status
Simulation time 34222515553 ps
CPU time 476.01 seconds
Started Jun 11 02:22:58 PM PDT 24
Finished Jun 11 02:30:55 PM PDT 24
Peak memory 240108 kb
Host smart-7a673960-2243-4c49-8cc2-7618807a8640
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3970126277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3970126277
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3227557467
Short name T162
Test name
Test status
Simulation time 382352237 ps
CPU time 9.96 seconds
Started Jun 11 02:23:00 PM PDT 24
Finished Jun 11 02:23:11 PM PDT 24
Peak memory 240008 kb
Host smart-ce28e131-b800-4f8b-9a81-33efb7f97ef2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3227557467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3227557467
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3037565203
Short name T727
Test name
Test status
Simulation time 574608842 ps
CPU time 12.15 seconds
Started Jun 11 02:23:01 PM PDT 24
Finished Jun 11 02:23:14 PM PDT 24
Peak memory 243652 kb
Host smart-9d3ee4a4-78e6-4093-b2bd-2d68bd802bdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037565203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3037565203
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1448833609
Short name T751
Test name
Test status
Simulation time 50742000 ps
CPU time 4.94 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:23:09 PM PDT 24
Peak memory 235752 kb
Host smart-3355d022-bff9-4621-8b63-eac93ce0eeae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1448833609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1448833609
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.310258910
Short name T352
Test name
Test status
Simulation time 13190809 ps
CPU time 1.39 seconds
Started Jun 11 02:22:59 PM PDT 24
Finished Jun 11 02:23:02 PM PDT 24
Peak memory 235692 kb
Host smart-5142b4ef-3eac-451e-a759-d8d18ba222dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=310258910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.310258910
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2280145093
Short name T829
Test name
Test status
Simulation time 299969489 ps
CPU time 21.96 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 243960 kb
Host smart-6ca73d43-32f9-4b77-8c77-8fd5ae10163a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2280145093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2280145093
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2645192207
Short name T152
Test name
Test status
Simulation time 10359218759 ps
CPU time 205.54 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:26:29 PM PDT 24
Peak memory 273032 kb
Host smart-43af7846-f59e-4901-8e4a-25db043bcc15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2645192207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2645192207
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3407185283
Short name T156
Test name
Test status
Simulation time 13528260501 ps
CPU time 986.06 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:39:30 PM PDT 24
Peak memory 265132 kb
Host smart-cade184f-43e7-4598-b4ac-99939950dc73
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407185283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3407185283
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1235820123
Short name T789
Test name
Test status
Simulation time 96262146 ps
CPU time 8.1 seconds
Started Jun 11 02:22:57 PM PDT 24
Finished Jun 11 02:23:06 PM PDT 24
Peak memory 248276 kb
Host smart-e0305192-820d-47bd-844a-f1303b580b7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1235820123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1235820123
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2961778697
Short name T736
Test name
Test status
Simulation time 23969354 ps
CPU time 1.35 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 235736 kb
Host smart-837119bf-c978-417e-b6e8-4fc300829834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2961778697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2961778697
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.165918373
Short name T350
Test name
Test status
Simulation time 18441295 ps
CPU time 1.48 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 236668 kb
Host smart-8de13db5-16f7-4fda-b62b-5a7d464c19fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=165918373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.165918373
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4095081318
Short name T822
Test name
Test status
Simulation time 10615121 ps
CPU time 1.61 seconds
Started Jun 11 02:23:27 PM PDT 24
Finished Jun 11 02:23:30 PM PDT 24
Peak memory 236712 kb
Host smart-94d522d3-d379-4bd6-b274-6bad8a187666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4095081318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4095081318
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.827189575
Short name T738
Test name
Test status
Simulation time 8771924 ps
CPU time 1.42 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 236592 kb
Host smart-7c5a123a-1440-4e29-a4ec-84425f09f867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=827189575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.827189575
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.4021140082
Short name T831
Test name
Test status
Simulation time 10439915 ps
CPU time 1.46 seconds
Started Jun 11 02:23:20 PM PDT 24
Finished Jun 11 02:23:23 PM PDT 24
Peak memory 234676 kb
Host smart-16bc466b-410e-4df7-ad00-ada32670224c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4021140082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.4021140082
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1897098158
Short name T757
Test name
Test status
Simulation time 10707140 ps
CPU time 1.22 seconds
Started Jun 11 02:23:20 PM PDT 24
Finished Jun 11 02:23:22 PM PDT 24
Peak memory 235772 kb
Host smart-07dda27d-6fd3-4bb6-b569-1ae247d31325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1897098158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1897098158
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2845146702
Short name T733
Test name
Test status
Simulation time 11290878 ps
CPU time 1.59 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 235772 kb
Host smart-c49dbeae-1b4e-40fa-ac60-38211996d1dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2845146702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2845146702
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1513442140
Short name T800
Test name
Test status
Simulation time 21435712 ps
CPU time 1.56 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 236676 kb
Host smart-1772ead4-4c40-4074-b81f-9252e284d296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1513442140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1513442140
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1879116093
Short name T735
Test name
Test status
Simulation time 8365370 ps
CPU time 1.53 seconds
Started Jun 11 02:23:35 PM PDT 24
Finished Jun 11 02:23:38 PM PDT 24
Peak memory 234664 kb
Host smart-a2c0b362-9f09-495a-99a7-a7db8b43dcb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1879116093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1879116093
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.167658201
Short name T792
Test name
Test status
Simulation time 15338991 ps
CPU time 1.4 seconds
Started Jun 11 02:23:32 PM PDT 24
Finished Jun 11 02:23:34 PM PDT 24
Peak memory 236684 kb
Host smart-05c6e8d0-c507-4dde-a9bf-16efeab2db86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=167658201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.167658201
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1702467052
Short name T771
Test name
Test status
Simulation time 7113434637 ps
CPU time 140.43 seconds
Started Jun 11 02:23:04 PM PDT 24
Finished Jun 11 02:25:26 PM PDT 24
Peak memory 236752 kb
Host smart-df254f65-772b-43b7-a6ee-addf030937e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1702467052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1702467052
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1857000988
Short name T772
Test name
Test status
Simulation time 22791943490 ps
CPU time 440.04 seconds
Started Jun 11 02:23:05 PM PDT 24
Finished Jun 11 02:30:26 PM PDT 24
Peak memory 236704 kb
Host smart-9a7448ef-8bad-4e1a-9fb1-564ad9de5f52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1857000988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1857000988
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4011296170
Short name T797
Test name
Test status
Simulation time 22054982 ps
CPU time 4.15 seconds
Started Jun 11 02:23:00 PM PDT 24
Finished Jun 11 02:23:05 PM PDT 24
Peak memory 240100 kb
Host smart-42c59609-2248-4269-be91-d9f076542b34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4011296170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.4011296170
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2237682452
Short name T783
Test name
Test status
Simulation time 266995188 ps
CPU time 10.86 seconds
Started Jun 11 02:23:04 PM PDT 24
Finished Jun 11 02:23:16 PM PDT 24
Peak memory 256412 kb
Host smart-59558d5e-c798-4ac2-827f-baca06f90f55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237682452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2237682452
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3504646650
Short name T777
Test name
Test status
Simulation time 63758406 ps
CPU time 3.36 seconds
Started Jun 11 02:23:04 PM PDT 24
Finished Jun 11 02:23:09 PM PDT 24
Peak memory 236680 kb
Host smart-d03caf9d-7d79-4fbf-9cde-3dc31101e103
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3504646650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3504646650
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2258299112
Short name T818
Test name
Test status
Simulation time 1677484443 ps
CPU time 45.13 seconds
Started Jun 11 02:23:06 PM PDT 24
Finished Jun 11 02:23:53 PM PDT 24
Peak memory 244840 kb
Host smart-3ece416d-ad2e-4947-bbd3-481b9ff440d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2258299112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2258299112
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2912647539
Short name T132
Test name
Test status
Simulation time 5706363611 ps
CPU time 380.19 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:29:23 PM PDT 24
Peak memory 265108 kb
Host smart-a953e3ee-f449-42cb-be3b-98b46d9c2cc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2912647539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2912647539
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2598713545
Short name T795
Test name
Test status
Simulation time 341734978 ps
CPU time 8.8 seconds
Started Jun 11 02:22:59 PM PDT 24
Finished Jun 11 02:23:09 PM PDT 24
Peak memory 252224 kb
Host smart-0118d87f-4d3e-4351-8a3f-04634534f8bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2598713545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2598713545
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3759042333
Short name T830
Test name
Test status
Simulation time 10054731 ps
CPU time 1.43 seconds
Started Jun 11 02:23:33 PM PDT 24
Finished Jun 11 02:23:35 PM PDT 24
Peak memory 236664 kb
Host smart-82848911-8244-4152-8b24-4d0542f4cc64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3759042333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3759042333
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3424624414
Short name T164
Test name
Test status
Simulation time 7576733 ps
CPU time 1.51 seconds
Started Jun 11 02:23:35 PM PDT 24
Finished Jun 11 02:23:37 PM PDT 24
Peak memory 234684 kb
Host smart-ba725d54-171e-419c-9b46-79ae6ab526ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3424624414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3424624414
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3708154938
Short name T749
Test name
Test status
Simulation time 10817725 ps
CPU time 1.34 seconds
Started Jun 11 02:23:33 PM PDT 24
Finished Jun 11 02:23:35 PM PDT 24
Peak memory 234704 kb
Host smart-57396499-8053-4146-8454-ebb12401de2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3708154938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3708154938
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.173415908
Short name T752
Test name
Test status
Simulation time 22239043 ps
CPU time 1.34 seconds
Started Jun 11 02:23:35 PM PDT 24
Finished Jun 11 02:23:37 PM PDT 24
Peak memory 236676 kb
Host smart-253e5153-505d-4a7f-8db7-fd3a8e6dc495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=173415908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.173415908
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.985945491
Short name T801
Test name
Test status
Simulation time 24745812 ps
CPU time 1.52 seconds
Started Jun 11 02:23:33 PM PDT 24
Finished Jun 11 02:23:35 PM PDT 24
Peak memory 235732 kb
Host smart-438ecbb1-2101-43aa-9228-20b3841ca662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=985945491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.985945491
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2990601310
Short name T769
Test name
Test status
Simulation time 25883804 ps
CPU time 1.48 seconds
Started Jun 11 02:23:31 PM PDT 24
Finished Jun 11 02:23:33 PM PDT 24
Peak memory 236712 kb
Host smart-a0faba41-6dca-40e4-8cec-a72cc0fce3ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2990601310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2990601310
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2523836951
Short name T758
Test name
Test status
Simulation time 9723257 ps
CPU time 1.58 seconds
Started Jun 11 02:23:31 PM PDT 24
Finished Jun 11 02:23:33 PM PDT 24
Peak memory 236692 kb
Host smart-3b8e586c-1a8d-4faa-8212-41c9d00ed128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2523836951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2523836951
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.628369476
Short name T760
Test name
Test status
Simulation time 6219696 ps
CPU time 1.4 seconds
Started Jun 11 02:23:31 PM PDT 24
Finished Jun 11 02:23:33 PM PDT 24
Peak memory 236636 kb
Host smart-7f958367-451a-49f4-baf3-267397c44b4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=628369476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.628369476
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2555561319
Short name T351
Test name
Test status
Simulation time 9880811 ps
CPU time 1.29 seconds
Started Jun 11 02:23:30 PM PDT 24
Finished Jun 11 02:23:32 PM PDT 24
Peak memory 236720 kb
Host smart-fd5940e6-8cd1-41b9-a586-e57662abf709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2555561319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2555561319
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1504543984
Short name T731
Test name
Test status
Simulation time 84772888 ps
CPU time 1.58 seconds
Started Jun 11 02:23:32 PM PDT 24
Finished Jun 11 02:23:34 PM PDT 24
Peak memory 235764 kb
Host smart-428febf3-92d0-48d8-ab0c-f76c7ccb18bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1504543984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1504543984
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1178562857
Short name T194
Test name
Test status
Simulation time 6949657604 ps
CPU time 84.66 seconds
Started Jun 11 02:23:03 PM PDT 24
Finished Jun 11 02:24:29 PM PDT 24
Peak memory 236644 kb
Host smart-0e85cbce-5a7a-4d91-9b90-fbd40062a65c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1178562857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1178562857
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.509179357
Short name T799
Test name
Test status
Simulation time 374708195 ps
CPU time 6.19 seconds
Started Jun 11 02:23:05 PM PDT 24
Finished Jun 11 02:23:13 PM PDT 24
Peak memory 240028 kb
Host smart-79d41c70-c1a0-46a3-8811-ba4e189224c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=509179357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.509179357
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3863085609
Short name T716
Test name
Test status
Simulation time 65561003 ps
CPU time 5.2 seconds
Started Jun 11 02:23:05 PM PDT 24
Finished Jun 11 02:23:12 PM PDT 24
Peak memory 249356 kb
Host smart-214afa1a-5106-4033-9117-bbbd41278c2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863085609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3863085609
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3022268860
Short name T183
Test name
Test status
Simulation time 64508247 ps
CPU time 5.27 seconds
Started Jun 11 02:23:02 PM PDT 24
Finished Jun 11 02:23:09 PM PDT 24
Peak memory 236564 kb
Host smart-05fadaf1-4e8c-4a96-afd9-fa0ad3e87da9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3022268860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3022268860
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.742065390
Short name T814
Test name
Test status
Simulation time 23092664 ps
CPU time 1.46 seconds
Started Jun 11 02:23:04 PM PDT 24
Finished Jun 11 02:23:07 PM PDT 24
Peak memory 234708 kb
Host smart-22600c01-d281-4cad-9584-7e07997b7cb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=742065390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.742065390
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2051832373
Short name T759
Test name
Test status
Simulation time 357150167 ps
CPU time 23.43 seconds
Started Jun 11 02:23:01 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 244860 kb
Host smart-6174e2d7-3e84-4042-9dcd-298be6d99e88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2051832373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2051832373
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2155594274
Short name T770
Test name
Test status
Simulation time 1017974540 ps
CPU time 9.39 seconds
Started Jun 11 02:23:05 PM PDT 24
Finished Jun 11 02:23:16 PM PDT 24
Peak memory 247916 kb
Host smart-6149e262-bce9-497e-8e6c-2492e0691039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2155594274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2155594274
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1355056442
Short name T828
Test name
Test status
Simulation time 13748855 ps
CPU time 1.38 seconds
Started Jun 11 02:23:33 PM PDT 24
Finished Jun 11 02:23:35 PM PDT 24
Peak memory 236724 kb
Host smart-c2cbee50-5e01-4654-90d3-b03a3c8ee339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1355056442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1355056442
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3029167908
Short name T728
Test name
Test status
Simulation time 17791583 ps
CPU time 1.41 seconds
Started Jun 11 02:23:30 PM PDT 24
Finished Jun 11 02:23:33 PM PDT 24
Peak memory 235768 kb
Host smart-1c839c8a-e7f5-44e7-9a55-715871334b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3029167908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3029167908
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1763699145
Short name T786
Test name
Test status
Simulation time 12777598 ps
CPU time 1.45 seconds
Started Jun 11 02:23:31 PM PDT 24
Finished Jun 11 02:23:34 PM PDT 24
Peak memory 236716 kb
Host smart-0ca0ba3c-3a40-4c2f-9133-d7528488fb1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1763699145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1763699145
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1972567943
Short name T347
Test name
Test status
Simulation time 10668461 ps
CPU time 1.65 seconds
Started Jun 11 02:23:32 PM PDT 24
Finished Jun 11 02:23:35 PM PDT 24
Peak memory 236656 kb
Host smart-be7eeecf-e497-4c28-b461-72232f5b54bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1972567943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1972567943
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2257803243
Short name T344
Test name
Test status
Simulation time 14507887 ps
CPU time 1.39 seconds
Started Jun 11 02:23:32 PM PDT 24
Finished Jun 11 02:23:35 PM PDT 24
Peak memory 236640 kb
Host smart-7e4e454e-5251-47d7-9e2c-7600ec17a60b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2257803243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2257803243
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2223518061
Short name T726
Test name
Test status
Simulation time 13917653 ps
CPU time 1.63 seconds
Started Jun 11 02:23:33 PM PDT 24
Finished Jun 11 02:23:36 PM PDT 24
Peak memory 236688 kb
Host smart-1ae786a4-247c-40cc-a6f3-b0f68d04419c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2223518061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2223518061
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3075268244
Short name T794
Test name
Test status
Simulation time 9331875 ps
CPU time 1.4 seconds
Started Jun 11 02:23:33 PM PDT 24
Finished Jun 11 02:23:36 PM PDT 24
Peak memory 234716 kb
Host smart-784bf2d4-98f3-4803-b14d-ddab1caa98d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3075268244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3075268244
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3733743095
Short name T163
Test name
Test status
Simulation time 8584700 ps
CPU time 1.48 seconds
Started Jun 11 02:23:31 PM PDT 24
Finished Jun 11 02:23:33 PM PDT 24
Peak memory 236700 kb
Host smart-127cb8b3-7dbb-49e7-a77b-dae5c3a148f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3733743095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3733743095
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1588169374
Short name T802
Test name
Test status
Simulation time 7986271 ps
CPU time 1.51 seconds
Started Jun 11 02:23:35 PM PDT 24
Finished Jun 11 02:23:37 PM PDT 24
Peak memory 234644 kb
Host smart-24d6ab69-1769-4cb4-97d3-130b3d24dfd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1588169374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1588169374
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.696617640
Short name T790
Test name
Test status
Simulation time 11314536 ps
CPU time 1.59 seconds
Started Jun 11 02:23:32 PM PDT 24
Finished Jun 11 02:23:35 PM PDT 24
Peak memory 235696 kb
Host smart-424666c7-b29a-49cc-abb6-182222c1c71e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=696617640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.696617640
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2961060475
Short name T754
Test name
Test status
Simulation time 170827998 ps
CPU time 6.49 seconds
Started Jun 11 02:23:05 PM PDT 24
Finished Jun 11 02:23:13 PM PDT 24
Peak memory 239016 kb
Host smart-535c1094-613b-473c-887f-f10673ff1666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961060475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2961060475
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.29499880
Short name T199
Test name
Test status
Simulation time 1255832341 ps
CPU time 6.08 seconds
Started Jun 11 02:23:03 PM PDT 24
Finished Jun 11 02:23:11 PM PDT 24
Peak memory 239252 kb
Host smart-2dbfcb27-1853-4964-bd0d-993532aea1ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=29499880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.29499880
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1930963630
Short name T805
Test name
Test status
Simulation time 35738120 ps
CPU time 1.3 seconds
Started Jun 11 02:23:04 PM PDT 24
Finished Jun 11 02:23:07 PM PDT 24
Peak memory 236684 kb
Host smart-ea065c09-6606-461d-9c53-50860ea2b01f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1930963630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1930963630
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2879530761
Short name T798
Test name
Test status
Simulation time 1553468684 ps
CPU time 25.82 seconds
Started Jun 11 02:23:04 PM PDT 24
Finished Jun 11 02:23:31 PM PDT 24
Peak memory 248292 kb
Host smart-850d4bae-3845-4fbf-9adc-f085eb30fd67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2879530761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2879530761
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.4283005676
Short name T158
Test name
Test status
Simulation time 54794839309 ps
CPU time 1071.34 seconds
Started Jun 11 02:23:03 PM PDT 24
Finished Jun 11 02:40:56 PM PDT 24
Peak memory 265000 kb
Host smart-2d1db63f-dc35-418b-ae4a-50d9528e8ea4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283005676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.4283005676
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.4079091383
Short name T732
Test name
Test status
Simulation time 154189249 ps
CPU time 11.7 seconds
Started Jun 11 02:23:04 PM PDT 24
Finished Jun 11 02:23:17 PM PDT 24
Peak memory 248180 kb
Host smart-d4374a1a-af17-4977-9e15-944d22e2892c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4079091383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.4079091383
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3974211729
Short name T804
Test name
Test status
Simulation time 598774575 ps
CPU time 10.88 seconds
Started Jun 11 02:23:10 PM PDT 24
Finished Jun 11 02:23:22 PM PDT 24
Peak memory 248304 kb
Host smart-a617c27a-8231-48fc-b8e5-738167821ba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974211729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3974211729
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.4293365685
Short name T355
Test name
Test status
Simulation time 123076020 ps
CPU time 6.67 seconds
Started Jun 11 02:23:14 PM PDT 24
Finished Jun 11 02:23:22 PM PDT 24
Peak memory 236668 kb
Host smart-486249dd-4151-4ed8-823e-463f7351fe02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4293365685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.4293365685
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.4151986433
Short name T348
Test name
Test status
Simulation time 7017897 ps
CPU time 1.27 seconds
Started Jun 11 02:23:11 PM PDT 24
Finished Jun 11 02:23:13 PM PDT 24
Peak memory 236684 kb
Host smart-e407d13b-c049-4de4-8fd4-fdc74f6fac00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4151986433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.4151986433
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2350711567
Short name T202
Test name
Test status
Simulation time 537662939 ps
CPU time 18.19 seconds
Started Jun 11 02:23:14 PM PDT 24
Finished Jun 11 02:23:33 PM PDT 24
Peak memory 243952 kb
Host smart-8b65b3ac-3eb2-474c-a463-e0128d7a5ebb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2350711567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2350711567
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2102458250
Short name T127
Test name
Test status
Simulation time 5220250680 ps
CPU time 339.26 seconds
Started Jun 11 02:23:18 PM PDT 24
Finished Jun 11 02:28:59 PM PDT 24
Peak memory 265264 kb
Host smart-265f9bb1-67ca-428b-ae78-6d67a49d6aa6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2102458250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2102458250
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2878774732
Short name T130
Test name
Test status
Simulation time 2195474669 ps
CPU time 305.82 seconds
Started Jun 11 02:23:14 PM PDT 24
Finished Jun 11 02:28:21 PM PDT 24
Peak memory 265104 kb
Host smart-06025816-107f-4d7e-8500-d5dfb1286a20
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878774732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2878774732
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.296462674
Short name T714
Test name
Test status
Simulation time 39655472 ps
CPU time 4.96 seconds
Started Jun 11 02:23:13 PM PDT 24
Finished Jun 11 02:23:19 PM PDT 24
Peak memory 251900 kb
Host smart-e72b46c7-b72c-4e3d-982e-b05394186190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=296462674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.296462674
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.59651468
Short name T184
Test name
Test status
Simulation time 294192526 ps
CPU time 10.36 seconds
Started Jun 11 02:23:10 PM PDT 24
Finished Jun 11 02:23:21 PM PDT 24
Peak memory 240124 kb
Host smart-043fe208-8100-488c-b5c6-832f5d5db0b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59651468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.alert_handler_csr_mem_rw_with_rand_reset.59651468
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3909566179
Short name T761
Test name
Test status
Simulation time 136071096 ps
CPU time 8.89 seconds
Started Jun 11 02:23:14 PM PDT 24
Finished Jun 11 02:23:24 PM PDT 24
Peak memory 236680 kb
Host smart-fc6135af-d134-4f4c-af50-fd6ef0c7ee15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3909566179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3909566179
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1764619133
Short name T778
Test name
Test status
Simulation time 22961239 ps
CPU time 1.27 seconds
Started Jun 11 02:23:15 PM PDT 24
Finished Jun 11 02:23:18 PM PDT 24
Peak memory 235660 kb
Host smart-1165ec4d-ed33-4132-abef-af9a07543cbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1764619133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1764619133
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2810146907
Short name T817
Test name
Test status
Simulation time 2013617699 ps
CPU time 38.72 seconds
Started Jun 11 02:23:10 PM PDT 24
Finished Jun 11 02:23:50 PM PDT 24
Peak memory 248136 kb
Host smart-4ac3ce6e-7f43-451c-b945-66e183bda723
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2810146907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2810146907
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1768112494
Short name T151
Test name
Test status
Simulation time 1174684819 ps
CPU time 123.46 seconds
Started Jun 11 02:23:11 PM PDT 24
Finished Jun 11 02:25:16 PM PDT 24
Peak memory 265100 kb
Host smart-b3c25666-e02d-46be-8c9f-1de5db540a81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1768112494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1768112494
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2285201986
Short name T142
Test name
Test status
Simulation time 42454131154 ps
CPU time 532.87 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:32:17 PM PDT 24
Peak memory 267540 kb
Host smart-8bc2c241-f813-422f-9e3e-dab2da8cdbcf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285201986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2285201986
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2261545757
Short name T741
Test name
Test status
Simulation time 367997600 ps
CPU time 5.23 seconds
Started Jun 11 02:23:12 PM PDT 24
Finished Jun 11 02:23:19 PM PDT 24
Peak memory 248360 kb
Host smart-e7eda6d5-d8f0-45bc-81c4-edcfacfc03d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2261545757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2261545757
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3480796242
Short name T787
Test name
Test status
Simulation time 262398905 ps
CPU time 7.59 seconds
Started Jun 11 02:23:19 PM PDT 24
Finished Jun 11 02:23:28 PM PDT 24
Peak memory 240208 kb
Host smart-0b687acf-4edc-451b-a909-c1a82846a0a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480796242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3480796242
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.475214799
Short name T781
Test name
Test status
Simulation time 91168146 ps
CPU time 5.17 seconds
Started Jun 11 02:23:11 PM PDT 24
Finished Jun 11 02:23:17 PM PDT 24
Peak memory 236688 kb
Host smart-858f613b-4dfb-4cd3-a700-aa0147d0ac00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=475214799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.475214799
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1843864736
Short name T725
Test name
Test status
Simulation time 9896441 ps
CPU time 1.31 seconds
Started Jun 11 02:23:18 PM PDT 24
Finished Jun 11 02:23:21 PM PDT 24
Peak memory 234712 kb
Host smart-91e3f112-a9ef-47f4-8ebc-ae9d619c5e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1843864736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1843864736
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3111991769
Short name T722
Test name
Test status
Simulation time 418475154 ps
CPU time 12.44 seconds
Started Jun 11 02:23:12 PM PDT 24
Finished Jun 11 02:23:25 PM PDT 24
Peak memory 248308 kb
Host smart-6e389493-0050-434d-8996-984d6a5977b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3111991769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3111991769
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.79671591
Short name T141
Test name
Test status
Simulation time 2000514922 ps
CPU time 130.48 seconds
Started Jun 11 02:23:15 PM PDT 24
Finished Jun 11 02:25:26 PM PDT 24
Peak memory 256856 kb
Host smart-75515977-47a8-423b-9c8e-8c9b7897fa4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=79671591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors
.79671591
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.238356847
Short name T155
Test name
Test status
Simulation time 3236979379 ps
CPU time 387.46 seconds
Started Jun 11 02:23:10 PM PDT 24
Finished Jun 11 02:29:38 PM PDT 24
Peak memory 267680 kb
Host smart-2e80d709-8540-4a74-a078-374d0346a787
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238356847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.238356847
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3717320408
Short name T717
Test name
Test status
Simulation time 355662606 ps
CPU time 25.03 seconds
Started Jun 11 02:23:18 PM PDT 24
Finished Jun 11 02:23:45 PM PDT 24
Peak memory 248276 kb
Host smart-4bd5f395-782e-41c2-ae08-ab3241be1d18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3717320408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3717320408
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3842669432
Short name T785
Test name
Test status
Simulation time 156437031 ps
CPU time 5.78 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:30 PM PDT 24
Peak memory 238344 kb
Host smart-02c8fb1f-eafa-43fd-ba9e-d08214fa0877
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842669432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3842669432
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2935433237
Short name T779
Test name
Test status
Simulation time 111918365 ps
CPU time 5.07 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:23:29 PM PDT 24
Peak memory 238136 kb
Host smart-2eaf0efc-aa55-44a6-98af-05fffe431750
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2935433237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2935433237
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3883973762
Short name T739
Test name
Test status
Simulation time 7492190 ps
CPU time 1.32 seconds
Started Jun 11 02:23:15 PM PDT 24
Finished Jun 11 02:23:17 PM PDT 24
Peak memory 236624 kb
Host smart-60dbdba2-a5f9-4962-91eb-7ab30524035d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3883973762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3883973762
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.85082920
Short name T766
Test name
Test status
Simulation time 1983150087 ps
CPU time 39.81 seconds
Started Jun 11 02:23:23 PM PDT 24
Finished Jun 11 02:24:04 PM PDT 24
Peak memory 248216 kb
Host smart-a293360d-610d-42af-ab7f-ce86c9cea66a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=85082920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outst
anding.85082920
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2459325957
Short name T813
Test name
Test status
Simulation time 6323029797 ps
CPU time 177.91 seconds
Started Jun 11 02:23:22 PM PDT 24
Finished Jun 11 02:26:22 PM PDT 24
Peak memory 265088 kb
Host smart-ac531da9-b3f8-45c2-83b4-e966e56d3d5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2459325957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2459325957
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.509956556
Short name T353
Test name
Test status
Simulation time 11911418081 ps
CPU time 462.75 seconds
Started Jun 11 02:23:13 PM PDT 24
Finished Jun 11 02:30:57 PM PDT 24
Peak memory 267548 kb
Host smart-f02388da-c700-4cf8-9e72-55557b2ebe2c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509956556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.509956556
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.248842584
Short name T807
Test name
Test status
Simulation time 916744000 ps
CPU time 17.54 seconds
Started Jun 11 02:23:15 PM PDT 24
Finished Jun 11 02:23:34 PM PDT 24
Peak memory 256504 kb
Host smart-2a7ab73f-d658-4e20-9a74-43b5d163c478
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=248842584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.248842584
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3513474215
Short name T171
Test name
Test status
Simulation time 3562666317 ps
CPU time 62.53 seconds
Started Jun 11 02:23:15 PM PDT 24
Finished Jun 11 02:24:18 PM PDT 24
Peak memory 238080 kb
Host smart-e9c633ed-ac0e-4eb4-b0f6-05f4f4e94f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3513474215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3513474215
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2692702893
Short name T386
Test name
Test status
Simulation time 140749620121 ps
CPU time 969.17 seconds
Started Jun 11 02:24:24 PM PDT 24
Finished Jun 11 02:40:34 PM PDT 24
Peak memory 273468 kb
Host smart-2a466fc0-1ec5-4639-8785-e180ddb6db78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692702893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2692702893
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3517343487
Short name T486
Test name
Test status
Simulation time 3289897091 ps
CPU time 39.91 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 02:25:08 PM PDT 24
Peak memory 249064 kb
Host smart-68abf802-f420-414d-ad35-cb0720389cb2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3517343487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3517343487
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1216216185
Short name T554
Test name
Test status
Simulation time 1560481956 ps
CPU time 122.34 seconds
Started Jun 11 02:24:27 PM PDT 24
Finished Jun 11 02:26:30 PM PDT 24
Peak memory 257120 kb
Host smart-c64f005a-d523-410e-9c51-bee3c4668fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12162
16185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1216216185
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3098266203
Short name T654
Test name
Test status
Simulation time 387790885 ps
CPU time 30.43 seconds
Started Jun 11 02:24:22 PM PDT 24
Finished Jun 11 02:24:54 PM PDT 24
Peak memory 248900 kb
Host smart-8a456670-3447-40e6-8fba-bd7fe5ded31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30982
66203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3098266203
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2645969028
Short name T399
Test name
Test status
Simulation time 618010903 ps
CPU time 18.88 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:24:43 PM PDT 24
Peak memory 248960 kb
Host smart-a020c6a8-cf44-4a18-9685-4794ae7ad5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26459
69028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2645969028
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.570185148
Short name T384
Test name
Test status
Simulation time 325200156 ps
CPU time 6.39 seconds
Started Jun 11 02:24:24 PM PDT 24
Finished Jun 11 02:24:31 PM PDT 24
Peak memory 250356 kb
Host smart-6a16a72f-caec-48e7-8c9f-adf8e0ce7ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57018
5148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.570185148
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2498398227
Short name T30
Test name
Test status
Simulation time 933936211 ps
CPU time 25.97 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:24:51 PM PDT 24
Peak memory 270468 kb
Host smart-8ee8aea3-a031-4f2a-8c24-6999ec09fb64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2498398227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2498398227
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2933908571
Short name T471
Test name
Test status
Simulation time 146270898 ps
CPU time 4.05 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 02:24:32 PM PDT 24
Peak memory 239556 kb
Host smart-07c1fabc-6177-4c38-ab65-960d97031027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29339
08571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2933908571
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3972566331
Short name T28
Test name
Test status
Simulation time 50081072091 ps
CPU time 1429.25 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:48:14 PM PDT 24
Peak memory 273652 kb
Host smart-3bc4e7b2-5b66-4b3b-878a-98531a63d0dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972566331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3972566331
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3795971071
Short name T516
Test name
Test status
Simulation time 25650932703 ps
CPU time 2898.7 seconds
Started Jun 11 02:24:24 PM PDT 24
Finished Jun 11 03:12:44 PM PDT 24
Peak memory 314676 kb
Host smart-c5b85085-0429-49c7-8606-8ddd81fd2ddd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795971071 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3795971071
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1879673128
Short name T2
Test name
Test status
Simulation time 31274612556 ps
CPU time 2293.72 seconds
Started Jun 11 02:24:25 PM PDT 24
Finished Jun 11 03:02:41 PM PDT 24
Peak memory 289252 kb
Host smart-22f6aaf9-d3ba-46fb-a129-ccf16c9f8688
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879673128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1879673128
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.429976814
Short name T520
Test name
Test status
Simulation time 144666577 ps
CPU time 8.73 seconds
Started Jun 11 02:24:22 PM PDT 24
Finished Jun 11 02:24:32 PM PDT 24
Peak memory 248892 kb
Host smart-a28983f6-3c5f-4b79-9eaf-3271380d8c88
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=429976814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.429976814
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.471598257
Short name T586
Test name
Test status
Simulation time 3594195559 ps
CPU time 92.63 seconds
Started Jun 11 02:24:24 PM PDT 24
Finished Jun 11 02:25:59 PM PDT 24
Peak memory 249044 kb
Host smart-417f01b2-d120-4363-a02b-b084b5628f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47159
8257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.471598257
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3619688293
Short name T37
Test name
Test status
Simulation time 2738114365 ps
CPU time 51.48 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 02:25:19 PM PDT 24
Peak memory 256464 kb
Host smart-9d5ff93a-6318-479d-adf5-aa48d89d2187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36196
88293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3619688293
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3026845601
Short name T708
Test name
Test status
Simulation time 17283135941 ps
CPU time 747.7 seconds
Started Jun 11 02:24:25 PM PDT 24
Finished Jun 11 02:36:55 PM PDT 24
Peak memory 265532 kb
Host smart-a30eeece-8350-426e-b40e-73ed9c4ce94e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026845601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3026845601
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1406551078
Short name T388
Test name
Test status
Simulation time 14641202965 ps
CPU time 768.27 seconds
Started Jun 11 02:24:25 PM PDT 24
Finished Jun 11 02:37:15 PM PDT 24
Peak memory 273248 kb
Host smart-a020f197-5767-45b2-bc85-b9e9bc682c49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406551078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1406551078
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.762382138
Short name T321
Test name
Test status
Simulation time 25627249004 ps
CPU time 538.69 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 02:33:26 PM PDT 24
Peak memory 248272 kb
Host smart-15b98335-3a1f-432e-abaf-afb014845e6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762382138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.762382138
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3473933784
Short name T535
Test name
Test status
Simulation time 1334631690 ps
CPU time 44.24 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 02:25:12 PM PDT 24
Peak memory 248948 kb
Host smart-7c3b37b3-a14d-4b7e-b19f-511579eedc45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34739
33784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3473933784
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2394180225
Short name T519
Test name
Test status
Simulation time 292913534 ps
CPU time 17.06 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 02:24:45 PM PDT 24
Peak memory 252628 kb
Host smart-5420d87e-88a5-403d-9a47-57c9b69166d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23941
80225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2394180225
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1599251031
Short name T12
Test name
Test status
Simulation time 1304004517 ps
CPU time 20.52 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 02:24:48 PM PDT 24
Peak memory 270168 kb
Host smart-fd31a5ed-308c-4b05-9a8d-4a880c9506a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1599251031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1599251031
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.541769724
Short name T422
Test name
Test status
Simulation time 1556424429 ps
CPU time 56.36 seconds
Started Jun 11 02:24:25 PM PDT 24
Finished Jun 11 02:25:24 PM PDT 24
Peak memory 248960 kb
Host smart-bf4ab5a0-fb46-4dab-80ec-e7ef1dfd43d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54176
9724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.541769724
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2494983629
Short name T263
Test name
Test status
Simulation time 55341894156 ps
CPU time 4971.8 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 03:47:20 PM PDT 24
Peak memory 332036 kb
Host smart-08ea176e-5fed-40fa-85a5-5e314521b17f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494983629 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2494983629
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1870297081
Short name T536
Test name
Test status
Simulation time 56069883604 ps
CPU time 1824.64 seconds
Started Jun 11 02:25:04 PM PDT 24
Finished Jun 11 02:55:30 PM PDT 24
Peak memory 289248 kb
Host smart-7b3f8db3-264b-4610-a6ab-5ccb8c83385d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870297081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1870297081
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3625883333
Short name T568
Test name
Test status
Simulation time 4612082293 ps
CPU time 31.48 seconds
Started Jun 11 02:25:03 PM PDT 24
Finished Jun 11 02:25:36 PM PDT 24
Peak memory 240720 kb
Host smart-f33c297c-822a-4a12-88e9-80c017a7c02c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3625883333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3625883333
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3169561071
Short name T264
Test name
Test status
Simulation time 4823983243 ps
CPU time 145.26 seconds
Started Jun 11 02:25:03 PM PDT 24
Finished Jun 11 02:27:30 PM PDT 24
Peak memory 250008 kb
Host smart-fee26329-ed5d-4c72-b713-77ef36c392cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31695
61071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3169561071
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2020328183
Short name T547
Test name
Test status
Simulation time 668653941 ps
CPU time 44.2 seconds
Started Jun 11 02:25:03 PM PDT 24
Finished Jun 11 02:25:49 PM PDT 24
Peak memory 248940 kb
Host smart-bff855c3-67d9-4420-a340-0e97157129ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20203
28183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2020328183
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1179045969
Short name T335
Test name
Test status
Simulation time 87926686497 ps
CPU time 1954.3 seconds
Started Jun 11 02:25:05 PM PDT 24
Finished Jun 11 02:57:40 PM PDT 24
Peak memory 281796 kb
Host smart-97808183-42d0-48da-9e3b-b8afb5bfcfba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179045969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1179045969
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2714534361
Short name T502
Test name
Test status
Simulation time 39098942780 ps
CPU time 592.38 seconds
Started Jun 11 02:25:04 PM PDT 24
Finished Jun 11 02:34:58 PM PDT 24
Peak memory 272624 kb
Host smart-c32b2eb3-e48a-431f-be60-64e9be8c60a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714534361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2714534361
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.4002461808
Short name T187
Test name
Test status
Simulation time 11215791659 ps
CPU time 462.51 seconds
Started Jun 11 02:25:03 PM PDT 24
Finished Jun 11 02:32:47 PM PDT 24
Peak memory 255536 kb
Host smart-3ea0ace5-cdab-492d-b5e8-1428140bf7ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002461808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.4002461808
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3150200555
Short name T694
Test name
Test status
Simulation time 32775014 ps
CPU time 5.56 seconds
Started Jun 11 02:25:08 PM PDT 24
Finished Jun 11 02:25:15 PM PDT 24
Peak memory 248980 kb
Host smart-05d3fead-a496-4dd4-bc60-04543fe2f964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31502
00555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3150200555
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3560658046
Short name T680
Test name
Test status
Simulation time 505461701 ps
CPU time 10.57 seconds
Started Jun 11 02:25:06 PM PDT 24
Finished Jun 11 02:25:18 PM PDT 24
Peak memory 248920 kb
Host smart-8a08929b-37f2-4a16-99b8-b8142c23d2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35606
58046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3560658046
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.648529728
Short name T282
Test name
Test status
Simulation time 508506270 ps
CPU time 34.68 seconds
Started Jun 11 02:25:05 PM PDT 24
Finished Jun 11 02:25:41 PM PDT 24
Peak memory 255860 kb
Host smart-67e490fb-3bf9-48e8-8621-7d071bd09b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64852
9728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.648529728
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2928524217
Short name T409
Test name
Test status
Simulation time 417516228 ps
CPU time 23.14 seconds
Started Jun 11 02:25:08 PM PDT 24
Finished Jun 11 02:25:32 PM PDT 24
Peak memory 248788 kb
Host smart-e66b12c2-ddc6-43fc-a016-6a4a0dac1dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29285
24217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2928524217
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3163153950
Short name T285
Test name
Test status
Simulation time 156226405007 ps
CPU time 4110.53 seconds
Started Jun 11 02:25:04 PM PDT 24
Finished Jun 11 03:33:36 PM PDT 24
Peak memory 305728 kb
Host smart-abc3ec08-9bff-46d8-9eca-a83401ff2baa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163153950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3163153950
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.319401219
Short name T55
Test name
Test status
Simulation time 165997633422 ps
CPU time 2681.86 seconds
Started Jun 11 02:25:15 PM PDT 24
Finished Jun 11 03:09:58 PM PDT 24
Peak memory 297608 kb
Host smart-d8672c18-e553-451e-b7c1-2abcf7f0c534
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319401219 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.319401219
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.681297965
Short name T671
Test name
Test status
Simulation time 103389625185 ps
CPU time 1193.17 seconds
Started Jun 11 02:25:15 PM PDT 24
Finished Jun 11 02:45:10 PM PDT 24
Peak memory 282812 kb
Host smart-513870e6-a6f3-4cce-b174-4d29a6d211cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681297965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.681297965
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1848694044
Short name T636
Test name
Test status
Simulation time 1104602856 ps
CPU time 46.16 seconds
Started Jun 11 02:25:19 PM PDT 24
Finished Jun 11 02:26:06 PM PDT 24
Peak memory 240704 kb
Host smart-d1ea3a91-e590-47a7-9af4-911e6db7242b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1848694044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1848694044
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1397882652
Short name T442
Test name
Test status
Simulation time 3998612495 ps
CPU time 40.54 seconds
Started Jun 11 02:25:21 PM PDT 24
Finished Jun 11 02:26:02 PM PDT 24
Peak memory 257188 kb
Host smart-3c2c3205-a85b-486a-9487-991161252f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13978
82652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1397882652
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1235498668
Short name T84
Test name
Test status
Simulation time 794410510 ps
CPU time 47.55 seconds
Started Jun 11 02:25:16 PM PDT 24
Finished Jun 11 02:26:05 PM PDT 24
Peak memory 255728 kb
Host smart-e2d7e158-75fa-471c-9e8c-2a1d35be93f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12354
98668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1235498668
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.740968976
Short name T683
Test name
Test status
Simulation time 40934323140 ps
CPU time 2466.21 seconds
Started Jun 11 02:25:16 PM PDT 24
Finished Jun 11 03:06:23 PM PDT 24
Peak memory 289932 kb
Host smart-da2bd34b-e69f-449f-b168-162ca5f12653
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740968976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.740968976
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1039712881
Short name T414
Test name
Test status
Simulation time 421089880967 ps
CPU time 2339.69 seconds
Started Jun 11 02:25:16 PM PDT 24
Finished Jun 11 03:04:17 PM PDT 24
Peak memory 289332 kb
Host smart-2898c765-4ef7-4cc5-94f9-c188946f6a33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039712881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1039712881
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3866246283
Short name T310
Test name
Test status
Simulation time 17739995055 ps
CPU time 188.65 seconds
Started Jun 11 02:25:15 PM PDT 24
Finished Jun 11 02:28:25 PM PDT 24
Peak memory 255260 kb
Host smart-f38b3385-8831-413b-8180-d36b1ace03fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866246283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3866246283
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1524396089
Short name T397
Test name
Test status
Simulation time 96482385 ps
CPU time 6.97 seconds
Started Jun 11 02:25:14 PM PDT 24
Finished Jun 11 02:25:21 PM PDT 24
Peak memory 252532 kb
Host smart-67b66cf6-76fd-4da4-82e1-80b66e41dbed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15243
96089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1524396089
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.9583210
Short name T489
Test name
Test status
Simulation time 255927298 ps
CPU time 9.36 seconds
Started Jun 11 02:25:14 PM PDT 24
Finished Jun 11 02:25:25 PM PDT 24
Peak memory 254392 kb
Host smart-88e5d996-908d-4893-a580-5f90395bd637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95832
10 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.9583210
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1963144931
Short name T87
Test name
Test status
Simulation time 124106365 ps
CPU time 13.45 seconds
Started Jun 11 02:25:18 PM PDT 24
Finished Jun 11 02:25:32 PM PDT 24
Peak memory 248876 kb
Host smart-58e2e097-9a8b-40ee-b8af-cac37bd514a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19631
44931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1963144931
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3658871484
Short name T394
Test name
Test status
Simulation time 4721796603 ps
CPU time 70.34 seconds
Started Jun 11 02:25:14 PM PDT 24
Finished Jun 11 02:26:25 PM PDT 24
Peak memory 249016 kb
Host smart-29417af6-4aae-49aa-9181-528f7516a209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36588
71484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3658871484
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2959431032
Short name T212
Test name
Test status
Simulation time 211628180 ps
CPU time 3.36 seconds
Started Jun 11 02:25:14 PM PDT 24
Finished Jun 11 02:25:19 PM PDT 24
Peak memory 249136 kb
Host smart-ae83fb63-ef4e-4b72-bb13-28a58fef789c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2959431032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2959431032
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2784245019
Short name T119
Test name
Test status
Simulation time 84824965733 ps
CPU time 2229.36 seconds
Started Jun 11 02:25:14 PM PDT 24
Finished Jun 11 03:02:24 PM PDT 24
Peak memory 289272 kb
Host smart-aa81c6bd-4248-4356-8107-a0f330ccf510
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784245019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2784245019
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2020212851
Short name T573
Test name
Test status
Simulation time 412002857 ps
CPU time 11.71 seconds
Started Jun 11 02:25:17 PM PDT 24
Finished Jun 11 02:25:30 PM PDT 24
Peak memory 248948 kb
Host smart-30bcac00-f8d8-4e81-a8f5-9e5fbdde314b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2020212851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2020212851
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1852954992
Short name T587
Test name
Test status
Simulation time 1522444411 ps
CPU time 96.46 seconds
Started Jun 11 02:25:14 PM PDT 24
Finished Jun 11 02:26:51 PM PDT 24
Peak memory 249068 kb
Host smart-87e1ad47-4f27-424a-81ce-6596be331b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18529
54992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1852954992
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1439063643
Short name T60
Test name
Test status
Simulation time 62843845 ps
CPU time 4.65 seconds
Started Jun 11 02:25:15 PM PDT 24
Finished Jun 11 02:25:21 PM PDT 24
Peak memory 240688 kb
Host smart-1d860123-86ca-41a8-b2ca-6ef40d988e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14390
63643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1439063643
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3581788076
Short name T318
Test name
Test status
Simulation time 42381040291 ps
CPU time 1427.65 seconds
Started Jun 11 02:25:16 PM PDT 24
Finished Jun 11 02:49:05 PM PDT 24
Peak memory 273496 kb
Host smart-6c897395-49bb-4693-ad91-95829db52346
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581788076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3581788076
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2834325880
Short name T632
Test name
Test status
Simulation time 90416401364 ps
CPU time 2968.32 seconds
Started Jun 11 02:25:16 PM PDT 24
Finished Jun 11 03:14:46 PM PDT 24
Peak memory 285432 kb
Host smart-7bc314a9-6b75-4aca-b6e2-08976d7cde9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834325880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2834325880
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3489791461
Short name T517
Test name
Test status
Simulation time 17158237395 ps
CPU time 222.61 seconds
Started Jun 11 02:25:14 PM PDT 24
Finished Jun 11 02:28:57 PM PDT 24
Peak memory 248364 kb
Host smart-5ca385f0-1c92-4bc5-8054-db657715b0db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489791461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3489791461
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.844427772
Short name T225
Test name
Test status
Simulation time 1002811216 ps
CPU time 54.26 seconds
Started Jun 11 02:25:15 PM PDT 24
Finished Jun 11 02:26:10 PM PDT 24
Peak memory 256520 kb
Host smart-f7520d57-5ad0-4587-8a70-b0e5ae77e482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84442
7772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.844427772
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3150944600
Short name T650
Test name
Test status
Simulation time 389352345 ps
CPU time 18.8 seconds
Started Jun 11 02:25:17 PM PDT 24
Finished Jun 11 02:25:37 PM PDT 24
Peak memory 247636 kb
Host smart-487e65a2-c68b-44cf-a80f-8679896acb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31509
44600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3150944600
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2307309555
Short name T572
Test name
Test status
Simulation time 215455978 ps
CPU time 13.44 seconds
Started Jun 11 02:25:16 PM PDT 24
Finished Jun 11 02:25:30 PM PDT 24
Peak memory 248912 kb
Host smart-d5177f6b-0739-4900-84c1-9305c980e533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23073
09555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2307309555
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.444493143
Short name T237
Test name
Test status
Simulation time 11493404904 ps
CPU time 1270.34 seconds
Started Jun 11 02:25:17 PM PDT 24
Finished Jun 11 02:46:28 PM PDT 24
Peak memory 289816 kb
Host smart-4852c5d0-cb9f-4d20-9c63-0a12a8eda56d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444493143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.444493143
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.251139428
Short name T205
Test name
Test status
Simulation time 14710020 ps
CPU time 2.57 seconds
Started Jun 11 02:25:24 PM PDT 24
Finished Jun 11 02:25:29 PM PDT 24
Peak memory 249080 kb
Host smart-80ebbe4b-62ca-4c68-94c2-e86009ee78bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=251139428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.251139428
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.777287433
Short name T459
Test name
Test status
Simulation time 23749961807 ps
CPU time 1145.6 seconds
Started Jun 11 02:25:24 PM PDT 24
Finished Jun 11 02:44:32 PM PDT 24
Peak memory 289352 kb
Host smart-acf6e531-8038-40d5-83bc-648396830ebb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777287433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.777287433
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1120558549
Short name T477
Test name
Test status
Simulation time 444969966 ps
CPU time 9.28 seconds
Started Jun 11 02:25:30 PM PDT 24
Finished Jun 11 02:25:41 PM PDT 24
Peak memory 248860 kb
Host smart-e694ac79-21b5-44c7-a607-7d8934d64d9a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1120558549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1120558549
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3256001978
Short name T631
Test name
Test status
Simulation time 562757152 ps
CPU time 39.31 seconds
Started Jun 11 02:25:25 PM PDT 24
Finished Jun 11 02:26:07 PM PDT 24
Peak memory 249020 kb
Host smart-a0f4b9b9-022d-4dd7-84d7-8eff86b63729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32560
01978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3256001978
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3399369643
Short name T281
Test name
Test status
Simulation time 1258165442 ps
CPU time 33.76 seconds
Started Jun 11 02:25:26 PM PDT 24
Finished Jun 11 02:26:02 PM PDT 24
Peak memory 248992 kb
Host smart-56ff2f9c-071e-42f3-a76d-0a982e09467b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33993
69643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3399369643
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3922232572
Short name T567
Test name
Test status
Simulation time 137271456407 ps
CPU time 2248.12 seconds
Started Jun 11 02:25:30 PM PDT 24
Finished Jun 11 03:03:00 PM PDT 24
Peak memory 273568 kb
Host smart-1228bdfc-77ad-4d72-a750-1eef47bbafea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922232572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3922232572
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.685944271
Short name T602
Test name
Test status
Simulation time 4392710337 ps
CPU time 179.1 seconds
Started Jun 11 02:25:26 PM PDT 24
Finished Jun 11 02:28:27 PM PDT 24
Peak memory 255012 kb
Host smart-8289b3af-c6d1-4b74-bf9c-ba563094caf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685944271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.685944271
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1532921337
Short name T270
Test name
Test status
Simulation time 208779284 ps
CPU time 15.21 seconds
Started Jun 11 02:25:16 PM PDT 24
Finished Jun 11 02:25:32 PM PDT 24
Peak memory 253528 kb
Host smart-8e9463b0-ffea-4e60-8c91-04904adf70a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15329
21337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1532921337
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2603103736
Short name T649
Test name
Test status
Simulation time 387968909 ps
CPU time 33.63 seconds
Started Jun 11 02:25:25 PM PDT 24
Finished Jun 11 02:26:01 PM PDT 24
Peak memory 248928 kb
Host smart-7f0f2f23-3860-4ce6-b9f5-551ed7da57de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26031
03736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2603103736
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.4132799723
Short name T189
Test name
Test status
Simulation time 193745975 ps
CPU time 19.6 seconds
Started Jun 11 02:25:28 PM PDT 24
Finished Jun 11 02:25:50 PM PDT 24
Peak memory 249140 kb
Host smart-8f202efa-8aa0-4049-b9e4-2679455026d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41327
99723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4132799723
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.581299765
Short name T643
Test name
Test status
Simulation time 125827204 ps
CPU time 9.14 seconds
Started Jun 11 02:25:14 PM PDT 24
Finished Jun 11 02:25:25 PM PDT 24
Peak memory 255552 kb
Host smart-8d373a26-5d30-4da1-b32f-7d94c7576763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58129
9765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.581299765
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.490986230
Short name T117
Test name
Test status
Simulation time 87559800530 ps
CPU time 2833.13 seconds
Started Jun 11 02:25:25 PM PDT 24
Finished Jun 11 03:12:41 PM PDT 24
Peak memory 289940 kb
Host smart-72e17716-fcf0-4cea-8e59-bd7a72e6079c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490986230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.490986230
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1768333290
Short name T258
Test name
Test status
Simulation time 119535542574 ps
CPU time 3088.16 seconds
Started Jun 11 02:25:29 PM PDT 24
Finished Jun 11 03:16:59 PM PDT 24
Peak memory 321952 kb
Host smart-968b7419-e420-4e42-b75d-b95731db3c0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768333290 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1768333290
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1093967447
Short name T209
Test name
Test status
Simulation time 43800914 ps
CPU time 2.36 seconds
Started Jun 11 02:25:26 PM PDT 24
Finished Jun 11 02:25:30 PM PDT 24
Peak memory 249168 kb
Host smart-cf3c177e-2215-4de4-9ab8-517db703af80
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1093967447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1093967447
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1750427149
Short name T82
Test name
Test status
Simulation time 220152377537 ps
CPU time 1554.47 seconds
Started Jun 11 02:25:31 PM PDT 24
Finished Jun 11 02:51:27 PM PDT 24
Peak memory 273556 kb
Host smart-fbd6cf57-c508-4e6e-a7ca-982021eed96b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750427149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1750427149
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1873375366
Short name T476
Test name
Test status
Simulation time 433355761 ps
CPU time 20.28 seconds
Started Jun 11 02:25:28 PM PDT 24
Finished Jun 11 02:25:50 PM PDT 24
Peak memory 248944 kb
Host smart-8346909c-115c-47b0-8e53-3aa6ccac4db1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1873375366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1873375366
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.4170839087
Short name T421
Test name
Test status
Simulation time 14339242189 ps
CPU time 231.79 seconds
Started Jun 11 02:25:28 PM PDT 24
Finished Jun 11 02:29:22 PM PDT 24
Peak memory 257128 kb
Host smart-179bac0b-1c7a-4c7a-bc58-9e694d24ea53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41708
39087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.4170839087
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2290734799
Short name T610
Test name
Test status
Simulation time 328654050 ps
CPU time 9.95 seconds
Started Jun 11 02:25:25 PM PDT 24
Finished Jun 11 02:25:37 PM PDT 24
Peak memory 248988 kb
Host smart-df694389-cb20-46d3-8a26-78a718a600f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22907
34799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2290734799
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2827002442
Short name T330
Test name
Test status
Simulation time 139028867650 ps
CPU time 1751.08 seconds
Started Jun 11 02:25:24 PM PDT 24
Finished Jun 11 02:54:37 PM PDT 24
Peak memory 289340 kb
Host smart-a655fdc9-4a14-45e1-9ab2-22d215c93779
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827002442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2827002442
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2859645755
Short name T35
Test name
Test status
Simulation time 147776682 ps
CPU time 15.04 seconds
Started Jun 11 02:25:25 PM PDT 24
Finished Jun 11 02:25:42 PM PDT 24
Peak memory 248884 kb
Host smart-ea505928-0b47-48c4-b886-81c26ed29282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28596
45755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2859645755
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.941446565
Short name T642
Test name
Test status
Simulation time 345962506 ps
CPU time 13.91 seconds
Started Jun 11 02:25:26 PM PDT 24
Finished Jun 11 02:25:42 PM PDT 24
Peak memory 247744 kb
Host smart-76c33e9e-5588-4b6a-a2e2-32ebfb6a993f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94144
6565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.941446565
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2764630406
Short name T79
Test name
Test status
Simulation time 76510708 ps
CPU time 5.88 seconds
Started Jun 11 02:25:30 PM PDT 24
Finished Jun 11 02:25:37 PM PDT 24
Peak memory 248956 kb
Host smart-1d6b70a7-7714-4d14-89a3-e081398c8d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27646
30406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2764630406
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.10222587
Short name T543
Test name
Test status
Simulation time 1195214337 ps
CPU time 31.33 seconds
Started Jun 11 02:25:26 PM PDT 24
Finished Jun 11 02:25:59 PM PDT 24
Peak memory 257128 kb
Host smart-16282a68-9ddc-450b-b9f3-b2692c0ca20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10222
587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.10222587
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.4280313120
Short name T537
Test name
Test status
Simulation time 34610664955 ps
CPU time 1561.1 seconds
Started Jun 11 02:25:27 PM PDT 24
Finished Jun 11 02:51:31 PM PDT 24
Peak memory 289484 kb
Host smart-9500a678-29ca-480c-9c83-f2f4a90367bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280313120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.4280313120
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2969736098
Short name T210
Test name
Test status
Simulation time 174874374 ps
CPU time 2.6 seconds
Started Jun 11 02:25:29 PM PDT 24
Finished Jun 11 02:25:33 PM PDT 24
Peak memory 249108 kb
Host smart-5833cc21-f169-4562-8691-86e87f399d3b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2969736098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2969736098
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3986908759
Short name T571
Test name
Test status
Simulation time 4138506443 ps
CPU time 12.53 seconds
Started Jun 11 02:25:29 PM PDT 24
Finished Jun 11 02:25:43 PM PDT 24
Peak memory 249008 kb
Host smart-19e21062-ca3a-44e3-bf08-2966711a9ecf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3986908759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3986908759
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3672821791
Short name T406
Test name
Test status
Simulation time 1274792334 ps
CPU time 71.51 seconds
Started Jun 11 02:25:26 PM PDT 24
Finished Jun 11 02:26:40 PM PDT 24
Peak memory 256396 kb
Host smart-f3383fc9-5c5b-47eb-a55c-05b07c316708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36728
21791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3672821791
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3926135572
Short name T371
Test name
Test status
Simulation time 4346917204 ps
CPU time 68.62 seconds
Started Jun 11 02:25:28 PM PDT 24
Finished Jun 11 02:26:39 PM PDT 24
Peak memory 256448 kb
Host smart-1eedc9ea-a129-4e5b-9467-8d9edee8a938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39261
35572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3926135572
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2391258850
Short name T341
Test name
Test status
Simulation time 19291443716 ps
CPU time 1554.43 seconds
Started Jun 11 02:25:25 PM PDT 24
Finished Jun 11 02:51:21 PM PDT 24
Peak memory 288888 kb
Host smart-e7248c15-6732-41be-8eb7-2f7b71498e6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391258850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2391258850
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3884435508
Short name T431
Test name
Test status
Simulation time 140699324016 ps
CPU time 1290.49 seconds
Started Jun 11 02:25:31 PM PDT 24
Finished Jun 11 02:47:03 PM PDT 24
Peak memory 289244 kb
Host smart-25fb810d-1f21-449d-9ed4-e3000e1304f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884435508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3884435508
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.750387357
Short name T302
Test name
Test status
Simulation time 12396566306 ps
CPU time 233.52 seconds
Started Jun 11 02:25:26 PM PDT 24
Finished Jun 11 02:29:22 PM PDT 24
Peak memory 255548 kb
Host smart-64fb3f44-117c-4707-9e32-9e3daf3cfa79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750387357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.750387357
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1068563925
Short name T381
Test name
Test status
Simulation time 178688416 ps
CPU time 6.06 seconds
Started Jun 11 02:25:27 PM PDT 24
Finished Jun 11 02:25:35 PM PDT 24
Peak memory 252136 kb
Host smart-dcda85a3-a701-4641-bcb4-22e908b060c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10685
63925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1068563925
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2691675777
Short name T107
Test name
Test status
Simulation time 139461927 ps
CPU time 10.11 seconds
Started Jun 11 02:25:25 PM PDT 24
Finished Jun 11 02:25:38 PM PDT 24
Peak memory 240908 kb
Host smart-dcbb114f-0d83-4559-9e00-826ed0b6798f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26916
75777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2691675777
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.402817171
Short name T490
Test name
Test status
Simulation time 45708314 ps
CPU time 3.92 seconds
Started Jun 11 02:25:30 PM PDT 24
Finished Jun 11 02:25:36 PM PDT 24
Peak memory 239632 kb
Host smart-a176ca6c-0040-49d3-8772-dceefb43d041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40281
7171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.402817171
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3427756612
Short name T483
Test name
Test status
Simulation time 1609560881 ps
CPU time 23.21 seconds
Started Jun 11 02:25:27 PM PDT 24
Finished Jun 11 02:25:52 PM PDT 24
Peak memory 248932 kb
Host smart-e517ad91-9b92-4646-bc87-337b0a820389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34277
56612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3427756612
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2304033239
Short name T710
Test name
Test status
Simulation time 83621327222 ps
CPU time 2828.53 seconds
Started Jun 11 02:25:30 PM PDT 24
Finished Jun 11 03:12:41 PM PDT 24
Peak memory 298136 kb
Host smart-4d56edbf-65b5-4505-90ef-02278e19d5d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304033239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2304033239
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3417950953
Short name T193
Test name
Test status
Simulation time 57099670033 ps
CPU time 2029.34 seconds
Started Jun 11 02:25:25 PM PDT 24
Finished Jun 11 02:59:17 PM PDT 24
Peak memory 303760 kb
Host smart-409495ea-e140-4227-8cef-99f4543be51c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417950953 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3417950953
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.853451966
Short name T213
Test name
Test status
Simulation time 252639019 ps
CPU time 3.27 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 02:25:41 PM PDT 24
Peak memory 249192 kb
Host smart-727a90f3-1773-44b4-b50d-45852e9c6829
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=853451966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.853451966
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2224734592
Short name T122
Test name
Test status
Simulation time 11394382575 ps
CPU time 668.81 seconds
Started Jun 11 02:25:38 PM PDT 24
Finished Jun 11 02:36:48 PM PDT 24
Peak memory 265332 kb
Host smart-fe6dc447-61cc-4f32-bc92-be58264d88b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224734592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2224734592
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.4088334952
Short name T541
Test name
Test status
Simulation time 5864819912 ps
CPU time 57.55 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 02:26:35 PM PDT 24
Peak memory 249008 kb
Host smart-280f29b2-59da-4f04-af6e-dc3df4e89e03
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4088334952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.4088334952
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2321075545
Short name T497
Test name
Test status
Simulation time 2116488541 ps
CPU time 171.56 seconds
Started Jun 11 02:25:37 PM PDT 24
Finished Jun 11 02:28:30 PM PDT 24
Peak memory 251216 kb
Host smart-321db7a8-b3ad-4b5c-bf24-664e2491f0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23210
75545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2321075545
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3118594300
Short name T408
Test name
Test status
Simulation time 2191576990 ps
CPU time 27.43 seconds
Started Jun 11 02:25:28 PM PDT 24
Finished Jun 11 02:25:57 PM PDT 24
Peak memory 256132 kb
Host smart-d213f815-09fe-4537-8835-97d16b98087d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31185
94300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3118594300
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2533019420
Short name T403
Test name
Test status
Simulation time 32582641532 ps
CPU time 2127.33 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 03:01:05 PM PDT 24
Peak memory 289012 kb
Host smart-1a310057-5a29-48e9-9c77-ad9af2d84d2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533019420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2533019420
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3575115604
Short name T539
Test name
Test status
Simulation time 12591154313 ps
CPU time 129.24 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 02:27:47 PM PDT 24
Peak memory 248428 kb
Host smart-f5fcec62-e5fa-41ef-82b0-5e9aefc58d8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575115604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3575115604
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2516251702
Short name T417
Test name
Test status
Simulation time 3555867178 ps
CPU time 18.56 seconds
Started Jun 11 02:25:29 PM PDT 24
Finished Jun 11 02:25:49 PM PDT 24
Peak memory 256312 kb
Host smart-1ddfdaa5-3237-4345-a572-3211748ac3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25162
51702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2516251702
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1143441713
Short name T261
Test name
Test status
Simulation time 866492459 ps
CPU time 46.68 seconds
Started Jun 11 02:25:25 PM PDT 24
Finished Jun 11 02:26:14 PM PDT 24
Peak memory 248956 kb
Host smart-e8fcb932-409d-4fde-8470-bd73249481ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11434
41713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1143441713
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2953342610
Short name T575
Test name
Test status
Simulation time 261476295 ps
CPU time 9.38 seconds
Started Jun 11 02:25:37 PM PDT 24
Finished Jun 11 02:25:47 PM PDT 24
Peak memory 248900 kb
Host smart-30849af4-eeb2-4295-88b4-ed4e724d225c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29533
42610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2953342610
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.4041931324
Short name T92
Test name
Test status
Simulation time 765055076 ps
CPU time 58.66 seconds
Started Jun 11 02:25:24 PM PDT 24
Finished Jun 11 02:26:24 PM PDT 24
Peak memory 248900 kb
Host smart-251f50b4-4585-4bae-8595-c3984a573efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40419
31324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.4041931324
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3992846924
Short name T481
Test name
Test status
Simulation time 422813971211 ps
CPU time 4616.04 seconds
Started Jun 11 02:25:38 PM PDT 24
Finished Jun 11 03:42:36 PM PDT 24
Peak memory 338764 kb
Host smart-0f09c033-5bda-415e-9565-b4f104eeb2c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992846924 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3992846924
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1355808695
Short name T191
Test name
Test status
Simulation time 20483290 ps
CPU time 2.96 seconds
Started Jun 11 02:25:39 PM PDT 24
Finished Jun 11 02:25:43 PM PDT 24
Peak memory 249144 kb
Host smart-adbb457a-039b-4645-98a6-d7ab0d0cd29b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1355808695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1355808695
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3251600141
Short name T596
Test name
Test status
Simulation time 657066605802 ps
CPU time 1999.9 seconds
Started Jun 11 02:25:37 PM PDT 24
Finished Jun 11 02:58:59 PM PDT 24
Peak memory 289392 kb
Host smart-4833d24c-bcde-418e-851f-f107b2eb3b08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251600141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3251600141
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3963267062
Short name T558
Test name
Test status
Simulation time 412980234 ps
CPU time 12.13 seconds
Started Jun 11 02:25:38 PM PDT 24
Finished Jun 11 02:25:51 PM PDT 24
Peak memory 248832 kb
Host smart-33d9ff28-9e80-47b4-9f77-060f23136970
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3963267062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3963267062
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2597662168
Short name T249
Test name
Test status
Simulation time 3462775470 ps
CPU time 210.08 seconds
Started Jun 11 02:25:35 PM PDT 24
Finished Jun 11 02:29:07 PM PDT 24
Peak memory 257000 kb
Host smart-c910bcb9-adb9-4b6e-b61d-dc25f114b069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25976
62168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2597662168
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.179377376
Short name T570
Test name
Test status
Simulation time 1265298217 ps
CPU time 28.74 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 02:26:06 PM PDT 24
Peak memory 256056 kb
Host smart-f9523ad6-ca6a-4f42-a18b-37e4fc146278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17937
7376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.179377376
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2528523622
Short name T334
Test name
Test status
Simulation time 39833951668 ps
CPU time 2520.22 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 03:07:37 PM PDT 24
Peak memory 289500 kb
Host smart-5bb2c9e5-77c3-45e2-9e97-d16d4117e4c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528523622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2528523622
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1964649298
Short name T32
Test name
Test status
Simulation time 144340125817 ps
CPU time 2337.52 seconds
Started Jun 11 02:25:38 PM PDT 24
Finished Jun 11 03:04:37 PM PDT 24
Peak memory 273536 kb
Host smart-a93dd14c-05ee-4f87-912f-7043e69666bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964649298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1964649298
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3973329781
Short name T323
Test name
Test status
Simulation time 6687851785 ps
CPU time 71.61 seconds
Started Jun 11 02:25:35 PM PDT 24
Finished Jun 11 02:26:48 PM PDT 24
Peak memory 253624 kb
Host smart-7b04397f-16d5-4b28-80b0-67cfed6531f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973329781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3973329781
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1660681889
Short name T434
Test name
Test status
Simulation time 477271655 ps
CPU time 30.06 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 02:26:08 PM PDT 24
Peak memory 249140 kb
Host smart-79ee577e-aa09-47b3-a1b4-e3e27ecd7bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16606
81889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1660681889
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.669737194
Short name T647
Test name
Test status
Simulation time 2001954395 ps
CPU time 52.13 seconds
Started Jun 11 02:25:37 PM PDT 24
Finished Jun 11 02:26:31 PM PDT 24
Peak memory 248856 kb
Host smart-a1eb0c4f-a3ef-460a-89e9-d29dcfd903d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66973
7194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.669737194
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2183311466
Short name T470
Test name
Test status
Simulation time 740975686 ps
CPU time 43.77 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 02:26:21 PM PDT 24
Peak memory 249152 kb
Host smart-35a282d5-e2c1-4e16-8ef0-59adfd8bc140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21833
11466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2183311466
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1548715484
Short name T360
Test name
Test status
Simulation time 3988978451 ps
CPU time 61.89 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 02:26:40 PM PDT 24
Peak memory 248988 kb
Host smart-4b21a3db-6c1d-430e-a14f-a61f9c89d932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15487
15484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1548715484
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2681626609
Short name T216
Test name
Test status
Simulation time 27969009 ps
CPU time 2.64 seconds
Started Jun 11 02:25:48 PM PDT 24
Finished Jun 11 02:25:51 PM PDT 24
Peak memory 249096 kb
Host smart-ba010605-6723-48cf-8e20-d0c10f1928ce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2681626609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2681626609
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1940055201
Short name T243
Test name
Test status
Simulation time 3450600393 ps
CPU time 11.07 seconds
Started Jun 11 02:25:39 PM PDT 24
Finished Jun 11 02:25:51 PM PDT 24
Peak memory 248992 kb
Host smart-af828844-e232-4de1-b4e3-2c11a58379da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1940055201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1940055201
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.438203136
Short name T423
Test name
Test status
Simulation time 1124320180 ps
CPU time 115.53 seconds
Started Jun 11 02:25:37 PM PDT 24
Finished Jun 11 02:27:34 PM PDT 24
Peak memory 250080 kb
Host smart-32897678-80f5-4d7d-9362-6bf23f098fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43820
3136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.438203136
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1412306070
Short name T370
Test name
Test status
Simulation time 291341522 ps
CPU time 24.38 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 02:26:02 PM PDT 24
Peak memory 255976 kb
Host smart-0d32d618-75cc-4792-8900-94bc25d10c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14123
06070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1412306070
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1586562997
Short name T463
Test name
Test status
Simulation time 40291369757 ps
CPU time 1680.56 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 02:53:38 PM PDT 24
Peak memory 289780 kb
Host smart-a3d8d8b0-fe07-42b0-9104-de9f108ba57d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586562997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1586562997
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1923870752
Short name T669
Test name
Test status
Simulation time 11420776351 ps
CPU time 231.76 seconds
Started Jun 11 02:25:39 PM PDT 24
Finished Jun 11 02:29:32 PM PDT 24
Peak memory 248548 kb
Host smart-20b07e10-bb06-4d20-9360-4ec9be8e8116
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923870752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1923870752
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1643417525
Short name T601
Test name
Test status
Simulation time 1164699059 ps
CPU time 20.3 seconds
Started Jun 11 02:25:38 PM PDT 24
Finished Jun 11 02:25:59 PM PDT 24
Peak memory 248868 kb
Host smart-9a241597-4310-4386-903f-250a67eab50a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16434
17525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1643417525
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1241236523
Short name T433
Test name
Test status
Simulation time 1132177555 ps
CPU time 35.77 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 02:26:13 PM PDT 24
Peak memory 256256 kb
Host smart-3227b34b-59bd-451f-9795-c96f9cc101ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12412
36523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1241236523
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2289729167
Short name T295
Test name
Test status
Simulation time 1617924328 ps
CPU time 25.93 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 02:26:03 PM PDT 24
Peak memory 256164 kb
Host smart-4d3aee04-c021-4b6d-ba69-8ae11c271164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22897
29167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2289729167
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.611116816
Short name T455
Test name
Test status
Simulation time 411471343 ps
CPU time 16.56 seconds
Started Jun 11 02:25:37 PM PDT 24
Finished Jun 11 02:25:55 PM PDT 24
Peak memory 248968 kb
Host smart-3611ef66-7c11-4c74-9b77-a840109ae31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61111
6816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.611116816
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.781331345
Short name T36
Test name
Test status
Simulation time 56640752546 ps
CPU time 3249.27 seconds
Started Jun 11 02:25:36 PM PDT 24
Finished Jun 11 03:19:48 PM PDT 24
Peak memory 289920 kb
Host smart-02e0941a-1cad-4bb7-8b93-c0e25612ce15
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781331345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.781331345
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1824660203
Short name T85
Test name
Test status
Simulation time 77964909164 ps
CPU time 4458.03 seconds
Started Jun 11 02:25:52 PM PDT 24
Finished Jun 11 03:40:11 PM PDT 24
Peak memory 339216 kb
Host smart-9b875109-2803-436e-829e-ba2329882a2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824660203 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1824660203
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1847365
Short name T208
Test name
Test status
Simulation time 134164957 ps
CPU time 3.53 seconds
Started Jun 11 02:25:47 PM PDT 24
Finished Jun 11 02:25:52 PM PDT 24
Peak memory 249240 kb
Host smart-7e2ff85f-bfd3-4d70-8747-bc5ec83fc686
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1847365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1847365
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.822228286
Short name T96
Test name
Test status
Simulation time 19792295805 ps
CPU time 1366.18 seconds
Started Jun 11 02:25:47 PM PDT 24
Finished Jun 11 02:48:34 PM PDT 24
Peak memory 265412 kb
Host smart-191bf7af-3945-44a8-8d84-ac568a582c28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822228286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.822228286
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2960931676
Short name T494
Test name
Test status
Simulation time 262512047 ps
CPU time 11.1 seconds
Started Jun 11 02:25:50 PM PDT 24
Finished Jun 11 02:26:02 PM PDT 24
Peak memory 249136 kb
Host smart-0ba09aa4-1d06-4ea0-9f03-952dce0766d6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2960931676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2960931676
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.30569894
Short name T521
Test name
Test status
Simulation time 1774288658 ps
CPU time 56.69 seconds
Started Jun 11 02:25:48 PM PDT 24
Finished Jun 11 02:26:45 PM PDT 24
Peak memory 256448 kb
Host smart-2d559cdc-8acb-4eb0-9fb9-38192534c957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30569
894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.30569894
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1169757980
Short name T269
Test name
Test status
Simulation time 380511779 ps
CPU time 10.89 seconds
Started Jun 11 02:25:49 PM PDT 24
Finished Jun 11 02:26:00 PM PDT 24
Peak memory 248964 kb
Host smart-74185ce9-a896-4d2c-bc78-f59471a1900a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11697
57980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1169757980
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1798421224
Short name T684
Test name
Test status
Simulation time 20838696640 ps
CPU time 935.02 seconds
Started Jun 11 02:25:50 PM PDT 24
Finished Jun 11 02:41:26 PM PDT 24
Peak memory 273276 kb
Host smart-e005e503-67c9-419b-a08c-f06d21bb3d08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798421224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1798421224
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.297092414
Short name T255
Test name
Test status
Simulation time 127582671889 ps
CPU time 1332.8 seconds
Started Jun 11 02:25:48 PM PDT 24
Finished Jun 11 02:48:02 PM PDT 24
Peak memory 272960 kb
Host smart-b0e93047-325e-428b-b425-23fe19273ffb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297092414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.297092414
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2930997720
Short name T578
Test name
Test status
Simulation time 2418378877 ps
CPU time 39.41 seconds
Started Jun 11 02:25:47 PM PDT 24
Finished Jun 11 02:26:28 PM PDT 24
Peak memory 256816 kb
Host smart-8e6830ff-59f1-4e2d-893e-a1bf3bec66e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29309
97720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2930997720
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.723880492
Short name T405
Test name
Test status
Simulation time 744548604 ps
CPU time 47.65 seconds
Started Jun 11 02:25:48 PM PDT 24
Finished Jun 11 02:26:36 PM PDT 24
Peak memory 255796 kb
Host smart-02ec711b-5def-4a6d-8f9c-67b29c5ba555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72388
0492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.723880492
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3881448882
Short name T553
Test name
Test status
Simulation time 1787898784 ps
CPU time 55.49 seconds
Started Jun 11 02:25:52 PM PDT 24
Finished Jun 11 02:26:48 PM PDT 24
Peak memory 248936 kb
Host smart-6d0a941e-4e82-45f1-a4a9-2f9403e46389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38814
48882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3881448882
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.248028812
Short name T214
Test name
Test status
Simulation time 42938830 ps
CPU time 2.23 seconds
Started Jun 11 02:24:34 PM PDT 24
Finished Jun 11 02:24:38 PM PDT 24
Peak memory 249168 kb
Host smart-4b77038a-2333-433d-8623-0e8fdfa58a1e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=248028812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.248028812
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.4236221075
Short name T26
Test name
Test status
Simulation time 50208266900 ps
CPU time 1605.11 seconds
Started Jun 11 02:24:34 PM PDT 24
Finished Jun 11 02:51:21 PM PDT 24
Peak memory 272944 kb
Host smart-86ab24db-3668-4fb6-a5b6-a900a2d17f0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236221075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.4236221075
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1522502382
Short name T592
Test name
Test status
Simulation time 216143741 ps
CPU time 12.96 seconds
Started Jun 11 02:24:29 PM PDT 24
Finished Jun 11 02:24:43 PM PDT 24
Peak memory 248976 kb
Host smart-efd96f59-d0a3-499d-bf9f-94d48f5fde17
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1522502382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1522502382
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.380135443
Short name T390
Test name
Test status
Simulation time 3816672175 ps
CPU time 176.02 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 02:27:24 PM PDT 24
Peak memory 257088 kb
Host smart-33e2c4b4-56e4-455e-876d-edd8c544ca2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38013
5443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.380135443
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1384401714
Short name T473
Test name
Test status
Simulation time 1854036494 ps
CPU time 27.4 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 02:24:55 PM PDT 24
Peak memory 255788 kb
Host smart-67e10e62-4b1e-4bf6-84aa-e9c90633a5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13844
01714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1384401714
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.525755213
Short name T336
Test name
Test status
Simulation time 141449191449 ps
CPU time 2420.91 seconds
Started Jun 11 02:24:27 PM PDT 24
Finished Jun 11 03:04:50 PM PDT 24
Peak memory 282536 kb
Host smart-03e67e1d-35f0-438a-a2e4-eae05f118f75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525755213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.525755213
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.310198118
Short name T457
Test name
Test status
Simulation time 50106437767 ps
CPU time 1083.5 seconds
Started Jun 11 02:24:28 PM PDT 24
Finished Jun 11 02:42:33 PM PDT 24
Peak memory 270708 kb
Host smart-05cb76c9-4eca-4da2-9316-5482f4fc5101
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310198118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.310198118
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3994600265
Short name T638
Test name
Test status
Simulation time 3201637577 ps
CPU time 94.2 seconds
Started Jun 11 02:24:34 PM PDT 24
Finished Jun 11 02:26:10 PM PDT 24
Peak memory 248412 kb
Host smart-f0b2e6c6-89c3-4547-a512-2df933556e90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994600265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3994600265
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2370296375
Short name T453
Test name
Test status
Simulation time 599035692 ps
CPU time 23.06 seconds
Started Jun 11 02:24:27 PM PDT 24
Finished Jun 11 02:24:52 PM PDT 24
Peak memory 255276 kb
Host smart-471737d3-57f0-46a9-87ee-b57073935d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23702
96375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2370296375
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.279224865
Short name T111
Test name
Test status
Simulation time 777120372 ps
CPU time 24.36 seconds
Started Jun 11 02:24:27 PM PDT 24
Finished Jun 11 02:24:53 PM PDT 24
Peak memory 255600 kb
Host smart-6a0761af-2951-4372-84f8-5c72fdc0d63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27922
4865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.279224865
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.463225649
Short name T31
Test name
Test status
Simulation time 1073409569 ps
CPU time 42.64 seconds
Started Jun 11 02:24:28 PM PDT 24
Finished Jun 11 02:25:12 PM PDT 24
Peak memory 273644 kb
Host smart-3d8d632a-2853-4b05-a6b5-be4eafab7bd8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=463225649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.463225649
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.903673692
Short name T672
Test name
Test status
Simulation time 585239917 ps
CPU time 33.42 seconds
Started Jun 11 02:24:26 PM PDT 24
Finished Jun 11 02:25:01 PM PDT 24
Peak memory 248820 kb
Host smart-4549a2e7-9fb8-44cd-9861-b881a8ae57f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90367
3692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.903673692
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3102870203
Short name T623
Test name
Test status
Simulation time 346413776 ps
CPU time 11.09 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:24:36 PM PDT 24
Peak memory 254544 kb
Host smart-1aac3cec-3828-4f6c-b353-b865beab44bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31028
70203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3102870203
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1591759821
Short name T420
Test name
Test status
Simulation time 1336462620 ps
CPU time 35.41 seconds
Started Jun 11 02:24:33 PM PDT 24
Finished Jun 11 02:25:10 PM PDT 24
Peak memory 256176 kb
Host smart-df730078-2ffc-4fd7-9fdf-899e2390746a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591759821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1591759821
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3045757969
Short name T452
Test name
Test status
Simulation time 185726981515 ps
CPU time 2462.69 seconds
Started Jun 11 02:25:49 PM PDT 24
Finished Jun 11 03:06:53 PM PDT 24
Peak memory 289124 kb
Host smart-1f65886c-198c-40bd-ab5b-e8850abd4d9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045757969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3045757969
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2775203899
Short name T441
Test name
Test status
Simulation time 8978854476 ps
CPU time 152.25 seconds
Started Jun 11 02:25:50 PM PDT 24
Finished Jun 11 02:28:23 PM PDT 24
Peak memory 257180 kb
Host smart-29020c04-2e45-4e46-a97f-e3dbb5630ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27752
03899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2775203899
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2180521153
Short name T391
Test name
Test status
Simulation time 3908150226 ps
CPU time 48.88 seconds
Started Jun 11 02:25:48 PM PDT 24
Finished Jun 11 02:26:38 PM PDT 24
Peak memory 256016 kb
Host smart-c45d112b-b441-477e-96e7-c236160cbeba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21805
21153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2180521153
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3805406842
Short name T337
Test name
Test status
Simulation time 8681307871 ps
CPU time 826.56 seconds
Started Jun 11 02:25:49 PM PDT 24
Finished Jun 11 02:39:37 PM PDT 24
Peak memory 273548 kb
Host smart-b1ba2e27-e9f5-4b95-be3c-304ab166f347
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805406842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3805406842
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2157301411
Short name T585
Test name
Test status
Simulation time 32649034665 ps
CPU time 1162.95 seconds
Started Jun 11 02:25:50 PM PDT 24
Finished Jun 11 02:45:14 PM PDT 24
Peak memory 286964 kb
Host smart-4428c90f-de51-4a30-8c87-a801bb18b070
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157301411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2157301411
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.651858617
Short name T599
Test name
Test status
Simulation time 768527159 ps
CPU time 27.13 seconds
Started Jun 11 02:25:49 PM PDT 24
Finished Jun 11 02:26:17 PM PDT 24
Peak memory 249252 kb
Host smart-087befac-bcb4-41d7-964d-7fd458fbc825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65185
8617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.651858617
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.44213908
Short name T230
Test name
Test status
Simulation time 889262136 ps
CPU time 31.9 seconds
Started Jun 11 02:25:52 PM PDT 24
Finished Jun 11 02:26:25 PM PDT 24
Peak memory 255256 kb
Host smart-be03ea04-ec15-4022-b84a-8d5cd902e86f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44213
908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.44213908
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1492853047
Short name T555
Test name
Test status
Simulation time 269621896 ps
CPU time 33.95 seconds
Started Jun 11 02:25:50 PM PDT 24
Finished Jun 11 02:26:25 PM PDT 24
Peak memory 247908 kb
Host smart-1fb9ba34-b927-4a47-8f9f-4b232ba497a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14928
53047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1492853047
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.449123127
Short name T379
Test name
Test status
Simulation time 3347641717 ps
CPU time 65.97 seconds
Started Jun 11 02:25:49 PM PDT 24
Finished Jun 11 02:26:56 PM PDT 24
Peak memory 256724 kb
Host smart-25bb3a62-f548-465f-8a7f-3b9b007af087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44912
3127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.449123127
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.4022513017
Short name T565
Test name
Test status
Simulation time 75682324003 ps
CPU time 2165.81 seconds
Started Jun 11 02:25:49 PM PDT 24
Finished Jun 11 03:01:56 PM PDT 24
Peak memory 290040 kb
Host smart-7f79f785-0417-408f-bb43-c010d8c3d530
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022513017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.4022513017
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.511166864
Short name T186
Test name
Test status
Simulation time 96970031622 ps
CPU time 1623.58 seconds
Started Jun 11 02:25:48 PM PDT 24
Finished Jun 11 02:52:52 PM PDT 24
Peak memory 289108 kb
Host smart-5a50dec2-5421-4f51-a704-5444a245158e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511166864 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.511166864
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2748785763
Short name T451
Test name
Test status
Simulation time 76979683881 ps
CPU time 2575 seconds
Started Jun 11 02:25:51 PM PDT 24
Finished Jun 11 03:08:47 PM PDT 24
Peak memory 289256 kb
Host smart-7344e9df-7bf7-422a-8501-3e2e03cd2808
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748785763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2748785763
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4235578721
Short name T228
Test name
Test status
Simulation time 5796279181 ps
CPU time 325.16 seconds
Started Jun 11 02:25:46 PM PDT 24
Finished Jun 11 02:31:12 PM PDT 24
Peak memory 251664 kb
Host smart-7cc052a8-79b9-4c6d-a0ba-6e96a42f437e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42355
78721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4235578721
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.4268924373
Short name T419
Test name
Test status
Simulation time 274698987 ps
CPU time 29.97 seconds
Started Jun 11 02:25:50 PM PDT 24
Finished Jun 11 02:26:21 PM PDT 24
Peak memory 256032 kb
Host smart-f534b9d0-7889-4b65-b7bd-9d475b39d912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42689
24373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.4268924373
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2755888626
Short name T4
Test name
Test status
Simulation time 144762006265 ps
CPU time 2474.83 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 03:07:15 PM PDT 24
Peak memory 288912 kb
Host smart-39e09f41-a90a-4b35-9402-bed5f52d5cfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755888626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2755888626
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3174563134
Short name T69
Test name
Test status
Simulation time 130862966257 ps
CPU time 2388.86 seconds
Started Jun 11 02:26:01 PM PDT 24
Finished Jun 11 03:05:51 PM PDT 24
Peak memory 285888 kb
Host smart-34fc77ec-eefe-483f-b454-52b5bb385916
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174563134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3174563134
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.4193737106
Short name T679
Test name
Test status
Simulation time 7724762230 ps
CPU time 162.21 seconds
Started Jun 11 02:25:48 PM PDT 24
Finished Jun 11 02:28:31 PM PDT 24
Peak memory 256024 kb
Host smart-d8a7aeee-4228-4692-a1e4-c05853468702
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193737106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.4193737106
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.207330794
Short name T607
Test name
Test status
Simulation time 1210692949 ps
CPU time 42.88 seconds
Started Jun 11 02:25:53 PM PDT 24
Finished Jun 11 02:26:36 PM PDT 24
Peak memory 256000 kb
Host smart-935974af-9b4a-417a-9dae-58e1a6792181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20733
0794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.207330794
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2305739627
Short name T593
Test name
Test status
Simulation time 1157365924 ps
CPU time 30.88 seconds
Started Jun 11 02:25:50 PM PDT 24
Finished Jun 11 02:26:22 PM PDT 24
Peak memory 255848 kb
Host smart-9b5590ac-dd59-471a-b3a8-baccd463f27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23057
39627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2305739627
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.909653770
Short name T86
Test name
Test status
Simulation time 2405506621 ps
CPU time 41.03 seconds
Started Jun 11 02:25:48 PM PDT 24
Finished Jun 11 02:26:30 PM PDT 24
Peak memory 249020 kb
Host smart-f9b68e95-c7b7-4227-aa57-84610037e641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90965
3770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.909653770
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1495244469
Short name T531
Test name
Test status
Simulation time 1171415160 ps
CPU time 19.01 seconds
Started Jun 11 02:25:49 PM PDT 24
Finished Jun 11 02:26:09 PM PDT 24
Peak memory 248900 kb
Host smart-6c0dda59-7b1a-4ebf-b6eb-0104ccc825d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14952
44469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1495244469
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1532384490
Short name T1
Test name
Test status
Simulation time 12465314769 ps
CPU time 452.15 seconds
Started Jun 11 02:26:00 PM PDT 24
Finished Jun 11 02:33:34 PM PDT 24
Peak memory 257168 kb
Host smart-1298cba0-1ea1-4356-9558-6db29b44fe53
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532384490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1532384490
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3453796646
Short name T544
Test name
Test status
Simulation time 95349044439 ps
CPU time 3060.05 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 03:17:00 PM PDT 24
Peak memory 289268 kb
Host smart-1c751292-cf35-4686-83fd-9306099d8a52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453796646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3453796646
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3037715585
Short name T609
Test name
Test status
Simulation time 772198024 ps
CPU time 40.66 seconds
Started Jun 11 02:26:01 PM PDT 24
Finished Jun 11 02:26:43 PM PDT 24
Peak memory 256256 kb
Host smart-8501083e-2371-49d1-9d72-11659772a900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30377
15585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3037715585
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.405796136
Short name T412
Test name
Test status
Simulation time 477922533 ps
CPU time 22.43 seconds
Started Jun 11 02:26:00 PM PDT 24
Finished Jun 11 02:26:23 PM PDT 24
Peak memory 255696 kb
Host smart-24649d53-cdd4-49cb-b97e-5b81df5373d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40579
6136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.405796136
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1687552159
Short name T369
Test name
Test status
Simulation time 176912127446 ps
CPU time 3004.72 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 03:16:05 PM PDT 24
Peak memory 289528 kb
Host smart-81b55c7d-3659-4141-9e04-3a2d495e45c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687552159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1687552159
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1280015790
Short name T76
Test name
Test status
Simulation time 6731045815 ps
CPU time 278.92 seconds
Started Jun 11 02:26:00 PM PDT 24
Finished Jun 11 02:30:40 PM PDT 24
Peak memory 248668 kb
Host smart-95e2efcc-4f30-46f4-bbc6-2f06f7065fac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280015790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1280015790
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1729773209
Short name T674
Test name
Test status
Simulation time 2307048481 ps
CPU time 44.19 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 02:26:44 PM PDT 24
Peak memory 249012 kb
Host smart-2f524e1a-8b16-4eb1-bcd1-ceded9df3cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17297
73209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1729773209
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.767490403
Short name T106
Test name
Test status
Simulation time 2333395572 ps
CPU time 38.12 seconds
Started Jun 11 02:26:00 PM PDT 24
Finished Jun 11 02:26:40 PM PDT 24
Peak memory 255808 kb
Host smart-ec7eba6d-4df3-4f29-836e-b3408060d8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76749
0403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.767490403
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.288436246
Short name T375
Test name
Test status
Simulation time 52182051 ps
CPU time 4.43 seconds
Started Jun 11 02:25:58 PM PDT 24
Finished Jun 11 02:26:04 PM PDT 24
Peak memory 239628 kb
Host smart-672b4cd4-e56d-4003-949b-6ddf7344db03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28843
6246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.288436246
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.505716427
Short name T663
Test name
Test status
Simulation time 262367887 ps
CPU time 11.91 seconds
Started Jun 11 02:25:58 PM PDT 24
Finished Jun 11 02:26:10 PM PDT 24
Peak memory 257088 kb
Host smart-d0ff3fa3-1d21-4786-a921-c914267ac284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50571
6427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.505716427
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2624109480
Short name T501
Test name
Test status
Simulation time 27058319991 ps
CPU time 756.83 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 02:38:37 PM PDT 24
Peak memory 265364 kb
Host smart-c5754a0a-3ddb-4190-b929-ce2de10ef7c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624109480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2624109480
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2957548026
Short name T364
Test name
Test status
Simulation time 181952340340 ps
CPU time 2783.76 seconds
Started Jun 11 02:26:02 PM PDT 24
Finished Jun 11 03:12:27 PM PDT 24
Peak memory 286492 kb
Host smart-5d98a627-235e-44c6-9cc6-6f03f8651258
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957548026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2957548026
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3407901121
Short name T616
Test name
Test status
Simulation time 3975616510 ps
CPU time 268.56 seconds
Started Jun 11 02:26:01 PM PDT 24
Finished Jun 11 02:30:30 PM PDT 24
Peak memory 251216 kb
Host smart-5251227f-5057-4256-8b77-258d669e2dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34079
01121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3407901121
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2338449221
Short name T595
Test name
Test status
Simulation time 3749848753 ps
CPU time 63.44 seconds
Started Jun 11 02:26:03 PM PDT 24
Finished Jun 11 02:27:08 PM PDT 24
Peak memory 255564 kb
Host smart-2d00e36a-d41b-4f3c-81a8-b3efefc2eea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23384
49221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2338449221
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2915342481
Short name T343
Test name
Test status
Simulation time 25771013243 ps
CPU time 1739.58 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 02:55:00 PM PDT 24
Peak memory 273612 kb
Host smart-081407d6-8fce-4ed8-9bd1-395396600ea8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915342481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2915342481
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2435898866
Short name T511
Test name
Test status
Simulation time 11041294932 ps
CPU time 1160.02 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 02:45:21 PM PDT 24
Peak memory 283700 kb
Host smart-ee0d37d1-6d9c-4c3f-b9d3-5f617722722c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435898866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2435898866
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.449426542
Short name T660
Test name
Test status
Simulation time 14072582671 ps
CPU time 522.7 seconds
Started Jun 11 02:26:00 PM PDT 24
Finished Jun 11 02:34:43 PM PDT 24
Peak memory 248352 kb
Host smart-69436e26-e881-4eb6-be18-c92388ed6eb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449426542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.449426542
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.4284915467
Short name T692
Test name
Test status
Simulation time 554427310 ps
CPU time 26.21 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 02:26:27 PM PDT 24
Peak memory 248940 kb
Host smart-5adf6021-bbfd-47df-b674-aa6030fe064e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42849
15467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.4284915467
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3334382159
Short name T436
Test name
Test status
Simulation time 491127625 ps
CPU time 6.1 seconds
Started Jun 11 02:25:57 PM PDT 24
Finished Jun 11 02:26:04 PM PDT 24
Peak memory 251916 kb
Host smart-d63cc435-0fbc-43de-bdbb-ae3d90af1edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33343
82159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3334382159
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.736663353
Short name T678
Test name
Test status
Simulation time 560231515 ps
CPU time 34.11 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 02:26:34 PM PDT 24
Peak memory 248968 kb
Host smart-f1395bf3-eeba-45d8-80df-27cb3ab99792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73666
3353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.736663353
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1590651457
Short name T23
Test name
Test status
Simulation time 24635551088 ps
CPU time 1307.4 seconds
Started Jun 11 02:26:00 PM PDT 24
Finished Jun 11 02:47:49 PM PDT 24
Peak memory 289420 kb
Host smart-384f744f-8176-4749-aad5-c9fea15e5510
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590651457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1590651457
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3302639090
Short name T110
Test name
Test status
Simulation time 44076724041 ps
CPU time 3853.04 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 03:30:14 PM PDT 24
Peak memory 322280 kb
Host smart-e1aa8280-e459-4e12-956b-1cd3e60d834b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302639090 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3302639090
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3326606874
Short name T617
Test name
Test status
Simulation time 48536084251 ps
CPU time 1236.39 seconds
Started Jun 11 02:26:02 PM PDT 24
Finished Jun 11 02:46:39 PM PDT 24
Peak memory 272672 kb
Host smart-4a0094ac-79e9-4681-95a8-26a60bdae3c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326606874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3326606874
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.338386576
Short name T712
Test name
Test status
Simulation time 1702483251 ps
CPU time 49.81 seconds
Started Jun 11 02:26:01 PM PDT 24
Finished Jun 11 02:26:52 PM PDT 24
Peak memory 256224 kb
Host smart-9f22fe48-46fd-4094-af58-daa20b4a08fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33838
6576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.338386576
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3978700218
Short name T429
Test name
Test status
Simulation time 794280537 ps
CPU time 48.1 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 02:26:48 PM PDT 24
Peak memory 255752 kb
Host smart-8d66db4d-9b95-41d4-a81f-2645f3273b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39787
00218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3978700218
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1735069744
Short name T109
Test name
Test status
Simulation time 114014805084 ps
CPU time 1839.24 seconds
Started Jun 11 02:25:58 PM PDT 24
Finished Jun 11 02:56:38 PM PDT 24
Peak memory 282344 kb
Host smart-eaf50d53-e8fe-4296-9bf8-52a14826fd5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735069744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1735069744
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1978884241
Short name T703
Test name
Test status
Simulation time 1564889470 ps
CPU time 67.54 seconds
Started Jun 11 02:26:02 PM PDT 24
Finished Jun 11 02:27:10 PM PDT 24
Peak memory 248560 kb
Host smart-74584ac8-cc99-4c4c-970b-60db251402ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978884241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1978884241
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2685064929
Short name T372
Test name
Test status
Simulation time 11820628961 ps
CPU time 71.61 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 02:27:12 PM PDT 24
Peak memory 249124 kb
Host smart-eb189077-b060-4e6c-8a9a-a1eb886007f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26850
64929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2685064929
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.875769928
Short name T98
Test name
Test status
Simulation time 2757776573 ps
CPU time 50.15 seconds
Started Jun 11 02:25:59 PM PDT 24
Finished Jun 11 02:26:50 PM PDT 24
Peak memory 257180 kb
Host smart-4986ccbb-548b-451b-9269-0599ab8f187b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87576
9928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.875769928
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.825486886
Short name T365
Test name
Test status
Simulation time 365566673 ps
CPU time 23.57 seconds
Started Jun 11 02:26:01 PM PDT 24
Finished Jun 11 02:26:26 PM PDT 24
Peak memory 255776 kb
Host smart-70c45f16-e3e4-44d1-9739-1cae35fcfe48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82548
6886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.825486886
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.794547797
Short name T460
Test name
Test status
Simulation time 471112903 ps
CPU time 29.65 seconds
Started Jun 11 02:26:01 PM PDT 24
Finished Jun 11 02:26:32 PM PDT 24
Peak memory 248804 kb
Host smart-a3ec75af-548b-4e3a-92b9-d3f935c1d897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79454
7797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.794547797
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.464148687
Short name T693
Test name
Test status
Simulation time 767488623267 ps
CPU time 2904.83 seconds
Started Jun 11 02:26:12 PM PDT 24
Finished Jun 11 03:14:38 PM PDT 24
Peak memory 289772 kb
Host smart-dfc0d999-f9c7-4483-8d32-4e1708215863
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464148687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.464148687
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1080444475
Short name T288
Test name
Test status
Simulation time 32181589984 ps
CPU time 2959.67 seconds
Started Jun 11 02:26:11 PM PDT 24
Finished Jun 11 03:15:32 PM PDT 24
Peak memory 322408 kb
Host smart-9c112af9-ffeb-42e0-abe3-cd3a44cf124a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080444475 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1080444475
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2547079281
Short name T446
Test name
Test status
Simulation time 150229968273 ps
CPU time 2117.89 seconds
Started Jun 11 02:26:34 PM PDT 24
Finished Jun 11 03:01:53 PM PDT 24
Peak memory 288532 kb
Host smart-0867f6a1-c8da-42ab-b6fb-1496524e64c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547079281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2547079281
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.980486714
Short name T432
Test name
Test status
Simulation time 7223692215 ps
CPU time 161.69 seconds
Started Jun 11 02:26:11 PM PDT 24
Finished Jun 11 02:28:53 PM PDT 24
Peak memory 257176 kb
Host smart-5beb3cd0-905c-4271-96e8-ff4cd0fd3ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98048
6714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.980486714
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.689495299
Short name T118
Test name
Test status
Simulation time 378616440 ps
CPU time 33.14 seconds
Started Jun 11 02:26:11 PM PDT 24
Finished Jun 11 02:26:45 PM PDT 24
Peak memory 256396 kb
Host smart-5409b263-5870-43c6-b5c2-d7f261edf36e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68949
5299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.689495299
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2718703870
Short name T306
Test name
Test status
Simulation time 49337653070 ps
CPU time 1348.62 seconds
Started Jun 11 02:26:12 PM PDT 24
Finished Jun 11 02:48:41 PM PDT 24
Peak memory 273568 kb
Host smart-d14ec659-44f6-497b-a60f-f84809f48b7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718703870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2718703870
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.4025140997
Short name T563
Test name
Test status
Simulation time 7321316056 ps
CPU time 1135.67 seconds
Started Jun 11 02:26:12 PM PDT 24
Finished Jun 11 02:45:08 PM PDT 24
Peak memory 281412 kb
Host smart-22a36a1a-56f4-43da-8a42-d142dc91b0e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025140997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.4025140997
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1969901511
Short name T317
Test name
Test status
Simulation time 2246915073 ps
CPU time 93.16 seconds
Started Jun 11 02:26:12 PM PDT 24
Finished Jun 11 02:27:46 PM PDT 24
Peak memory 247372 kb
Host smart-f600d62c-9b69-4790-985e-d3fdf5321c59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969901511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1969901511
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.143013625
Short name T22
Test name
Test status
Simulation time 11267904045 ps
CPU time 51.44 seconds
Started Jun 11 02:26:14 PM PDT 24
Finished Jun 11 02:27:06 PM PDT 24
Peak memory 248948 kb
Host smart-d4a22cdc-548f-41e3-991c-07730de11310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14301
3625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.143013625
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.613160950
Short name T656
Test name
Test status
Simulation time 254323227 ps
CPU time 17.3 seconds
Started Jun 11 02:26:13 PM PDT 24
Finished Jun 11 02:26:31 PM PDT 24
Peak memory 248868 kb
Host smart-f2a52d36-aafe-4c57-b1f3-a91a53c5ed4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61316
0950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.613160950
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3942284890
Short name T466
Test name
Test status
Simulation time 642813603 ps
CPU time 44.88 seconds
Started Jun 11 02:26:13 PM PDT 24
Finished Jun 11 02:26:59 PM PDT 24
Peak memory 255832 kb
Host smart-73813725-d2d1-44fe-baa5-4b66e5fd032c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39422
84890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3942284890
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2976382480
Short name T357
Test name
Test status
Simulation time 2035240864 ps
CPU time 29.67 seconds
Started Jun 11 02:26:14 PM PDT 24
Finished Jun 11 02:26:44 PM PDT 24
Peak memory 248940 kb
Host smart-080161d2-5e3c-4c69-a1a9-757615f8903e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29763
82480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2976382480
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.180053917
Short name T73
Test name
Test status
Simulation time 80397617709 ps
CPU time 2352.81 seconds
Started Jun 11 02:26:13 PM PDT 24
Finished Jun 11 03:05:27 PM PDT 24
Peak memory 289848 kb
Host smart-d05ac7d1-d734-47db-9527-a5f133ed0320
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180053917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.180053917
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2068400809
Short name T245
Test name
Test status
Simulation time 71047976819 ps
CPU time 4276.02 seconds
Started Jun 11 02:26:13 PM PDT 24
Finished Jun 11 03:37:30 PM PDT 24
Peak memory 305784 kb
Host smart-b7e70cda-cc7b-4b25-be09-61862c617d3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068400809 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2068400809
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2473769465
Short name T687
Test name
Test status
Simulation time 18671149244 ps
CPU time 1279.6 seconds
Started Jun 11 02:26:11 PM PDT 24
Finished Jun 11 02:47:31 PM PDT 24
Peak memory 273124 kb
Host smart-eda7fb63-e727-429b-b1d5-53c89ed70983
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473769465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2473769465
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1982892762
Short name T462
Test name
Test status
Simulation time 1225923841 ps
CPU time 105.41 seconds
Started Jun 11 02:26:10 PM PDT 24
Finished Jun 11 02:27:56 PM PDT 24
Peak memory 250052 kb
Host smart-2204aa73-47d3-4610-bfca-00b5dd0eff6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19828
92762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1982892762
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1111011492
Short name T701
Test name
Test status
Simulation time 897492303 ps
CPU time 50.4 seconds
Started Jun 11 02:26:12 PM PDT 24
Finished Jun 11 02:27:04 PM PDT 24
Peak memory 248896 kb
Host smart-6f490ef0-e5bd-4b61-a2cc-cb981b5ec953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11110
11492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1111011492
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1908040659
Short name T637
Test name
Test status
Simulation time 204207974235 ps
CPU time 3146.5 seconds
Started Jun 11 02:26:11 PM PDT 24
Finished Jun 11 03:18:39 PM PDT 24
Peak memory 281672 kb
Host smart-34e13fc8-ade8-442c-81c6-9fa381599309
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908040659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1908040659
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.307753841
Short name T480
Test name
Test status
Simulation time 140469311444 ps
CPU time 1921.06 seconds
Started Jun 11 02:26:12 PM PDT 24
Finished Jun 11 02:58:15 PM PDT 24
Peak memory 273188 kb
Host smart-011e24c6-58e9-422a-b849-1fe66606c28a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307753841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.307753841
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3104612515
Short name T232
Test name
Test status
Simulation time 13467536176 ps
CPU time 542.76 seconds
Started Jun 11 02:26:14 PM PDT 24
Finished Jun 11 02:35:18 PM PDT 24
Peak memory 248552 kb
Host smart-a348db98-66ce-4083-9ce5-d73bbc8de919
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104612515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3104612515
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2871541312
Short name T443
Test name
Test status
Simulation time 1739894382 ps
CPU time 30.81 seconds
Started Jun 11 02:26:12 PM PDT 24
Finished Jun 11 02:26:44 PM PDT 24
Peak memory 256564 kb
Host smart-76564aff-3fd8-4803-b863-e4ce82b0e158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28715
41312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2871541312
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3757476340
Short name T123
Test name
Test status
Simulation time 338731008 ps
CPU time 11.56 seconds
Started Jun 11 02:26:12 PM PDT 24
Finished Jun 11 02:26:25 PM PDT 24
Peak memory 248928 kb
Host smart-d705d68a-44c9-4181-8a86-c3173fc07cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37574
76340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3757476340
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3622191112
Short name T668
Test name
Test status
Simulation time 1340577311 ps
CPU time 70.75 seconds
Started Jun 11 02:26:11 PM PDT 24
Finished Jun 11 02:27:23 PM PDT 24
Peak memory 248916 kb
Host smart-bb66cc76-5f19-474d-bb43-df58aad38104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36221
91112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3622191112
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1866280504
Short name T557
Test name
Test status
Simulation time 339076178 ps
CPU time 28.73 seconds
Started Jun 11 02:26:11 PM PDT 24
Finished Jun 11 02:26:41 PM PDT 24
Peak memory 248908 kb
Host smart-eeed1e6c-e4eb-4553-abaa-5028e748ec9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18662
80504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1866280504
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.4208329167
Short name T105
Test name
Test status
Simulation time 161268783570 ps
CPU time 2951.6 seconds
Started Jun 11 02:26:15 PM PDT 24
Finished Jun 11 03:15:27 PM PDT 24
Peak memory 289336 kb
Host smart-02d7d89d-7a48-48b3-a682-8a040cc748df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208329167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.4208329167
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2035721686
Short name T266
Test name
Test status
Simulation time 73949224439 ps
CPU time 3839.54 seconds
Started Jun 11 02:26:14 PM PDT 24
Finished Jun 11 03:30:14 PM PDT 24
Peak memory 298164 kb
Host smart-19803373-9470-4b2a-945d-93a5c13bf2fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035721686 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2035721686
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1477030359
Short name T698
Test name
Test status
Simulation time 15204524719 ps
CPU time 1566.01 seconds
Started Jun 11 02:26:24 PM PDT 24
Finished Jun 11 02:52:31 PM PDT 24
Peak memory 289732 kb
Host smart-a0c2e504-23df-4dda-8ace-03c59f6767e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477030359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1477030359
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1362220759
Short name T358
Test name
Test status
Simulation time 1188659107 ps
CPU time 132.88 seconds
Started Jun 11 02:26:24 PM PDT 24
Finished Jun 11 02:28:38 PM PDT 24
Peak memory 257016 kb
Host smart-a998fbb1-45ae-4137-816a-28314a21b42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13622
20759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1362220759
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.570247483
Short name T427
Test name
Test status
Simulation time 557425609 ps
CPU time 16.4 seconds
Started Jun 11 02:26:27 PM PDT 24
Finished Jun 11 02:26:44 PM PDT 24
Peak memory 249092 kb
Host smart-9918038d-6486-46ff-b54a-ab6a58bfee5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57024
7483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.570247483
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2107011221
Short name T333
Test name
Test status
Simulation time 85992907803 ps
CPU time 2617.52 seconds
Started Jun 11 02:26:24 PM PDT 24
Finished Jun 11 03:10:03 PM PDT 24
Peak memory 289884 kb
Host smart-5cd2450d-31fe-4d7e-86db-af9447f6e117
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107011221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2107011221
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.4196754313
Short name T574
Test name
Test status
Simulation time 23731651150 ps
CPU time 1383.39 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 02:49:30 PM PDT 24
Peak memory 272696 kb
Host smart-050bfe78-b433-4689-a998-bd5042785127
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196754313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.4196754313
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.399095958
Short name T308
Test name
Test status
Simulation time 9150951825 ps
CPU time 111.79 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 02:28:19 PM PDT 24
Peak memory 253220 kb
Host smart-9b06156e-5dc1-46c0-886f-0f797ab7dc76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399095958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.399095958
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1402220702
Short name T709
Test name
Test status
Simulation time 331068431 ps
CPU time 30.01 seconds
Started Jun 11 02:26:13 PM PDT 24
Finished Jun 11 02:26:44 PM PDT 24
Peak memory 249068 kb
Host smart-d706faaf-b279-45ee-90ec-d75d24a0d99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14022
20702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1402220702
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3242912622
Short name T268
Test name
Test status
Simulation time 555638944 ps
CPU time 38.25 seconds
Started Jun 11 02:26:25 PM PDT 24
Finished Jun 11 02:27:05 PM PDT 24
Peak memory 249076 kb
Host smart-3a7e6b71-0ceb-484a-bb41-defbc439936b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32429
12622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3242912622
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3018077999
Short name T509
Test name
Test status
Simulation time 204800642 ps
CPU time 21.6 seconds
Started Jun 11 02:26:13 PM PDT 24
Finished Jun 11 02:26:35 PM PDT 24
Peak memory 248860 kb
Host smart-42ac5f7e-06cc-4b6b-95ea-614ebc1564f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30180
77999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3018077999
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.293865848
Short name T248
Test name
Test status
Simulation time 116680935270 ps
CPU time 2193.21 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 03:03:00 PM PDT 24
Peak memory 289468 kb
Host smart-22a3c123-e460-46de-b6b3-d753068cd524
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293865848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.293865848
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3477285255
Short name T276
Test name
Test status
Simulation time 39782025324 ps
CPU time 2624.2 seconds
Started Jun 11 02:26:23 PM PDT 24
Finished Jun 11 03:10:08 PM PDT 24
Peak memory 289104 kb
Host smart-aea4bacd-74c5-4e25-943b-115ba95eb022
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477285255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3477285255
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2200155212
Short name T395
Test name
Test status
Simulation time 6180773699 ps
CPU time 169.6 seconds
Started Jun 11 02:26:29 PM PDT 24
Finished Jun 11 02:29:19 PM PDT 24
Peak memory 257220 kb
Host smart-ece08e4c-1965-4582-bfb6-84f2744f4895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22001
55212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2200155212
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.669441864
Short name T373
Test name
Test status
Simulation time 220917329 ps
CPU time 14.5 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 02:26:41 PM PDT 24
Peak memory 255228 kb
Host smart-69ef0032-88f2-4e9b-b314-3d64570ea6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66944
1864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.669441864
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2335243741
Short name T300
Test name
Test status
Simulation time 23525778848 ps
CPU time 1309.5 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 02:48:16 PM PDT 24
Peak memory 273612 kb
Host smart-28fef3db-87b9-4698-a6ce-6110361362a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335243741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2335243741
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.832091386
Short name T262
Test name
Test status
Simulation time 259775452508 ps
CPU time 2412.94 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 03:06:40 PM PDT 24
Peak memory 272500 kb
Host smart-3b7b85a3-c98b-4c82-b06e-cf2d061cd314
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832091386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.832091386
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2078314977
Short name T59
Test name
Test status
Simulation time 2936824763 ps
CPU time 119.22 seconds
Started Jun 11 02:26:30 PM PDT 24
Finished Jun 11 02:28:30 PM PDT 24
Peak memory 248272 kb
Host smart-4bb07cbb-7d2d-4c55-805b-4d239e50b15f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078314977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2078314977
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2907192061
Short name T529
Test name
Test status
Simulation time 757492593 ps
CPU time 42.19 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 02:27:09 PM PDT 24
Peak memory 248944 kb
Host smart-98aa04c8-b5e9-498c-b8c4-f704ced55834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29071
92061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2907192061
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.4079768007
Short name T361
Test name
Test status
Simulation time 55624886 ps
CPU time 4.39 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 02:26:31 PM PDT 24
Peak memory 239632 kb
Host smart-72d0ddc9-ead3-4fd8-a553-1cf4161853ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40797
68007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.4079768007
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1383158853
Short name T624
Test name
Test status
Simulation time 222575217 ps
CPU time 14.73 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 02:26:42 PM PDT 24
Peak memory 248816 kb
Host smart-21d03d29-3d1e-4b28-a215-f272986c1198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13831
58853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1383158853
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3053690028
Short name T706
Test name
Test status
Simulation time 2892180905 ps
CPU time 181.94 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 02:29:29 PM PDT 24
Peak memory 257192 kb
Host smart-cf36c9a5-2455-44a4-8575-0f103a66947f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053690028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3053690028
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3689772696
Short name T58
Test name
Test status
Simulation time 62686920006 ps
CPU time 1182.95 seconds
Started Jun 11 02:26:25 PM PDT 24
Finished Jun 11 02:46:09 PM PDT 24
Peak memory 284512 kb
Host smart-f27ef557-5c02-4380-8f78-b5b743bb2ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689772696 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3689772696
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2539850510
Short name T366
Test name
Test status
Simulation time 2083782485 ps
CPU time 36.3 seconds
Started Jun 11 02:26:23 PM PDT 24
Finished Jun 11 02:27:00 PM PDT 24
Peak memory 256376 kb
Host smart-5b1e5660-7a59-4a87-9bfd-9897dc56ee1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25398
50510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2539850510
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2868372856
Short name T80
Test name
Test status
Simulation time 1399428023 ps
CPU time 45.71 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 02:27:13 PM PDT 24
Peak memory 248948 kb
Host smart-daff0799-81f3-4492-a788-4193768e1445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28683
72856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2868372856
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3154064043
Short name T659
Test name
Test status
Simulation time 16851459554 ps
CPU time 1635.21 seconds
Started Jun 11 02:26:28 PM PDT 24
Finished Jun 11 02:53:44 PM PDT 24
Peak memory 289284 kb
Host smart-21371a55-cbbd-4c40-949d-943f91d8fd0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154064043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3154064043
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.291305504
Short name T562
Test name
Test status
Simulation time 51132828090 ps
CPU time 3199.03 seconds
Started Jun 11 02:26:24 PM PDT 24
Finished Jun 11 03:19:44 PM PDT 24
Peak memory 289480 kb
Host smart-46c26b17-d1ac-468c-b221-0149cb747e88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291305504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.291305504
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.927318315
Short name T542
Test name
Test status
Simulation time 6217136225 ps
CPU time 241.3 seconds
Started Jun 11 02:26:25 PM PDT 24
Finished Jun 11 02:30:27 PM PDT 24
Peak memory 248100 kb
Host smart-9e8c5608-657a-4075-8820-7bd81e366927
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927318315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.927318315
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1083770453
Short name T233
Test name
Test status
Simulation time 883069859 ps
CPU time 17.46 seconds
Started Jun 11 02:26:25 PM PDT 24
Finished Jun 11 02:26:43 PM PDT 24
Peak memory 256408 kb
Host smart-0b9f9a9e-db08-4f9f-b5bf-ef0016062700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10837
70453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1083770453
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3953141793
Short name T512
Test name
Test status
Simulation time 719530990 ps
CPU time 40.41 seconds
Started Jun 11 02:26:27 PM PDT 24
Finished Jun 11 02:27:08 PM PDT 24
Peak memory 255964 kb
Host smart-08a08081-73da-491f-9a6d-001c6833fded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39531
41793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3953141793
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2450916196
Short name T478
Test name
Test status
Simulation time 704623930 ps
CPU time 52.57 seconds
Started Jun 11 02:26:25 PM PDT 24
Finished Jun 11 02:27:18 PM PDT 24
Peak memory 248896 kb
Host smart-56b3894a-e37f-400f-8fd8-01d92c2ef046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24509
16196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2450916196
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.693541456
Short name T362
Test name
Test status
Simulation time 629692610 ps
CPU time 16.47 seconds
Started Jun 11 02:26:26 PM PDT 24
Finished Jun 11 02:26:44 PM PDT 24
Peak memory 248876 kb
Host smart-d73ea261-db6a-47f7-afc4-284fc71820eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69354
1456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.693541456
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.4026399576
Short name T666
Test name
Test status
Simulation time 55187661320 ps
CPU time 3327.45 seconds
Started Jun 11 02:26:25 PM PDT 24
Finished Jun 11 03:21:54 PM PDT 24
Peak memory 289688 kb
Host smart-68294e97-1433-442b-9c6a-1c3077e60487
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026399576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.4026399576
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3253444192
Short name T114
Test name
Test status
Simulation time 110244232825 ps
CPU time 689.45 seconds
Started Jun 11 02:26:28 PM PDT 24
Finished Jun 11 02:37:58 PM PDT 24
Peak memory 283676 kb
Host smart-fae39d69-27da-4af3-9d49-a035a75509d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253444192 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3253444192
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3522811968
Short name T38
Test name
Test status
Simulation time 39357916 ps
CPU time 3.96 seconds
Started Jun 11 02:24:32 PM PDT 24
Finished Jun 11 02:24:37 PM PDT 24
Peak memory 249084 kb
Host smart-4d388dda-912e-45ef-ab1f-6487f4bd62b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3522811968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3522811968
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2362277810
Short name T428
Test name
Test status
Simulation time 11438214455 ps
CPU time 1246.9 seconds
Started Jun 11 02:24:34 PM PDT 24
Finished Jun 11 02:45:23 PM PDT 24
Peak memory 282640 kb
Host smart-2c947e4e-7e5b-4f55-8b81-d168b658c173
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362277810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2362277810
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.942976590
Short name T439
Test name
Test status
Simulation time 2223191339 ps
CPU time 25.62 seconds
Started Jun 11 02:24:32 PM PDT 24
Finished Jun 11 02:24:59 PM PDT 24
Peak memory 248924 kb
Host smart-02d6d1fe-01ee-4ff5-b7ac-8b1291d6263b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=942976590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.942976590
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2842053060
Short name T510
Test name
Test status
Simulation time 15395905830 ps
CPU time 305.83 seconds
Started Jun 11 02:24:33 PM PDT 24
Finished Jun 11 02:29:41 PM PDT 24
Peak memory 257192 kb
Host smart-01cdfe79-8f8b-4d42-9259-6bfc3a762593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28420
53060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2842053060
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2443805500
Short name T657
Test name
Test status
Simulation time 284081553 ps
CPU time 18.55 seconds
Started Jun 11 02:24:32 PM PDT 24
Finished Jun 11 02:24:52 PM PDT 24
Peak memory 255740 kb
Host smart-e59d9da0-0ba9-4961-ba8d-26afa0f78600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24438
05500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2443805500
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.4011693582
Short name T681
Test name
Test status
Simulation time 23679791788 ps
CPU time 1194.45 seconds
Started Jun 11 02:24:34 PM PDT 24
Finished Jun 11 02:44:30 PM PDT 24
Peak memory 265376 kb
Host smart-6815c5c1-de39-4cad-9a5c-2180d971ce49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011693582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.4011693582
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.222338567
Short name T665
Test name
Test status
Simulation time 104465457077 ps
CPU time 1851.93 seconds
Started Jun 11 02:24:35 PM PDT 24
Finished Jun 11 02:55:28 PM PDT 24
Peak memory 273568 kb
Host smart-cbc88d50-2dfe-44b3-9513-993e5d262a85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222338567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.222338567
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.690785121
Short name T62
Test name
Test status
Simulation time 8739465637 ps
CPU time 334.73 seconds
Started Jun 11 02:24:33 PM PDT 24
Finished Jun 11 02:30:10 PM PDT 24
Peak memory 248276 kb
Host smart-44eddead-786f-4545-a85e-e442f543b43e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690785121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.690785121
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.4205474507
Short name T691
Test name
Test status
Simulation time 1013294240 ps
CPU time 14.98 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:24:39 PM PDT 24
Peak memory 254364 kb
Host smart-3a72c18a-2b2e-495d-92f3-cd009f5ef6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42054
74507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.4205474507
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1587370594
Short name T633
Test name
Test status
Simulation time 6456407869 ps
CPU time 41.2 seconds
Started Jun 11 02:24:34 PM PDT 24
Finished Jun 11 02:25:17 PM PDT 24
Peak memory 255772 kb
Host smart-88166f08-452d-40b3-8a35-699cd246de2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15873
70594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1587370594
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2920497840
Short name T496
Test name
Test status
Simulation time 208104658 ps
CPU time 14.89 seconds
Started Jun 11 02:24:34 PM PDT 24
Finished Jun 11 02:24:51 PM PDT 24
Peak memory 248936 kb
Host smart-99794bdb-674e-432b-804f-1d72e318adc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29204
97840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2920497840
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.594337034
Short name T528
Test name
Test status
Simulation time 11786249333 ps
CPU time 1463.47 seconds
Started Jun 11 02:24:32 PM PDT 24
Finished Jun 11 02:48:57 PM PDT 24
Peak memory 289504 kb
Host smart-e43dd62d-43e5-4f64-a0d9-72f3b0cf7e58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594337034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.594337034
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3884229378
Short name T244
Test name
Test status
Simulation time 30056717806 ps
CPU time 1917.01 seconds
Started Jun 11 02:24:32 PM PDT 24
Finished Jun 11 02:56:30 PM PDT 24
Peak memory 272820 kb
Host smart-e07b24d4-8141-4d42-b064-f4710a9de3e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884229378 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3884229378
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1135690908
Short name T505
Test name
Test status
Simulation time 138869991909 ps
CPU time 1132.45 seconds
Started Jun 11 02:26:35 PM PDT 24
Finished Jun 11 02:45:29 PM PDT 24
Peak memory 289680 kb
Host smart-37b8b4d1-fe9e-4037-ab9a-8902f20614e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135690908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1135690908
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.4251740460
Short name T377
Test name
Test status
Simulation time 924627442 ps
CPU time 93.8 seconds
Started Jun 11 02:26:36 PM PDT 24
Finished Jun 11 02:28:11 PM PDT 24
Peak memory 256996 kb
Host smart-e53ac2b3-9f67-4f9d-8f48-61e4a87a6405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42517
40460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.4251740460
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.256355934
Short name T294
Test name
Test status
Simulation time 1447893089 ps
CPU time 24.59 seconds
Started Jun 11 02:26:35 PM PDT 24
Finished Jun 11 02:27:01 PM PDT 24
Peak memory 248884 kb
Host smart-f6db0765-fc2c-435b-9be0-9e78b2d31f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25635
5934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.256355934
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3628624029
Short name T464
Test name
Test status
Simulation time 28227019638 ps
CPU time 1404.35 seconds
Started Jun 11 02:26:37 PM PDT 24
Finished Jun 11 02:50:02 PM PDT 24
Peak memory 281456 kb
Host smart-927be52d-032e-4611-8c3c-73ca252e7f92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628624029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3628624029
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3915185457
Short name T41
Test name
Test status
Simulation time 92767334 ps
CPU time 3.9 seconds
Started Jun 11 02:26:27 PM PDT 24
Finished Jun 11 02:26:31 PM PDT 24
Peak memory 240752 kb
Host smart-1a210f36-8f4f-49cd-800f-c28b89cd61bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39151
85457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3915185457
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3126878502
Short name T116
Test name
Test status
Simulation time 3766514864 ps
CPU time 57.29 seconds
Started Jun 11 02:26:36 PM PDT 24
Finished Jun 11 02:27:34 PM PDT 24
Peak memory 256044 kb
Host smart-d66bbd55-dcb8-4e58-81a9-fc3e3b54e7df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31268
78502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3126878502
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1370562158
Short name T560
Test name
Test status
Simulation time 750333680 ps
CPU time 21.13 seconds
Started Jun 11 02:26:36 PM PDT 24
Finished Jun 11 02:26:58 PM PDT 24
Peak memory 249312 kb
Host smart-1347b90b-e943-4622-9dad-f0b79324fe5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13705
62158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1370562158
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3741912927
Short name T121
Test name
Test status
Simulation time 353402341 ps
CPU time 20.49 seconds
Started Jun 11 02:26:28 PM PDT 24
Finished Jun 11 02:26:49 PM PDT 24
Peak memory 248972 kb
Host smart-6df68b60-8b17-40a8-a73c-9a69d3670d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37419
12927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3741912927
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.388590321
Short name T605
Test name
Test status
Simulation time 108242830935 ps
CPU time 4322.64 seconds
Started Jun 11 02:26:36 PM PDT 24
Finished Jun 11 03:38:39 PM PDT 24
Peak memory 298008 kb
Host smart-ddd87b4b-c3aa-4b67-a728-0b2008da9cb4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388590321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.388590321
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1520023400
Short name T465
Test name
Test status
Simulation time 47100414493 ps
CPU time 3312.52 seconds
Started Jun 11 02:28:15 PM PDT 24
Finished Jun 11 03:23:29 PM PDT 24
Peak memory 298152 kb
Host smart-bbd36103-d1d5-40bd-8e28-ea610e1880bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520023400 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1520023400
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1625610885
Short name T53
Test name
Test status
Simulation time 50148897569 ps
CPU time 1351.09 seconds
Started Jun 11 02:26:36 PM PDT 24
Finished Jun 11 02:49:08 PM PDT 24
Peak memory 288848 kb
Host smart-86d1f22a-cb7e-45e3-8be7-5497c3754d4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625610885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1625610885
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.4079936256
Short name T72
Test name
Test status
Simulation time 7914708034 ps
CPU time 135.37 seconds
Started Jun 11 02:26:36 PM PDT 24
Finished Jun 11 02:28:53 PM PDT 24
Peak memory 257168 kb
Host smart-0f7dbef6-a3b0-41bb-bc99-2a3825ad8233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40799
36256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4079936256
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3754535114
Short name T590
Test name
Test status
Simulation time 694633298 ps
CPU time 39.05 seconds
Started Jun 11 02:26:37 PM PDT 24
Finished Jun 11 02:27:17 PM PDT 24
Peak memory 255944 kb
Host smart-7fac543e-a758-40ae-8af6-78910bde8aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37545
35114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3754535114
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3072001325
Short name T338
Test name
Test status
Simulation time 8768482239 ps
CPU time 668.37 seconds
Started Jun 11 02:26:37 PM PDT 24
Finished Jun 11 02:37:46 PM PDT 24
Peak memory 273372 kb
Host smart-525b7277-ab8a-4979-b008-8ac8386b03bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072001325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3072001325
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1813889073
Short name T696
Test name
Test status
Simulation time 95919887005 ps
CPU time 789.54 seconds
Started Jun 11 02:26:34 PM PDT 24
Finished Jun 11 02:39:44 PM PDT 24
Peak memory 273508 kb
Host smart-d1ed1559-c549-42dd-b01d-4f36f65f3a4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813889073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1813889073
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1678750676
Short name T303
Test name
Test status
Simulation time 27447085378 ps
CPU time 591.09 seconds
Started Jun 11 02:26:35 PM PDT 24
Finished Jun 11 02:36:27 PM PDT 24
Peak memory 248560 kb
Host smart-92d1587d-7cfb-41dd-8154-88efb358514b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678750676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1678750676
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1985759427
Short name T469
Test name
Test status
Simulation time 1386704382 ps
CPU time 34.48 seconds
Started Jun 11 02:26:37 PM PDT 24
Finished Jun 11 02:27:12 PM PDT 24
Peak memory 256452 kb
Host smart-06aaaf2f-d1a5-4f7d-aa7a-ffbd65040096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19857
59427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1985759427
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1658008699
Short name T670
Test name
Test status
Simulation time 1838026729 ps
CPU time 32.78 seconds
Started Jun 11 02:26:35 PM PDT 24
Finished Jun 11 02:27:09 PM PDT 24
Peak memory 248164 kb
Host smart-4ae92d92-397b-4319-b76c-924e179aa9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16580
08699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1658008699
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.252473914
Short name T368
Test name
Test status
Simulation time 2150966833 ps
CPU time 63.19 seconds
Started Jun 11 02:26:36 PM PDT 24
Finished Jun 11 02:27:40 PM PDT 24
Peak memory 256992 kb
Host smart-2a8f6050-4be1-48ca-bda4-71ae60d794a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25247
3914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.252473914
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1306057116
Short name T629
Test name
Test status
Simulation time 1264629347 ps
CPU time 46.48 seconds
Started Jun 11 02:26:37 PM PDT 24
Finished Jun 11 02:27:24 PM PDT 24
Peak memory 248920 kb
Host smart-45d76657-d6b6-4fef-bad4-489a25830291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13060
57116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1306057116
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2453431302
Short name T550
Test name
Test status
Simulation time 2023579013 ps
CPU time 112.06 seconds
Started Jun 11 02:26:38 PM PDT 24
Finished Jun 11 02:28:31 PM PDT 24
Peak memory 257100 kb
Host smart-36265469-3e9c-4931-896a-8151d1c36e2e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453431302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2453431302
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1233128808
Short name T383
Test name
Test status
Simulation time 1830728503 ps
CPU time 165.94 seconds
Started Jun 11 02:26:45 PM PDT 24
Finished Jun 11 02:29:32 PM PDT 24
Peak memory 257172 kb
Host smart-05ae3869-b0ef-4050-a6f6-3e876a395fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12331
28808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1233128808
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.86253521
Short name T81
Test name
Test status
Simulation time 152446137 ps
CPU time 15.72 seconds
Started Jun 11 02:26:46 PM PDT 24
Finished Jun 11 02:27:03 PM PDT 24
Peak memory 249488 kb
Host smart-5ca525fe-d65b-4733-981d-48c34903dd4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86253
521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.86253521
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.241247023
Short name T630
Test name
Test status
Simulation time 103207596530 ps
CPU time 1623.19 seconds
Started Jun 11 02:26:45 PM PDT 24
Finished Jun 11 02:53:49 PM PDT 24
Peak memory 265344 kb
Host smart-1d92608e-7069-4f83-b631-4a701a365c45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241247023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.241247023
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2452253121
Short name T667
Test name
Test status
Simulation time 13234040337 ps
CPU time 1132.04 seconds
Started Jun 11 02:26:48 PM PDT 24
Finished Jun 11 02:45:41 PM PDT 24
Peak memory 288260 kb
Host smart-8aac4c9f-a320-44c0-b0d5-3c235f93249e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452253121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2452253121
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3933892546
Short name T49
Test name
Test status
Simulation time 2261270844 ps
CPU time 36.26 seconds
Started Jun 11 02:26:46 PM PDT 24
Finished Jun 11 02:27:23 PM PDT 24
Peak memory 248920 kb
Host smart-08167868-7dd9-4066-b51b-e2d5a1526978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39338
92546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3933892546
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.479740036
Short name T440
Test name
Test status
Simulation time 92506538 ps
CPU time 9.04 seconds
Started Jun 11 02:26:46 PM PDT 24
Finished Jun 11 02:26:56 PM PDT 24
Peak memory 252536 kb
Host smart-3e5c2f59-cb42-4422-985c-8bae91691f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47974
0036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.479740036
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1344732072
Short name T444
Test name
Test status
Simulation time 523520620 ps
CPU time 16.62 seconds
Started Jun 11 02:26:46 PM PDT 24
Finished Jun 11 02:27:03 PM PDT 24
Peak memory 256220 kb
Host smart-168ef914-1c57-45f4-88f9-b952922c1c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13447
32072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1344732072
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.877350885
Short name T598
Test name
Test status
Simulation time 219860894 ps
CPU time 14.19 seconds
Started Jun 11 02:26:47 PM PDT 24
Finished Jun 11 02:27:02 PM PDT 24
Peak memory 257140 kb
Host smart-2845022b-fda4-4679-b0b5-f9ea9e95b065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87735
0885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.877350885
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1826761927
Short name T603
Test name
Test status
Simulation time 31899449619 ps
CPU time 909.89 seconds
Started Jun 11 02:26:47 PM PDT 24
Finished Jun 11 02:41:58 PM PDT 24
Peak memory 282704 kb
Host smart-a428d704-3c72-41e1-b2ae-4a81a2504d7d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826761927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1826761927
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2883536633
Short name T484
Test name
Test status
Simulation time 126657811137 ps
CPU time 1782.6 seconds
Started Jun 11 02:26:45 PM PDT 24
Finished Jun 11 02:56:28 PM PDT 24
Peak memory 273476 kb
Host smart-32a61ef5-0a8b-44ed-a1e7-8f783ec40e74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883536633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2883536633
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3244687785
Short name T68
Test name
Test status
Simulation time 3255789967 ps
CPU time 206.04 seconds
Started Jun 11 02:26:45 PM PDT 24
Finished Jun 11 02:30:12 PM PDT 24
Peak memory 250448 kb
Host smart-0ac3b98f-9259-488e-9a7c-335c4ea7432d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32446
87785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3244687785
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2304253841
Short name T329
Test name
Test status
Simulation time 316204712435 ps
CPU time 3297.76 seconds
Started Jun 11 02:26:45 PM PDT 24
Finished Jun 11 03:21:44 PM PDT 24
Peak memory 287056 kb
Host smart-1d9553a8-bc6e-4bc4-bd51-fb8f64b29e98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304253841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2304253841
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1651658360
Short name T75
Test name
Test status
Simulation time 102193583971 ps
CPU time 1764.33 seconds
Started Jun 11 02:26:47 PM PDT 24
Finished Jun 11 02:56:13 PM PDT 24
Peak memory 273196 kb
Host smart-1575305d-e7c4-4740-88b7-fa24760645fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651658360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1651658360
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.278000438
Short name T64
Test name
Test status
Simulation time 12462641951 ps
CPU time 261.28 seconds
Started Jun 11 02:26:48 PM PDT 24
Finished Jun 11 02:31:10 PM PDT 24
Peak memory 248528 kb
Host smart-a9099d54-dff1-4380-af62-bf24541c6f35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278000438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.278000438
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3232762297
Short name T646
Test name
Test status
Simulation time 45845377 ps
CPU time 6.56 seconds
Started Jun 11 02:26:47 PM PDT 24
Finished Jun 11 02:26:54 PM PDT 24
Peak memory 254304 kb
Host smart-c295841f-acbb-4a77-9122-05a5f9348058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32327
62297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3232762297
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2483213314
Short name T546
Test name
Test status
Simulation time 309100691 ps
CPU time 9.92 seconds
Started Jun 11 02:26:46 PM PDT 24
Finished Jun 11 02:26:57 PM PDT 24
Peak memory 248876 kb
Host smart-48b7efe5-4318-441d-9d7a-eb44bde169cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24832
13314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2483213314
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1530062042
Short name T83
Test name
Test status
Simulation time 1899161614 ps
CPU time 44.74 seconds
Started Jun 11 02:26:47 PM PDT 24
Finished Jun 11 02:27:32 PM PDT 24
Peak memory 248864 kb
Host smart-ada5a2a0-97db-4317-a5ad-0e94bbe8c0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15300
62042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1530062042
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3629702320
Short name T404
Test name
Test status
Simulation time 398532381 ps
CPU time 36.39 seconds
Started Jun 11 02:26:45 PM PDT 24
Finished Jun 11 02:27:22 PM PDT 24
Peak memory 257048 kb
Host smart-ede41075-8d4a-4b41-a447-8eabafac0cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36297
02320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3629702320
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2093889681
Short name T103
Test name
Test status
Simulation time 386957605830 ps
CPU time 3615.08 seconds
Started Jun 11 02:26:45 PM PDT 24
Finished Jun 11 03:27:01 PM PDT 24
Peak memory 289424 kb
Host smart-89402044-d06c-4e26-bb15-c18d81c0a7af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093889681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2093889681
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.392124491
Short name T604
Test name
Test status
Simulation time 5714773406 ps
CPU time 699.03 seconds
Started Jun 11 02:27:00 PM PDT 24
Finished Jun 11 02:38:39 PM PDT 24
Peak memory 265304 kb
Host smart-982b0951-698f-4026-a6b4-cf23a473daed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392124491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.392124491
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2929227673
Short name T260
Test name
Test status
Simulation time 3925967649 ps
CPU time 70.98 seconds
Started Jun 11 02:26:55 PM PDT 24
Finished Jun 11 02:28:06 PM PDT 24
Peak memory 256800 kb
Host smart-f12a8c4d-902b-4a0c-837f-941b149c1305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29292
27673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2929227673
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.4020635279
Short name T581
Test name
Test status
Simulation time 4197895772 ps
CPU time 44.85 seconds
Started Jun 11 02:26:57 PM PDT 24
Finished Jun 11 02:27:43 PM PDT 24
Peak memory 249032 kb
Host smart-a7a3678b-7cae-4e0f-a42d-682dc03a3d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40206
35279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.4020635279
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.4251236491
Short name T226
Test name
Test status
Simulation time 33506542484 ps
CPU time 691.5 seconds
Started Jun 11 02:26:58 PM PDT 24
Finished Jun 11 02:38:30 PM PDT 24
Peak memory 265252 kb
Host smart-12e8b94c-975e-4603-a4e5-a8e6c0e551c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251236491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.4251236491
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2329860499
Short name T42
Test name
Test status
Simulation time 16930911497 ps
CPU time 1105.56 seconds
Started Jun 11 02:26:58 PM PDT 24
Finished Jun 11 02:45:25 PM PDT 24
Peak memory 273260 kb
Host smart-6af65587-d1f3-4bd9-bc5a-c15299366631
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329860499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2329860499
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2195149352
Short name T312
Test name
Test status
Simulation time 39425391819 ps
CPU time 369.19 seconds
Started Jun 11 02:26:59 PM PDT 24
Finished Jun 11 02:33:09 PM PDT 24
Peak memory 248500 kb
Host smart-150e055b-31dd-4892-b524-9c0d1cc1b263
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195149352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2195149352
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2384574787
Short name T450
Test name
Test status
Simulation time 94363853 ps
CPU time 7.86 seconds
Started Jun 11 02:26:46 PM PDT 24
Finished Jun 11 02:26:55 PM PDT 24
Peak memory 248884 kb
Host smart-978cadc4-15d4-45f6-899d-01a20e6d4d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23845
74787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2384574787
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3523749206
Short name T611
Test name
Test status
Simulation time 775290951 ps
CPU time 51.68 seconds
Started Jun 11 02:26:58 PM PDT 24
Finished Jun 11 02:27:50 PM PDT 24
Peak memory 255852 kb
Host smart-171734a9-5157-40aa-a413-139ede77a9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35237
49206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3523749206
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.319360630
Short name T416
Test name
Test status
Simulation time 84524722 ps
CPU time 10.1 seconds
Started Jun 11 02:26:57 PM PDT 24
Finished Jun 11 02:27:08 PM PDT 24
Peak memory 247808 kb
Host smart-326d1e99-64ae-42c1-bae4-fc667dc8b5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31936
0630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.319360630
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3549758754
Short name T487
Test name
Test status
Simulation time 3406147205 ps
CPU time 35 seconds
Started Jun 11 02:26:46 PM PDT 24
Finished Jun 11 02:27:21 PM PDT 24
Peak memory 248936 kb
Host smart-a5eb2427-5d2c-49cd-a240-0a3dc8ec820e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35497
58754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3549758754
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2914787931
Short name T246
Test name
Test status
Simulation time 48885909418 ps
CPU time 2935.4 seconds
Started Jun 11 02:27:01 PM PDT 24
Finished Jun 11 03:15:58 PM PDT 24
Peak memory 290100 kb
Host smart-fbd7ad9a-9bc6-4e2c-bbd5-04a3651bfe5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914787931 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2914787931
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.38321383
Short name T267
Test name
Test status
Simulation time 10639593629 ps
CPU time 740.6 seconds
Started Jun 11 02:26:57 PM PDT 24
Finished Jun 11 02:39:18 PM PDT 24
Peak memory 272796 kb
Host smart-baf8ec1e-ad2b-46c5-8c0a-d324a2efac51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38321383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.38321383
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.255364768
Short name T426
Test name
Test status
Simulation time 13079124172 ps
CPU time 159.03 seconds
Started Jun 11 02:26:56 PM PDT 24
Finished Jun 11 02:29:36 PM PDT 24
Peak memory 257088 kb
Host smart-2d519354-119b-4d63-988a-3af04dce63f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25536
4768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.255364768
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2134369162
Short name T88
Test name
Test status
Simulation time 603091179 ps
CPU time 9.23 seconds
Started Jun 11 02:27:01 PM PDT 24
Finished Jun 11 02:27:11 PM PDT 24
Peak memory 249308 kb
Host smart-fe208991-8399-433b-8b90-dc60f60cebdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21343
69162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2134369162
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3142811965
Short name T524
Test name
Test status
Simulation time 111505833077 ps
CPU time 1942.92 seconds
Started Jun 11 02:26:58 PM PDT 24
Finished Jun 11 02:59:22 PM PDT 24
Peak memory 273596 kb
Host smart-6acb736f-1bd8-4c44-9345-3cea1d739c09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142811965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3142811965
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.720745515
Short name T20
Test name
Test status
Simulation time 192085092376 ps
CPU time 2858.83 seconds
Started Jun 11 02:27:10 PM PDT 24
Finished Jun 11 03:14:49 PM PDT 24
Peak memory 289364 kb
Host smart-697cbf96-6ee4-492d-a773-c01c0f0bbbd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720745515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.720745515
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3714748361
Short name T322
Test name
Test status
Simulation time 26279355868 ps
CPU time 268.95 seconds
Started Jun 11 02:26:58 PM PDT 24
Finished Jun 11 02:31:27 PM PDT 24
Peak memory 248432 kb
Host smart-581a9b77-454b-4e46-8e4e-c822c5cac8ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714748361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3714748361
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2917075142
Short name T47
Test name
Test status
Simulation time 761674016 ps
CPU time 41.09 seconds
Started Jun 11 02:26:55 PM PDT 24
Finished Jun 11 02:27:37 PM PDT 24
Peak memory 256460 kb
Host smart-30d4940e-135d-4b35-b7fc-f7f44856a755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29170
75142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2917075142
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2405158603
Short name T514
Test name
Test status
Simulation time 466493031 ps
CPU time 36.68 seconds
Started Jun 11 02:26:58 PM PDT 24
Finished Jun 11 02:27:36 PM PDT 24
Peak memory 257032 kb
Host smart-cec80009-ce98-415a-95c1-81c7a95c0dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24051
58603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2405158603
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3408450938
Short name T291
Test name
Test status
Simulation time 465876244 ps
CPU time 9.35 seconds
Started Jun 11 02:26:57 PM PDT 24
Finished Jun 11 02:27:07 PM PDT 24
Peak memory 252580 kb
Host smart-9b8cbdf9-23b9-4aef-b01f-131975aa58d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34084
50938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3408450938
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2859562599
Short name T614
Test name
Test status
Simulation time 96328731 ps
CPU time 7.62 seconds
Started Jun 11 02:26:58 PM PDT 24
Finished Jun 11 02:27:06 PM PDT 24
Peak memory 248912 kb
Host smart-2055d79f-40a5-4f4b-bbcf-695a9c0b47ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28595
62599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2859562599
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2397532442
Short name T387
Test name
Test status
Simulation time 61754127 ps
CPU time 4.41 seconds
Started Jun 11 02:27:07 PM PDT 24
Finished Jun 11 02:27:13 PM PDT 24
Peak memory 239556 kb
Host smart-4eb223f5-e7cf-40a2-bffe-9181b45678db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23975
32442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2397532442
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3089758931
Short name T653
Test name
Test status
Simulation time 65393530 ps
CPU time 7.62 seconds
Started Jun 11 02:27:08 PM PDT 24
Finished Jun 11 02:27:16 PM PDT 24
Peak memory 253408 kb
Host smart-1d1b1332-9560-4dad-8b56-85b765935d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30897
58931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3089758931
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2645702549
Short name T40
Test name
Test status
Simulation time 68154989612 ps
CPU time 2093.69 seconds
Started Jun 11 02:27:09 PM PDT 24
Finished Jun 11 03:02:03 PM PDT 24
Peak memory 273604 kb
Host smart-951d7c3c-7e4f-43f7-8bbe-f31dbc0011d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645702549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2645702549
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2553955503
Short name T21
Test name
Test status
Simulation time 80900594050 ps
CPU time 2085.26 seconds
Started Jun 11 02:27:09 PM PDT 24
Finished Jun 11 03:01:55 PM PDT 24
Peak memory 288876 kb
Host smart-f7da2c8d-6c97-4932-aedb-8b425dc51166
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553955503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2553955503
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2266700068
Short name T314
Test name
Test status
Simulation time 38227517045 ps
CPU time 441.3 seconds
Started Jun 11 02:27:10 PM PDT 24
Finished Jun 11 02:34:31 PM PDT 24
Peak memory 248060 kb
Host smart-f56d95f9-bd99-4dc4-9a83-c44eb8ac165e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266700068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2266700068
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1242288901
Short name T445
Test name
Test status
Simulation time 4892159950 ps
CPU time 56.16 seconds
Started Jun 11 02:27:11 PM PDT 24
Finished Jun 11 02:28:07 PM PDT 24
Peak memory 257208 kb
Host smart-3423ddb2-d9f0-4272-a281-e6890cd7abf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12422
88901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1242288901
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3499630015
Short name T257
Test name
Test status
Simulation time 284396164 ps
CPU time 16.98 seconds
Started Jun 11 02:27:09 PM PDT 24
Finished Jun 11 02:27:27 PM PDT 24
Peak memory 247896 kb
Host smart-5f985c79-c56d-41ad-9b00-56683edde005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34996
30015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3499630015
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3934101128
Short name T376
Test name
Test status
Simulation time 587914316 ps
CPU time 41.66 seconds
Started Jun 11 02:27:10 PM PDT 24
Finished Jun 11 02:27:52 PM PDT 24
Peak memory 255912 kb
Host smart-f755f561-ab5f-4cf3-89aa-49d2ffbb3e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39341
01128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3934101128
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.907450120
Short name T472
Test name
Test status
Simulation time 665346802 ps
CPU time 21.78 seconds
Started Jun 11 02:27:10 PM PDT 24
Finished Jun 11 02:27:33 PM PDT 24
Peak memory 256980 kb
Host smart-4541f6a9-7e17-43f2-8616-3ee19c41e97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90745
0120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.907450120
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1610594570
Short name T495
Test name
Test status
Simulation time 48617872430 ps
CPU time 194.24 seconds
Started Jun 11 02:27:07 PM PDT 24
Finished Jun 11 02:30:22 PM PDT 24
Peak memory 257092 kb
Host smart-9f368a24-60bf-495e-9f81-100e672fa7e2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610594570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1610594570
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2433960333
Short name T540
Test name
Test status
Simulation time 13467161304 ps
CPU time 780.44 seconds
Started Jun 11 02:27:08 PM PDT 24
Finished Jun 11 02:40:10 PM PDT 24
Peak memory 273008 kb
Host smart-aac16133-25bb-4687-8b0f-f6659e738c1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433960333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2433960333
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2977660828
Short name T468
Test name
Test status
Simulation time 3755786189 ps
CPU time 210.71 seconds
Started Jun 11 02:27:06 PM PDT 24
Finished Jun 11 02:30:38 PM PDT 24
Peak memory 250236 kb
Host smart-71a27497-0d65-4f0a-b71b-3745ffbc98a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29776
60828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2977660828
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.4017658996
Short name T63
Test name
Test status
Simulation time 5521517445 ps
CPU time 63.35 seconds
Started Jun 11 02:27:08 PM PDT 24
Finished Jun 11 02:28:12 PM PDT 24
Peak memory 255408 kb
Host smart-9cef566e-883f-4dbd-bd9d-e3c07b5bfbf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40176
58996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.4017658996
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1070052767
Short name T625
Test name
Test status
Simulation time 29475310035 ps
CPU time 1149.55 seconds
Started Jun 11 02:27:18 PM PDT 24
Finished Jun 11 02:46:28 PM PDT 24
Peak memory 289316 kb
Host smart-7c1279ee-d2cc-406e-9f63-cb92f3b34283
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070052767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1070052767
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2407549214
Short name T580
Test name
Test status
Simulation time 52555240366 ps
CPU time 1654.3 seconds
Started Jun 11 02:27:19 PM PDT 24
Finished Jun 11 02:54:54 PM PDT 24
Peak memory 273636 kb
Host smart-e0408737-104f-49da-a675-05b7d295d995
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407549214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2407549214
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3001095571
Short name T561
Test name
Test status
Simulation time 105934841 ps
CPU time 11.01 seconds
Started Jun 11 02:27:08 PM PDT 24
Finished Jun 11 02:27:20 PM PDT 24
Peak memory 254600 kb
Host smart-ef7f9100-0e70-4b5a-8170-0a3f9bd6aba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30010
95571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3001095571
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.904922346
Short name T613
Test name
Test status
Simulation time 159892315 ps
CPU time 6.41 seconds
Started Jun 11 02:27:08 PM PDT 24
Finished Jun 11 02:27:15 PM PDT 24
Peak memory 239528 kb
Host smart-4c4961d3-3571-4e25-9b14-b46b2531b37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90492
2346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.904922346
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3192257170
Short name T576
Test name
Test status
Simulation time 715966363 ps
CPU time 49.97 seconds
Started Jun 11 02:27:09 PM PDT 24
Finished Jun 11 02:27:59 PM PDT 24
Peak memory 247848 kb
Host smart-72819ce9-c6af-4ec0-90da-e9c0686f16c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31922
57170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3192257170
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2946565970
Short name T482
Test name
Test status
Simulation time 1678893871 ps
CPU time 50.05 seconds
Started Jun 11 02:27:11 PM PDT 24
Finished Jun 11 02:28:02 PM PDT 24
Peak memory 248972 kb
Host smart-92723c4f-df26-40b8-9ff7-0629c7aa025d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29465
65970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2946565970
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1851442642
Short name T286
Test name
Test status
Simulation time 5216191557 ps
CPU time 312.92 seconds
Started Jun 11 02:27:19 PM PDT 24
Finished Jun 11 02:32:33 PM PDT 24
Peak memory 257168 kb
Host smart-97bfc0b0-15ba-4d90-937e-db8f5762d9ce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851442642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1851442642
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2339926122
Short name T292
Test name
Test status
Simulation time 38093528686 ps
CPU time 3876.36 seconds
Started Jun 11 02:27:18 PM PDT 24
Finished Jun 11 03:31:56 PM PDT 24
Peak memory 322784 kb
Host smart-36820924-553b-4a54-82da-cbfa374f0140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339926122 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2339926122
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.863162175
Short name T527
Test name
Test status
Simulation time 17106425403 ps
CPU time 1824.52 seconds
Started Jun 11 02:27:21 PM PDT 24
Finished Jun 11 02:57:46 PM PDT 24
Peak memory 289152 kb
Host smart-c85246af-e3b8-44c3-bc16-5c19da9c2eb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863162175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.863162175
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.111487529
Short name T192
Test name
Test status
Simulation time 11260973892 ps
CPU time 141.78 seconds
Started Jun 11 02:27:20 PM PDT 24
Finished Jun 11 02:29:43 PM PDT 24
Peak memory 257192 kb
Host smart-97281798-ba41-4e3f-9a04-6eba55769d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11148
7529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.111487529
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.572538440
Short name T597
Test name
Test status
Simulation time 1188082247 ps
CPU time 24.16 seconds
Started Jun 11 02:27:19 PM PDT 24
Finished Jun 11 02:27:44 PM PDT 24
Peak memory 256944 kb
Host smart-4fa8437b-318f-412b-ad66-1df91585c7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57253
8440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.572538440
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1364251990
Short name T97
Test name
Test status
Simulation time 6235498661 ps
CPU time 618.92 seconds
Started Jun 11 02:27:17 PM PDT 24
Finished Jun 11 02:37:37 PM PDT 24
Peak memory 265532 kb
Host smart-28380186-e93b-4f52-baba-c8cb9a9b37b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364251990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1364251990
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1220015577
Short name T356
Test name
Test status
Simulation time 19149005669 ps
CPU time 1952.53 seconds
Started Jun 11 02:27:19 PM PDT 24
Finished Jun 11 02:59:52 PM PDT 24
Peak memory 289960 kb
Host smart-3e830d23-a98d-416e-af73-e7613966d9a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220015577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1220015577
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2212804115
Short name T5
Test name
Test status
Simulation time 8365799274 ps
CPU time 344.87 seconds
Started Jun 11 02:27:18 PM PDT 24
Finished Jun 11 02:33:04 PM PDT 24
Peak memory 248420 kb
Host smart-adc42e62-0008-4e54-9265-694e7f484edf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212804115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2212804115
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3992428404
Short name T621
Test name
Test status
Simulation time 890340068 ps
CPU time 36.33 seconds
Started Jun 11 02:27:18 PM PDT 24
Finished Jun 11 02:27:56 PM PDT 24
Peak memory 248968 kb
Host smart-597883ec-3459-4cc7-9450-44a0b4d5b006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39924
28404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3992428404
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.580888965
Short name T589
Test name
Test status
Simulation time 2519376420 ps
CPU time 40.1 seconds
Started Jun 11 02:27:19 PM PDT 24
Finished Jun 11 02:28:00 PM PDT 24
Peak memory 255564 kb
Host smart-e8f6a38a-19f9-4b56-a8fb-4bb630761039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58088
8965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.580888965
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2939130364
Short name T488
Test name
Test status
Simulation time 274683471 ps
CPU time 27.53 seconds
Started Jun 11 02:27:18 PM PDT 24
Finished Jun 11 02:27:47 PM PDT 24
Peak memory 255196 kb
Host smart-9bf4bef5-5bb0-48ec-8109-9830f28bc0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29391
30364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2939130364
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.77166605
Short name T190
Test name
Test status
Simulation time 582553569 ps
CPU time 42.69 seconds
Started Jun 11 02:27:19 PM PDT 24
Finished Jun 11 02:28:02 PM PDT 24
Peak memory 248848 kb
Host smart-320d7b4b-319a-4391-8c4d-b2d142ecd1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77166
605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.77166605
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.662734533
Short name T634
Test name
Test status
Simulation time 6014637580 ps
CPU time 335.69 seconds
Started Jun 11 02:27:17 PM PDT 24
Finished Jun 11 02:32:54 PM PDT 24
Peak memory 256136 kb
Host smart-b5b4ef27-bcb5-4a1d-a349-46cab670e351
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662734533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.662734533
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.973627784
Short name T247
Test name
Test status
Simulation time 70604775668 ps
CPU time 4558.75 seconds
Started Jun 11 02:27:18 PM PDT 24
Finished Jun 11 03:43:19 PM PDT 24
Peak memory 321796 kb
Host smart-15c57d93-7974-4228-a21f-5d55ff4b8c50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973627784 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.973627784
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3011122159
Short name T686
Test name
Test status
Simulation time 227923938848 ps
CPU time 3186.03 seconds
Started Jun 11 02:27:19 PM PDT 24
Finished Jun 11 03:20:26 PM PDT 24
Peak memory 289176 kb
Host smart-0ef870d4-7cdd-45c9-a200-b170af30c11a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011122159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3011122159
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1385680199
Short name T438
Test name
Test status
Simulation time 1894791711 ps
CPU time 134.4 seconds
Started Jun 11 02:27:20 PM PDT 24
Finished Jun 11 02:29:35 PM PDT 24
Peak memory 257000 kb
Host smart-7681c9bc-1a96-4b1f-9dab-a35583652cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13856
80199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1385680199
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1223701289
Short name T89
Test name
Test status
Simulation time 1176983475 ps
CPU time 39.5 seconds
Started Jun 11 02:27:20 PM PDT 24
Finished Jun 11 02:28:00 PM PDT 24
Peak memory 256312 kb
Host smart-29322733-513b-4006-822b-0bb01eb622e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12237
01289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1223701289
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.252545826
Short name T615
Test name
Test status
Simulation time 15892417500 ps
CPU time 1427.25 seconds
Started Jun 11 02:27:18 PM PDT 24
Finished Jun 11 02:51:06 PM PDT 24
Peak memory 273556 kb
Host smart-6119b745-51b6-4fc7-897f-0d0fe25d87d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252545826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.252545826
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3900109615
Short name T513
Test name
Test status
Simulation time 80877111337 ps
CPU time 1358.33 seconds
Started Jun 11 02:27:18 PM PDT 24
Finished Jun 11 02:49:58 PM PDT 24
Peak memory 267416 kb
Host smart-63a80c1d-e91c-4598-95cb-4b18fb34f6d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900109615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3900109615
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1819975203
Short name T313
Test name
Test status
Simulation time 26786814187 ps
CPU time 278.67 seconds
Started Jun 11 02:27:21 PM PDT 24
Finished Jun 11 02:32:00 PM PDT 24
Peak memory 248604 kb
Host smart-e34d9688-ac01-45af-858f-ce0560653f73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819975203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1819975203
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.613348787
Short name T675
Test name
Test status
Simulation time 1681244592 ps
CPU time 54.41 seconds
Started Jun 11 02:27:20 PM PDT 24
Finished Jun 11 02:28:15 PM PDT 24
Peak memory 248924 kb
Host smart-7a9eaf5a-1054-4f7d-a9fb-09bba458ff43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61334
8787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.613348787
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.74332722
Short name T104
Test name
Test status
Simulation time 997258164 ps
CPU time 66.77 seconds
Started Jun 11 02:27:18 PM PDT 24
Finished Jun 11 02:28:26 PM PDT 24
Peak memory 255900 kb
Host smart-807dcf75-e1eb-462a-9e0a-104d1ca07004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74332
722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.74332722
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1725635902
Short name T658
Test name
Test status
Simulation time 290810688 ps
CPU time 20.86 seconds
Started Jun 11 02:27:20 PM PDT 24
Finished Jun 11 02:27:42 PM PDT 24
Peak memory 255520 kb
Host smart-0ff1b9a2-334c-4783-b3a4-77682f67b078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17256
35902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1725635902
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.293510259
Short name T700
Test name
Test status
Simulation time 555028977 ps
CPU time 31.87 seconds
Started Jun 11 02:27:18 PM PDT 24
Finished Jun 11 02:27:51 PM PDT 24
Peak memory 256720 kb
Host smart-9f381aa2-f011-4baa-8247-42c94cf4f3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29351
0259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.293510259
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4024342427
Short name T283
Test name
Test status
Simulation time 7790856920 ps
CPU time 487.01 seconds
Started Jun 11 02:27:31 PM PDT 24
Finished Jun 11 02:35:38 PM PDT 24
Peak memory 257148 kb
Host smart-90792c69-a176-42f9-b575-c3f96f525a19
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024342427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4024342427
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.420441186
Short name T639
Test name
Test status
Simulation time 111574244239 ps
CPU time 6056.88 seconds
Started Jun 11 02:27:34 PM PDT 24
Finished Jun 11 04:08:33 PM PDT 24
Peak memory 367976 kb
Host smart-82e2e224-833a-450d-94f8-2b87f86993d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420441186 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.420441186
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.4106423571
Short name T219
Test name
Test status
Simulation time 25203110 ps
CPU time 2.5 seconds
Started Jun 11 02:24:34 PM PDT 24
Finished Jun 11 02:24:38 PM PDT 24
Peak memory 249196 kb
Host smart-9b9ab919-4f05-4db5-845a-0d837b20f26a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4106423571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.4106423571
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1871250978
Short name T559
Test name
Test status
Simulation time 25777917666 ps
CPU time 1697.99 seconds
Started Jun 11 02:24:33 PM PDT 24
Finished Jun 11 02:52:53 PM PDT 24
Peak memory 289844 kb
Host smart-8cc74183-f438-49d5-b95e-487379c4b722
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871250978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1871250978
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2219901440
Short name T711
Test name
Test status
Simulation time 684718486 ps
CPU time 11.63 seconds
Started Jun 11 02:24:33 PM PDT 24
Finished Jun 11 02:24:46 PM PDT 24
Peak memory 248808 kb
Host smart-8435707a-3fcd-43c6-b1e6-fa4b82bb983c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2219901440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2219901440
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2163149357
Short name T655
Test name
Test status
Simulation time 1673052616 ps
CPU time 118.12 seconds
Started Jun 11 02:24:34 PM PDT 24
Finished Jun 11 02:26:34 PM PDT 24
Peak memory 256864 kb
Host smart-e7676122-41a1-437d-87b4-bc7599c306ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21631
49357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2163149357
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3051843906
Short name T447
Test name
Test status
Simulation time 754565898 ps
CPU time 40.44 seconds
Started Jun 11 02:24:32 PM PDT 24
Finished Jun 11 02:25:14 PM PDT 24
Peak memory 249348 kb
Host smart-363e571a-95e8-4518-84e3-1c895179a948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30518
43906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3051843906
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.597137214
Short name T552
Test name
Test status
Simulation time 21299927845 ps
CPU time 911.69 seconds
Started Jun 11 02:24:34 PM PDT 24
Finished Jun 11 02:39:47 PM PDT 24
Peak memory 273540 kb
Host smart-8027cb65-9ee1-44cc-b9a4-541750144bdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597137214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.597137214
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.142018780
Short name T275
Test name
Test status
Simulation time 393371770390 ps
CPU time 1811.62 seconds
Started Jun 11 02:24:34 PM PDT 24
Finished Jun 11 02:54:47 PM PDT 24
Peak memory 271508 kb
Host smart-38ddd344-e392-424c-a8d4-889d5f578ef9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142018780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.142018780
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1806349043
Short name T305
Test name
Test status
Simulation time 6455239881 ps
CPU time 223.51 seconds
Started Jun 11 02:24:31 PM PDT 24
Finished Jun 11 02:28:16 PM PDT 24
Peak memory 248564 kb
Host smart-bef14865-85a7-4eab-be85-119b4a190a6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806349043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1806349043
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.235539467
Short name T415
Test name
Test status
Simulation time 1359479782 ps
CPU time 36.21 seconds
Started Jun 11 02:24:34 PM PDT 24
Finished Jun 11 02:25:13 PM PDT 24
Peak memory 248952 kb
Host smart-551483c7-a2d6-4352-874f-0c96ea95bdeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23553
9467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.235539467
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2009086547
Short name T475
Test name
Test status
Simulation time 362893929 ps
CPU time 30.22 seconds
Started Jun 11 02:24:32 PM PDT 24
Finished Jun 11 02:25:04 PM PDT 24
Peak memory 247824 kb
Host smart-4476c03c-7102-4ff1-b508-0516d29f7ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20090
86547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2009086547
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1272285010
Short name T13
Test name
Test status
Simulation time 654586378 ps
CPU time 18.45 seconds
Started Jun 11 02:24:42 PM PDT 24
Finished Jun 11 02:25:02 PM PDT 24
Peak memory 271992 kb
Host smart-dbbe2b10-103a-4701-9c96-88523c5178f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1272285010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1272285010
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.554312041
Short name T374
Test name
Test status
Simulation time 64444331 ps
CPU time 4.85 seconds
Started Jun 11 02:24:31 PM PDT 24
Finished Jun 11 02:24:37 PM PDT 24
Peak memory 239496 kb
Host smart-40dfc69e-eab8-4397-b8e5-958a1360e79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55431
2041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.554312041
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.656760458
Short name T651
Test name
Test status
Simulation time 115730604 ps
CPU time 9.05 seconds
Started Jun 11 02:24:35 PM PDT 24
Finished Jun 11 02:24:46 PM PDT 24
Peak memory 248944 kb
Host smart-c0f1246e-e036-4093-9c12-beb0d541feb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65676
0458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.656760458
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2338382083
Short name T65
Test name
Test status
Simulation time 60172937016 ps
CPU time 1846.89 seconds
Started Jun 11 02:27:32 PM PDT 24
Finished Jun 11 02:58:20 PM PDT 24
Peak memory 272904 kb
Host smart-49687db2-20cc-45ce-8342-a6a41518232c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338382083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2338382083
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.4201146055
Short name T252
Test name
Test status
Simulation time 2786566418 ps
CPU time 163.66 seconds
Started Jun 11 02:27:31 PM PDT 24
Finished Jun 11 02:30:15 PM PDT 24
Peak memory 250212 kb
Host smart-cf8fb50c-2552-441c-b308-e44a395b3aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42011
46055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.4201146055
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.578663360
Short name T702
Test name
Test status
Simulation time 152876644 ps
CPU time 5.62 seconds
Started Jun 11 02:27:35 PM PDT 24
Finished Jun 11 02:27:42 PM PDT 24
Peak memory 239696 kb
Host smart-f7361501-3b98-4178-a53a-318e7e32e75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57866
3360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.578663360
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.16153181
Short name T320
Test name
Test status
Simulation time 31422876395 ps
CPU time 1224.87 seconds
Started Jun 11 02:27:36 PM PDT 24
Finished Jun 11 02:48:02 PM PDT 24
Peak memory 281788 kb
Host smart-b1cad829-7193-4cbb-9e14-562e6532d677
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16153181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.16153181
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3062025073
Short name T188
Test name
Test status
Simulation time 118397226077 ps
CPU time 1732.76 seconds
Started Jun 11 02:27:36 PM PDT 24
Finished Jun 11 02:56:30 PM PDT 24
Peak memory 273596 kb
Host smart-d945418e-2682-4d38-90ad-87bb368db398
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062025073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3062025073
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2447504041
Short name T325
Test name
Test status
Simulation time 4863362279 ps
CPU time 212.06 seconds
Started Jun 11 02:27:31 PM PDT 24
Finished Jun 11 02:31:04 PM PDT 24
Peak memory 248128 kb
Host smart-c909a9ba-9570-44ed-a4ab-bde95c2498c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447504041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2447504041
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.470926778
Short name T254
Test name
Test status
Simulation time 371684902 ps
CPU time 34.33 seconds
Started Jun 11 02:27:32 PM PDT 24
Finished Jun 11 02:28:07 PM PDT 24
Peak memory 248884 kb
Host smart-a218e525-dbe6-4acf-8b47-7e623a6b043d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47092
6778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.470926778
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.306993146
Short name T34
Test name
Test status
Simulation time 733605162 ps
CPU time 5.22 seconds
Started Jun 11 02:27:31 PM PDT 24
Finished Jun 11 02:27:37 PM PDT 24
Peak memory 239356 kb
Host smart-ef853e1a-6991-45f9-8253-6104a4f8d0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30699
3146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.306993146
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2967447360
Short name T499
Test name
Test status
Simulation time 3110526684 ps
CPU time 56.37 seconds
Started Jun 11 02:27:32 PM PDT 24
Finished Jun 11 02:28:29 PM PDT 24
Peak memory 249408 kb
Host smart-91983fb2-232f-4277-9fa4-018f607dfd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29674
47360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2967447360
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3517204790
Short name T239
Test name
Test status
Simulation time 135678794 ps
CPU time 15.35 seconds
Started Jun 11 02:27:32 PM PDT 24
Finished Jun 11 02:27:48 PM PDT 24
Peak memory 248944 kb
Host smart-14475073-458c-4ab7-b282-ae01d1bd7212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35172
04790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3517204790
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2268994069
Short name T579
Test name
Test status
Simulation time 10882858438 ps
CPU time 1293.88 seconds
Started Jun 11 02:27:33 PM PDT 24
Finished Jun 11 02:49:08 PM PDT 24
Peak memory 289884 kb
Host smart-3e22e041-fe95-470f-b2ee-787ef5efa159
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268994069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2268994069
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.4119632337
Short name T461
Test name
Test status
Simulation time 58280837306 ps
CPU time 812.18 seconds
Started Jun 11 02:27:34 PM PDT 24
Finished Jun 11 02:41:07 PM PDT 24
Peak memory 270476 kb
Host smart-f3fa6a77-54c2-4b51-8be6-10926f1be9fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119632337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.4119632337
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1850458120
Short name T640
Test name
Test status
Simulation time 475351198 ps
CPU time 34.37 seconds
Started Jun 11 02:27:34 PM PDT 24
Finished Jun 11 02:28:09 PM PDT 24
Peak memory 255040 kb
Host smart-afa9cc12-2727-4d7e-bef3-48231ed1c2a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18504
58120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1850458120
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.873458166
Short name T474
Test name
Test status
Simulation time 1124864171 ps
CPU time 34.91 seconds
Started Jun 11 02:27:33 PM PDT 24
Finished Jun 11 02:28:09 PM PDT 24
Peak memory 248952 kb
Host smart-9461f77b-d461-41e2-bc0b-967eb8e539ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87345
8166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.873458166
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3777579227
Short name T707
Test name
Test status
Simulation time 141055753271 ps
CPU time 2119.02 seconds
Started Jun 11 02:27:33 PM PDT 24
Finished Jun 11 03:02:53 PM PDT 24
Peak memory 273544 kb
Host smart-991aa428-b3bd-48e7-a7cc-ae142f017ee7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777579227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3777579227
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3745164394
Short name T430
Test name
Test status
Simulation time 156793538842 ps
CPU time 2628.76 seconds
Started Jun 11 02:27:32 PM PDT 24
Finished Jun 11 03:11:22 PM PDT 24
Peak memory 273744 kb
Host smart-49b8029f-8314-4046-8f7f-67549c8fcc76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745164394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3745164394
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.4230522398
Short name T456
Test name
Test status
Simulation time 28856551221 ps
CPU time 323.46 seconds
Started Jun 11 02:27:32 PM PDT 24
Finished Jun 11 02:32:57 PM PDT 24
Peak memory 248452 kb
Host smart-bc5f342f-a6e0-4940-bfbf-beed42390e9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230522398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.4230522398
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3311576417
Short name T363
Test name
Test status
Simulation time 892270638 ps
CPU time 51.31 seconds
Started Jun 11 02:27:32 PM PDT 24
Finished Jun 11 02:28:25 PM PDT 24
Peak memory 248936 kb
Host smart-c304b0da-a83d-4927-a5ce-a36ad6162c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33115
76417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3311576417
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1360175253
Short name T57
Test name
Test status
Simulation time 1399706890 ps
CPU time 28.31 seconds
Started Jun 11 02:27:31 PM PDT 24
Finished Jun 11 02:28:00 PM PDT 24
Peak memory 256728 kb
Host smart-9cab5a1e-85a5-4b8f-bd2d-76520bec3dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13601
75253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1360175253
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.120808039
Short name T594
Test name
Test status
Simulation time 828788072 ps
CPU time 50.1 seconds
Started Jun 11 02:27:34 PM PDT 24
Finished Jun 11 02:28:26 PM PDT 24
Peak memory 255672 kb
Host smart-1a9f71c0-ff60-4668-ba18-9ad46902e48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12080
8039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.120808039
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2522023076
Short name T577
Test name
Test status
Simulation time 653065560 ps
CPU time 17.65 seconds
Started Jun 11 02:27:34 PM PDT 24
Finished Jun 11 02:27:53 PM PDT 24
Peak memory 256344 kb
Host smart-bc1e3b8f-c0aa-42a5-b232-977073a86689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25220
23076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2522023076
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2608377451
Short name T493
Test name
Test status
Simulation time 1632843866 ps
CPU time 73.6 seconds
Started Jun 11 02:27:34 PM PDT 24
Finished Jun 11 02:28:48 PM PDT 24
Peak memory 257092 kb
Host smart-4776cf3c-973c-4c11-9454-e7828a008c14
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608377451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2608377451
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4122544964
Short name T301
Test name
Test status
Simulation time 28255595313 ps
CPU time 2089.99 seconds
Started Jun 11 02:27:34 PM PDT 24
Finished Jun 11 03:02:25 PM PDT 24
Peak memory 285596 kb
Host smart-bae171f8-6d92-4899-9b3f-4fab83ace82d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122544964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4122544964
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.335977126
Short name T504
Test name
Test status
Simulation time 10379634994 ps
CPU time 298.32 seconds
Started Jun 11 02:27:33 PM PDT 24
Finished Jun 11 02:32:33 PM PDT 24
Peak memory 251192 kb
Host smart-43a7ae65-be3f-4380-8356-52890df7e39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33597
7126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.335977126
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.4020551281
Short name T485
Test name
Test status
Simulation time 3140876905 ps
CPU time 25.9 seconds
Started Jun 11 02:27:30 PM PDT 24
Finished Jun 11 02:27:56 PM PDT 24
Peak memory 249292 kb
Host smart-464bb089-bfb9-4d98-b392-aa5fa4c8c663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40205
51281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4020551281
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.651246105
Short name T532
Test name
Test status
Simulation time 7529033290 ps
CPU time 683 seconds
Started Jun 11 02:27:40 PM PDT 24
Finished Jun 11 02:39:04 PM PDT 24
Peak memory 273080 kb
Host smart-ff3621be-03ef-4608-a584-3d8cb17698d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651246105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.651246105
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1858213355
Short name T66
Test name
Test status
Simulation time 161584470369 ps
CPU time 2982.65 seconds
Started Jun 11 02:27:39 PM PDT 24
Finished Jun 11 03:17:23 PM PDT 24
Peak memory 287768 kb
Host smart-2a9bcd55-a585-42e5-8f5a-0b611db26114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858213355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1858213355
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3766973786
Short name T319
Test name
Test status
Simulation time 6374949723 ps
CPU time 131.54 seconds
Started Jun 11 02:27:33 PM PDT 24
Finished Jun 11 02:29:46 PM PDT 24
Peak memory 248120 kb
Host smart-d52fa5e5-35e8-4cc7-9a82-0b8d5e4bc8a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766973786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3766973786
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.4064583341
Short name T662
Test name
Test status
Simulation time 425082844 ps
CPU time 29.55 seconds
Started Jun 11 02:27:36 PM PDT 24
Finished Jun 11 02:28:06 PM PDT 24
Peak memory 257112 kb
Host smart-d675976c-3508-4f17-b7e7-897204cb550a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40645
83341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.4064583341
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3682932854
Short name T235
Test name
Test status
Simulation time 6178526168 ps
CPU time 50.77 seconds
Started Jun 11 02:27:32 PM PDT 24
Finished Jun 11 02:28:24 PM PDT 24
Peak memory 256400 kb
Host smart-da61b374-6fa4-481f-8610-d11cf3dd474d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36829
32854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3682932854
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1642779683
Short name T699
Test name
Test status
Simulation time 195730657 ps
CPU time 14.06 seconds
Started Jun 11 02:27:32 PM PDT 24
Finished Jun 11 02:27:48 PM PDT 24
Peak memory 254156 kb
Host smart-6aca222f-e228-4496-88cd-4c7c7a18f31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16427
79683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1642779683
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3315135281
Short name T359
Test name
Test status
Simulation time 3271483282 ps
CPU time 52.23 seconds
Started Jun 11 02:27:33 PM PDT 24
Finished Jun 11 02:28:26 PM PDT 24
Peak memory 248844 kb
Host smart-641f7b31-fed7-4197-87da-42555f8336c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33151
35281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3315135281
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2369909947
Short name T50
Test name
Test status
Simulation time 37579881741 ps
CPU time 2038.74 seconds
Started Jun 11 02:27:38 PM PDT 24
Finished Jun 11 03:01:39 PM PDT 24
Peak memory 285456 kb
Host smart-1974c733-1483-4e91-b211-1bba7e306266
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369909947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2369909947
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2285317975
Short name T612
Test name
Test status
Simulation time 58922568224 ps
CPU time 2004.89 seconds
Started Jun 11 02:27:40 PM PDT 24
Finished Jun 11 03:01:07 PM PDT 24
Peak memory 281820 kb
Host smart-c2b67996-089d-4796-bd3c-210568bacd73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285317975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2285317975
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3388676194
Short name T606
Test name
Test status
Simulation time 1942121791 ps
CPU time 143.31 seconds
Started Jun 11 02:27:40 PM PDT 24
Finished Jun 11 02:30:05 PM PDT 24
Peak memory 257016 kb
Host smart-4a0c05e8-90e7-43ce-a846-b28c52defb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33886
76194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3388676194
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.247682692
Short name T622
Test name
Test status
Simulation time 221019138 ps
CPU time 21.01 seconds
Started Jun 11 02:27:39 PM PDT 24
Finished Jun 11 02:28:02 PM PDT 24
Peak memory 256164 kb
Host smart-c2149f48-8403-47d2-99ea-909871bac2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24768
2692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.247682692
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.330154231
Short name T677
Test name
Test status
Simulation time 112646037489 ps
CPU time 1566.74 seconds
Started Jun 11 02:27:41 PM PDT 24
Finished Jun 11 02:53:50 PM PDT 24
Peak memory 270548 kb
Host smart-def42c84-493e-4918-a201-8273ad0b0695
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330154231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.330154231
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3792112235
Short name T410
Test name
Test status
Simulation time 62808065717 ps
CPU time 1442.58 seconds
Started Jun 11 02:27:41 PM PDT 24
Finished Jun 11 02:51:45 PM PDT 24
Peak memory 289012 kb
Host smart-a13f3095-1e8f-4a07-a221-9fc1e1011b18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792112235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3792112235
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3109696181
Short name T324
Test name
Test status
Simulation time 14251760775 ps
CPU time 293.15 seconds
Started Jun 11 02:27:40 PM PDT 24
Finished Jun 11 02:32:35 PM PDT 24
Peak memory 248540 kb
Host smart-3f4172e6-4ae5-48cd-bd73-e4feb4190aab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109696181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3109696181
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.820855068
Short name T545
Test name
Test status
Simulation time 494436355 ps
CPU time 29 seconds
Started Jun 11 02:27:40 PM PDT 24
Finished Jun 11 02:28:10 PM PDT 24
Peak memory 257064 kb
Host smart-e25098a0-c622-4011-b7f0-e2138223cbaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82085
5068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.820855068
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3208799049
Short name T626
Test name
Test status
Simulation time 282821744 ps
CPU time 29.43 seconds
Started Jun 11 02:27:40 PM PDT 24
Finished Jun 11 02:28:11 PM PDT 24
Peak memory 248024 kb
Host smart-c98acabf-2fd2-4a76-ba1a-4f04fe19678f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32087
99049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3208799049
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1102286751
Short name T278
Test name
Test status
Simulation time 749300704 ps
CPU time 15.08 seconds
Started Jun 11 02:27:39 PM PDT 24
Finished Jun 11 02:27:55 PM PDT 24
Peak memory 254740 kb
Host smart-624f01e4-053a-4fc0-adbc-21270802dee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11022
86751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1102286751
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3811455045
Short name T690
Test name
Test status
Simulation time 118537825 ps
CPU time 5.19 seconds
Started Jun 11 02:27:38 PM PDT 24
Finished Jun 11 02:27:44 PM PDT 24
Peak memory 240648 kb
Host smart-f4ac5a6a-5203-4f87-8c4c-100c7f12ab6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38114
55045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3811455045
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1137390835
Short name T51
Test name
Test status
Simulation time 12303062130 ps
CPU time 1137.6 seconds
Started Jun 11 02:27:39 PM PDT 24
Finished Jun 11 02:46:39 PM PDT 24
Peak memory 287032 kb
Host smart-309991f0-c783-48c4-b432-1cb99627509f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137390835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1137390835
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2632082278
Short name T56
Test name
Test status
Simulation time 91957406503 ps
CPU time 9060.02 seconds
Started Jun 11 02:27:38 PM PDT 24
Finished Jun 11 04:58:41 PM PDT 24
Peak memory 395084 kb
Host smart-1724d70d-9064-425f-9148-7fbd60a9cb53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632082278 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2632082278
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1636593909
Short name T229
Test name
Test status
Simulation time 161050235412 ps
CPU time 3105.15 seconds
Started Jun 11 02:27:48 PM PDT 24
Finished Jun 11 03:19:35 PM PDT 24
Peak memory 281740 kb
Host smart-35f1060f-b5af-44eb-afba-d07859083d3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636593909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1636593909
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.194538150
Short name T508
Test name
Test status
Simulation time 20086098125 ps
CPU time 282.79 seconds
Started Jun 11 02:27:50 PM PDT 24
Finished Jun 11 02:32:34 PM PDT 24
Peak memory 257076 kb
Host smart-de07e80a-65aa-4246-8c60-9f9f61d0311c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453
8150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.194538150
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2026752015
Short name T588
Test name
Test status
Simulation time 88121477 ps
CPU time 8.9 seconds
Started Jun 11 02:27:49 PM PDT 24
Finished Jun 11 02:28:00 PM PDT 24
Peak memory 252804 kb
Host smart-458b3892-1e77-4339-8ff5-ac81121a9730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20267
52015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2026752015
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1210783383
Short name T645
Test name
Test status
Simulation time 36784094338 ps
CPU time 1002.13 seconds
Started Jun 11 02:27:50 PM PDT 24
Finished Jun 11 02:44:34 PM PDT 24
Peak memory 273584 kb
Host smart-7c1e85de-5ddd-4405-8e55-801af18bd85c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210783383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1210783383
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3128814082
Short name T223
Test name
Test status
Simulation time 28388932056 ps
CPU time 1485.75 seconds
Started Jun 11 02:27:50 PM PDT 24
Finished Jun 11 02:52:38 PM PDT 24
Peak memory 285204 kb
Host smart-c5a79e01-dbe8-4474-9f0b-355ea3b1f353
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128814082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3128814082
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.927448855
Short name T396
Test name
Test status
Simulation time 4118468434 ps
CPU time 67.79 seconds
Started Jun 11 02:27:40 PM PDT 24
Finished Jun 11 02:28:50 PM PDT 24
Peak memory 249144 kb
Host smart-e5984475-262d-4602-961e-4f4d4c65e525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92744
8855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.927448855
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.341857434
Short name T234
Test name
Test status
Simulation time 294943081 ps
CPU time 17.28 seconds
Started Jun 11 02:27:48 PM PDT 24
Finished Jun 11 02:28:06 PM PDT 24
Peak memory 255816 kb
Host smart-ab188222-beca-4a24-806c-b9ab0fee49c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34185
7434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.341857434
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1086101153
Short name T591
Test name
Test status
Simulation time 1823807654 ps
CPU time 55.09 seconds
Started Jun 11 02:27:41 PM PDT 24
Finished Jun 11 02:28:37 PM PDT 24
Peak memory 257152 kb
Host smart-bda793c8-02e4-46e6-bdfb-13f68657381e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861
01153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1086101153
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3280390783
Short name T54
Test name
Test status
Simulation time 221067485210 ps
CPU time 3662.86 seconds
Started Jun 11 02:27:49 PM PDT 24
Finished Jun 11 03:28:54 PM PDT 24
Peak memory 305580 kb
Host smart-9014ca39-200a-4ce9-8e84-c312c5c75e23
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280390783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3280390783
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.458237807
Short name T94
Test name
Test status
Simulation time 36505205891 ps
CPU time 1767.26 seconds
Started Jun 11 02:27:48 PM PDT 24
Finished Jun 11 02:57:17 PM PDT 24
Peak memory 281848 kb
Host smart-7d1e54eb-104d-40cf-a626-f40e5006a3f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458237807 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.458237807
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1422810148
Short name T620
Test name
Test status
Simulation time 61328388508 ps
CPU time 1102.22 seconds
Started Jun 11 02:27:49 PM PDT 24
Finished Jun 11 02:46:13 PM PDT 24
Peak memory 265368 kb
Host smart-614df54c-f538-4d12-89e9-0f0ea1b70c08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422810148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1422810148
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3310617536
Short name T582
Test name
Test status
Simulation time 28950744357 ps
CPU time 245.33 seconds
Started Jun 11 02:27:50 PM PDT 24
Finished Jun 11 02:31:57 PM PDT 24
Peak memory 257160 kb
Host smart-a11fcc2d-7d60-4479-b57f-35534846a5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33106
17536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3310617536
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2477922000
Short name T8
Test name
Test status
Simulation time 29554340 ps
CPU time 4.6 seconds
Started Jun 11 02:27:51 PM PDT 24
Finished Jun 11 02:27:57 PM PDT 24
Peak memory 251256 kb
Host smart-5dfb164e-3abe-4d79-8bbf-8c3d0ba48041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24779
22000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2477922000
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1422829082
Short name T538
Test name
Test status
Simulation time 9968894299 ps
CPU time 1283.21 seconds
Started Jun 11 02:27:51 PM PDT 24
Finished Jun 11 02:49:16 PM PDT 24
Peak memory 289440 kb
Host smart-5fa11d74-7714-4618-9d67-f600ead7d247
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422829082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1422829082
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1791456448
Short name T227
Test name
Test status
Simulation time 12134653399 ps
CPU time 242.38 seconds
Started Jun 11 02:27:49 PM PDT 24
Finished Jun 11 02:31:53 PM PDT 24
Peak memory 247340 kb
Host smart-12285607-65f1-49ba-a6a5-7652f669f29a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791456448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1791456448
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3609060733
Short name T644
Test name
Test status
Simulation time 199587702 ps
CPU time 19.7 seconds
Started Jun 11 02:27:48 PM PDT 24
Finished Jun 11 02:28:09 PM PDT 24
Peak memory 248912 kb
Host smart-d2a40271-a7a6-4bd5-ba10-198c48f9533c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36090
60733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3609060733
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1180531746
Short name T454
Test name
Test status
Simulation time 1150059026 ps
CPU time 58.91 seconds
Started Jun 11 02:27:49 PM PDT 24
Finished Jun 11 02:28:50 PM PDT 24
Peak memory 257124 kb
Host smart-5f70f11d-2506-4451-87c4-61dae92fb5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11805
31746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1180531746
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.157450654
Short name T458
Test name
Test status
Simulation time 1867749294 ps
CPU time 46.14 seconds
Started Jun 11 02:27:49 PM PDT 24
Finished Jun 11 02:28:36 PM PDT 24
Peak memory 256376 kb
Host smart-f7ab0a2e-bb4e-4405-9d1d-a01222ff2cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15745
0654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.157450654
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.496642299
Short name T673
Test name
Test status
Simulation time 301414403 ps
CPU time 23.16 seconds
Started Jun 11 02:27:49 PM PDT 24
Finished Jun 11 02:28:14 PM PDT 24
Peak memory 256916 kb
Host smart-69b3d342-de2d-489e-afcf-48fad1032fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49664
2299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.496642299
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3973345197
Short name T25
Test name
Test status
Simulation time 16862330110 ps
CPU time 1862.89 seconds
Started Jun 11 02:27:51 PM PDT 24
Finished Jun 11 02:58:55 PM PDT 24
Peak memory 306364 kb
Host smart-1c779d5c-85af-4624-89ea-d5524f3ad991
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973345197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3973345197
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.181291068
Short name T618
Test name
Test status
Simulation time 272218742419 ps
CPU time 1779.36 seconds
Started Jun 11 02:28:02 PM PDT 24
Finished Jun 11 02:57:42 PM PDT 24
Peak memory 282728 kb
Host smart-e03423d5-b12f-475d-a84d-84ff9c93c2d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181291068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.181291068
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1670560866
Short name T43
Test name
Test status
Simulation time 1570205403 ps
CPU time 24.38 seconds
Started Jun 11 02:28:01 PM PDT 24
Finished Jun 11 02:28:26 PM PDT 24
Peak memory 255712 kb
Host smart-2a786c48-99a8-4229-af8b-99f867b3729d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16705
60866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1670560866
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2759872779
Short name T77
Test name
Test status
Simulation time 259117863 ps
CPU time 21.39 seconds
Started Jun 11 02:27:48 PM PDT 24
Finished Jun 11 02:28:11 PM PDT 24
Peak memory 256176 kb
Host smart-35e6d60b-d5ac-4b4a-9c96-b89554741e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27598
72779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2759872779
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.4173515798
Short name T522
Test name
Test status
Simulation time 40733609422 ps
CPU time 772.38 seconds
Started Jun 11 02:27:58 PM PDT 24
Finished Jun 11 02:40:51 PM PDT 24
Peak memory 271772 kb
Host smart-735249e6-1a47-434c-93cd-bc65a4a9e078
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173515798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.4173515798
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3804038181
Short name T556
Test name
Test status
Simulation time 46621643740 ps
CPU time 2748.77 seconds
Started Jun 11 02:28:03 PM PDT 24
Finished Jun 11 03:13:53 PM PDT 24
Peak memory 289044 kb
Host smart-05e312ff-5570-4e9b-b684-445d6a6c3dc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804038181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3804038181
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.555699985
Short name T311
Test name
Test status
Simulation time 5130272008 ps
CPU time 197.98 seconds
Started Jun 11 02:28:01 PM PDT 24
Finished Jun 11 02:31:20 PM PDT 24
Peak memory 248672 kb
Host smart-1dfcd341-f8d7-4148-96d8-cd5f1b9716d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555699985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.555699985
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.5020308
Short name T407
Test name
Test status
Simulation time 2170293296 ps
CPU time 38.1 seconds
Started Jun 11 02:27:50 PM PDT 24
Finished Jun 11 02:28:30 PM PDT 24
Peak memory 248956 kb
Host smart-cfc3280a-7d74-4bf0-9a7e-df724403e90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50203
08 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.5020308
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.455520591
Short name T393
Test name
Test status
Simulation time 1262907196 ps
CPU time 23.07 seconds
Started Jun 11 02:27:48 PM PDT 24
Finished Jun 11 02:28:12 PM PDT 24
Peak memory 248900 kb
Host smart-8f33983e-f151-4c14-96df-9affcfa7863f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45552
0591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.455520591
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3364932901
Short name T664
Test name
Test status
Simulation time 409722390 ps
CPU time 24.3 seconds
Started Jun 11 02:28:00 PM PDT 24
Finished Jun 11 02:28:25 PM PDT 24
Peak memory 248012 kb
Host smart-72555b2b-be39-4209-8b87-a880491033c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33649
32901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3364932901
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3022350873
Short name T548
Test name
Test status
Simulation time 2224793099 ps
CPU time 25.33 seconds
Started Jun 11 02:27:49 PM PDT 24
Finished Jun 11 02:28:16 PM PDT 24
Peak memory 248992 kb
Host smart-990c6c37-22d2-48ee-8524-600a9734e13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30223
50873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3022350873
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2975733675
Short name T518
Test name
Test status
Simulation time 314545100031 ps
CPU time 2871.14 seconds
Started Jun 11 02:28:02 PM PDT 24
Finished Jun 11 03:15:54 PM PDT 24
Peak memory 289412 kb
Host smart-9f9e958d-fd75-4c74-805e-fefddbdd260c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975733675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2975733675
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2229186440
Short name T661
Test name
Test status
Simulation time 84974661982 ps
CPU time 1560.53 seconds
Started Jun 11 02:28:01 PM PDT 24
Finished Jun 11 02:54:02 PM PDT 24
Peak memory 272984 kb
Host smart-57b8cf53-d19b-480f-aef8-c889bb08e7be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229186440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2229186440
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1452202532
Short name T635
Test name
Test status
Simulation time 2476079213 ps
CPU time 129.99 seconds
Started Jun 11 02:27:59 PM PDT 24
Finished Jun 11 02:30:10 PM PDT 24
Peak memory 257092 kb
Host smart-46bcb187-06dc-441c-af42-4d6ba6ab5181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14522
02532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1452202532
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1601312500
Short name T222
Test name
Test status
Simulation time 342047600 ps
CPU time 33.4 seconds
Started Jun 11 02:28:02 PM PDT 24
Finished Jun 11 02:28:37 PM PDT 24
Peak memory 248972 kb
Host smart-e3a655a4-7802-4e3f-8b83-43d09c08e710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16013
12500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1601312500
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2546397423
Short name T340
Test name
Test status
Simulation time 11575000199 ps
CPU time 911.62 seconds
Started Jun 11 02:28:11 PM PDT 24
Finished Jun 11 02:43:23 PM PDT 24
Peak memory 271504 kb
Host smart-c6e396b5-ed92-42be-9954-f13e500427a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546397423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2546397423
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2625357731
Short name T273
Test name
Test status
Simulation time 69106456427 ps
CPU time 1944.41 seconds
Started Jun 11 02:28:11 PM PDT 24
Finished Jun 11 03:00:36 PM PDT 24
Peak memory 272700 kb
Host smart-90f4b752-5155-4444-b6da-778dee1fcbe9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625357731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2625357731
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3148473644
Short name T449
Test name
Test status
Simulation time 1135727376 ps
CPU time 16.14 seconds
Started Jun 11 02:28:03 PM PDT 24
Finished Jun 11 02:28:20 PM PDT 24
Peak memory 254500 kb
Host smart-fd95f4ff-46c4-4489-ad20-d822ce3e419e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31484
73644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3148473644
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2135651206
Short name T392
Test name
Test status
Simulation time 2110548805 ps
CPU time 33.84 seconds
Started Jun 11 02:28:01 PM PDT 24
Finished Jun 11 02:28:36 PM PDT 24
Peak memory 255880 kb
Host smart-0ed19a74-de60-4820-90aa-9c5cd447e60d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21356
51206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2135651206
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1809617649
Short name T382
Test name
Test status
Simulation time 1752349569 ps
CPU time 55.43 seconds
Started Jun 11 02:28:02 PM PDT 24
Finished Jun 11 02:28:58 PM PDT 24
Peak memory 257008 kb
Host smart-6c9fc620-5a73-4f87-b1cc-2792bfdbd598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18096
17649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1809617649
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2099032553
Short name T367
Test name
Test status
Simulation time 292228604 ps
CPU time 24.37 seconds
Started Jun 11 02:28:01 PM PDT 24
Finished Jun 11 02:28:26 PM PDT 24
Peak memory 257100 kb
Host smart-bfa445ad-93c0-49f5-9ed3-07c28f4e64b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20990
32553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2099032553
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1640459908
Short name T52
Test name
Test status
Simulation time 94959040592 ps
CPU time 2728.32 seconds
Started Jun 11 02:28:11 PM PDT 24
Finished Jun 11 03:13:41 PM PDT 24
Peak memory 317668 kb
Host smart-d3f5acaf-256e-44c0-ab76-82bba540a881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640459908 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1640459908
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.686340372
Short name T93
Test name
Test status
Simulation time 282562019531 ps
CPU time 2762.75 seconds
Started Jun 11 02:28:12 PM PDT 24
Finished Jun 11 03:14:16 PM PDT 24
Peak memory 287112 kb
Host smart-d4ad955d-af7f-4934-af9d-a5314f303779
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686340372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.686340372
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1814575948
Short name T70
Test name
Test status
Simulation time 782452493 ps
CPU time 61.28 seconds
Started Jun 11 02:28:12 PM PDT 24
Finished Jun 11 02:29:14 PM PDT 24
Peak memory 257120 kb
Host smart-20bac5e3-a7a1-49a3-8cee-bac8cc33e326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18145
75948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1814575948
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1334782708
Short name T526
Test name
Test status
Simulation time 229021506 ps
CPU time 5.77 seconds
Started Jun 11 02:28:10 PM PDT 24
Finished Jun 11 02:28:17 PM PDT 24
Peak memory 250248 kb
Host smart-f06a8f2f-bf54-4b4a-9b66-19e7d6582ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13347
82708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1334782708
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3190048857
Short name T297
Test name
Test status
Simulation time 122581370219 ps
CPU time 1783.88 seconds
Started Jun 11 02:28:11 PM PDT 24
Finished Jun 11 02:57:56 PM PDT 24
Peak memory 281956 kb
Host smart-cef0c019-072c-434b-a4e4-13e7d5e47f72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190048857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3190048857
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.116966788
Short name T551
Test name
Test status
Simulation time 28037459489 ps
CPU time 655.99 seconds
Started Jun 11 02:28:11 PM PDT 24
Finished Jun 11 02:39:08 PM PDT 24
Peak memory 272900 kb
Host smart-349164f4-0fb5-45ed-ad07-b17052c14406
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116966788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.116966788
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.12945276
Short name T697
Test name
Test status
Simulation time 10780880394 ps
CPU time 113.59 seconds
Started Jun 11 02:28:12 PM PDT 24
Finished Jun 11 02:30:06 PM PDT 24
Peak memory 248188 kb
Host smart-805cf4cf-e3e4-496b-a4fa-00a69a56a014
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12945276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.12945276
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2728083806
Short name T78
Test name
Test status
Simulation time 1396713963 ps
CPU time 31.95 seconds
Started Jun 11 02:28:12 PM PDT 24
Finished Jun 11 02:28:45 PM PDT 24
Peak memory 256288 kb
Host smart-8dcc70e0-0af6-4374-8051-5d747fe0eb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27280
83806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2728083806
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2202040326
Short name T231
Test name
Test status
Simulation time 249651697 ps
CPU time 14.44 seconds
Started Jun 11 02:28:10 PM PDT 24
Finished Jun 11 02:28:26 PM PDT 24
Peak memory 255916 kb
Host smart-2188e950-8ff2-4077-a507-e9e15e7217b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22020
40326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2202040326
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.4021310024
Short name T503
Test name
Test status
Simulation time 779121246 ps
CPU time 19.19 seconds
Started Jun 11 02:28:11 PM PDT 24
Finished Jun 11 02:28:31 PM PDT 24
Peak memory 248988 kb
Host smart-84002242-7db8-4c7b-9656-847810b6d815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40213
10024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4021310024
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2280738404
Short name T492
Test name
Test status
Simulation time 1157470533495 ps
CPU time 8278.25 seconds
Started Jun 11 02:28:24 PM PDT 24
Finished Jun 11 04:46:24 PM PDT 24
Peak memory 403012 kb
Host smart-5b968cf9-e2bf-499a-b58a-9059ee53627f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280738404 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2280738404
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.160804821
Short name T507
Test name
Test status
Simulation time 45672790091 ps
CPU time 2236.45 seconds
Started Jun 11 02:28:24 PM PDT 24
Finished Jun 11 03:05:41 PM PDT 24
Peak memory 285444 kb
Host smart-27d55af0-2620-4a77-ad2c-f707d5cdf03a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160804821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.160804821
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.41912422
Short name T689
Test name
Test status
Simulation time 23647953367 ps
CPU time 372.88 seconds
Started Jun 11 02:28:23 PM PDT 24
Finished Jun 11 02:34:37 PM PDT 24
Peak memory 257164 kb
Host smart-fcb956ae-be51-4236-a111-77f7c086ed4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41912
422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.41912422
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3198194823
Short name T491
Test name
Test status
Simulation time 372208602 ps
CPU time 23.53 seconds
Started Jun 11 02:28:23 PM PDT 24
Finished Jun 11 02:28:47 PM PDT 24
Peak memory 249136 kb
Host smart-1d1178b2-e041-4c10-9f33-1a2eff69bfd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31981
94823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3198194823
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2214420865
Short name T298
Test name
Test status
Simulation time 76413386895 ps
CPU time 2278.54 seconds
Started Jun 11 02:28:24 PM PDT 24
Finished Jun 11 03:06:23 PM PDT 24
Peak memory 272884 kb
Host smart-29860bd4-bb62-4901-8155-840101c35414
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214420865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2214420865
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.4036802790
Short name T448
Test name
Test status
Simulation time 11831783111 ps
CPU time 944.24 seconds
Started Jun 11 02:28:24 PM PDT 24
Finished Jun 11 02:44:10 PM PDT 24
Peak memory 269948 kb
Host smart-07af8e4a-e7f3-486c-a7de-53a73c267a6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036802790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.4036802790
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3537596186
Short name T506
Test name
Test status
Simulation time 24915443088 ps
CPU time 271.83 seconds
Started Jun 11 02:28:24 PM PDT 24
Finished Jun 11 02:32:57 PM PDT 24
Peak memory 248344 kb
Host smart-5566859c-44f6-4fa9-af9e-cfd3c1b80e0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537596186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3537596186
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.235416858
Short name T530
Test name
Test status
Simulation time 724702509 ps
CPU time 25.25 seconds
Started Jun 11 02:28:24 PM PDT 24
Finished Jun 11 02:28:51 PM PDT 24
Peak memory 257116 kb
Host smart-ee570ec6-bfcf-447f-9263-4c1053a8b1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23541
6858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.235416858
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1580406739
Short name T224
Test name
Test status
Simulation time 277727622 ps
CPU time 21.22 seconds
Started Jun 11 02:28:24 PM PDT 24
Finished Jun 11 02:28:46 PM PDT 24
Peak memory 247912 kb
Host smart-4581afb9-79f8-4dd0-9d41-cd8ea00db62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15804
06739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1580406739
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1225122580
Short name T534
Test name
Test status
Simulation time 3114233599 ps
CPU time 50.1 seconds
Started Jun 11 02:28:23 PM PDT 24
Finished Jun 11 02:29:14 PM PDT 24
Peak memory 255980 kb
Host smart-a2af057a-5e3c-4694-b4a4-57daa2189b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12251
22580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1225122580
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2750060356
Short name T435
Test name
Test status
Simulation time 855500574 ps
CPU time 49.13 seconds
Started Jun 11 02:28:24 PM PDT 24
Finished Jun 11 02:29:15 PM PDT 24
Peak memory 248896 kb
Host smart-91c53ea7-a934-4b07-999d-e3af3f704a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27500
60356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2750060356
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.360293680
Short name T102
Test name
Test status
Simulation time 12448188010 ps
CPU time 732.38 seconds
Started Jun 11 02:28:25 PM PDT 24
Finished Jun 11 02:40:38 PM PDT 24
Peak memory 273628 kb
Host smart-4ab7c555-203a-4cbe-9066-0d04650745c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360293680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.360293680
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.4054837401
Short name T215
Test name
Test status
Simulation time 38726599 ps
CPU time 3.47 seconds
Started Jun 11 02:24:41 PM PDT 24
Finished Jun 11 02:24:47 PM PDT 24
Peak memory 249092 kb
Host smart-c001bf54-fc3b-4f6b-ad20-65a713f70be7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4054837401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.4054837401
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1397347664
Short name T45
Test name
Test status
Simulation time 22902495237 ps
CPU time 1308.94 seconds
Started Jun 11 02:24:41 PM PDT 24
Finished Jun 11 02:46:32 PM PDT 24
Peak memory 265312 kb
Host smart-62f3a703-b9cf-48c1-b719-48818a06ac7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397347664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1397347664
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3202728484
Short name T695
Test name
Test status
Simulation time 731096937 ps
CPU time 31.41 seconds
Started Jun 11 02:24:41 PM PDT 24
Finished Jun 11 02:25:14 PM PDT 24
Peak memory 240756 kb
Host smart-cc40fc8c-fe84-4ddf-b79b-2da4f8d9c908
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3202728484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3202728484
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1977760044
Short name T385
Test name
Test status
Simulation time 3272436108 ps
CPU time 194.89 seconds
Started Jun 11 02:24:41 PM PDT 24
Finished Jun 11 02:27:58 PM PDT 24
Peak memory 257148 kb
Host smart-771bd309-4d50-4052-9357-5b46fbc6f746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19777
60044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1977760044
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1238504038
Short name T467
Test name
Test status
Simulation time 584811793 ps
CPU time 10.9 seconds
Started Jun 11 02:24:43 PM PDT 24
Finished Jun 11 02:24:55 PM PDT 24
Peak memory 252600 kb
Host smart-28470471-cfd0-4164-be1b-3afb770c85d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12385
04038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1238504038
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2219287675
Short name T525
Test name
Test status
Simulation time 30576462273 ps
CPU time 748.09 seconds
Started Jun 11 02:24:43 PM PDT 24
Finished Jun 11 02:37:12 PM PDT 24
Peak memory 268412 kb
Host smart-04932a89-ff4e-4aa3-bb19-0300e435a790
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219287675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2219287675
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2828583751
Short name T652
Test name
Test status
Simulation time 424774760 ps
CPU time 26.1 seconds
Started Jun 11 02:24:41 PM PDT 24
Finished Jun 11 02:25:09 PM PDT 24
Peak memory 248972 kb
Host smart-22b30328-2a42-4861-a132-636957d69e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28285
83751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2828583751
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2641104245
Short name T380
Test name
Test status
Simulation time 360790831 ps
CPU time 34.21 seconds
Started Jun 11 02:24:42 PM PDT 24
Finished Jun 11 02:25:18 PM PDT 24
Peak memory 248868 kb
Host smart-f1e33201-c744-4ca4-9570-a5992adfd7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26411
04245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2641104245
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1096152776
Short name T479
Test name
Test status
Simulation time 179901061 ps
CPU time 21.6 seconds
Started Jun 11 02:24:47 PM PDT 24
Finished Jun 11 02:25:10 PM PDT 24
Peak memory 248896 kb
Host smart-bc98c2ff-1be6-4a20-a245-5d32112d171b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10961
52776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1096152776
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2738215083
Short name T378
Test name
Test status
Simulation time 157917648 ps
CPU time 11.99 seconds
Started Jun 11 02:24:41 PM PDT 24
Finished Jun 11 02:24:55 PM PDT 24
Peak memory 248848 kb
Host smart-cac3092d-2857-4134-bc01-3142e6dbf5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27382
15083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2738215083
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2665753108
Short name T549
Test name
Test status
Simulation time 61875701892 ps
CPU time 1447.44 seconds
Started Jun 11 02:24:42 PM PDT 24
Finished Jun 11 02:48:51 PM PDT 24
Peak memory 300692 kb
Host smart-631b07d3-7ffa-4ce1-8dd1-958512736936
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665753108 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2665753108
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.987839363
Short name T220
Test name
Test status
Simulation time 105753745 ps
CPU time 3.01 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:24:56 PM PDT 24
Peak memory 249156 kb
Host smart-d7b84aeb-d107-46d8-b17f-138bc945a6bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=987839363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.987839363
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3766751032
Short name T242
Test name
Test status
Simulation time 99472490342 ps
CPU time 1453.13 seconds
Started Jun 11 02:24:53 PM PDT 24
Finished Jun 11 02:49:07 PM PDT 24
Peak memory 286780 kb
Host smart-1eab66fc-bf62-4cba-affb-8ce73b38f048
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766751032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3766751032
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.871120132
Short name T641
Test name
Test status
Simulation time 977591202 ps
CPU time 23.2 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:25:17 PM PDT 24
Peak memory 248956 kb
Host smart-9d0461e0-0770-4168-a622-1f3ec70a503b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=871120132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.871120132
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.595378622
Short name T411
Test name
Test status
Simulation time 8491881736 ps
CPU time 59.18 seconds
Started Jun 11 02:24:51 PM PDT 24
Finished Jun 11 02:25:52 PM PDT 24
Peak memory 256456 kb
Host smart-80f0d1cf-e33f-4247-8e96-f0b1bf179a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59537
8622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.595378622
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.522857868
Short name T600
Test name
Test status
Simulation time 281755609 ps
CPU time 31.77 seconds
Started Jun 11 02:24:41 PM PDT 24
Finished Jun 11 02:25:15 PM PDT 24
Peak memory 248888 kb
Host smart-fdd2fda2-4879-4c90-ba50-e86a8c314ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52285
7868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.522857868
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2918942266
Short name T33
Test name
Test status
Simulation time 114339781503 ps
CPU time 1703 seconds
Started Jun 11 02:24:53 PM PDT 24
Finished Jun 11 02:53:17 PM PDT 24
Peak memory 273572 kb
Host smart-a03cecc2-b7c7-41bb-9946-76976ad3a127
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918942266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2918942266
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.12737148
Short name T648
Test name
Test status
Simulation time 135999819268 ps
CPU time 1827.15 seconds
Started Jun 11 02:24:51 PM PDT 24
Finished Jun 11 02:55:19 PM PDT 24
Peak memory 272932 kb
Host smart-c2e5be0a-4509-4835-8d6c-f62a7e0784d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12737148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.12737148
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1415835606
Short name T500
Test name
Test status
Simulation time 2688075728 ps
CPU time 110.65 seconds
Started Jun 11 02:24:50 PM PDT 24
Finished Jun 11 02:26:42 PM PDT 24
Peak memory 248452 kb
Host smart-e02716ff-41aa-41ff-9100-ca0499459702
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415835606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1415835606
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1720802633
Short name T425
Test name
Test status
Simulation time 1206706787 ps
CPU time 22.08 seconds
Started Jun 11 02:24:40 PM PDT 24
Finished Jun 11 02:25:04 PM PDT 24
Peak memory 256032 kb
Host smart-c02f851e-316a-4acf-a7c3-a6b8410d5d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17208
02633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1720802633
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.49924518
Short name T533
Test name
Test status
Simulation time 337050310 ps
CPU time 24.36 seconds
Started Jun 11 02:24:41 PM PDT 24
Finished Jun 11 02:25:07 PM PDT 24
Peak memory 248904 kb
Host smart-c81c911c-88f3-48aa-a4d3-0a2592057804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49924
518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.49924518
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3345640401
Short name T284
Test name
Test status
Simulation time 1305685063 ps
CPU time 43.76 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:25:37 PM PDT 24
Peak memory 248856 kb
Host smart-53a643be-98df-40ec-a17c-fb2e51a9c9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33456
40401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3345640401
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.57525153
Short name T608
Test name
Test status
Simulation time 1994988744 ps
CPU time 28.52 seconds
Started Jun 11 02:24:41 PM PDT 24
Finished Jun 11 02:25:12 PM PDT 24
Peak memory 248880 kb
Host smart-10db01f3-4909-49ec-9337-ee173a8e3a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57525
153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.57525153
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1670163803
Short name T71
Test name
Test status
Simulation time 99428767 ps
CPU time 4.21 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:24:58 PM PDT 24
Peak memory 249152 kb
Host smart-80025aa5-321c-44bb-8cce-c00435371db2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1670163803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1670163803
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.891857312
Short name T101
Test name
Test status
Simulation time 23906127081 ps
CPU time 1684.38 seconds
Started Jun 11 02:24:53 PM PDT 24
Finished Jun 11 02:52:59 PM PDT 24
Peak memory 272884 kb
Host smart-26effdf0-9585-4a39-8c83-3aef9c473c48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891857312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.891857312
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2117813706
Short name T437
Test name
Test status
Simulation time 544995400 ps
CPU time 14.27 seconds
Started Jun 11 02:24:53 PM PDT 24
Finished Jun 11 02:25:08 PM PDT 24
Peak memory 248992 kb
Host smart-942540d3-c772-48bf-b5ac-e54514e6bc5c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2117813706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2117813706
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1857512713
Short name T9
Test name
Test status
Simulation time 150793936 ps
CPU time 10.18 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:25:03 PM PDT 24
Peak memory 254792 kb
Host smart-0003b6bd-75fa-43df-b4b1-a5da43fde2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18575
12713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1857512713
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2686042144
Short name T90
Test name
Test status
Simulation time 362843924 ps
CPU time 23.02 seconds
Started Jun 11 02:24:53 PM PDT 24
Finished Jun 11 02:25:17 PM PDT 24
Peak memory 255580 kb
Host smart-c3e6a0ea-0e8a-470c-b6f8-c06abe2d63ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26860
42144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2686042144
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4011266612
Short name T296
Test name
Test status
Simulation time 22637602975 ps
CPU time 971.38 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:41:05 PM PDT 24
Peak memory 273500 kb
Host smart-334580d0-da2e-481b-aedd-34667b1c5977
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011266612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4011266612
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.313177996
Short name T564
Test name
Test status
Simulation time 72782211154 ps
CPU time 1178.71 seconds
Started Jun 11 02:24:51 PM PDT 24
Finished Jun 11 02:44:32 PM PDT 24
Peak memory 273400 kb
Host smart-dfdb3232-ad38-4eb5-9a01-e8e0f1f6d0a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313177996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.313177996
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2669684782
Short name T304
Test name
Test status
Simulation time 42932102507 ps
CPU time 331.98 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:30:25 PM PDT 24
Peak memory 256588 kb
Host smart-d5846324-9975-414e-a1d3-23e4279fcf1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669684782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2669684782
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2211683752
Short name T498
Test name
Test status
Simulation time 574778638 ps
CPU time 12.44 seconds
Started Jun 11 02:24:51 PM PDT 24
Finished Jun 11 02:25:05 PM PDT 24
Peak memory 253160 kb
Host smart-9d275f05-d9c7-4019-8c47-5e09c760d9ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22116
83752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2211683752
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1635720416
Short name T418
Test name
Test status
Simulation time 2397192481 ps
CPU time 34.84 seconds
Started Jun 11 02:24:51 PM PDT 24
Finished Jun 11 02:25:27 PM PDT 24
Peak memory 256524 kb
Host smart-b2a47c4a-7f7e-4e98-89e3-59e5994ecabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16357
20416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1635720416
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.270877695
Short name T389
Test name
Test status
Simulation time 43271693 ps
CPU time 3.42 seconds
Started Jun 11 02:24:54 PM PDT 24
Finished Jun 11 02:24:58 PM PDT 24
Peak memory 239556 kb
Host smart-376023d9-330c-49ca-bca4-fd32404b9954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27087
7695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.270877695
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2674725710
Short name T401
Test name
Test status
Simulation time 240303641 ps
CPU time 17.99 seconds
Started Jun 11 02:24:51 PM PDT 24
Finished Jun 11 02:25:11 PM PDT 24
Peak memory 248952 kb
Host smart-ef280690-ebfe-4a8b-9f7d-62fdddaf4e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26747
25710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2674725710
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3668267695
Short name T290
Test name
Test status
Simulation time 27486839214 ps
CPU time 2028.15 seconds
Started Jun 11 02:24:53 PM PDT 24
Finished Jun 11 02:58:43 PM PDT 24
Peak memory 285196 kb
Host smart-adbb34c9-3345-4f30-9677-6a65767635cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668267695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3668267695
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1094012142
Short name T120
Test name
Test status
Simulation time 38750726554 ps
CPU time 4201.02 seconds
Started Jun 11 02:24:54 PM PDT 24
Finished Jun 11 03:34:56 PM PDT 24
Peak memory 305044 kb
Host smart-3c09e3e1-97c3-4bd2-b320-6b5159da39fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094012142 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1094012142
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.427896807
Short name T206
Test name
Test status
Simulation time 51082275 ps
CPU time 4.06 seconds
Started Jun 11 02:24:53 PM PDT 24
Finished Jun 11 02:24:58 PM PDT 24
Peak memory 249156 kb
Host smart-b4627081-8495-4a42-83e8-10b973e6ddef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=427896807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.427896807
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3202262329
Short name T628
Test name
Test status
Simulation time 47617882721 ps
CPU time 1107.33 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:43:20 PM PDT 24
Peak memory 273532 kb
Host smart-574c81b7-16d4-460e-84a0-2de8cdf58ab5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202262329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3202262329
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3228872104
Short name T424
Test name
Test status
Simulation time 212064636 ps
CPU time 10.86 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:25:04 PM PDT 24
Peak memory 248928 kb
Host smart-2c4e7051-1f37-440a-b53c-5dfcdadb1f17
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3228872104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3228872104
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2565893566
Short name T583
Test name
Test status
Simulation time 477205544 ps
CPU time 44.89 seconds
Started Jun 11 02:24:53 PM PDT 24
Finished Jun 11 02:25:39 PM PDT 24
Peak memory 257088 kb
Host smart-fda032b4-a5ee-4d81-91be-4c3fc400075f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25658
93566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2565893566
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.204407521
Short name T400
Test name
Test status
Simulation time 3000565668 ps
CPU time 33.68 seconds
Started Jun 11 02:24:51 PM PDT 24
Finished Jun 11 02:25:26 PM PDT 24
Peak memory 248952 kb
Host smart-01ed7aef-a5af-4527-9925-c11a44fd325e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20440
7521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.204407521
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2854914021
Short name T332
Test name
Test status
Simulation time 24047291381 ps
CPU time 1507.75 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:50:01 PM PDT 24
Peak memory 273476 kb
Host smart-57965930-0ba6-4bc4-a577-3207651141c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854914021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2854914021
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1723558492
Short name T566
Test name
Test status
Simulation time 89363311004 ps
CPU time 2690.76 seconds
Started Jun 11 02:24:54 PM PDT 24
Finished Jun 11 03:09:46 PM PDT 24
Peak memory 283892 kb
Host smart-2e309f64-7fdf-4105-8bec-6e02423ed030
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723558492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1723558492
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.184923250
Short name T326
Test name
Test status
Simulation time 13798549768 ps
CPU time 547.53 seconds
Started Jun 11 02:24:51 PM PDT 24
Finished Jun 11 02:33:59 PM PDT 24
Peak memory 256068 kb
Host smart-db38050e-7cba-481d-b1ea-0aa62ee6515a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184923250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.184923250
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3852341847
Short name T515
Test name
Test status
Simulation time 1852267879 ps
CPU time 41.67 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:25:35 PM PDT 24
Peak memory 248916 kb
Host smart-fde2b29c-e32f-4d95-875c-3f68b95b9976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38523
41847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3852341847
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.143893846
Short name T413
Test name
Test status
Simulation time 170358584 ps
CPU time 13.04 seconds
Started Jun 11 02:24:54 PM PDT 24
Finished Jun 11 02:25:08 PM PDT 24
Peak memory 247604 kb
Host smart-c9b252d3-8150-46cd-a71b-c8c7e958f3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14389
3846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.143893846
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1649817259
Short name T265
Test name
Test status
Simulation time 144634671 ps
CPU time 14.42 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:25:08 PM PDT 24
Peak memory 248896 kb
Host smart-9a553aa9-ffb2-435c-8921-5428b43898d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16498
17259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1649817259
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1584470871
Short name T402
Test name
Test status
Simulation time 155057894 ps
CPU time 12.11 seconds
Started Jun 11 02:24:54 PM PDT 24
Finished Jun 11 02:25:07 PM PDT 24
Peak memory 248940 kb
Host smart-3e27a1c5-3a72-4ec8-8ba9-e45f55e1527e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15844
70871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1584470871
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.4208944505
Short name T569
Test name
Test status
Simulation time 49114328606 ps
CPU time 2037.03 seconds
Started Jun 11 02:24:52 PM PDT 24
Finished Jun 11 02:58:51 PM PDT 24
Peak memory 289956 kb
Host smart-7121bab7-c0d2-4499-9601-515fd6e2fb22
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208944505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.4208944505
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.276897229
Short name T185
Test name
Test status
Simulation time 122280204166 ps
CPU time 3399.59 seconds
Started Jun 11 02:25:08 PM PDT 24
Finished Jun 11 03:21:49 PM PDT 24
Peak memory 322324 kb
Host smart-a73daa70-5b4e-4c5d-9243-c447959040e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276897229 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.276897229
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1375581580
Short name T211
Test name
Test status
Simulation time 95092213 ps
CPU time 2.51 seconds
Started Jun 11 02:25:03 PM PDT 24
Finished Jun 11 02:25:07 PM PDT 24
Peak memory 249144 kb
Host smart-7bcc8495-63ae-4ef1-ae5c-d55c8d6b4ce5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1375581580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1375581580
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.650588901
Short name T627
Test name
Test status
Simulation time 32222839900 ps
CPU time 1762.56 seconds
Started Jun 11 02:25:04 PM PDT 24
Finished Jun 11 02:54:28 PM PDT 24
Peak memory 271980 kb
Host smart-b1e8dba5-a8f7-4281-b70e-c15fa989fa58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650588901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.650588901
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3519160753
Short name T241
Test name
Test status
Simulation time 697407638 ps
CPU time 8.67 seconds
Started Jun 11 02:25:08 PM PDT 24
Finished Jun 11 02:25:18 PM PDT 24
Peak memory 248980 kb
Host smart-98b36333-1353-4c1c-9902-72647505d224
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3519160753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3519160753
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3228912985
Short name T584
Test name
Test status
Simulation time 13994545522 ps
CPU time 183.67 seconds
Started Jun 11 02:25:04 PM PDT 24
Finished Jun 11 02:28:09 PM PDT 24
Peak memory 257184 kb
Host smart-0a71fc2e-2e8a-4eb2-81e2-a6cd77318401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32289
12985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3228912985
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3789555065
Short name T523
Test name
Test status
Simulation time 121202508 ps
CPU time 9.71 seconds
Started Jun 11 02:25:02 PM PDT 24
Finished Jun 11 02:25:13 PM PDT 24
Peak memory 248976 kb
Host smart-9eaf91d3-6bac-4d6a-9845-ab1dbf3a7899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37895
55065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3789555065
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1738862896
Short name T685
Test name
Test status
Simulation time 21461999565 ps
CPU time 1078.28 seconds
Started Jun 11 02:25:05 PM PDT 24
Finished Jun 11 02:43:04 PM PDT 24
Peak memory 271832 kb
Host smart-98710ecc-199f-4da8-a4c4-8e09dee4ce48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738862896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1738862896
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.263301442
Short name T74
Test name
Test status
Simulation time 356095572737 ps
CPU time 2755.76 seconds
Started Jun 11 02:25:05 PM PDT 24
Finished Jun 11 03:11:02 PM PDT 24
Peak memory 289304 kb
Host smart-529755c6-0241-4e1e-8e85-18814847e104
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263301442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.263301442
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1874624188
Short name T309
Test name
Test status
Simulation time 11254785428 ps
CPU time 438.67 seconds
Started Jun 11 02:25:04 PM PDT 24
Finished Jun 11 02:32:24 PM PDT 24
Peak memory 247984 kb
Host smart-dad809b0-16eb-41c6-bec1-375072f5ed79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874624188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1874624188
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1861529893
Short name T676
Test name
Test status
Simulation time 1016606277 ps
CPU time 56.78 seconds
Started Jun 11 02:25:06 PM PDT 24
Finished Jun 11 02:26:04 PM PDT 24
Peak memory 255788 kb
Host smart-d725a7f0-a2c7-4cc3-a0df-9b8efc58036b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18615
29893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1861529893
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2785034923
Short name T10
Test name
Test status
Simulation time 54446801 ps
CPU time 3.25 seconds
Started Jun 11 02:25:04 PM PDT 24
Finished Jun 11 02:25:09 PM PDT 24
Peak memory 239648 kb
Host smart-e65db872-9c01-46ec-887c-f6866d78e772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27850
34923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2785034923
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2496459904
Short name T67
Test name
Test status
Simulation time 1139471824 ps
CPU time 18.58 seconds
Started Jun 11 02:25:05 PM PDT 24
Finished Jun 11 02:25:25 PM PDT 24
Peak memory 252804 kb
Host smart-7e79d4a0-d8b6-4675-a187-e0589f8a3dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24964
59904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2496459904
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.492373833
Short name T688
Test name
Test status
Simulation time 255894747 ps
CPU time 17.16 seconds
Started Jun 11 02:25:03 PM PDT 24
Finished Jun 11 02:25:21 PM PDT 24
Peak memory 248916 kb
Host smart-36d3d62b-7303-43eb-a787-8aa02f09764c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49237
3833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.492373833
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2214378123
Short name T289
Test name
Test status
Simulation time 14841374149 ps
CPU time 1492.51 seconds
Started Jun 11 02:25:04 PM PDT 24
Finished Jun 11 02:49:58 PM PDT 24
Peak memory 288824 kb
Host smart-01194133-96e8-4ced-80b8-23eb98b86bc7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214378123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2214378123
Directory /workspace/9.alert_handler_stress_all/latest
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