Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	88575	1			T5	15		T14	1811		T15	470
class_i[0x1]	35831	1			T3	2942		T5	1		T14	1556
class_i[0x2]	63650	1			T3	2		T5	1		T12	2
class_i[0x3]	54505	1			T3	4		T5	1		T12	3345

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	61962	1			T3	864		T5	3		T12	811
alert[0x1]	61197	1			T3	751		T5	8		T12	880
alert[0x2]	57876	1			T3	641		T5	2		T12	850
alert[0x3]	61526	1			T3	692		T5	5		T12	806

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

242301

1

T3

2948

T5

12

T12

3347

esc_ping_fail

260

1

T5

6

T7

9

T8

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	61885	1			T3	864		T5	2		T12	811
esc_integrity_fail	alert[0x1]	61127	1			T3	751		T5	6		T12	880
esc_integrity_fail	alert[0x2]	57816	1			T3	641		T5	1		T12	850
esc_integrity_fail	alert[0x3]	61473	1			T3	692		T5	3		T12	806
esc_ping_fail	alert[0x0]	77	1			T5	1		T7	2		T8	2
esc_ping_fail	alert[0x1]	70	1			T5	2		T7	2		T8	2
esc_ping_fail	alert[0x2]	60	1			T5	1		T7	3		T8	2
esc_ping_fail	alert[0x3]	53	1			T5	2		T7	2		T8	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	88505	1			T5	12		T14	1811		T15	470
esc_integrity_fail	class_i[0x1]	35769	1			T3	2942		T14	1556		T15	1205
esc_integrity_fail	class_i[0x2]	63574	1			T3	2		T12	2		T17	3372
esc_integrity_fail	class_i[0x3]	54453	1			T3	4		T12	3345		T15	4388
esc_ping_fail	class_i[0x0]	70	1			T5	3		T74	3		T296	7
esc_ping_fail	class_i[0x1]	62	1			T5	1		T73	2		T84	1
esc_ping_fail	class_i[0x2]	76	1			T5	1		T7	7		T8	8
esc_ping_fail	class_i[0x3]	52	1			T5	1		T7	2		T301	6