Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	161	1			T1	1		T3	1		T38	1
index[0x1]	153	1			T3	2		T17	1		T14	2
index[0x2]	157	1			T3	1		T17	1		T13	1
index[0x3]	162	1			T17	1		T13	1		T34	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	215	1			T13	1		T14	1		T39	1
lens_less_than_1000[1]	132	1			T3	1		T14	1		T38	2
lens_less_than_1000[2]	62	1			T3	2		T13	1		T40	1
lens_less_than_1000[3]	62	1			T17	1		T45	5		T49	1
lens_less_than_1000[4]	59	1			T1	1		T15	2		T63	1
lens_less_than_1000[5]	43	1			T3	1		T17	1		T15	2
lens_less_than_1000[6]	18	1			T34	1		T24	1		T195	1
lens_less_than_1000[7]	12	1			T17	1		T110	1		T269	1
lens_less_than_1000[8]	19	1			T74	1		T47	2		T48	1
lens_less_than_1000[9]	6	1			T270	2		T94	1		T271	1
len_2	5	1			T223	3		T242	1		T272	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x2]]	[lens_less_than_1000[9] , len_2]	--	--	2
[index[0x3]]	[len_2]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	51	1			T73	2		T23	1		T273	1
index[0x0]	lens_less_than_1000[1]	27	1			T38	1		T15	1		T42	1
index[0x0]	lens_less_than_1000[2]	20	1			T3	1		T45	1		T48	1
index[0x0]	lens_less_than_1000[3]	18	1			T45	2		T49	1		T92	1
index[0x0]	lens_less_than_1000[4]	17	1			T1	1		T89	1		T274	3
index[0x0]	lens_less_than_1000[5]	14	1			T49	2		T222	1		T275	1
index[0x0]	lens_less_than_1000[6]	5	1			T24	1		T246	1		T233	3
index[0x0]	lens_less_than_1000[7]	1	1			T276	1		-	-		-	-
index[0x0]	lens_less_than_1000[8]	3	1			T47	2		T48	1		-	-
index[0x0]	lens_less_than_1000[9]	3	1			T270	2		T277	1		-	-
index[0x0]	len_2	2	1			T242	1		T272	1		-	-
index[0x1]	lens_less_than_1000[0]	41	1			T14	1		T8	1		T116	1
index[0x1]	lens_less_than_1000[1]	46	1			T14	1		T78	1		T45	1
index[0x1]	lens_less_than_1000[2]	14	1			T3	1		T44	1		T116	1
index[0x1]	lens_less_than_1000[3]	10	1			T17	1		T45	1		T243	1
index[0x1]	lens_less_than_1000[4]	17	1			T15	2		T119	1		T278	1
index[0x1]	lens_less_than_1000[5]	11	1			T3	1		T47	2		T279	1
index[0x1]	lens_less_than_1000[6]	4	1			T280	1		T235	1		T281	1
index[0x1]	lens_less_than_1000[7]	3	1			T196	1		T282	2		-	-
index[0x1]	lens_less_than_1000[8]	2	1			T74	1		T283	1		-	-
index[0x1]	lens_less_than_1000[9]	2	1			T94	1		T284	1		-	-
index[0x1]	len_2	3	1			T223	3		-	-		-	-
index[0x2]	lens_less_than_1000[0]	66	1			T39	1		T8	1		T73	1
index[0x2]	lens_less_than_1000[1]	29	1			T3	1		T42	1		T113	1
index[0x2]	lens_less_than_1000[2]	13	1			T13	1		T46	1		T50	1
index[0x2]	lens_less_than_1000[3]	18	1			T111	1		T285	1		T112	1
index[0x2]	lens_less_than_1000[4]	4	1			T63	1		T52	1		T286	1
index[0x2]	lens_less_than_1000[5]	12	1			T17	1		T15	2		T89	1
index[0x2]	lens_less_than_1000[6]	5	1			T195	1		T54	1		T287	1
index[0x2]	lens_less_than_1000[7]	3	1			T288	1		T100	1		T289	1
index[0x2]	lens_less_than_1000[8]	7	1			T96	7		-	-		-	-
index[0x3]	lens_less_than_1000[0]	57	1			T13	1		T73	2		T27	2
index[0x3]	lens_less_than_1000[1]	30	1			T38	1		T195	1		T89	1
index[0x3]	lens_less_than_1000[2]	15	1			T40	1		T78	1		T113	1
index[0x3]	lens_less_than_1000[3]	16	1			T45	2		T92	1		T110	2
index[0x3]	lens_less_than_1000[4]	21	1			T290	1		T68	1		T45	1
index[0x3]	lens_less_than_1000[5]	6	1			T88	1		T276	1		T112	1
index[0x3]	lens_less_than_1000[6]	4	1			T34	1		T101	1		T263	1
index[0x3]	lens_less_than_1000[7]	5	1			T17	1		T110	1		T269	1
index[0x3]	lens_less_than_1000[8]	7	1			T243	1		T271	1		T100	3
index[0x3]	lens_less_than_1000[9]	1	1			T271	1		-	-		-	-