Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	50	1			T20	3		T14	2		T78	1
class_index[0x1]	57	1			T3	2		T20	3		T71	1
class_index[0x2]	65	1			T15	3		T71	2		T45	3
class_index[0x3]	59	1			T3	1		T45	1		T47	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	78	1			T14	2		T78	1		T71	1
intr_timeout_cnt[1]	56	1			T3	3		T20	3		T15	3
intr_timeout_cnt[2]	25	1			T20	3		T45	1		T48	1
intr_timeout_cnt[3]	22	1			T71	1		T28	1		T91	1
intr_timeout_cnt[4]	11	1			T71	1		T47	1		T87	1
intr_timeout_cnt[5]	11	1			T45	2		T87	1		T91	1
intr_timeout_cnt[6]	8	1			T89	1		T103	2		T248	1
intr_timeout_cnt[7]	7	1			T49	1		T249	1		T250	1
intr_timeout_cnt[8]	4	1			T45	1		T251	1		T252	2
intr_timeout_cnt[9]	9	1			T132	2		T97	2		T54	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	18	1			T14	2		T78	1		T50	1
class_index[0x0]	intr_timeout_cnt[1]	14	1			T80	1		T253	1		T103	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T20	3		T48	1		T92	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T53	1		T95	1		T94	1
class_index[0x0]	intr_timeout_cnt[4]	1	1			T254	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	1	1			T87	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T49	1		T249	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T97	2		T255	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	20	1			T45	1		T50	1		T88	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T3	2		T20	3		T51	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T45	1		T49	1		T50	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T256	1		T257	1		T54	1
class_index[0x1]	intr_timeout_cnt[4]	6	1			T71	1		T47	1		T51	1
class_index[0x1]	intr_timeout_cnt[5]	5	1			T258	1		T259	1		T260	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T89	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T250	1		T259	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	23	1			T71	1		T45	1		T86	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T15	3		T90	3		T261	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T89	1		T97	1		T262	1
class_index[0x2]	intr_timeout_cnt[3]	6	1			T71	1		T28	1		T101	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T92	1		T263	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	4	1			T45	2		T91	1		T264	1
class_index[0x2]	intr_timeout_cnt[6]	5	1			T103	2		T248	1		T265	2
class_index[0x2]	intr_timeout_cnt[7]	2	1			T259	1		T232	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T252	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T266	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	17	1			T48	1		T24	1		T86	1
class_index[0x3]	intr_timeout_cnt[1]	15	1			T3	1		T47	1		T49	2
class_index[0x3]	intr_timeout_cnt[2]	5	1			T50	1		T100	1		T231	1
class_index[0x3]	intr_timeout_cnt[3]	8	1			T91	1		T125	7		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T87	1		T91	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T259	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T257	1		T245	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T260	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	3	1			T45	1		T251	1		T252	1
class_index[0x3]	intr_timeout_cnt[9]	5	1			T132	2		T54	1		T255	1