Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	339979	1			T1	957		T2	1379		T3	1373
all_values[1]	339979	1			T1	957		T2	1379		T3	1373
all_values[2]	339979	1			T1	957		T2	1379		T3	1373
all_values[3]	339979	1			T1	957		T2	1379		T3	1373

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

676719

1

T1

1861

T2

2696

T3

2756

auto[1]

683197

1

T1

1967

T2

2820

T3

2736

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

813129

1

T1

1958

T2

4130

T3

2885

auto[1]

546787

1

T1

1870

T2

1386

T3

2607

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98124	1			T1	234		T2	490		T3	365
all_values[0]	auto[0]	auto[1]	71348	1			T1	233		T2	190		T3	334
all_values[0]	auto[1]	auto[0]	99182	1			T1	245		T2	545		T3	353
all_values[0]	auto[1]	auto[1]	71325	1			T1	245		T2	154		T3	321
all_values[1]	auto[0]	auto[0]	101698	1			T1	238		T2	694		T3	373
all_values[1]	auto[0]	auto[1]	67613	1			T1	231		T2	1		T3	345
all_values[1]	auto[1]	auto[0]	102891	1			T1	246		T2	682		T3	338
all_values[1]	auto[1]	auto[1]	67777	1			T1	242		T2	2		T3	317
all_values[2]	auto[0]	auto[0]	101805	1			T1	261		T2	411		T3	369
all_values[2]	auto[0]	auto[1]	66939	1			T1	234		T2	255		T3	334
all_values[2]	auto[1]	auto[0]	103847	1			T1	242		T2	437		T3	355
all_values[2]	auto[1]	auto[1]	67388	1			T1	220		T2	276		T3	315
all_values[3]	auto[0]	auto[0]	102145	1			T1	218		T2	413		T3	338
all_values[3]	auto[0]	auto[1]	67047	1			T1	212		T2	242		T3	298
all_values[3]	auto[1]	auto[0]	103437	1			T1	274		T2	458		T3	394
all_values[3]	auto[1]	auto[1]	67350	1			T1	253		T2	266		T3	343