Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	339979	1			T1	957		T2	1379		T3	1373
all_pins[1]	339979	1			T1	957		T2	1379		T3	1373
all_pins[2]	339979	1			T1	957		T2	1379		T3	1373
all_pins[3]	339979	1			T1	957		T2	1379		T3	1373

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1086076	1			T1	2868		T2	4818		T3	4196
values[0x1]	273840	1			T1	960		T2	698		T3	1296
transitions[0x0=>0x1]	181580	1			T1	614		T2	588		T3	844
transitions[0x1=>0x0]	181808	1			T1	614		T2	588		T3	844

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	268654	1			T1	712		T2	1225		T3	1052
all_pins[0]	values[0x1]	71325	1			T1	245		T2	154		T3	321
all_pins[0]	transitions[0x0=>0x1]	70730	1			T1	245		T2	154		T3	321
all_pins[0]	transitions[0x1=>0x0]	66983	1			T1	253		T2	266		T3	343
all_pins[1]	values[0x0]	272202	1			T1	715		T2	1377		T3	1056
all_pins[1]	values[0x1]	67777	1			T1	242		T2	2		T3	317
all_pins[1]	transitions[0x0=>0x1]	37123	1			T1	109		T2	2		T3	166
all_pins[1]	transitions[0x1=>0x0]	40671	1			T1	112		T2	154		T3	170
all_pins[2]	values[0x0]	272591	1			T1	737		T2	1103		T3	1058
all_pins[2]	values[0x1]	67388	1			T1	220		T2	276		T3	315
all_pins[2]	transitions[0x0=>0x1]	36937	1			T1	115		T2	276		T3	172
all_pins[2]	transitions[0x1=>0x0]	37326	1			T1	137		T2	2		T3	174
all_pins[3]	values[0x0]	272629	1			T1	704		T2	1113		T3	1030
all_pins[3]	values[0x1]	67350	1			T1	253		T2	266		T3	343
all_pins[3]	transitions[0x0=>0x1]	36790	1			T1	145		T2	156		T3	185
all_pins[3]	transitions[0x1=>0x0]	36828	1			T1	112		T2	166		T3	157