Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	248	1			T173	7		T174	4		T175	7
all_values[1]	248	1			T173	7		T174	4		T175	7
all_values[2]	248	1			T173	7		T174	4		T175	7
all_values[3]	248	1			T173	7		T174	4		T175	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

520

1

T173

19

T174

7

T175

12

auto[1]

472

1

T173

9

T174

9

T175

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

427

1

T173

6

T174

10

T175

9

auto[1]

565

1

T173

22

T174

6

T175

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

605

1

T173

13

T174

13

T175

15

auto[1]

387

1

T173

15

T174

3

T175

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

50

1

T173

1

T174

3

T175

1

all_values[0]

auto[0]

auto[0]

auto[1]

24

1

T173

2

T343

1

T344

1

all_values[0]

auto[0]

auto[1]

auto[0]

48

1

T174

1

T175

2

T345

2

all_values[0]

auto[0]

auto[1]

auto[1]

26

1

T175

1

T346

1

T343

2

all_values[0]

auto[1]

auto[0]

auto[1]

56

1

T173

4

T175

2

T230

1

all_values[0]

auto[1]

auto[1]

auto[1]

44

1

T175

1

T346

1

T344

1

all_values[1]

auto[0]

auto[0]

auto[0]

74

1

T173

2

T174

1

T175

2

all_values[1]

auto[0]

auto[0]

auto[1]

11

1

T175

1

T346

1

T347

1

all_values[1]

auto[0]

auto[1]

auto[0]

52

1

T173

1

T174

1

T175

1

all_values[1]

auto[0]

auto[1]

auto[1]

22

1

T173

1

T174

1

T175

1

all_values[1]

auto[1]

auto[0]

auto[1]

58

1

T173

2

T175

2

T346

1

all_values[1]

auto[1]

auto[1]

auto[1]

31

1

T173

1

T174

1

T346

2

all_values[2]

auto[0]

auto[0]

auto[0]

55

1

T173

1

T174

1

T175

1

all_values[2]

auto[0]

auto[0]

auto[1]

18

1

T173

1

T230

1

T346

1

all_values[2]

auto[0]

auto[1]

auto[0]

42

1

T174

2

T175

2

T345

2

all_values[2]

auto[0]

auto[1]

auto[1]

26

1

T173

1

T346

1

T348

1

all_values[2]

auto[1]

auto[0]

auto[1]

40

1

T173

2

T174

1

T230

1

all_values[2]

auto[1]

auto[1]

auto[1]

67

1

T173

2

T175

4

T230

1

all_values[3]

auto[0]

auto[0]

auto[0]

58

1

T173

1

T174

1

T346

2

all_values[3]

auto[0]

auto[0]

auto[1]

24

1

T173

2

T175

1

T230

1

all_values[3]

auto[0]

auto[1]

auto[0]

48

1

T346

3

T345

4

T347

1

all_values[3]

auto[0]

auto[1]

auto[1]

27

1

T174

2

T175

2

T349

1

all_values[3]

auto[1]

auto[0]

auto[1]

52

1

T173

1

T175

2

T230

2

all_values[3]

auto[1]

auto[1]

auto[1]

39

1

T173

3

T174

1

T175

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal