Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	97283	1			T3	508		T12	406		T17	348
accum_cnt_1000	213759	1			T1	588		T3	1529		T12	508
accum_cnt_100	27768	1			T1	50		T3	162		T12	23
accum_cnt_50	57093	1			T1	40		T3	209		T5	11
accum_cnt_10	174295	1			T1	12		T2	1047		T3	993
accum_cnt_0	388027	1			T1	2094		T2	3133		T3	332

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	251235	1			T1	696		T2	1045		T3	1048
class_index[0x1]	251235	1			T1	696		T2	1045		T3	1048
class_index[0x2]	251235	1			T1	696		T2	1045		T3	1048
class_index[0x3]	251235	1			T1	696		T2	1045		T3	1048

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	28173	1			T12	406		T17	275		T15	587
class_index[0x0]	accum_cnt_1000	56102	1			T3	1		T12	508		T17	689
class_index[0x0]	accum_cnt_100	7240	1			T3	32		T12	23		T17	33
class_index[0x0]	accum_cnt_50	14293	1			T3	29		T5	11		T12	25
class_index[0x0]	accum_cnt_10	46197	1			T3	930		T5	10		T12	10
class_index[0x0]	accum_cnt_0	80308	1			T1	696		T2	1045		T3	56
class_index[0x1]	accum_cnt_2000	24248	1			T3	198		T17	73		T14	269
class_index[0x1]	accum_cnt_1000	58283	1			T3	206		T17	877		T19	45
class_index[0x1]	accum_cnt_100	8523	1			T3	16		T17	43		T19	18
class_index[0x1]	accum_cnt_50	13602	1			T3	80		T17	24		T19	12
class_index[0x1]	accum_cnt_10	40568	1			T2	1041		T3	39		T5	25
class_index[0x1]	accum_cnt_0	99743	1			T1	696		T2	4		T3	50
class_index[0x2]	accum_cnt_2000	20572	1			T3	129		T22	261		T68	559
class_index[0x2]	accum_cnt_1000	47254	1			T1	588		T3	689		T14	508
class_index[0x2]	accum_cnt_100	5999	1			T1	50		T3	40		T14	21
class_index[0x2]	accum_cnt_50	12715	1			T1	40		T3	50		T19	70
class_index[0x2]	accum_cnt_10	43509	1			T1	9		T2	3		T3	7
class_index[0x2]	accum_cnt_0	111652	1			T1	9		T2	1042		T3	133
class_index[0x3]	accum_cnt_2000	24290	1			T3	181		T15	224		T40	552
class_index[0x3]	accum_cnt_1000	52120	1			T3	633		T13	529		T14	638
class_index[0x3]	accum_cnt_100	6006	1			T3	74		T13	33		T14	43
class_index[0x3]	accum_cnt_50	16483	1			T3	50		T17	10		T13	25
class_index[0x3]	accum_cnt_10	44021	1			T1	3		T2	3		T3	17
class_index[0x3]	accum_cnt_0	96324	1			T1	693		T2	1042		T3	93