Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	8105	1			T14	5		T60	136		T7	1
alert[0x1]	11056	1			T14	10		T60	50		T8	1
alert[0x2]	5961	1			T15	118		T47	102		T296	1
alert[0x3]	7207	1			T14	15		T15	19		T60	976
alert[0x4]	6613	1			T15	123		T113	188		T128	3
alert[0x5]	4492	1			T5	3		T7	1		T8	1
alert[0x6]	10920	1			T60	1		T7	1		T74	1
alert[0x7]	6573	1			T60	42		T73	1		T113	348
alert[0x8]	7975	1			T14	10		T15	23		T7	2
alert[0x9]	5930	1			T15	186		T7	1		T113	43
alert[0xa]	2733	1			T5	1		T14	31		T60	30
alert[0xb]	10596	1			T14	4		T15	589		T8	1
alert[0xc]	4541	1			T13	3		T14	114		T15	98
alert[0xd]	4852	1			T14	19		T7	1		T79	11
alert[0xe]	4288	1			T15	21		T60	59		T113	11
alert[0xf]	6708	1			T14	33		T15	56		T45	18
alert[0x10]	6880	1			T60	654		T79	1		T113	325
alert[0x11]	1791	1			T5	1		T14	74		T15	103
alert[0x12]	7760	1			T5	1		T14	119		T15	141
alert[0x13]	4343	1			T3	2		T5	1		T15	214
alert[0x14]	11282	1			T6	1		T14	8		T15	216
alert[0x15]	5180	1			T5	1		T14	37		T15	104
alert[0x16]	7991	1			T14	417		T73	1		T74	2
alert[0x17]	4364	1			T5	1		T12	5		T15	32
alert[0x18]	6200	1			T14	1		T113	633		T45	29
alert[0x19]	5315	1			T60	845		T113	61		T128	6
alert[0x1a]	5843	1			T5	1		T15	769		T8	1
alert[0x1b]	12066	1			T12	2		T60	286		T74	1
alert[0x1c]	6448	1			T117	31		T28	8		T195	61
alert[0x1d]	6391	1			T60	62		T113	6		T45	2619
alert[0x1e]	7768	1			T14	14		T60	25		T47	400
alert[0x1f]	13524	1			T14	32		T113	1060		T45	5658
alert[0x20]	8305	1			T14	65		T60	7		T113	26
alert[0x21]	7064	1			T14	44		T15	677		T60	57
alert[0x22]	4708	1			T14	7		T60	34		T7	1
alert[0x23]	4424	1			T14	124		T113	17		T45	19
alert[0x24]	7286	1			T5	1		T14	3		T8	1
alert[0x25]	9018	1			T15	523		T8	1		T47	204
alert[0x26]	2786	1			T14	755		T15	220		T8	1
alert[0x27]	8113	1			T12	26		T14	295		T113	129
alert[0x28]	5065	1			T5	1		T13	4		T14	248
alert[0x29]	4666	1			T12	2		T14	183		T15	10
alert[0x2a]	5346	1			T14	54		T73	1		T83	1
alert[0x2b]	4200	1			T14	218		T15	34		T113	120
alert[0x2c]	4735	1			T14	126		T15	31		T60	464
alert[0x2d]	3432	1			T113	196		T28	33		T49	3
alert[0x2e]	6267	1			T5	1		T113	471		T45	2
alert[0x2f]	2423	1			T14	107		T15	120		T47	18
alert[0x30]	3198	1			T6	1		T15	157		T60	121
alert[0x31]	7949	1			T14	21		T15	458		T84	1
alert[0x32]	6975	1			T60	399		T8	1		T47	232
alert[0x33]	16165	1			T14	714		T15	418		T7	1
alert[0x34]	2193	1			T14	8		T84	1		T79	4
alert[0x35]	6219	1			T15	24		T113	297		T128	2
alert[0x36]	5820	1			T14	19		T84	1		T113	449
alert[0x37]	5886	1			T15	37		T7	1		T71	2
alert[0x38]	11273	1			T15	5300		T8	1		T113	103
alert[0x39]	8931	1			T13	1		T14	23		T15	121
alert[0x3a]	5830	1			T15	20		T22	1		T113	30
alert[0x3b]	10876	1			T15	164		T7	1		T113	166
alert[0x3c]	6332	1			T15	461		T113	1727		T45	47
alert[0x3d]	2783	1			T14	18		T15	41		T45	8
alert[0x3e]	2464	1			T5	1		T14	6		T7	1
alert[0x3f]	3110	1			T14	15		T15	38		T7	1
alert[0x40]	5591	1			T5	1		T60	17		T8	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	124537	1			T3	2		T5	14		T14	307
class_i[0x1]	85720	1			T12	6		T13	4		T14	3687
class_i[0x2]	110265	1			T12	14		T13	4		T6	2
class_i[0x3]	100607	1			T5	1		T12	15		T15	11

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

420488

1

T3

2

T12

35

T13

8

alert_ping_fail

641

1

T5

15

T6

2

T7

16

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	8096	1			T14	5		T60	136		T45	149
alert_integrity_fail	alert[0x1]	11049	1			T14	10		T60	50		T45	219
alert_integrity_fail	alert[0x2]	5953	1			T15	118		T47	102		T24	27
alert_integrity_fail	alert[0x3]	7202	1			T14	15		T15	19		T60	976
alert_integrity_fail	alert[0x4]	6605	1			T15	123		T113	188		T128	3
alert_integrity_fail	alert[0x5]	4472	1			T195	73		T49	42		T89	6
alert_integrity_fail	alert[0x6]	10902	1			T60	1		T79	10		T48	2
alert_integrity_fail	alert[0x7]	6559	1			T60	42		T113	348		T45	2
alert_integrity_fail	alert[0x8]	7959	1			T14	10		T15	23		T113	181
alert_integrity_fail	alert[0x9]	5926	1			T15	186		T113	43		T45	7
alert_integrity_fail	alert[0xa]	2720	1			T14	31		T60	30		T113	81
alert_integrity_fail	alert[0xb]	10588	1			T14	4		T15	589		T113	42
alert_integrity_fail	alert[0xc]	4534	1			T13	3		T14	114		T15	98
alert_integrity_fail	alert[0xd]	4846	1			T14	19		T79	11		T113	302
alert_integrity_fail	alert[0xe]	4279	1			T15	21		T60	59		T113	11
alert_integrity_fail	alert[0xf]	6699	1			T14	33		T15	56		T45	18
alert_integrity_fail	alert[0x10]	6874	1			T60	654		T79	1		T113	325
alert_integrity_fail	alert[0x11]	1786	1			T14	74		T15	103		T60	18
alert_integrity_fail	alert[0x12]	7753	1			T14	119		T15	141		T79	1
alert_integrity_fail	alert[0x13]	4332	1			T3	2		T15	214		T60	214
alert_integrity_fail	alert[0x14]	11268	1			T14	8		T15	216		T113	7148
alert_integrity_fail	alert[0x15]	5165	1			T14	37		T15	104		T60	78
alert_integrity_fail	alert[0x16]	7974	1			T14	417		T113	301		T45	2
alert_integrity_fail	alert[0x17]	4358	1			T12	5		T15	32		T113	565
alert_integrity_fail	alert[0x18]	6192	1			T14	1		T113	633		T45	29
alert_integrity_fail	alert[0x19]	5310	1			T60	845		T113	61		T128	6
alert_integrity_fail	alert[0x1a]	5834	1			T15	769		T45	94		T117	114
alert_integrity_fail	alert[0x1b]	12054	1			T12	2		T60	286		T113	244
alert_integrity_fail	alert[0x1c]	6433	1			T117	31		T28	8		T195	61
alert_integrity_fail	alert[0x1d]	6381	1			T60	62		T113	6		T45	2619
alert_integrity_fail	alert[0x1e]	7762	1			T14	14		T60	25		T47	400
alert_integrity_fail	alert[0x1f]	13508	1			T14	32		T113	1060		T45	5658
alert_integrity_fail	alert[0x20]	8298	1			T14	65		T60	7		T113	26
alert_integrity_fail	alert[0x21]	7054	1			T14	44		T15	677		T60	57
alert_integrity_fail	alert[0x22]	4697	1			T14	7		T60	34		T113	390
alert_integrity_fail	alert[0x23]	4410	1			T14	124		T113	17		T45	19
alert_integrity_fail	alert[0x24]	7278	1			T14	3		T71	1		T45	17
alert_integrity_fail	alert[0x25]	9007	1			T15	523		T47	204		T195	1
alert_integrity_fail	alert[0x26]	2778	1			T14	755		T15	220		T45	14
alert_integrity_fail	alert[0x27]	8107	1			T12	26		T14	295		T113	129
alert_integrity_fail	alert[0x28]	5053	1			T13	4		T14	248		T15	22
alert_integrity_fail	alert[0x29]	4657	1			T12	2		T14	183		T15	10
alert_integrity_fail	alert[0x2a]	5330	1			T14	54		T45	44		T47	306
alert_integrity_fail	alert[0x2b]	4193	1			T14	218		T15	34		T113	120
alert_integrity_fail	alert[0x2c]	4719	1			T14	126		T15	31		T60	464
alert_integrity_fail	alert[0x2d]	3429	1			T113	196		T28	33		T49	3
alert_integrity_fail	alert[0x2e]	6258	1			T113	471		T45	2		T128	4
alert_integrity_fail	alert[0x2f]	2415	1			T14	107		T15	120		T47	18
alert_integrity_fail	alert[0x30]	3188	1			T15	157		T60	121		T113	121
alert_integrity_fail	alert[0x31]	7942	1			T14	21		T15	458		T71	2
alert_integrity_fail	alert[0x32]	6965	1			T60	399		T47	232		T117	16
alert_integrity_fail	alert[0x33]	16154	1			T14	714		T15	418		T117	1648
alert_integrity_fail	alert[0x34]	2180	1			T14	8		T79	4		T45	6
alert_integrity_fail	alert[0x35]	6201	1			T15	24		T113	297		T128	2
alert_integrity_fail	alert[0x36]	5813	1			T14	19		T113	449		T45	441
alert_integrity_fail	alert[0x37]	5878	1			T15	37		T71	2		T113	82
alert_integrity_fail	alert[0x38]	11265	1			T15	5300		T113	103		T128	19
alert_integrity_fail	alert[0x39]	8920	1			T13	1		T14	23		T15	121
alert_integrity_fail	alert[0x3a]	5826	1			T15	20		T22	1		T113	30
alert_integrity_fail	alert[0x3b]	10864	1			T15	164		T113	166		T128	4
alert_integrity_fail	alert[0x3c]	6321	1			T15	461		T113	1727		T45	47
alert_integrity_fail	alert[0x3d]	2774	1			T14	18		T15	41		T45	8
alert_integrity_fail	alert[0x3e]	2455	1			T14	6		T45	127		T195	138
alert_integrity_fail	alert[0x3f]	3103	1			T14	15		T15	38		T113	75
alert_integrity_fail	alert[0x40]	5583	1			T60	17		T47	236		T48	1
alert_ping_fail	alert[0x0]	9	1			T7	1		T296	1		T297	2
alert_ping_fail	alert[0x1]	7	1			T8	1		T225	1		T298	1
alert_ping_fail	alert[0x2]	8	1			T296	1		T29	1		T297	1
alert_ping_fail	alert[0x3]	5	1			T7	1		T298	1		T299	1
alert_ping_fail	alert[0x4]	8	1			T296	1		T300	1		T297	1
alert_ping_fail	alert[0x5]	20	1			T5	3		T7	1		T8	1
alert_ping_fail	alert[0x6]	18	1			T7	1		T74	1		T84	1
alert_ping_fail	alert[0x7]	14	1			T73	1		T292	1		T301	1
alert_ping_fail	alert[0x8]	16	1			T7	2		T302	1		T297	1
alert_ping_fail	alert[0x9]	4	1			T7	1		T303	1		T304	1
alert_ping_fail	alert[0xa]	13	1			T5	1		T7	1		T29	1
alert_ping_fail	alert[0xb]	8	1			T8	1		T301	1		T29	1
alert_ping_fail	alert[0xc]	7	1			T29	1		T305	1		T240	1
alert_ping_fail	alert[0xd]	6	1			T7	1		T306	1		T281	1
alert_ping_fail	alert[0xe]	9	1			T307	1		T308	1		T240	1
alert_ping_fail	alert[0xf]	9	1			T296	1		T29	1		T225	1
alert_ping_fail	alert[0x10]	6	1			T297	1		T240	1		T306	2
alert_ping_fail	alert[0x11]	5	1			T5	1		T300	1		T240	1
alert_ping_fail	alert[0x12]	7	1			T5	1		T281	1		T309	1
alert_ping_fail	alert[0x13]	11	1			T5	1		T8	1		T120	1
alert_ping_fail	alert[0x14]	14	1			T6	1		T8	1		T73	1
alert_ping_fail	alert[0x15]	15	1			T5	1		T301	1		T310	1
alert_ping_fail	alert[0x16]	17	1			T73	1		T74	2		T311	1
alert_ping_fail	alert[0x17]	6	1			T5	1		T312	1		T313	1
alert_ping_fail	alert[0x18]	8	1			T301	1		T29	1		T297	1
alert_ping_fail	alert[0x19]	5	1			T29	1		T225	1		T240	1
alert_ping_fail	alert[0x1a]	9	1			T5	1		T8	1		T29	1
alert_ping_fail	alert[0x1b]	12	1			T74	1		T29	1		T307	1
alert_ping_fail	alert[0x1c]	15	1			T314	1		T307	2		T300	1
alert_ping_fail	alert[0x1d]	10	1			T300	1		T308	1		T240	1
alert_ping_fail	alert[0x1e]	6	1			T300	1		T298	1		T308	1
alert_ping_fail	alert[0x1f]	16	1			T278	1		T240	1		T315	2
alert_ping_fail	alert[0x20]	7	1			T301	1		T316	1		T317	1
alert_ping_fail	alert[0x21]	10	1			T7	1		T296	1		T316	1
alert_ping_fail	alert[0x22]	11	1			T7	1		T29	1		T310	1
alert_ping_fail	alert[0x23]	14	1			T296	1		T29	1		T307	1
alert_ping_fail	alert[0x24]	8	1			T5	1		T8	1		T307	1
alert_ping_fail	alert[0x25]	11	1			T8	1		T301	1		T307	1
alert_ping_fail	alert[0x26]	8	1			T8	1		T301	1		T318	1
alert_ping_fail	alert[0x27]	6	1			T29	1		T297	1		T308	1
alert_ping_fail	alert[0x28]	12	1			T5	1		T296	2		T29	1
alert_ping_fail	alert[0x29]	9	1			T298	1		T308	1		T306	1
alert_ping_fail	alert[0x2a]	16	1			T73	1		T83	1		T296	1
alert_ping_fail	alert[0x2b]	7	1			T316	1		T318	1		T319	1
alert_ping_fail	alert[0x2c]	16	1			T301	1		T278	2		T300	1
alert_ping_fail	alert[0x2d]	3	1			T320	1		T321	1		T322	1
alert_ping_fail	alert[0x2e]	9	1			T5	1		T294	1		T301	1
alert_ping_fail	alert[0x2f]	8	1			T316	1		T240	1		T323	1
alert_ping_fail	alert[0x30]	10	1			T6	1		T301	1		T307	1
alert_ping_fail	alert[0x31]	7	1			T84	1		T29	1		T321	1
alert_ping_fail	alert[0x32]	10	1			T8	1		T296	1		T316	1
alert_ping_fail	alert[0x33]	11	1			T7	1		T301	1		T225	1
alert_ping_fail	alert[0x34]	13	1			T84	1		T296	1		T225	1
alert_ping_fail	alert[0x35]	18	1			T296	2		T301	1		T225	1
alert_ping_fail	alert[0x36]	7	1			T84	1		T225	1		T305	1
alert_ping_fail	alert[0x37]	8	1			T7	1		T318	1		T240	1
alert_ping_fail	alert[0x38]	8	1			T8	1		T308	1		T319	1
alert_ping_fail	alert[0x39]	11	1			T73	1		T296	1		T307	1
alert_ping_fail	alert[0x3a]	4	1			T301	1		T313	1		T324	1
alert_ping_fail	alert[0x3b]	12	1			T7	1		T296	1		T319	1
alert_ping_fail	alert[0x3c]	11	1			T298	1		T318	1		T240	1
alert_ping_fail	alert[0x3d]	9	1			T298	1		T305	1		T297	1
alert_ping_fail	alert[0x3e]	9	1			T5	1		T7	1		T29	1
alert_ping_fail	alert[0x3f]	7	1			T7	1		T298	1		T320	1
alert_ping_fail	alert[0x40]	8	1			T5	1		T8	1		T73	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	124336	1			T3	2		T14	307		T15	9
alert_integrity_fail	class_i[0x1]	85586	1			T12	6		T13	4		T14	3687
alert_integrity_fail	class_i[0x2]	110094	1			T12	14		T13	4		T14	2
alert_integrity_fail	class_i[0x3]	100472	1			T12	15		T15	11		T60	6057
alert_ping_fail	class_i[0x0]	201	1			T5	14		T7	13		T83	1
alert_ping_fail	class_i[0x1]	134	1			T7	1		T73	6		T225	3
alert_ping_fail	class_i[0x2]	171	1			T6	2		T7	2		T74	4
alert_ping_fail	class_i[0x3]	135	1			T5	1		T8	12		T84	1