Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.67 100.00 100.00 100.00 99.38 99.52


Total test records in report: 822
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T158 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2972377198 Jun 29 05:22:48 PM PDT 24 Jun 29 05:32:43 PM PDT 24 17867071737 ps
T772 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.799764525 Jun 29 05:22:45 PM PDT 24 Jun 29 05:22:52 PM PDT 24 49743547 ps
T773 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3319665767 Jun 29 05:22:24 PM PDT 24 Jun 29 05:22:27 PM PDT 24 15552714 ps
T267 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1023079579 Jun 29 05:22:36 PM PDT 24 Jun 29 05:22:39 PM PDT 24 49609045 ps
T161 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4098258759 Jun 29 05:22:24 PM PDT 24 Jun 29 05:30:52 PM PDT 24 25679500474 ps
T774 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3307438789 Jun 29 05:22:18 PM PDT 24 Jun 29 05:24:44 PM PDT 24 4756172663 ps
T775 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2353863229 Jun 29 05:22:52 PM PDT 24 Jun 29 05:22:54 PM PDT 24 9949989 ps
T776 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1662453001 Jun 29 05:22:53 PM PDT 24 Jun 29 05:22:56 PM PDT 24 10909131 ps
T777 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.935426840 Jun 29 05:22:25 PM PDT 24 Jun 29 05:25:05 PM PDT 24 4659197223 ps
T778 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3964767761 Jun 29 05:22:43 PM PDT 24 Jun 29 05:22:46 PM PDT 24 13676195 ps
T154 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3057994070 Jun 29 05:22:25 PM PDT 24 Jun 29 05:25:26 PM PDT 24 9791316507 ps
T779 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.324378242 Jun 29 05:22:39 PM PDT 24 Jun 29 05:22:49 PM PDT 24 246439946 ps
T160 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3364863560 Jun 29 05:22:28 PM PDT 24 Jun 29 05:29:51 PM PDT 24 6033367327 ps
T780 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4284627285 Jun 29 05:22:16 PM PDT 24 Jun 29 05:22:18 PM PDT 24 10114275 ps
T166 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1432799055 Jun 29 05:22:41 PM PDT 24 Jun 29 05:27:36 PM PDT 24 15333544666 ps
T781 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3169127388 Jun 29 05:22:36 PM PDT 24 Jun 29 05:22:49 PM PDT 24 158622502 ps
T782 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.282083801 Jun 29 05:22:42 PM PDT 24 Jun 29 05:22:53 PM PDT 24 783711003 ps
T783 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2186801966 Jun 29 05:22:26 PM PDT 24 Jun 29 05:22:29 PM PDT 24 8877529 ps
T784 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1720903446 Jun 29 05:22:17 PM PDT 24 Jun 29 05:22:43 PM PDT 24 357812738 ps
T785 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1352190457 Jun 29 05:22:31 PM PDT 24 Jun 29 05:23:12 PM PDT 24 1039868995 ps
T786 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2519289657 Jun 29 05:22:45 PM PDT 24 Jun 29 05:22:48 PM PDT 24 27562652 ps
T165 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1625248810 Jun 29 05:22:46 PM PDT 24 Jun 29 05:32:48 PM PDT 24 26734484293 ps
T787 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3679112611 Jun 29 05:22:28 PM PDT 24 Jun 29 05:24:27 PM PDT 24 7712099116 ps
T788 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1028887067 Jun 29 05:22:42 PM PDT 24 Jun 29 05:22:44 PM PDT 24 9898588 ps
T789 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3474483869 Jun 29 05:22:23 PM PDT 24 Jun 29 05:22:26 PM PDT 24 127852138 ps
T790 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3284004634 Jun 29 05:22:26 PM PDT 24 Jun 29 05:22:28 PM PDT 24 16257691 ps
T791 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3427070601 Jun 29 05:22:25 PM PDT 24 Jun 29 05:22:39 PM PDT 24 577540488 ps
T162 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2342643921 Jun 29 05:22:42 PM PDT 24 Jun 29 05:27:46 PM PDT 24 15813623716 ps
T792 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.4011190522 Jun 29 05:22:36 PM PDT 24 Jun 29 05:22:46 PM PDT 24 1019164980 ps
T793 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2252991428 Jun 29 05:22:28 PM PDT 24 Jun 29 05:22:30 PM PDT 24 25997338 ps
T794 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.4261204611 Jun 29 05:22:28 PM PDT 24 Jun 29 05:22:47 PM PDT 24 266128146 ps
T795 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1795482618 Jun 29 05:22:49 PM PDT 24 Jun 29 05:23:05 PM PDT 24 163454030 ps
T796 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2065234127 Jun 29 05:22:45 PM PDT 24 Jun 29 05:23:07 PM PDT 24 2162997974 ps
T797 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3648916339 Jun 29 05:22:49 PM PDT 24 Jun 29 05:23:03 PM PDT 24 187589296 ps
T163 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2135469335 Jun 29 05:22:40 PM PDT 24 Jun 29 05:45:18 PM PDT 24 18863243447 ps
T268 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1455463848 Jun 29 05:22:24 PM PDT 24 Jun 29 05:23:02 PM PDT 24 570511218 ps
T798 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1602987682 Jun 29 05:22:39 PM PDT 24 Jun 29 05:22:50 PM PDT 24 90437248 ps
T177 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4228451394 Jun 29 05:22:49 PM PDT 24 Jun 29 05:24:13 PM PDT 24 4999226288 ps
T799 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3245354999 Jun 29 05:22:45 PM PDT 24 Jun 29 05:22:55 PM PDT 24 127047799 ps
T168 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2677450522 Jun 29 05:22:49 PM PDT 24 Jun 29 05:24:44 PM PDT 24 803307212 ps
T800 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1457344332 Jun 29 05:22:21 PM PDT 24 Jun 29 05:24:14 PM PDT 24 3213386629 ps
T183 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3085108735 Jun 29 05:22:40 PM PDT 24 Jun 29 05:22:46 PM PDT 24 89091805 ps
T169 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2100633501 Jun 29 05:22:22 PM PDT 24 Jun 29 05:32:10 PM PDT 24 100574769479 ps
T801 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2433472513 Jun 29 05:22:40 PM PDT 24 Jun 29 05:22:50 PM PDT 24 63173004 ps
T802 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3466069314 Jun 29 05:22:49 PM PDT 24 Jun 29 05:22:56 PM PDT 24 519184708 ps
T178 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1560030456 Jun 29 05:22:37 PM PDT 24 Jun 29 05:23:14 PM PDT 24 477200428 ps
T803 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1603673799 Jun 29 05:22:29 PM PDT 24 Jun 29 05:22:53 PM PDT 24 369920825 ps
T164 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1924641003 Jun 29 05:22:39 PM PDT 24 Jun 29 05:33:03 PM PDT 24 18066804920 ps
T804 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2504697659 Jun 29 05:22:29 PM PDT 24 Jun 29 05:22:31 PM PDT 24 6378059 ps
T805 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2822763594 Jun 29 05:22:45 PM PDT 24 Jun 29 05:23:05 PM PDT 24 1000480076 ps
T351 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.160832680 Jun 29 05:22:32 PM PDT 24 Jun 29 05:30:01 PM PDT 24 36122316422 ps
T806 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2200652648 Jun 29 05:22:45 PM PDT 24 Jun 29 05:22:59 PM PDT 24 419868029 ps
T807 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2565444196 Jun 29 05:22:45 PM PDT 24 Jun 29 05:22:54 PM PDT 24 1320726656 ps
T808 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2652425846 Jun 29 05:22:24 PM PDT 24 Jun 29 05:22:36 PM PDT 24 241738301 ps
T809 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3936425736 Jun 29 05:22:46 PM PDT 24 Jun 29 05:22:53 PM PDT 24 336917197 ps
T810 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.270729081 Jun 29 05:22:39 PM PDT 24 Jun 29 05:22:51 PM PDT 24 154219383 ps
T811 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3881948173 Jun 29 05:22:15 PM PDT 24 Jun 29 05:30:57 PM PDT 24 34126710199 ps
T812 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3954026505 Jun 29 05:22:45 PM PDT 24 Jun 29 05:22:54 PM PDT 24 367937945 ps
T813 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1636256043 Jun 29 05:22:24 PM PDT 24 Jun 29 05:22:29 PM PDT 24 28647298 ps
T167 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3880369946 Jun 29 05:22:39 PM PDT 24 Jun 29 05:25:34 PM PDT 24 3033715294 ps
T186 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2667494065 Jun 29 05:22:29 PM PDT 24 Jun 29 05:23:16 PM PDT 24 2476223674 ps
T814 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4043488104 Jun 29 05:22:29 PM PDT 24 Jun 29 05:22:52 PM PDT 24 1189553319 ps
T193 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3467377997 Jun 29 05:22:26 PM PDT 24 Jun 29 05:22:49 PM PDT 24 320882700 ps
T815 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1120819630 Jun 29 05:22:54 PM PDT 24 Jun 29 05:22:56 PM PDT 24 7334532 ps
T816 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.895575304 Jun 29 05:22:50 PM PDT 24 Jun 29 05:23:00 PM PDT 24 227054771 ps
T817 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3319350559 Jun 29 05:22:43 PM PDT 24 Jun 29 05:23:05 PM PDT 24 1072781979 ps
T818 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.735083812 Jun 29 05:22:22 PM PDT 24 Jun 29 05:25:45 PM PDT 24 15018412830 ps
T819 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2965214386 Jun 29 05:22:17 PM PDT 24 Jun 29 05:23:17 PM PDT 24 523325506 ps
T820 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2199142959 Jun 29 05:22:37 PM PDT 24 Jun 29 05:26:28 PM PDT 24 5951749335 ps
T821 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1984891235 Jun 29 05:22:38 PM PDT 24 Jun 29 05:22:48 PM PDT 24 1460112201 ps
T822 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3796379875 Jun 29 05:22:22 PM PDT 24 Jun 29 05:23:59 PM PDT 24 1637937949 ps
T182 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3409700569 Jun 29 05:22:46 PM PDT 24 Jun 29 05:23:59 PM PDT 24 1053975727 ps

Test location /workspace/coverage/default/19.alert_handler_stress_all.3060994532
Short name T3
Test name
Test status
Simulation time 168892368709 ps
CPU time 2503.93 seconds
Started Jun 29 05:54:18 PM PDT 24
Finished Jun 29 06:36:03 PM PDT 24
Peak memory 282236 kb
Host smart-b404d48b-1626-4ddf-b6b0-f83e60d4b4a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060994532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3060994532
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.760410999
Short name T14
Test name
Test status
Simulation time 822987094752 ps
CPU time 8123.06 seconds
Started Jun 29 05:59:24 PM PDT 24
Finished Jun 29 08:14:48 PM PDT 24
Peak memory 322312 kb
Host smart-5226f7d6-100c-4e8d-9e5d-af53e44deb19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760410999 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.760410999
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3923153800
Short name T9
Test name
Test status
Simulation time 671703828 ps
CPU time 14.72 seconds
Started Jun 29 05:51:47 PM PDT 24
Finished Jun 29 05:52:02 PM PDT 24
Peak memory 271548 kb
Host smart-8597f47d-90b5-40ee-a95e-e16f2ee45222
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3923153800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3923153800
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1953281150
Short name T171
Test name
Test status
Simulation time 7431479117 ps
CPU time 43.51 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:23:13 PM PDT 24
Peak memory 237772 kb
Host smart-7f5947c6-6a74-4643-8f57-a9f32b0b57b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1953281150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1953281150
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3873300720
Short name T15
Test name
Test status
Simulation time 84024458131 ps
CPU time 2569.64 seconds
Started Jun 29 05:58:03 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 290344 kb
Host smart-cd64b9ed-f0bd-4dfc-bc80-8e38225033cd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873300720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3873300720
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.706585659
Short name T104
Test name
Test status
Simulation time 62177058460 ps
CPU time 1092.03 seconds
Started Jun 29 05:55:33 PM PDT 24
Finished Jun 29 06:13:46 PM PDT 24
Peak memory 284832 kb
Host smart-30e7fc4e-ae2a-4025-99d1-a97bcbbc82b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706585659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.706585659
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1943391979
Short name T47
Test name
Test status
Simulation time 53406948990 ps
CPU time 1622.55 seconds
Started Jun 29 05:52:32 PM PDT 24
Finished Jun 29 06:19:36 PM PDT 24
Peak memory 289824 kb
Host smart-a277f6d3-8807-48f1-abc3-42c5c56db8f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943391979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1943391979
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.7177971
Short name T75
Test name
Test status
Simulation time 30148065945 ps
CPU time 1549.85 seconds
Started Jun 29 05:58:33 PM PDT 24
Finished Jun 29 06:24:24 PM PDT 24
Peak memory 273940 kb
Host smart-d9882710-208d-42c5-bcd6-a0f996803ab4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7177971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.7177971
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.705096226
Short name T147
Test name
Test status
Simulation time 5502335546 ps
CPU time 357.52 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:28:48 PM PDT 24
Peak memory 265476 kb
Host smart-6e4170ee-1d71-42b6-903e-04b2026bb1bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=705096226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.705096226
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1939050902
Short name T94
Test name
Test status
Simulation time 21228147161 ps
CPU time 363.07 seconds
Started Jun 29 05:58:19 PM PDT 24
Finished Jun 29 06:04:22 PM PDT 24
Peak memory 273156 kb
Host smart-353a25e2-284d-4fc6-a4f7-f428597e9228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939050902 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1939050902
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.4278560519
Short name T96
Test name
Test status
Simulation time 226819687395 ps
CPU time 3448.71 seconds
Started Jun 29 05:53:53 PM PDT 24
Finished Jun 29 06:51:23 PM PDT 24
Peak memory 289312 kb
Host smart-ff699d05-233e-4ab7-b40e-9d97bb6778ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278560519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.4278560519
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3815464355
Short name T197
Test name
Test status
Simulation time 77320726081 ps
CPU time 7863.04 seconds
Started Jun 29 05:51:56 PM PDT 24
Finished Jun 29 08:03:00 PM PDT 24
Peak memory 371524 kb
Host smart-0e80b182-d974-40a7-8c73-be78025ce995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815464355 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3815464355
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2696096090
Short name T138
Test name
Test status
Simulation time 7726283850 ps
CPU time 307.56 seconds
Started Jun 29 05:22:25 PM PDT 24
Finished Jun 29 05:27:34 PM PDT 24
Peak memory 265512 kb
Host smart-143418af-aab1-4c21-a6b0-94242b48fc36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2696096090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2696096090
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2120528232
Short name T67
Test name
Test status
Simulation time 1597350319 ps
CPU time 68.06 seconds
Started Jun 29 05:53:29 PM PDT 24
Finished Jun 29 05:54:38 PM PDT 24
Peak memory 249232 kb
Host smart-68a8f14f-4ba2-4780-8a6a-cd2a4358f9ad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2120528232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2120528232
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1831952397
Short name T151
Test name
Test status
Simulation time 17716884774 ps
CPU time 655.94 seconds
Started Jun 29 05:22:39 PM PDT 24
Finished Jun 29 05:33:36 PM PDT 24
Peak memory 265512 kb
Host smart-4e7bb7e7-943f-4e1f-b4bc-c92c2705d873
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831952397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1831952397
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.763137791
Short name T336
Test name
Test status
Simulation time 505082340570 ps
CPU time 2145.36 seconds
Started Jun 29 05:57:17 PM PDT 24
Finished Jun 29 06:33:03 PM PDT 24
Peak memory 273852 kb
Host smart-a8db81bd-f33f-4185-b2bc-ea3c9cfb4cb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763137791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.763137791
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2972377198
Short name T158
Test name
Test status
Simulation time 17867071737 ps
CPU time 593.66 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:32:43 PM PDT 24
Peak memory 265520 kb
Host smart-cd21ea4c-b219-4e57-90a5-070cf6aa622c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972377198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2972377198
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.4245510286
Short name T7
Test name
Test status
Simulation time 12455545828 ps
CPU time 513.64 seconds
Started Jun 29 05:57:32 PM PDT 24
Finished Jun 29 06:06:06 PM PDT 24
Peak memory 248264 kb
Host smart-467401e9-0bd6-4daf-86ed-970b29498303
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245510286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.4245510286
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3777886377
Short name T173
Test name
Test status
Simulation time 10109473 ps
CPU time 1.34 seconds
Started Jun 29 05:22:51 PM PDT 24
Finished Jun 29 05:22:53 PM PDT 24
Peak memory 237608 kb
Host smart-c3052180-8dc9-46f6-b501-b0655fe470c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3777886377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3777886377
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1557568140
Short name T141
Test name
Test status
Simulation time 8977315062 ps
CPU time 602.77 seconds
Started Jun 29 05:22:44 PM PDT 24
Finished Jun 29 05:32:48 PM PDT 24
Peak memory 265564 kb
Host smart-05a7e99b-68ca-44f5-954f-d361c66b7627
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557568140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1557568140
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2278975981
Short name T45
Test name
Test status
Simulation time 85331205973 ps
CPU time 1836.33 seconds
Started Jun 29 05:57:08 PM PDT 24
Finished Jun 29 06:27:45 PM PDT 24
Peak memory 298596 kb
Host smart-7cac3229-4704-42ec-b596-4326b8b768f7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278975981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2278975981
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.32703332
Short name T83
Test name
Test status
Simulation time 205351302360 ps
CPU time 2847.33 seconds
Started Jun 29 05:51:58 PM PDT 24
Finished Jun 29 06:39:26 PM PDT 24
Peak memory 290324 kb
Host smart-31ffe3a2-b8f5-405e-bbfd-cb8f1e2a6cf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32703332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.32703332
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1551993942
Short name T135
Test name
Test status
Simulation time 16133707216 ps
CPU time 286.1 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:27:15 PM PDT 24
Peak memory 265444 kb
Host smart-bdb1b48c-9b85-4d5d-9eb6-394c142e1672
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1551993942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1551993942
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1500142215
Short name T240
Test name
Test status
Simulation time 58511612460 ps
CPU time 662.57 seconds
Started Jun 29 05:58:42 PM PDT 24
Finished Jun 29 06:09:46 PM PDT 24
Peak memory 249396 kb
Host smart-915ea0b0-a22a-4f3d-9453-427f04c0f382
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500142215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1500142215
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2185814700
Short name T278
Test name
Test status
Simulation time 256840653383 ps
CPU time 3423.43 seconds
Started Jun 29 05:52:24 PM PDT 24
Finished Jun 29 06:49:28 PM PDT 24
Peak memory 290064 kb
Host smart-d4b9bad0-43f4-431f-9947-698d8876a3fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185814700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2185814700
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.583514407
Short name T49
Test name
Test status
Simulation time 192863060711 ps
CPU time 3954.8 seconds
Started Jun 29 05:53:13 PM PDT 24
Finished Jun 29 06:59:08 PM PDT 24
Peak memory 338644 kb
Host smart-1b195801-07e8-461c-b50f-e57218e5cf66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583514407 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.583514407
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1625878367
Short name T139
Test name
Test status
Simulation time 1794024490 ps
CPU time 217.49 seconds
Started Jun 29 05:22:27 PM PDT 24
Finished Jun 29 05:26:05 PM PDT 24
Peak memory 272228 kb
Host smart-387398b1-7de5-4213-a4e8-44117424f524
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1625878367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1625878367
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2221889828
Short name T8
Test name
Test status
Simulation time 11214321638 ps
CPU time 221.4 seconds
Started Jun 29 05:53:13 PM PDT 24
Finished Jun 29 05:56:55 PM PDT 24
Peak memory 249380 kb
Host smart-619f4bc0-d7c7-4d03-bd1d-33fdaeeea951
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221889828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2221889828
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.134746869
Short name T172
Test name
Test status
Simulation time 596067142 ps
CPU time 41.63 seconds
Started Jun 29 05:22:26 PM PDT 24
Finished Jun 29 05:23:09 PM PDT 24
Peak memory 240412 kb
Host smart-bddbbd42-95cc-4abe-a930-94fe44707bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=134746869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.134746869
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1625248810
Short name T165
Test name
Test status
Simulation time 26734484293 ps
CPU time 601.36 seconds
Started Jun 29 05:22:46 PM PDT 24
Finished Jun 29 05:32:48 PM PDT 24
Peak memory 265396 kb
Host smart-78c232dd-ebcd-49fa-ae88-c51b31690deb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625248810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1625248810
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1651691916
Short name T296
Test name
Test status
Simulation time 11280508514 ps
CPU time 451.82 seconds
Started Jun 29 05:59:23 PM PDT 24
Finished Jun 29 06:06:56 PM PDT 24
Peak memory 249228 kb
Host smart-0a0e6ae1-35cb-485c-9b5b-5f0950d93f87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651691916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1651691916
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.799556728
Short name T110
Test name
Test status
Simulation time 10925036562 ps
CPU time 1144.47 seconds
Started Jun 29 05:54:58 PM PDT 24
Finished Jun 29 06:14:04 PM PDT 24
Peak memory 290000 kb
Host smart-699df70c-abc6-4187-9a9f-d28de2558ac4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799556728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.799556728
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3187145268
Short name T330
Test name
Test status
Simulation time 86343697433 ps
CPU time 2447.4 seconds
Started Jun 29 06:00:23 PM PDT 24
Finished Jun 29 06:41:12 PM PDT 24
Peak memory 289444 kb
Host smart-6ff2ad9f-c4ab-42bb-99cf-55595c8addec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187145268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3187145268
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.920525453
Short name T175
Test name
Test status
Simulation time 11076582 ps
CPU time 1.37 seconds
Started Jun 29 05:22:47 PM PDT 24
Finished Jun 29 05:22:49 PM PDT 24
Peak memory 236664 kb
Host smart-ca459d81-6c50-4e77-98bd-ae5c88727025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=920525453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.920525453
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3588308088
Short name T676
Test name
Test status
Simulation time 9946988881 ps
CPU time 356.47 seconds
Started Jun 29 05:54:11 PM PDT 24
Finished Jun 29 06:00:08 PM PDT 24
Peak memory 249388 kb
Host smart-ac86440b-56a7-425d-9f6c-49550f943e50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588308088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3588308088
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3234650936
Short name T255
Test name
Test status
Simulation time 305058370 ps
CPU time 39.47 seconds
Started Jun 29 05:54:09 PM PDT 24
Finished Jun 29 05:54:48 PM PDT 24
Peak memory 250228 kb
Host smart-f3982fea-350d-44af-8c67-ef50a51c6645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32346
50936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3234650936
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2087090644
Short name T259
Test name
Test status
Simulation time 696704911151 ps
CPU time 5336.14 seconds
Started Jun 29 05:59:49 PM PDT 24
Finished Jun 29 07:28:46 PM PDT 24
Peak memory 323144 kb
Host smart-455faece-735c-4df9-b829-005443540f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087090644 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2087090644
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1529927058
Short name T311
Test name
Test status
Simulation time 105056027719 ps
CPU time 2396.88 seconds
Started Jun 29 05:51:40 PM PDT 24
Finished Jun 29 06:31:38 PM PDT 24
Peak memory 273872 kb
Host smart-0bf08bb7-c743-4b54-880c-f89f3722926b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529927058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1529927058
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3808774781
Short name T101
Test name
Test status
Simulation time 47445571162 ps
CPU time 4100.84 seconds
Started Jun 29 05:54:08 PM PDT 24
Finished Jun 29 07:02:30 PM PDT 24
Peak memory 319688 kb
Host smart-0e10bd8b-ca39-47ca-96e5-57a88897caf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808774781 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3808774781
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3738309434
Short name T153
Test name
Test status
Simulation time 4445194852 ps
CPU time 298.65 seconds
Started Jun 29 05:22:42 PM PDT 24
Finished Jun 29 05:27:41 PM PDT 24
Peak memory 265576 kb
Host smart-7b47469d-cc9b-446a-8d47-c5c3dc88cccc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3738309434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3738309434
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1128413815
Short name T306
Test name
Test status
Simulation time 17589842582 ps
CPU time 368.35 seconds
Started Jun 29 05:53:36 PM PDT 24
Finished Jun 29 05:59:45 PM PDT 24
Peak memory 249104 kb
Host smart-7bdf1650-16b1-4e9d-bdfb-fcd502833e3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128413815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1128413815
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3703380019
Short name T23
Test name
Test status
Simulation time 47093612536 ps
CPU time 2938.11 seconds
Started Jun 29 05:52:04 PM PDT 24
Finished Jun 29 06:41:03 PM PDT 24
Peak memory 282136 kb
Host smart-4c5a5340-0853-477e-85d0-4a6dfc74aa6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703380019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3703380019
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.865124590
Short name T149
Test name
Test status
Simulation time 6777492916 ps
CPU time 467.99 seconds
Started Jun 29 05:22:27 PM PDT 24
Finished Jun 29 05:30:16 PM PDT 24
Peak memory 265472 kb
Host smart-ed907906-7df4-4698-a008-c41248962785
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=865124590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.865124590
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2677450522
Short name T168
Test name
Test status
Simulation time 803307212 ps
CPU time 113.24 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:24:44 PM PDT 24
Peak memory 265408 kb
Host smart-abeeeb4c-b91e-4fa0-a800-b638a87f3ad9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2677450522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2677450522
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3670670572
Short name T319
Test name
Test status
Simulation time 7040347126 ps
CPU time 273.53 seconds
Started Jun 29 05:51:49 PM PDT 24
Finished Jun 29 05:56:23 PM PDT 24
Peak memory 249400 kb
Host smart-ad740f5d-216e-43ed-b725-157202b37aad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670670572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3670670572
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1565318924
Short name T314
Test name
Test status
Simulation time 36378882325 ps
CPU time 2066.77 seconds
Started Jun 29 05:57:09 PM PDT 24
Finished Jun 29 06:31:37 PM PDT 24
Peak memory 273332 kb
Host smart-e3792724-3920-4c3f-a47d-6df91e80b8a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565318924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1565318924
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2558089379
Short name T89
Test name
Test status
Simulation time 6386760008 ps
CPU time 380.5 seconds
Started Jun 29 05:52:15 PM PDT 24
Finished Jun 29 05:58:35 PM PDT 24
Peak memory 254860 kb
Host smart-99b9a015-28fa-4c13-bc60-f3b52dcc2e77
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558089379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2558089379
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.842920137
Short name T157
Test name
Test status
Simulation time 8912021647 ps
CPU time 664.51 seconds
Started Jun 29 05:22:27 PM PDT 24
Finished Jun 29 05:33:32 PM PDT 24
Peak memory 265432 kb
Host smart-a420e5bb-2c8e-4268-bfc5-959b303aa91d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842920137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.842920137
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1023079579
Short name T267
Test name
Test status
Simulation time 49609045 ps
CPU time 2.53 seconds
Started Jun 29 05:22:36 PM PDT 24
Finished Jun 29 05:22:39 PM PDT 24
Peak memory 237604 kb
Host smart-e9a55fb0-e53a-46d2-8e7a-c3cbb1cf36c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1023079579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1023079579
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.4243224420
Short name T17
Test name
Test status
Simulation time 62935134950 ps
CPU time 2130.09 seconds
Started Jun 29 05:53:15 PM PDT 24
Finished Jun 29 06:28:46 PM PDT 24
Peak memory 289464 kb
Host smart-2c65c7a6-2ff5-4aa5-9334-9477551cb5c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243224420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.4243224420
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2058055342
Short name T219
Test name
Test status
Simulation time 807734373 ps
CPU time 3.66 seconds
Started Jun 29 05:51:41 PM PDT 24
Finished Jun 29 05:51:45 PM PDT 24
Peak memory 249532 kb
Host smart-d74fb7e8-f333-4fae-a78d-637e969ff56c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2058055342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2058055342
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3082215144
Short name T209
Test name
Test status
Simulation time 143938310 ps
CPU time 3.83 seconds
Started Jun 29 05:52:54 PM PDT 24
Finished Jun 29 05:52:58 PM PDT 24
Peak memory 249568 kb
Host smart-cc72097d-2921-4d1e-b56a-1e29a763c897
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3082215144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3082215144
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3853831080
Short name T204
Test name
Test status
Simulation time 27604085 ps
CPU time 2.78 seconds
Started Jun 29 05:53:05 PM PDT 24
Finished Jun 29 05:53:08 PM PDT 24
Peak memory 249576 kb
Host smart-a6b5db65-d4f7-42c3-abca-339429b04ad1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3853831080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3853831080
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.415076554
Short name T207
Test name
Test status
Simulation time 166629709 ps
CPU time 3.6 seconds
Started Jun 29 05:54:05 PM PDT 24
Finished Jun 29 05:54:09 PM PDT 24
Peak memory 249528 kb
Host smart-03d5e986-e453-4a72-a37d-8f853c54ab65
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=415076554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.415076554
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2814131304
Short name T87
Test name
Test status
Simulation time 44915375856 ps
CPU time 3092.57 seconds
Started Jun 29 05:51:40 PM PDT 24
Finished Jun 29 06:43:14 PM PDT 24
Peak memory 302556 kb
Host smart-24d41305-b49b-49ac-94d4-1991eaa3feda
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814131304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2814131304
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.95363983
Short name T272
Test name
Test status
Simulation time 294933628 ps
CPU time 14.07 seconds
Started Jun 29 05:53:45 PM PDT 24
Finished Jun 29 05:53:59 PM PDT 24
Peak memory 248800 kb
Host smart-4a4b9e81-bc9c-416e-a369-53fb2193934c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95363
983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.95363983
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.859620508
Short name T271
Test name
Test status
Simulation time 730133243 ps
CPU time 25.47 seconds
Started Jun 29 05:54:37 PM PDT 24
Finished Jun 29 05:55:03 PM PDT 24
Peak memory 256988 kb
Host smart-3ae0165b-ad5f-4981-bee7-63360a6f7bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85962
0508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.859620508
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3737133691
Short name T92
Test name
Test status
Simulation time 48956851237 ps
CPU time 1337.18 seconds
Started Jun 29 05:56:37 PM PDT 24
Finished Jun 29 06:18:54 PM PDT 24
Peak memory 290212 kb
Host smart-ec4a80c6-ef96-4cd7-9d85-59e717ebc600
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737133691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3737133691
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.232233161
Short name T609
Test name
Test status
Simulation time 28102939436 ps
CPU time 1633.7 seconds
Started Jun 29 05:57:48 PM PDT 24
Finished Jun 29 06:25:02 PM PDT 24
Peak memory 265808 kb
Host smart-1658bf51-c0e7-47ed-8c99-ba87b2af1637
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232233161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.232233161
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3173320165
Short name T103
Test name
Test status
Simulation time 158797677057 ps
CPU time 2592.77 seconds
Started Jun 29 05:52:54 PM PDT 24
Finished Jun 29 06:36:08 PM PDT 24
Peak memory 290180 kb
Host smart-673792bb-5fe5-44b6-8c41-3ec7f0de6c6d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173320165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3173320165
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1432799055
Short name T166
Test name
Test status
Simulation time 15333544666 ps
CPU time 294.31 seconds
Started Jun 29 05:22:41 PM PDT 24
Finished Jun 29 05:27:36 PM PDT 24
Peak memory 265472 kb
Host smart-fc95a7d0-12ff-414c-ab32-fc3e50ed751d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1432799055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1432799055
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2135469335
Short name T163
Test name
Test status
Simulation time 18863243447 ps
CPU time 1357.25 seconds
Started Jun 29 05:22:40 PM PDT 24
Finished Jun 29 05:45:18 PM PDT 24
Peak memory 265312 kb
Host smart-b7356896-4318-4279-a088-28f40735be03
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135469335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2135469335
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3352203503
Short name T712
Test name
Test status
Simulation time 8969265 ps
CPU time 1.29 seconds
Started Jun 29 05:22:35 PM PDT 24
Finished Jun 29 05:22:37 PM PDT 24
Peak memory 236620 kb
Host smart-fe9f150b-03ed-4e07-8f93-1dca05dd18f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3352203503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3352203503
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1065961146
Short name T159
Test name
Test status
Simulation time 8362763602 ps
CPU time 312.69 seconds
Started Jun 29 05:22:22 PM PDT 24
Finished Jun 29 05:27:35 PM PDT 24
Peak memory 265504 kb
Host smart-addc451d-111f-43e9-b3e0-f2f0d21eaf3c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065961146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1065961146
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1618161039
Short name T580
Test name
Test status
Simulation time 304280865234 ps
CPU time 3163.41 seconds
Started Jun 29 05:51:40 PM PDT 24
Finished Jun 29 06:44:24 PM PDT 24
Peak memory 290364 kb
Host smart-f9615962-f0f5-4384-822e-657da63b499c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618161039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1618161039
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1157901836
Short name T63
Test name
Test status
Simulation time 1260271521 ps
CPU time 56.89 seconds
Started Jun 29 05:51:39 PM PDT 24
Finished Jun 29 05:52:37 PM PDT 24
Peak memory 257016 kb
Host smart-e6c9b646-8a4b-4d78-95b5-6f2d2dec8ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11579
01836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1157901836
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1174623588
Short name T246
Test name
Test status
Simulation time 63917253879 ps
CPU time 5815.77 seconds
Started Jun 29 05:51:47 PM PDT 24
Finished Jun 29 07:28:44 PM PDT 24
Peak memory 370336 kb
Host smart-7e0227ff-0ce2-40f6-98f9-ba1d2571631a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174623588 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1174623588
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2509693313
Short name T260
Test name
Test status
Simulation time 779563313 ps
CPU time 47.74 seconds
Started Jun 29 05:52:38 PM PDT 24
Finished Jun 29 05:53:26 PM PDT 24
Peak memory 249080 kb
Host smart-53b5cca6-d070-4ff4-9bfe-1f39652949aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25096
93313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2509693313
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.812393402
Short name T322
Test name
Test status
Simulation time 25118981911 ps
CPU time 426.85 seconds
Started Jun 29 05:52:54 PM PDT 24
Finished Jun 29 06:00:01 PM PDT 24
Peak memory 249128 kb
Host smart-6defc4cf-acd8-4c52-a0a3-b8b550ef5bfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812393402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.812393402
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3377332013
Short name T340
Test name
Test status
Simulation time 125509070397 ps
CPU time 1955.76 seconds
Started Jun 29 05:53:06 PM PDT 24
Finished Jun 29 06:25:42 PM PDT 24
Peak memory 273960 kb
Host smart-6a973f9d-9612-4215-824b-4bc2b28b20e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377332013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3377332013
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3921360734
Short name T257
Test name
Test status
Simulation time 3362386636 ps
CPU time 85.33 seconds
Started Jun 29 05:53:28 PM PDT 24
Finished Jun 29 05:54:54 PM PDT 24
Peak memory 257616 kb
Host smart-ef281f8d-52b5-4074-b6aa-cb9da08fed61
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921360734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3921360734
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3071350281
Short name T288
Test name
Test status
Simulation time 1150441089987 ps
CPU time 6000.73 seconds
Started Jun 29 05:53:48 PM PDT 24
Finished Jun 29 07:33:49 PM PDT 24
Peak memory 323288 kb
Host smart-29b3e9d8-52fd-4a68-9ea8-aadd1f8acbdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071350281 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3071350281
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.580906526
Short name T277
Test name
Test status
Simulation time 58236739191 ps
CPU time 1798.66 seconds
Started Jun 29 05:53:51 PM PDT 24
Finished Jun 29 06:23:50 PM PDT 24
Peak memory 286636 kb
Host smart-85b316e8-3ad9-40fc-8f30-52c302ed2e44
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580906526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.580906526
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.4227943157
Short name T281
Test name
Test status
Simulation time 15681533379 ps
CPU time 168.94 seconds
Started Jun 29 05:54:26 PM PDT 24
Finished Jun 29 05:57:15 PM PDT 24
Peak memory 249392 kb
Host smart-164b5592-14cd-409f-a8ac-4dea17008246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227943157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.4227943157
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3447497884
Short name T91
Test name
Test status
Simulation time 323274533 ps
CPU time 20.3 seconds
Started Jun 29 05:54:34 PM PDT 24
Finished Jun 29 05:54:54 PM PDT 24
Peak memory 255876 kb
Host smart-20e2479f-695f-4e1d-9005-f06fdd373393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34474
97884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3447497884
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3710445564
Short name T196
Test name
Test status
Simulation time 16225432998 ps
CPU time 978.62 seconds
Started Jun 29 05:55:56 PM PDT 24
Finished Jun 29 06:12:15 PM PDT 24
Peak memory 268192 kb
Host smart-e6df46fa-0fb6-4b1a-96a0-a593c5acfbe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710445564 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3710445564
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1430846380
Short name T266
Test name
Test status
Simulation time 1307774873 ps
CPU time 35.28 seconds
Started Jun 29 05:56:23 PM PDT 24
Finished Jun 29 05:56:58 PM PDT 24
Peak memory 257212 kb
Host smart-192e442e-5d70-44a8-878c-08afa348a105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14308
46380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1430846380
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.4020448940
Short name T254
Test name
Test status
Simulation time 1138870299 ps
CPU time 63.64 seconds
Started Jun 29 05:56:35 PM PDT 24
Finished Jun 29 05:57:39 PM PDT 24
Peak memory 257096 kb
Host smart-8753e7b8-0748-4685-9332-072ad744649e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40204
48940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.4020448940
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3271063291
Short name T74
Test name
Test status
Simulation time 2941508704 ps
CPU time 126.06 seconds
Started Jun 29 05:52:06 PM PDT 24
Finished Jun 29 05:54:13 PM PDT 24
Peak memory 249404 kb
Host smart-ff787207-5a31-44ea-8801-7ef4b36a8caa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271063291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3271063291
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2788076912
Short name T223
Test name
Test status
Simulation time 1255385218 ps
CPU time 25.96 seconds
Started Jun 29 05:59:24 PM PDT 24
Finished Jun 29 05:59:50 PM PDT 24
Peak memory 256992 kb
Host smart-2f2fba62-cbab-4231-9976-46e2176cfc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27880
76912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2788076912
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1625374221
Short name T276
Test name
Test status
Simulation time 48120545928 ps
CPU time 1284.6 seconds
Started Jun 29 06:00:02 PM PDT 24
Finished Jun 29 06:21:27 PM PDT 24
Peak memory 286064 kb
Host smart-8133be69-8f7f-49b2-9328-f1c8e2920fbe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625374221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1625374221
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.257695193
Short name T252
Test name
Test status
Simulation time 59882751780 ps
CPU time 1768.34 seconds
Started Jun 29 06:00:34 PM PDT 24
Finished Jun 29 06:30:03 PM PDT 24
Peak memory 289948 kb
Host smart-58811622-be90-4870-82a4-2514a6145642
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257695193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.257695193
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.4172493598
Short name T170
Test name
Test status
Simulation time 52789305 ps
CPU time 4.59 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:22:56 PM PDT 24
Peak memory 237604 kb
Host smart-578c66d0-6015-477e-bc03-5d60f3650c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4172493598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.4172493598
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2063169639
Short name T134
Test name
Test status
Simulation time 2254283768 ps
CPU time 148.96 seconds
Started Jun 29 05:22:27 PM PDT 24
Finished Jun 29 05:24:57 PM PDT 24
Peak memory 265716 kb
Host smart-495003c3-ced3-442b-8271-66413d59076b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2063169639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2063169639
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3750410802
Short name T156
Test name
Test status
Simulation time 25310204486 ps
CPU time 505.02 seconds
Started Jun 29 05:22:29 PM PDT 24
Finished Jun 29 05:30:55 PM PDT 24
Peak memory 265420 kb
Host smart-b8e44650-c985-4a60-9698-8e3047a24fea
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750410802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3750410802
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3695415376
Short name T176
Test name
Test status
Simulation time 3431011609 ps
CPU time 63.84 seconds
Started Jun 29 05:22:44 PM PDT 24
Finished Jun 29 05:23:49 PM PDT 24
Peak memory 248760 kb
Host smart-152f2c09-6330-4068-86e7-7077983d70bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3695415376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3695415376
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3409700569
Short name T182
Test name
Test status
Simulation time 1053975727 ps
CPU time 72.17 seconds
Started Jun 29 05:22:46 PM PDT 24
Finished Jun 29 05:23:59 PM PDT 24
Peak memory 240560 kb
Host smart-640bd90a-0228-4771-9715-7a8459254aae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3409700569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3409700569
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4228451394
Short name T177
Test name
Test status
Simulation time 4999226288 ps
CPU time 81.58 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:24:13 PM PDT 24
Peak memory 240592 kb
Host smart-c9330366-5ef6-44c9-99d4-cbf3ec21733b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4228451394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.4228451394
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2370411459
Short name T184
Test name
Test status
Simulation time 362857512 ps
CPU time 47.28 seconds
Started Jun 29 05:22:15 PM PDT 24
Finished Jun 29 05:23:03 PM PDT 24
Peak memory 240528 kb
Host smart-b4844c0c-b8be-46fb-9fe3-dc32a9727da0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2370411459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2370411459
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.131259157
Short name T191
Test name
Test status
Simulation time 1276717662 ps
CPU time 93.96 seconds
Started Jun 29 05:22:29 PM PDT 24
Finished Jun 29 05:24:04 PM PDT 24
Peak memory 240556 kb
Host smart-b1d5fb7c-c21e-449c-8f28-74627f728abf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=131259157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.131259157
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1560030456
Short name T178
Test name
Test status
Simulation time 477200428 ps
CPU time 36.55 seconds
Started Jun 29 05:22:37 PM PDT 24
Finished Jun 29 05:23:14 PM PDT 24
Peak memory 240524 kb
Host smart-a85010e4-416e-4c82-8fe3-f771ad0cf191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1560030456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1560030456
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3629830007
Short name T180
Test name
Test status
Simulation time 2476397958 ps
CPU time 40.65 seconds
Started Jun 29 05:22:18 PM PDT 24
Finished Jun 29 05:22:59 PM PDT 24
Peak memory 240608 kb
Host smart-c4c6bc13-3538-4025-b25f-e9bc515d1135
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3629830007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3629830007
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2207283563
Short name T192
Test name
Test status
Simulation time 50888520 ps
CPU time 2.75 seconds
Started Jun 29 05:22:29 PM PDT 24
Finished Jun 29 05:22:33 PM PDT 24
Peak memory 237632 kb
Host smart-651e9032-0e75-4b8d-9470-c08f041b6e17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2207283563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2207283563
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3075470853
Short name T179
Test name
Test status
Simulation time 5192910362 ps
CPU time 84.03 seconds
Started Jun 29 05:22:35 PM PDT 24
Finished Jun 29 05:24:00 PM PDT 24
Peak memory 247820 kb
Host smart-77f9e1e1-2edd-490c-9f78-583c3f7c41c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3075470853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3075470853
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3085108735
Short name T183
Test name
Test status
Simulation time 89091805 ps
CPU time 4.59 seconds
Started Jun 29 05:22:40 PM PDT 24
Finished Jun 29 05:22:46 PM PDT 24
Peak memory 236652 kb
Host smart-5b553de2-ec8a-428d-a225-c8889b548eac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3085108735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3085108735
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3906039479
Short name T185
Test name
Test status
Simulation time 162805041 ps
CPU time 24.2 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:23:14 PM PDT 24
Peak memory 240552 kb
Host smart-819d1516-7fd8-47f3-bc18-be6e7f3c9aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3906039479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3906039479
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3824988257
Short name T181
Test name
Test status
Simulation time 932119391 ps
CPU time 68.15 seconds
Started Jun 29 05:22:43 PM PDT 24
Finished Jun 29 05:23:52 PM PDT 24
Peak memory 240488 kb
Host smart-355d1879-2c52-468d-92a5-bbf273dedb79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3824988257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3824988257
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2276690263
Short name T194
Test name
Test status
Simulation time 219776988 ps
CPU time 3.85 seconds
Started Jun 29 05:22:21 PM PDT 24
Finished Jun 29 05:22:25 PM PDT 24
Peak memory 236636 kb
Host smart-e16eb17f-5bde-4efc-9ec8-412daa18696c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2276690263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2276690263
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3467377997
Short name T193
Test name
Test status
Simulation time 320882700 ps
CPU time 22.29 seconds
Started Jun 29 05:22:26 PM PDT 24
Finished Jun 29 05:22:49 PM PDT 24
Peak memory 245860 kb
Host smart-15d0ada3-d724-440f-b173-b06d91aa01fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3467377997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3467377997
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2667494065
Short name T186
Test name
Test status
Simulation time 2476223674 ps
CPU time 46.11 seconds
Started Jun 29 05:22:29 PM PDT 24
Finished Jun 29 05:23:16 PM PDT 24
Peak memory 240616 kb
Host smart-09a81773-dedc-41c3-948f-93e8c5c651f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2667494065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2667494065
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2965214386
Short name T819
Test name
Test status
Simulation time 523325506 ps
CPU time 59.35 seconds
Started Jun 29 05:22:17 PM PDT 24
Finished Jun 29 05:23:17 PM PDT 24
Peak memory 237676 kb
Host smart-8e42f98c-c4f5-40a5-a393-1590cef06e03
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2965214386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2965214386
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.735083812
Short name T818
Test name
Test status
Simulation time 15018412830 ps
CPU time 203.07 seconds
Started Jun 29 05:22:22 PM PDT 24
Finished Jun 29 05:25:45 PM PDT 24
Peak memory 237664 kb
Host smart-be6e2c65-7eb1-4c97-96fd-a399d79abf02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=735083812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.735083812
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2652425846
Short name T808
Test name
Test status
Simulation time 241738301 ps
CPU time 11.43 seconds
Started Jun 29 05:22:24 PM PDT 24
Finished Jun 29 05:22:36 PM PDT 24
Peak memory 248756 kb
Host smart-0b25c0ac-c610-4835-9082-7e45796ee728
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2652425846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2652425846
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1201448478
Short name T350
Test name
Test status
Simulation time 131146557 ps
CPU time 12.25 seconds
Started Jun 29 05:22:15 PM PDT 24
Finished Jun 29 05:22:27 PM PDT 24
Peak memory 253584 kb
Host smart-c8297265-64cf-4891-a6b3-2046b841fe85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201448478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1201448478
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3782680440
Short name T769
Test name
Test status
Simulation time 1226984621 ps
CPU time 8.55 seconds
Started Jun 29 05:22:15 PM PDT 24
Finished Jun 29 05:22:24 PM PDT 24
Peak memory 236644 kb
Host smart-b37d1647-baea-4ec8-8b3a-e987b1815a7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3782680440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3782680440
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4284627285
Short name T780
Test name
Test status
Simulation time 10114275 ps
CPU time 1.28 seconds
Started Jun 29 05:22:16 PM PDT 24
Finished Jun 29 05:22:18 PM PDT 24
Peak memory 235644 kb
Host smart-5be33049-e24e-46e9-bf5d-11e64201411c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4284627285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.4284627285
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3944409784
Short name T190
Test name
Test status
Simulation time 642259353 ps
CPU time 22.41 seconds
Started Jun 29 05:22:20 PM PDT 24
Finished Jun 29 05:22:42 PM PDT 24
Peak memory 245812 kb
Host smart-ea8362e7-5440-47fd-9421-4ee84b74c4e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3944409784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3944409784
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1089411788
Short name T152
Test name
Test status
Simulation time 13318354528 ps
CPU time 77.02 seconds
Started Jun 29 05:22:21 PM PDT 24
Finished Jun 29 05:23:39 PM PDT 24
Peak memory 265472 kb
Host smart-1164f354-2126-4986-9470-f3f9c573029e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1089411788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1089411788
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3018361392
Short name T735
Test name
Test status
Simulation time 287330595 ps
CPU time 16.84 seconds
Started Jun 29 05:22:14 PM PDT 24
Finished Jun 29 05:22:31 PM PDT 24
Peak memory 248828 kb
Host smart-a4e0cdfe-6344-47e1-9f2b-75a3e2336d70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3018361392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3018361392
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1455463848
Short name T268
Test name
Test status
Simulation time 570511218 ps
CPU time 37.65 seconds
Started Jun 29 05:22:24 PM PDT 24
Finished Jun 29 05:23:02 PM PDT 24
Peak memory 240540 kb
Host smart-c03cab00-b146-4aec-b47c-fee0bf24f8b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1455463848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1455463848
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.935426840
Short name T777
Test name
Test status
Simulation time 4659197223 ps
CPU time 158.73 seconds
Started Jun 29 05:22:25 PM PDT 24
Finished Jun 29 05:25:05 PM PDT 24
Peak memory 240736 kb
Host smart-d72552ce-f7bd-4e84-9754-c4e2674fd4f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=935426840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.935426840
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3796379875
Short name T822
Test name
Test status
Simulation time 1637937949 ps
CPU time 96.61 seconds
Started Jun 29 05:22:22 PM PDT 24
Finished Jun 29 05:23:59 PM PDT 24
Peak memory 236652 kb
Host smart-61ea4329-dc76-4084-98a1-b12b4adfb8ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3796379875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3796379875
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1684210573
Short name T728
Test name
Test status
Simulation time 22835025 ps
CPU time 4.26 seconds
Started Jun 29 05:22:15 PM PDT 24
Finished Jun 29 05:22:20 PM PDT 24
Peak memory 240560 kb
Host smart-4fac55c7-c088-45ea-abef-c7fe04e8d39d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1684210573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1684210573
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2526716483
Short name T755
Test name
Test status
Simulation time 587706164 ps
CPU time 6.96 seconds
Started Jun 29 05:22:27 PM PDT 24
Finished Jun 29 05:22:35 PM PDT 24
Peak memory 252616 kb
Host smart-435e3769-362d-4371-8c71-11530a4ef9fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526716483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2526716483
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1202680250
Short name T198
Test name
Test status
Simulation time 19937477 ps
CPU time 3.51 seconds
Started Jun 29 05:22:14 PM PDT 24
Finished Jun 29 05:22:18 PM PDT 24
Peak memory 239440 kb
Host smart-f0d79bdc-9df0-498e-9ddf-af378fcf426c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1202680250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1202680250
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3319665767
Short name T773
Test name
Test status
Simulation time 15552714 ps
CPU time 1.61 seconds
Started Jun 29 05:22:24 PM PDT 24
Finished Jun 29 05:22:27 PM PDT 24
Peak memory 237508 kb
Host smart-c4538050-53e7-4f18-9421-821f45c323bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3319665767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3319665767
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1720903446
Short name T784
Test name
Test status
Simulation time 357812738 ps
CPU time 25.49 seconds
Started Jun 29 05:22:17 PM PDT 24
Finished Jun 29 05:22:43 PM PDT 24
Peak memory 245812 kb
Host smart-b0c4cc55-7010-4ecf-b813-0a04d791b9e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1720903446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1720903446
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4048111881
Short name T142
Test name
Test status
Simulation time 2095208010 ps
CPU time 307.13 seconds
Started Jun 29 05:22:21 PM PDT 24
Finished Jun 29 05:27:29 PM PDT 24
Peak memory 265340 kb
Host smart-56db1b83-2b64-46aa-9cde-67a065700373
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048111881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.4048111881
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2324572453
Short name T699
Test name
Test status
Simulation time 648641410 ps
CPU time 16.63 seconds
Started Jun 29 05:22:32 PM PDT 24
Finished Jun 29 05:22:49 PM PDT 24
Peak memory 248252 kb
Host smart-069c13dc-ae3b-46d6-a3e5-d9b23a93ddd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2324572453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2324572453
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.140804070
Short name T722
Test name
Test status
Simulation time 300360369 ps
CPU time 9.55 seconds
Started Jun 29 05:22:35 PM PDT 24
Finished Jun 29 05:22:45 PM PDT 24
Peak memory 238368 kb
Host smart-3b5db93e-ba29-479d-bf96-d57957ab6bf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140804070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.140804070
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.282083801
Short name T782
Test name
Test status
Simulation time 783711003 ps
CPU time 10.11 seconds
Started Jun 29 05:22:42 PM PDT 24
Finished Jun 29 05:22:53 PM PDT 24
Peak memory 237604 kb
Host smart-c093a7ba-f987-4d78-b4df-0e4127524c57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=282083801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.282083801
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4034058533
Short name T344
Test name
Test status
Simulation time 9813535 ps
CPU time 1.31 seconds
Started Jun 29 05:22:44 PM PDT 24
Finished Jun 29 05:22:46 PM PDT 24
Peak memory 235696 kb
Host smart-6804d321-e9cf-4e35-b402-e76bdfa10273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4034058533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4034058533
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4043488104
Short name T814
Test name
Test status
Simulation time 1189553319 ps
CPU time 22.23 seconds
Started Jun 29 05:22:29 PM PDT 24
Finished Jun 29 05:22:52 PM PDT 24
Peak memory 248748 kb
Host smart-bcbb52c5-775c-4aaa-a784-c2c24c6abb3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4043488104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.4043488104
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3097786021
Short name T133
Test name
Test status
Simulation time 2227853810 ps
CPU time 318.97 seconds
Started Jun 29 05:22:38 PM PDT 24
Finished Jun 29 05:27:57 PM PDT 24
Peak memory 270456 kb
Host smart-160977d5-dcf0-4d44-a1a8-814647cb40ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097786021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3097786021
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.223432127
Short name T729
Test name
Test status
Simulation time 375093323 ps
CPU time 8.24 seconds
Started Jun 29 05:22:46 PM PDT 24
Finished Jun 29 05:22:55 PM PDT 24
Peak memory 248812 kb
Host smart-b5fb6225-5f07-42c4-a2f5-ae945c11ef85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=223432127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.223432127
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.4011190522
Short name T792
Test name
Test status
Simulation time 1019164980 ps
CPU time 9.72 seconds
Started Jun 29 05:22:36 PM PDT 24
Finished Jun 29 05:22:46 PM PDT 24
Peak memory 256988 kb
Host smart-9aeda08e-ed73-45db-ad84-b1cf215bc4d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011190522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.4011190522
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.269261141
Short name T763
Test name
Test status
Simulation time 117497355 ps
CPU time 4.6 seconds
Started Jun 29 05:22:47 PM PDT 24
Finished Jun 29 05:22:52 PM PDT 24
Peak memory 236648 kb
Host smart-45b8c462-5a5e-4dda-a8f7-968c48c4ab4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=269261141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.269261141
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2504697659
Short name T804
Test name
Test status
Simulation time 6378059 ps
CPU time 1.48 seconds
Started Jun 29 05:22:29 PM PDT 24
Finished Jun 29 05:22:31 PM PDT 24
Peak memory 236568 kb
Host smart-42f180f6-f79f-48fc-9685-4db476be50bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2504697659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2504697659
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3319350559
Short name T817
Test name
Test status
Simulation time 1072781979 ps
CPU time 20.81 seconds
Started Jun 29 05:22:43 PM PDT 24
Finished Jun 29 05:23:05 PM PDT 24
Peak memory 245800 kb
Host smart-fec8b9b3-3c1d-45cb-a467-b92a52472171
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3319350559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3319350559
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2199142959
Short name T820
Test name
Test status
Simulation time 5951749335 ps
CPU time 230.01 seconds
Started Jun 29 05:22:37 PM PDT 24
Finished Jun 29 05:26:28 PM PDT 24
Peak memory 265472 kb
Host smart-049962bb-3d3c-4c99-ae7e-dfcd79191b09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2199142959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2199142959
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.160832680
Short name T351
Test name
Test status
Simulation time 36122316422 ps
CPU time 447.99 seconds
Started Jun 29 05:22:32 PM PDT 24
Finished Jun 29 05:30:01 PM PDT 24
Peak memory 265268 kb
Host smart-bbb763cf-68e8-462d-966e-bced6fe85a93
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160832680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.160832680
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3169127388
Short name T781
Test name
Test status
Simulation time 158622502 ps
CPU time 12.34 seconds
Started Jun 29 05:22:36 PM PDT 24
Finished Jun 29 05:22:49 PM PDT 24
Peak memory 248172 kb
Host smart-37fc8007-af1d-4160-8a28-9dcd0a3fc065
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3169127388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3169127388
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2433472513
Short name T801
Test name
Test status
Simulation time 63173004 ps
CPU time 9.07 seconds
Started Jun 29 05:22:40 PM PDT 24
Finished Jun 29 05:22:50 PM PDT 24
Peak memory 251476 kb
Host smart-b3027c28-ce20-4497-9be9-86a76ce3070d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433472513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2433472513
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.795806872
Short name T758
Test name
Test status
Simulation time 35395511 ps
CPU time 5.45 seconds
Started Jun 29 05:22:36 PM PDT 24
Finished Jun 29 05:22:42 PM PDT 24
Peak memory 240552 kb
Host smart-64115d5a-babd-4220-9f60-e623a10cee18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=795806872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.795806872
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3853763188
Short name T734
Test name
Test status
Simulation time 527931522 ps
CPU time 40.43 seconds
Started Jun 29 05:22:37 PM PDT 24
Finished Jun 29 05:23:18 PM PDT 24
Peak memory 245800 kb
Host smart-97565a6e-e25b-4a30-9611-d14995b96583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3853763188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3853763188
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.144944986
Short name T140
Test name
Test status
Simulation time 785531146 ps
CPU time 91.74 seconds
Started Jun 29 05:22:42 PM PDT 24
Finished Jun 29 05:24:15 PM PDT 24
Peak memory 269164 kb
Host smart-8f56853d-90c4-4a34-8b39-8c3a259ca8b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=144944986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.144944986
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.270729081
Short name T810
Test name
Test status
Simulation time 154219383 ps
CPU time 11.23 seconds
Started Jun 29 05:22:39 PM PDT 24
Finished Jun 29 05:22:51 PM PDT 24
Peak memory 246036 kb
Host smart-ed2343ff-6c01-41c2-bdcd-a36f1ccf55b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=270729081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.270729081
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2281712028
Short name T754
Test name
Test status
Simulation time 362471109 ps
CPU time 6.54 seconds
Started Jun 29 05:22:47 PM PDT 24
Finished Jun 29 05:22:54 PM PDT 24
Peak memory 240520 kb
Host smart-da5cc2ee-4b33-40ac-a618-ae0061e45974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281712028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2281712028
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1984891235
Short name T821
Test name
Test status
Simulation time 1460112201 ps
CPU time 8.99 seconds
Started Jun 29 05:22:38 PM PDT 24
Finished Jun 29 05:22:48 PM PDT 24
Peak memory 240552 kb
Host smart-d039bb98-ed87-453c-b6be-00c51a1d3e73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1984891235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1984891235
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1602987682
Short name T798
Test name
Test status
Simulation time 90437248 ps
CPU time 10.67 seconds
Started Jun 29 05:22:39 PM PDT 24
Finished Jun 29 05:22:50 PM PDT 24
Peak memory 240540 kb
Host smart-ebba7934-b167-41e3-a813-451182b3a1c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1602987682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1602987682
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3412504724
Short name T155
Test name
Test status
Simulation time 13738426557 ps
CPU time 164.37 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:25:34 PM PDT 24
Peak memory 267116 kb
Host smart-d258d21b-8716-4bd7-b2e9-d6e91460255b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3412504724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3412504724
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1803407785
Short name T145
Test name
Test status
Simulation time 41256655138 ps
CPU time 556.38 seconds
Started Jun 29 05:22:46 PM PDT 24
Finished Jun 29 05:32:03 PM PDT 24
Peak memory 268084 kb
Host smart-d19cc55a-f951-44a8-ab78-bb1b46d05a12
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803407785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1803407785
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3594945696
Short name T721
Test name
Test status
Simulation time 137665282 ps
CPU time 10 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:23:01 PM PDT 24
Peak memory 254968 kb
Host smart-e56539f1-efb8-40f9-9d6d-90e1e094e6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3594945696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3594945696
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3954026505
Short name T812
Test name
Test status
Simulation time 367937945 ps
CPU time 7.48 seconds
Started Jun 29 05:22:45 PM PDT 24
Finished Jun 29 05:22:54 PM PDT 24
Peak memory 240568 kb
Host smart-1cb85fcb-88b0-4c61-a89f-ee18fe749ed9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954026505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3954026505
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4092250590
Short name T189
Test name
Test status
Simulation time 50611408 ps
CPU time 4.75 seconds
Started Jun 29 05:22:42 PM PDT 24
Finished Jun 29 05:22:48 PM PDT 24
Peak memory 240532 kb
Host smart-1a87b32c-1db2-4590-ac51-7d8bb014df8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4092250590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.4092250590
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.429384122
Short name T759
Test name
Test status
Simulation time 9972488 ps
CPU time 1.76 seconds
Started Jun 29 05:22:46 PM PDT 24
Finished Jun 29 05:22:49 PM PDT 24
Peak memory 236524 kb
Host smart-9b0e7d9b-5673-4a0e-b494-60e298b3e264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=429384122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.429384122
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3789366983
Short name T706
Test name
Test status
Simulation time 696417182 ps
CPU time 27.35 seconds
Started Jun 29 05:22:47 PM PDT 24
Finished Jun 29 05:23:15 PM PDT 24
Peak memory 245800 kb
Host smart-2ba2df0f-e9b1-49d8-b938-1dd8ae685ad4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3789366983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3789366983
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2190950490
Short name T143
Test name
Test status
Simulation time 4731934704 ps
CPU time 335.87 seconds
Started Jun 29 05:22:47 PM PDT 24
Finished Jun 29 05:28:24 PM PDT 24
Peak memory 271060 kb
Host smart-2b6ad210-633b-427d-8baa-38161a7617d3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190950490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2190950490
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1857563450
Short name T757
Test name
Test status
Simulation time 66369696 ps
CPU time 8.88 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:22:58 PM PDT 24
Peak memory 248608 kb
Host smart-02d6f7fe-a2e5-4327-a01d-9b0dffba812a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1857563450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1857563450
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1055039878
Short name T710
Test name
Test status
Simulation time 142382765 ps
CPU time 5.8 seconds
Started Jun 29 05:22:47 PM PDT 24
Finished Jun 29 05:22:53 PM PDT 24
Peak memory 239664 kb
Host smart-49a9e5cb-2245-4c66-9678-712aa17cec78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055039878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1055039878
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.895575304
Short name T816
Test name
Test status
Simulation time 227054771 ps
CPU time 8.51 seconds
Started Jun 29 05:22:50 PM PDT 24
Finished Jun 29 05:23:00 PM PDT 24
Peak memory 236648 kb
Host smart-968d5ba5-d2d5-4d4a-8373-f41db87edda6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=895575304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.895575304
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1028887067
Short name T788
Test name
Test status
Simulation time 9898588 ps
CPU time 1.41 seconds
Started Jun 29 05:22:42 PM PDT 24
Finished Jun 29 05:22:44 PM PDT 24
Peak memory 237608 kb
Host smart-d5166479-b0b1-48ca-a019-ca0c974adcdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1028887067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1028887067
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2200652648
Short name T806
Test name
Test status
Simulation time 419868029 ps
CPU time 12.82 seconds
Started Jun 29 05:22:45 PM PDT 24
Finished Jun 29 05:22:59 PM PDT 24
Peak memory 248744 kb
Host smart-006c039d-02fc-4553-be1f-34017b3be9a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2200652648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2200652648
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3880369946
Short name T167
Test name
Test status
Simulation time 3033715294 ps
CPU time 173.68 seconds
Started Jun 29 05:22:39 PM PDT 24
Finished Jun 29 05:25:34 PM PDT 24
Peak memory 265524 kb
Host smart-c146e3b0-b70c-4dd2-97b6-b6e957499351
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3880369946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3880369946
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.6621988
Short name T148
Test name
Test status
Simulation time 2178458227 ps
CPU time 360.81 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:28:52 PM PDT 24
Peak memory 265424 kb
Host smart-32137a0b-ae90-464a-b713-11f28f9e6c19
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6621988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_shadow_reg_errors_with_csr_rw.6621988
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3764462896
Short name T714
Test name
Test status
Simulation time 73188391 ps
CPU time 10.65 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:23:02 PM PDT 24
Peak memory 249836 kb
Host smart-6e9db245-85b9-49bc-9491-914182a305db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3764462896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3764462896
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.451631966
Short name T761
Test name
Test status
Simulation time 387685084 ps
CPU time 14.38 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:23:05 PM PDT 24
Peak memory 255272 kb
Host smart-796b5ec2-3864-40ee-af44-c26192685143
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451631966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.451631966
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2546844593
Short name T741
Test name
Test status
Simulation time 261053328 ps
CPU time 5.48 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:22:55 PM PDT 24
Peak memory 240552 kb
Host smart-61c67d13-1ad0-46e4-b14c-1c33c3d00394
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2546844593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2546844593
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1458080994
Short name T715
Test name
Test status
Simulation time 10663544 ps
CPU time 1.61 seconds
Started Jun 29 05:22:44 PM PDT 24
Finished Jun 29 05:22:46 PM PDT 24
Peak memory 237512 kb
Host smart-eadccf2e-4501-458d-a5ce-aa341f47e3cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1458080994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1458080994
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2822763594
Short name T805
Test name
Test status
Simulation time 1000480076 ps
CPU time 19.13 seconds
Started Jun 29 05:22:45 PM PDT 24
Finished Jun 29 05:23:05 PM PDT 24
Peak memory 245800 kb
Host smart-37feac4c-c018-4dcd-8eb2-c334ab8ce987
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2822763594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2822763594
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4027884700
Short name T144
Test name
Test status
Simulation time 10012588803 ps
CPU time 158.44 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:25:32 PM PDT 24
Peak memory 265680 kb
Host smart-8edec427-dea1-4d26-9ead-9f48cbc90959
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4027884700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.4027884700
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3733802409
Short name T705
Test name
Test status
Simulation time 169784101 ps
CPU time 12.37 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:23:02 PM PDT 24
Peak memory 248716 kb
Host smart-d23f06db-8aab-4bb4-bb22-80201e16fbab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3733802409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3733802409
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.701802969
Short name T188
Test name
Test status
Simulation time 265272474 ps
CPU time 10.65 seconds
Started Jun 29 05:22:43 PM PDT 24
Finished Jun 29 05:22:55 PM PDT 24
Peak memory 256708 kb
Host smart-11dab415-48dd-473a-9fdc-d72d2c94bffa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701802969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.701802969
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3245354999
Short name T799
Test name
Test status
Simulation time 127047799 ps
CPU time 9.12 seconds
Started Jun 29 05:22:45 PM PDT 24
Finished Jun 29 05:22:55 PM PDT 24
Peak memory 240412 kb
Host smart-72c45691-8dff-4fe6-8661-0ecffd404ff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3245354999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3245354999
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1990292245
Short name T739
Test name
Test status
Simulation time 6798108 ps
CPU time 1.46 seconds
Started Jun 29 05:22:47 PM PDT 24
Finished Jun 29 05:22:50 PM PDT 24
Peak memory 236668 kb
Host smart-bee3ebdf-bfc9-4598-a111-e5d15c144f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1990292245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1990292245
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.343812762
Short name T771
Test name
Test status
Simulation time 882537186 ps
CPU time 10.68 seconds
Started Jun 29 05:22:41 PM PDT 24
Finished Jun 29 05:22:52 PM PDT 24
Peak memory 244844 kb
Host smart-67a68cac-ee37-4f1d-b306-502be77e4b1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=343812762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.343812762
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2921372766
Short name T724
Test name
Test status
Simulation time 306544853 ps
CPU time 12.09 seconds
Started Jun 29 05:22:44 PM PDT 24
Finished Jun 29 05:22:57 PM PDT 24
Peak memory 249836 kb
Host smart-7d9134ae-94fe-449c-bdec-aa4dacd61588
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2921372766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2921372766
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3466069314
Short name T802
Test name
Test status
Simulation time 519184708 ps
CPU time 5.46 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:22:56 PM PDT 24
Peak memory 239952 kb
Host smart-353ddc83-16ba-4974-8f7f-521b5dabd61d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466069314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3466069314
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2565444196
Short name T807
Test name
Test status
Simulation time 1320726656 ps
CPU time 8.75 seconds
Started Jun 29 05:22:45 PM PDT 24
Finished Jun 29 05:22:54 PM PDT 24
Peak memory 236628 kb
Host smart-18d616b5-080c-46d9-8e45-e768a783e99f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2565444196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2565444196
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2128256281
Short name T345
Test name
Test status
Simulation time 16614028 ps
CPU time 1.28 seconds
Started Jun 29 05:22:47 PM PDT 24
Finished Jun 29 05:22:49 PM PDT 24
Peak memory 235616 kb
Host smart-8214e840-4785-4674-839d-22680786e3c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2128256281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2128256281
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1795482618
Short name T795
Test name
Test status
Simulation time 163454030 ps
CPU time 14.23 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:23:05 PM PDT 24
Peak memory 245800 kb
Host smart-5b3423a1-b7a0-4231-947b-fb2291910c04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1795482618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1795482618
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3021182023
Short name T146
Test name
Test status
Simulation time 1958328233 ps
CPU time 98.83 seconds
Started Jun 29 05:22:47 PM PDT 24
Finished Jun 29 05:24:27 PM PDT 24
Peak memory 265400 kb
Host smart-9906b243-b637-40c1-8811-ba01b3cd8887
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3021182023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3021182023
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.799764525
Short name T772
Test name
Test status
Simulation time 49743547 ps
CPU time 6.22 seconds
Started Jun 29 05:22:45 PM PDT 24
Finished Jun 29 05:22:52 PM PDT 24
Peak memory 248812 kb
Host smart-908bb3ae-b421-414d-80ab-3a65aeee3127
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=799764525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.799764525
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3936425736
Short name T809
Test name
Test status
Simulation time 336917197 ps
CPU time 6.55 seconds
Started Jun 29 05:22:46 PM PDT 24
Finished Jun 29 05:22:53 PM PDT 24
Peak memory 239604 kb
Host smart-60af7e9b-129e-4dfa-b97a-154518235be8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936425736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3936425736
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1171846757
Short name T199
Test name
Test status
Simulation time 100144418 ps
CPU time 8.39 seconds
Started Jun 29 05:22:45 PM PDT 24
Finished Jun 29 05:22:55 PM PDT 24
Peak memory 237600 kb
Host smart-ce950317-07b8-4a1d-af68-2e78d0900a47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1171846757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1171846757
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.736500314
Short name T742
Test name
Test status
Simulation time 20565553 ps
CPU time 1.45 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:22:52 PM PDT 24
Peak memory 236628 kb
Host smart-44bfeac7-a5ba-4347-a77b-c048dcd85214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=736500314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.736500314
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2065234127
Short name T796
Test name
Test status
Simulation time 2162997974 ps
CPU time 20.65 seconds
Started Jun 29 05:22:45 PM PDT 24
Finished Jun 29 05:23:07 PM PDT 24
Peak memory 244912 kb
Host smart-841a6996-7184-4e1d-80dc-a0bb31a22fb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2065234127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2065234127
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2342643921
Short name T162
Test name
Test status
Simulation time 15813623716 ps
CPU time 302.85 seconds
Started Jun 29 05:22:42 PM PDT 24
Finished Jun 29 05:27:46 PM PDT 24
Peak memory 272760 kb
Host smart-2d35580d-d968-40ee-8272-ac08a46da83d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2342643921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2342643921
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3648916339
Short name T797
Test name
Test status
Simulation time 187589296 ps
CPU time 12.41 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:23:03 PM PDT 24
Peak memory 248740 kb
Host smart-1d570432-9f21-4349-aaf2-b68832890d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3648916339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3648916339
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3307438789
Short name T774
Test name
Test status
Simulation time 4756172663 ps
CPU time 145.7 seconds
Started Jun 29 05:22:18 PM PDT 24
Finished Jun 29 05:24:44 PM PDT 24
Peak memory 240612 kb
Host smart-f7fa11a3-420e-4c86-84c7-734a9a13f0b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3307438789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3307438789
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3881948173
Short name T811
Test name
Test status
Simulation time 34126710199 ps
CPU time 521.52 seconds
Started Jun 29 05:22:15 PM PDT 24
Finished Jun 29 05:30:57 PM PDT 24
Peak memory 237644 kb
Host smart-ed7b2630-5ad4-457b-bfd4-5b5b0e1f4e70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3881948173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3881948173
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.119344378
Short name T720
Test name
Test status
Simulation time 140429597 ps
CPU time 12.02 seconds
Started Jun 29 05:22:30 PM PDT 24
Finished Jun 29 05:22:43 PM PDT 24
Peak memory 249072 kb
Host smart-ceacdb84-10bd-4dc4-b603-da384a5c1bdb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=119344378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.119344378
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3047780450
Short name T768
Test name
Test status
Simulation time 77026813 ps
CPU time 7.13 seconds
Started Jun 29 05:22:25 PM PDT 24
Finished Jun 29 05:22:33 PM PDT 24
Peak memory 240572 kb
Host smart-6c3c9019-9d1c-4f47-bfcf-7a5458b2c004
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047780450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3047780450
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1089365086
Short name T713
Test name
Test status
Simulation time 98034968 ps
CPU time 8.36 seconds
Started Jun 29 05:22:17 PM PDT 24
Finished Jun 29 05:22:25 PM PDT 24
Peak memory 237600 kb
Host smart-c36e347e-92bb-49a9-8f11-d314e4f6035b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1089365086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1089365086
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.135934702
Short name T749
Test name
Test status
Simulation time 8053098 ps
CPU time 1.47 seconds
Started Jun 29 05:22:24 PM PDT 24
Finished Jun 29 05:22:26 PM PDT 24
Peak memory 236632 kb
Host smart-fc5cd8e0-d4bb-4e3f-8e20-c1b74386dc11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=135934702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.135934702
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3250126464
Short name T760
Test name
Test status
Simulation time 321130112 ps
CPU time 11.88 seconds
Started Jun 29 05:22:23 PM PDT 24
Finished Jun 29 05:22:35 PM PDT 24
Peak memory 240524 kb
Host smart-d24c6763-93a0-447f-ba8a-b64f334f6544
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3250126464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3250126464
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1457344332
Short name T800
Test name
Test status
Simulation time 3213386629 ps
CPU time 112.19 seconds
Started Jun 29 05:22:21 PM PDT 24
Finished Jun 29 05:24:14 PM PDT 24
Peak memory 265472 kb
Host smart-37635f7e-23cc-4cad-8fea-3571cb75f342
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1457344332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1457344332
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1129469504
Short name T744
Test name
Test status
Simulation time 654852689 ps
CPU time 5.02 seconds
Started Jun 29 05:22:25 PM PDT 24
Finished Jun 29 05:22:31 PM PDT 24
Peak memory 247908 kb
Host smart-7dd4a84a-ff50-4801-abad-add587481e93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1129469504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1129469504
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3990234354
Short name T740
Test name
Test status
Simulation time 19704657 ps
CPU time 1.5 seconds
Started Jun 29 05:22:39 PM PDT 24
Finished Jun 29 05:22:42 PM PDT 24
Peak memory 237612 kb
Host smart-c5f9f4a3-2837-460f-bb9d-f3bcf2705a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3990234354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3990234354
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2504319277
Short name T716
Test name
Test status
Simulation time 9110135 ps
CPU time 1.46 seconds
Started Jun 29 05:22:44 PM PDT 24
Finished Jun 29 05:22:47 PM PDT 24
Peak memory 237600 kb
Host smart-d2cda002-df7e-42b5-8440-4ba066261adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2504319277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2504319277
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.441209557
Short name T725
Test name
Test status
Simulation time 7838674 ps
CPU time 1.33 seconds
Started Jun 29 05:22:50 PM PDT 24
Finished Jun 29 05:22:53 PM PDT 24
Peak memory 237608 kb
Host smart-810039e7-c033-454c-b3cd-2abca3f9c437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=441209557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.441209557
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3833169312
Short name T764
Test name
Test status
Simulation time 11788091 ps
CPU time 1.36 seconds
Started Jun 29 05:22:50 PM PDT 24
Finished Jun 29 05:22:53 PM PDT 24
Peak memory 236700 kb
Host smart-a2fe0954-1243-4d27-a0d4-f2573f06715a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3833169312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3833169312
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.135378695
Short name T174
Test name
Test status
Simulation time 62533850 ps
CPU time 1.35 seconds
Started Jun 29 05:22:47 PM PDT 24
Finished Jun 29 05:22:49 PM PDT 24
Peak memory 237436 kb
Host smart-6de1d73a-1780-4a11-a06f-4f07e1c4ec20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=135378695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.135378695
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3578343862
Short name T347
Test name
Test status
Simulation time 7547057 ps
CPU time 1.47 seconds
Started Jun 29 05:22:50 PM PDT 24
Finished Jun 29 05:22:53 PM PDT 24
Peak memory 237500 kb
Host smart-156d7319-b318-4f40-914a-0a0c9b266e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3578343862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3578343862
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3074151525
Short name T230
Test name
Test status
Simulation time 17031354 ps
CPU time 1.39 seconds
Started Jun 29 05:22:50 PM PDT 24
Finished Jun 29 05:22:53 PM PDT 24
Peak memory 236632 kb
Host smart-30d9416a-978f-4f83-9abb-15b7b994a5b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3074151525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3074151525
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3964767761
Short name T778
Test name
Test status
Simulation time 13676195 ps
CPU time 1.69 seconds
Started Jun 29 05:22:43 PM PDT 24
Finished Jun 29 05:22:46 PM PDT 24
Peak memory 235800 kb
Host smart-d7ebeb26-ae22-420f-9698-65f3c2b450fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3964767761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3964767761
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1090372354
Short name T753
Test name
Test status
Simulation time 13455064 ps
CPU time 1.45 seconds
Started Jun 29 05:22:39 PM PDT 24
Finished Jun 29 05:22:42 PM PDT 24
Peak memory 235648 kb
Host smart-98997024-38a8-40fa-8cfc-a5b4d834b6a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1090372354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1090372354
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1214877038
Short name T765
Test name
Test status
Simulation time 15288611 ps
CPU time 1.38 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:22:52 PM PDT 24
Peak memory 235660 kb
Host smart-50d53b4e-4a6b-40ad-a8b3-7901552108aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1214877038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1214877038
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3679112611
Short name T787
Test name
Test status
Simulation time 7712099116 ps
CPU time 118.96 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:24:27 PM PDT 24
Peak memory 240612 kb
Host smart-750b9221-a230-4265-af2b-1d834ad7254c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3679112611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3679112611
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3907992681
Short name T736
Test name
Test status
Simulation time 15884589722 ps
CPU time 200.08 seconds
Started Jun 29 05:22:26 PM PDT 24
Finished Jun 29 05:25:47 PM PDT 24
Peak memory 237524 kb
Host smart-3fa45daa-9af1-439d-b44f-ca60230b5bfd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3907992681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3907992681
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2409592538
Short name T738
Test name
Test status
Simulation time 73727536 ps
CPU time 6.63 seconds
Started Jun 29 05:22:25 PM PDT 24
Finished Jun 29 05:22:33 PM PDT 24
Peak memory 248756 kb
Host smart-35a87bb5-95d1-491c-a4ad-b5d890e37b43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2409592538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2409592538
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1636256043
Short name T813
Test name
Test status
Simulation time 28647298 ps
CPU time 5.26 seconds
Started Jun 29 05:22:24 PM PDT 24
Finished Jun 29 05:22:29 PM PDT 24
Peak memory 240600 kb
Host smart-15a58bc5-f6c0-4f9c-a5f8-1b1956634de4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636256043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1636256043
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1489572216
Short name T708
Test name
Test status
Simulation time 66904802 ps
CPU time 3.9 seconds
Started Jun 29 05:22:25 PM PDT 24
Finished Jun 29 05:22:30 PM PDT 24
Peak memory 240504 kb
Host smart-8e327a9d-89e9-4098-a853-a005c213c339
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1489572216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1489572216
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.475511867
Short name T701
Test name
Test status
Simulation time 21565837 ps
CPU time 1.44 seconds
Started Jun 29 05:22:24 PM PDT 24
Finished Jun 29 05:22:26 PM PDT 24
Peak memory 236664 kb
Host smart-86f9a120-52b7-47ac-91aa-7517ffff12b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=475511867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.475511867
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.4261204611
Short name T794
Test name
Test status
Simulation time 266128146 ps
CPU time 17.77 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:22:47 PM PDT 24
Peak memory 244860 kb
Host smart-428a6887-77ab-4479-9f92-ac13dd49b916
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4261204611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.4261204611
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4098258759
Short name T161
Test name
Test status
Simulation time 25679500474 ps
CPU time 507.49 seconds
Started Jun 29 05:22:24 PM PDT 24
Finished Jun 29 05:30:52 PM PDT 24
Peak memory 265328 kb
Host smart-ba366388-295a-4bbf-a041-f0e804a1bee2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098258759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.4098258759
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3388145738
Short name T746
Test name
Test status
Simulation time 952006193 ps
CPU time 16.54 seconds
Started Jun 29 05:22:24 PM PDT 24
Finished Jun 29 05:22:42 PM PDT 24
Peak memory 248760 kb
Host smart-b428d5b4-93c4-48a9-b381-b6b11991cfad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3388145738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3388145738
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3205583177
Short name T745
Test name
Test status
Simulation time 19177746 ps
CPU time 1.39 seconds
Started Jun 29 05:22:50 PM PDT 24
Finished Jun 29 05:22:53 PM PDT 24
Peak memory 237588 kb
Host smart-78b4f9e1-c550-4ea5-9efa-498764f632e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3205583177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3205583177
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2353863229
Short name T775
Test name
Test status
Simulation time 9949989 ps
CPU time 1.39 seconds
Started Jun 29 05:22:52 PM PDT 24
Finished Jun 29 05:22:54 PM PDT 24
Peak memory 235620 kb
Host smart-15eb5feb-c0a3-46f3-9cfb-06f5768f561f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2353863229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2353863229
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1120819630
Short name T815
Test name
Test status
Simulation time 7334532 ps
CPU time 1.35 seconds
Started Jun 29 05:22:54 PM PDT 24
Finished Jun 29 05:22:56 PM PDT 24
Peak memory 237612 kb
Host smart-8903dd56-7717-4b0f-ad20-900beb3f5bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1120819630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1120819630
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1809365458
Short name T703
Test name
Test status
Simulation time 7042284 ps
CPU time 1.5 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:22:52 PM PDT 24
Peak memory 237620 kb
Host smart-45b52188-7be1-4eec-9dc6-6bf2639d5497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1809365458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1809365458
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.422940987
Short name T709
Test name
Test status
Simulation time 8335677 ps
CPU time 1.55 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:22:52 PM PDT 24
Peak memory 237608 kb
Host smart-6be0a7e7-87a9-4f38-9684-3ea63dee3ca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=422940987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.422940987
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3234957261
Short name T349
Test name
Test status
Simulation time 15492828 ps
CPU time 1.24 seconds
Started Jun 29 05:22:57 PM PDT 24
Finished Jun 29 05:22:59 PM PDT 24
Peak memory 237612 kb
Host smart-d13deda9-62ae-4d40-88bd-47fcf408d835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3234957261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3234957261
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1874824397
Short name T727
Test name
Test status
Simulation time 7431741 ps
CPU time 1.51 seconds
Started Jun 29 05:22:57 PM PDT 24
Finished Jun 29 05:23:00 PM PDT 24
Peak memory 235640 kb
Host smart-252f6479-4ed9-4769-8657-f56c5f816c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1874824397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1874824397
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2519289657
Short name T786
Test name
Test status
Simulation time 27562652 ps
CPU time 1.58 seconds
Started Jun 29 05:22:45 PM PDT 24
Finished Jun 29 05:22:48 PM PDT 24
Peak memory 237564 kb
Host smart-104e0e9e-482b-407c-bb1e-c2a26b7c6b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2519289657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2519289657
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2579787549
Short name T704
Test name
Test status
Simulation time 8327084 ps
CPU time 1.46 seconds
Started Jun 29 05:22:59 PM PDT 24
Finished Jun 29 05:23:02 PM PDT 24
Peak memory 236660 kb
Host smart-8f698aa4-7df1-4078-b77d-a97aaa73925b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2579787549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2579787549
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.981009715
Short name T203
Test name
Test status
Simulation time 5574195811 ps
CPU time 156.52 seconds
Started Jun 29 05:22:27 PM PDT 24
Finished Jun 29 05:25:04 PM PDT 24
Peak memory 240616 kb
Host smart-8fd5a8ff-a84f-4474-b9e0-519064e9150a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=981009715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.981009715
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3441944384
Short name T187
Test name
Test status
Simulation time 21890314717 ps
CPU time 197.33 seconds
Started Jun 29 05:22:25 PM PDT 24
Finished Jun 29 05:25:43 PM PDT 24
Peak memory 237636 kb
Host smart-d7974bd6-e56c-47be-8356-ee297d32a53a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3441944384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3441944384
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3920075988
Short name T700
Test name
Test status
Simulation time 104353263 ps
CPU time 8.47 seconds
Started Jun 29 05:22:29 PM PDT 24
Finished Jun 29 05:22:38 PM PDT 24
Peak memory 248760 kb
Host smart-077a14ce-6970-4352-88e3-95620c61dbbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3920075988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3920075988
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3732132085
Short name T730
Test name
Test status
Simulation time 126052640 ps
CPU time 10.82 seconds
Started Jun 29 05:22:24 PM PDT 24
Finished Jun 29 05:22:36 PM PDT 24
Peak memory 256680 kb
Host smart-9f99f3f8-3632-4cae-9efc-2d9b4734329b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732132085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3732132085
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.835447473
Short name T718
Test name
Test status
Simulation time 64633060 ps
CPU time 3.69 seconds
Started Jun 29 05:22:30 PM PDT 24
Finished Jun 29 05:22:34 PM PDT 24
Peak memory 237564 kb
Host smart-4750e0c7-07d2-4171-8c67-bab40e1fe43c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=835447473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.835447473
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3284004634
Short name T790
Test name
Test status
Simulation time 16257691 ps
CPU time 1.62 seconds
Started Jun 29 05:22:26 PM PDT 24
Finished Jun 29 05:22:28 PM PDT 24
Peak memory 236652 kb
Host smart-58009e6a-ca57-43f6-9e18-882e81251e5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3284004634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3284004634
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.905171698
Short name T719
Test name
Test status
Simulation time 511924518 ps
CPU time 33.27 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:23:03 PM PDT 24
Peak memory 245792 kb
Host smart-cd8e4cf4-f493-4859-b6bf-648345508fa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=905171698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.905171698
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3364863560
Short name T160
Test name
Test status
Simulation time 6033367327 ps
CPU time 441.74 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:29:51 PM PDT 24
Peak memory 265204 kb
Host smart-32191a0e-4aed-4b50-826c-a97f4b9aa301
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364863560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3364863560
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1304145859
Short name T702
Test name
Test status
Simulation time 68110416 ps
CPU time 5.14 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:22:35 PM PDT 24
Peak memory 248676 kb
Host smart-28a84084-a042-46da-9956-b49ab713b043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1304145859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1304145859
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1413433473
Short name T723
Test name
Test status
Simulation time 19084624 ps
CPU time 1.37 seconds
Started Jun 29 05:22:52 PM PDT 24
Finished Jun 29 05:22:54 PM PDT 24
Peak memory 237536 kb
Host smart-e3385839-1edb-4a75-8b82-2ab4a6cec722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1413433473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1413433473
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.446886989
Short name T766
Test name
Test status
Simulation time 6409682 ps
CPU time 1.45 seconds
Started Jun 29 05:22:55 PM PDT 24
Finished Jun 29 05:22:57 PM PDT 24
Peak memory 235608 kb
Host smart-b1ac2fe6-a0c2-4735-9b97-5bdb02fe7141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=446886989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.446886989
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2025002622
Short name T752
Test name
Test status
Simulation time 25112791 ps
CPU time 1.48 seconds
Started Jun 29 05:22:49 PM PDT 24
Finished Jun 29 05:22:53 PM PDT 24
Peak memory 236668 kb
Host smart-cabc38ea-74f4-403d-800e-d45aede2e5f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2025002622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2025002622
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3987295512
Short name T748
Test name
Test status
Simulation time 7488632 ps
CPU time 1.35 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:22:55 PM PDT 24
Peak memory 236664 kb
Host smart-d3c389e8-930c-43e6-9a88-e0d4b0cd6001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3987295512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3987295512
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1662453001
Short name T776
Test name
Test status
Simulation time 10909131 ps
CPU time 1.33 seconds
Started Jun 29 05:22:53 PM PDT 24
Finished Jun 29 05:22:56 PM PDT 24
Peak memory 237460 kb
Host smart-69aefb54-2736-4917-854b-6d8b540229f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1662453001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1662453001
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2992008721
Short name T343
Test name
Test status
Simulation time 14995400 ps
CPU time 1.32 seconds
Started Jun 29 05:22:52 PM PDT 24
Finished Jun 29 05:22:54 PM PDT 24
Peak memory 235644 kb
Host smart-0e949096-1d87-4a25-a5b5-b445c98d929e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2992008721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2992008721
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2570308676
Short name T733
Test name
Test status
Simulation time 20824936 ps
CPU time 1.23 seconds
Started Jun 29 05:22:50 PM PDT 24
Finished Jun 29 05:22:53 PM PDT 24
Peak memory 236436 kb
Host smart-407d690b-4d5b-4b92-a6c8-98ca80cce1fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2570308676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2570308676
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2606833315
Short name T346
Test name
Test status
Simulation time 13010818 ps
CPU time 1.44 seconds
Started Jun 29 05:22:46 PM PDT 24
Finished Jun 29 05:22:48 PM PDT 24
Peak memory 237612 kb
Host smart-921e7c93-0033-437b-a6cb-920de5afec86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2606833315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2606833315
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1751388753
Short name T750
Test name
Test status
Simulation time 16216194 ps
CPU time 1.38 seconds
Started Jun 29 05:22:46 PM PDT 24
Finished Jun 29 05:22:49 PM PDT 24
Peak memory 237580 kb
Host smart-1022045a-1c87-4ef5-bcac-1e470b6cdb43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1751388753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1751388753
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1542129707
Short name T726
Test name
Test status
Simulation time 9982216 ps
CPU time 1.44 seconds
Started Jun 29 05:22:48 PM PDT 24
Finished Jun 29 05:22:51 PM PDT 24
Peak memory 236668 kb
Host smart-41b5709e-878b-48f3-a601-065b9749e695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1542129707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1542129707
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4189421640
Short name T756
Test name
Test status
Simulation time 45940145 ps
CPU time 6.08 seconds
Started Jun 29 05:22:22 PM PDT 24
Finished Jun 29 05:22:28 PM PDT 24
Peak memory 256980 kb
Host smart-cb44c64c-4848-4a65-bc10-be239463b313
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189421640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.4189421640
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1406992396
Short name T200
Test name
Test status
Simulation time 35588289 ps
CPU time 5.12 seconds
Started Jun 29 05:22:25 PM PDT 24
Finished Jun 29 05:22:31 PM PDT 24
Peak memory 240548 kb
Host smart-bcac3fc1-d1c1-4806-9f37-bc86bec2d943
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1406992396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1406992396
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2186801966
Short name T783
Test name
Test status
Simulation time 8877529 ps
CPU time 1.62 seconds
Started Jun 29 05:22:26 PM PDT 24
Finished Jun 29 05:22:29 PM PDT 24
Peak memory 237612 kb
Host smart-f0b5bddf-97ba-48a5-abeb-e845191d92da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2186801966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2186801966
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1938572168
Short name T707
Test name
Test status
Simulation time 2051884634 ps
CPU time 46.98 seconds
Started Jun 29 05:22:29 PM PDT 24
Finished Jun 29 05:23:17 PM PDT 24
Peak memory 245812 kb
Host smart-fbb45ee0-02d4-4135-b247-dc355f52ea54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1938572168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1938572168
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1250974448
Short name T136
Test name
Test status
Simulation time 61361901380 ps
CPU time 492.8 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:30:41 PM PDT 24
Peak memory 265320 kb
Host smart-6c29d602-4336-4936-bb49-3809bb1b5bb8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250974448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1250974448
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2247619638
Short name T717
Test name
Test status
Simulation time 1191114009 ps
CPU time 22.54 seconds
Started Jun 29 05:22:27 PM PDT 24
Finished Jun 29 05:22:50 PM PDT 24
Peak memory 248968 kb
Host smart-d987736b-e9a2-41cf-8b2a-029baf30ae09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2247619638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2247619638
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.780963214
Short name T747
Test name
Test status
Simulation time 100153217 ps
CPU time 8.71 seconds
Started Jun 29 05:22:26 PM PDT 24
Finished Jun 29 05:22:35 PM PDT 24
Peak memory 256956 kb
Host smart-23c52cac-392e-4481-83fd-63c97a484098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780963214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.alert_handler_csr_mem_rw_with_rand_reset.780963214
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3984060386
Short name T711
Test name
Test status
Simulation time 80760722 ps
CPU time 6.01 seconds
Started Jun 29 05:22:32 PM PDT 24
Finished Jun 29 05:22:39 PM PDT 24
Peak memory 240484 kb
Host smart-a4e5816c-c7f4-4ae4-ab6d-0d6bcd661ede
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3984060386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3984060386
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.972061296
Short name T737
Test name
Test status
Simulation time 19666449 ps
CPU time 1.39 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:22:30 PM PDT 24
Peak memory 237608 kb
Host smart-faabc41f-f12d-4cef-89a6-3a459788f071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=972061296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.972061296
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1319824
Short name T202
Test name
Test status
Simulation time 331717085 ps
CPU time 21.1 seconds
Started Jun 29 05:22:27 PM PDT 24
Finished Jun 29 05:22:49 PM PDT 24
Peak memory 245764 kb
Host smart-88b028ce-b335-44e4-b4be-abbd1957345a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1319824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outsta
nding.1319824
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3057994070
Short name T154
Test name
Test status
Simulation time 9791316507 ps
CPU time 179.94 seconds
Started Jun 29 05:22:25 PM PDT 24
Finished Jun 29 05:25:26 PM PDT 24
Peak memory 265468 kb
Host smart-9fb05e0c-0bf2-4f86-b519-f2eb75bb87aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3057994070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3057994070
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.990976944
Short name T770
Test name
Test status
Simulation time 1655449026 ps
CPU time 28.58 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:22:57 PM PDT 24
Peak memory 255404 kb
Host smart-a474e645-0bb0-4f97-b012-807d9fb0768f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=990976944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.990976944
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2745560928
Short name T751
Test name
Test status
Simulation time 285878033 ps
CPU time 5.21 seconds
Started Jun 29 05:22:26 PM PDT 24
Finished Jun 29 05:22:32 PM PDT 24
Peak memory 256956 kb
Host smart-6bf557a2-94d1-4cf7-8288-bd45df03400a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745560928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2745560928
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3931822944
Short name T201
Test name
Test status
Simulation time 33247792 ps
CPU time 4.94 seconds
Started Jun 29 05:22:25 PM PDT 24
Finished Jun 29 05:22:30 PM PDT 24
Peak memory 237504 kb
Host smart-e226dd5b-9585-4ad3-a0da-43c0cf414545
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3931822944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3931822944
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2252991428
Short name T793
Test name
Test status
Simulation time 25997338 ps
CPU time 1.32 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:22:30 PM PDT 24
Peak memory 236508 kb
Host smart-c149a93d-176c-4c44-9413-fe20848a3b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2252991428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2252991428
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1352190457
Short name T785
Test name
Test status
Simulation time 1039868995 ps
CPU time 40.36 seconds
Started Jun 29 05:22:31 PM PDT 24
Finished Jun 29 05:23:12 PM PDT 24
Peak memory 245808 kb
Host smart-679ec2dc-8bed-4bc6-a436-3aea578dbaa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1352190457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1352190457
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.905764932
Short name T137
Test name
Test status
Simulation time 8177733181 ps
CPU time 143.04 seconds
Started Jun 29 05:22:37 PM PDT 24
Finished Jun 29 05:25:01 PM PDT 24
Peak memory 265468 kb
Host smart-e86def13-efb2-4577-b53a-cfbd371b8dbf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=905764932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.905764932
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2100633501
Short name T169
Test name
Test status
Simulation time 100574769479 ps
CPU time 587.74 seconds
Started Jun 29 05:22:22 PM PDT 24
Finished Jun 29 05:32:10 PM PDT 24
Peak memory 270272 kb
Host smart-d9d70b96-3606-42cc-9c8a-84dc411ac898
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100633501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2100633501
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1603673799
Short name T803
Test name
Test status
Simulation time 369920825 ps
CPU time 23 seconds
Started Jun 29 05:22:29 PM PDT 24
Finished Jun 29 05:22:53 PM PDT 24
Peak memory 256068 kb
Host smart-830892cf-9624-48e9-89f4-861f53cbf6c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1603673799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1603673799
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3909594655
Short name T234
Test name
Test status
Simulation time 129850907 ps
CPU time 10.23 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:22:39 PM PDT 24
Peak memory 237948 kb
Host smart-439c5b4a-72bd-4bfa-ac58-ea4bc9072882
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909594655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3909594655
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3474483869
Short name T789
Test name
Test status
Simulation time 127852138 ps
CPU time 3.41 seconds
Started Jun 29 05:22:23 PM PDT 24
Finished Jun 29 05:22:26 PM PDT 24
Peak memory 237464 kb
Host smart-56e98313-5e3d-4eab-a7c8-cb7ac95d7687
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3474483869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3474483869
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2575604149
Short name T732
Test name
Test status
Simulation time 8035973 ps
CPU time 1.36 seconds
Started Jun 29 05:22:29 PM PDT 24
Finished Jun 29 05:22:31 PM PDT 24
Peak memory 237612 kb
Host smart-21af65e2-9e00-432c-bce4-a5b9bf9c7f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2575604149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2575604149
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2829680783
Short name T767
Test name
Test status
Simulation time 200412170 ps
CPU time 27.71 seconds
Started Jun 29 05:22:25 PM PDT 24
Finished Jun 29 05:22:54 PM PDT 24
Peak memory 245812 kb
Host smart-06e857f2-f533-45d4-905f-9502b16cd48b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2829680783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2829680783
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3610442572
Short name T150
Test name
Test status
Simulation time 24679073365 ps
CPU time 461.19 seconds
Started Jun 29 05:22:28 PM PDT 24
Finished Jun 29 05:30:10 PM PDT 24
Peak memory 269944 kb
Host smart-c84a84fc-9253-4b5c-8a28-5d342fdc3476
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610442572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3610442572
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3427070601
Short name T791
Test name
Test status
Simulation time 577540488 ps
CPU time 13.21 seconds
Started Jun 29 05:22:25 PM PDT 24
Finished Jun 29 05:22:39 PM PDT 24
Peak memory 253104 kb
Host smart-d15c39c4-03ee-42c3-bbe0-80b31dceedd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3427070601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3427070601
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.4072827657
Short name T731
Test name
Test status
Simulation time 113799958 ps
CPU time 9.89 seconds
Started Jun 29 05:22:43 PM PDT 24
Finished Jun 29 05:22:54 PM PDT 24
Peak memory 252704 kb
Host smart-b07855f9-901f-4f0c-98a5-0083c0127858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072827657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.4072827657
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.4105098992
Short name T743
Test name
Test status
Simulation time 294872540 ps
CPU time 5.59 seconds
Started Jun 29 05:22:40 PM PDT 24
Finished Jun 29 05:22:46 PM PDT 24
Peak memory 237608 kb
Host smart-42c48787-8a7d-49eb-9550-95247cf71170
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4105098992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.4105098992
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3192113807
Short name T348
Test name
Test status
Simulation time 15030003 ps
CPU time 1.32 seconds
Started Jun 29 05:22:41 PM PDT 24
Finished Jun 29 05:22:43 PM PDT 24
Peak memory 236668 kb
Host smart-9b4e221e-939e-4575-9c06-1fb70715fe82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3192113807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3192113807
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1764205110
Short name T762
Test name
Test status
Simulation time 651322201 ps
CPU time 49.04 seconds
Started Jun 29 05:22:37 PM PDT 24
Finished Jun 29 05:23:26 PM PDT 24
Peak memory 245716 kb
Host smart-c58df6b7-69a6-4020-bad0-a53d9755c7cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1764205110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1764205110
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1924641003
Short name T164
Test name
Test status
Simulation time 18066804920 ps
CPU time 624.08 seconds
Started Jun 29 05:22:39 PM PDT 24
Finished Jun 29 05:33:03 PM PDT 24
Peak memory 273420 kb
Host smart-0f6f1c72-147d-42d6-8b6f-7af78c73b74d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924641003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1924641003
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.324378242
Short name T779
Test name
Test status
Simulation time 246439946 ps
CPU time 9.56 seconds
Started Jun 29 05:22:39 PM PDT 24
Finished Jun 29 05:22:49 PM PDT 24
Peak memory 247972 kb
Host smart-5b022c30-8004-4fee-b93f-028cd7123d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=324378242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.324378242
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.300793495
Short name T534
Test name
Test status
Simulation time 2213593400 ps
CPU time 18.2 seconds
Started Jun 29 05:51:39 PM PDT 24
Finished Jun 29 05:51:57 PM PDT 24
Peak memory 249408 kb
Host smart-97681ac2-bb60-47b6-ade1-2a72e6845544
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=300793495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.300793495
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.4017954704
Short name T226
Test name
Test status
Simulation time 74339653 ps
CPU time 5.25 seconds
Started Jun 29 05:51:39 PM PDT 24
Finished Jun 29 05:51:45 PM PDT 24
Peak memory 240548 kb
Host smart-757d830b-b891-4ba4-a09a-94ac51172a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40179
54704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.4017954704
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.4082539807
Short name T1
Test name
Test status
Simulation time 14764740146 ps
CPU time 730.56 seconds
Started Jun 29 05:51:44 PM PDT 24
Finished Jun 29 06:03:55 PM PDT 24
Peak memory 273952 kb
Host smart-252b82e2-86f8-4816-b391-9cfd2cfa3790
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082539807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.4082539807
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3563109193
Short name T525
Test name
Test status
Simulation time 6645611078 ps
CPU time 164.44 seconds
Started Jun 29 05:51:40 PM PDT 24
Finished Jun 29 05:54:25 PM PDT 24
Peak memory 249424 kb
Host smart-685d9175-3472-4d69-ace9-1def0f5c0de2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563109193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3563109193
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2666859673
Short name T669
Test name
Test status
Simulation time 265762836 ps
CPU time 10.19 seconds
Started Jun 29 05:51:40 PM PDT 24
Finished Jun 29 05:51:50 PM PDT 24
Peak memory 249312 kb
Host smart-eea6021d-60ef-47d3-821a-6849eda24d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26668
59673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2666859673
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1545065404
Short name T403
Test name
Test status
Simulation time 914086875 ps
CPU time 19.49 seconds
Started Jun 29 05:51:42 PM PDT 24
Finished Jun 29 05:52:01 PM PDT 24
Peak memory 248752 kb
Host smart-0c73c94e-4eab-4e7f-9aa6-d59a8bc97d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15450
65404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1545065404
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1338252897
Short name T11
Test name
Test status
Simulation time 845577335 ps
CPU time 14.82 seconds
Started Jun 29 05:51:45 PM PDT 24
Finished Jun 29 05:52:00 PM PDT 24
Peak memory 267552 kb
Host smart-61d2b1cb-b488-4814-b410-d1e540448090
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1338252897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1338252897
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.4086532808
Short name T478
Test name
Test status
Simulation time 500864242 ps
CPU time 28.07 seconds
Started Jun 29 05:51:45 PM PDT 24
Finished Jun 29 05:52:13 PM PDT 24
Peak memory 257000 kb
Host smart-9714ee63-b9d9-4b4b-8231-a8e4d525db86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40865
32808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.4086532808
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2847216538
Short name T428
Test name
Test status
Simulation time 317083425 ps
CPU time 29.79 seconds
Started Jun 29 05:51:44 PM PDT 24
Finished Jun 29 05:52:14 PM PDT 24
Peak memory 257068 kb
Host smart-2d9bf181-6631-4793-95ef-cf043f709a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28472
16538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2847216538
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2993758991
Short name T214
Test name
Test status
Simulation time 139892541 ps
CPU time 3.58 seconds
Started Jun 29 05:51:49 PM PDT 24
Finished Jun 29 05:51:52 PM PDT 24
Peak memory 249596 kb
Host smart-92bd2656-436c-4729-95c5-d1b5faa1a4c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2993758991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2993758991
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.385916110
Short name T453
Test name
Test status
Simulation time 357797756880 ps
CPU time 2257.2 seconds
Started Jun 29 05:51:47 PM PDT 24
Finished Jun 29 06:29:25 PM PDT 24
Peak memory 290288 kb
Host smart-ade1776d-c35c-4438-913e-8408a5ed6728
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385916110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.385916110
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2660004108
Short name T524
Test name
Test status
Simulation time 1477922423 ps
CPU time 17.44 seconds
Started Jun 29 05:51:48 PM PDT 24
Finished Jun 29 05:52:06 PM PDT 24
Peak memory 249292 kb
Host smart-7ac99ad5-5698-4f51-ba42-8aed7456a7c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2660004108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2660004108
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1869500424
Short name T632
Test name
Test status
Simulation time 4464137113 ps
CPU time 98.69 seconds
Started Jun 29 05:51:48 PM PDT 24
Finished Jun 29 05:53:27 PM PDT 24
Peak memory 257136 kb
Host smart-5a613809-f117-45fe-ad29-ee96e241f271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18695
00424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1869500424
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.4168504653
Short name T612
Test name
Test status
Simulation time 2628135078 ps
CPU time 41.58 seconds
Started Jun 29 05:51:50 PM PDT 24
Finished Jun 29 05:52:32 PM PDT 24
Peak memory 256784 kb
Host smart-0732aeb4-cfbc-4cb4-9df2-a6aefd3ca988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41685
04653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.4168504653
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1465708036
Short name T326
Test name
Test status
Simulation time 128400949675 ps
CPU time 1832.9 seconds
Started Jun 29 05:51:49 PM PDT 24
Finished Jun 29 06:22:22 PM PDT 24
Peak memory 273852 kb
Host smart-fdf8167c-1ec3-4383-b78d-b0c01750e4db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465708036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1465708036
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2814048582
Short name T488
Test name
Test status
Simulation time 87827227060 ps
CPU time 1299.91 seconds
Started Jun 29 05:51:48 PM PDT 24
Finished Jun 29 06:13:28 PM PDT 24
Peak memory 272900 kb
Host smart-180d349b-70da-4db8-b68c-e523683182bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814048582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2814048582
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.465670743
Short name T593
Test name
Test status
Simulation time 1755182928 ps
CPU time 56.9 seconds
Started Jun 29 05:51:39 PM PDT 24
Finished Jun 29 05:52:36 PM PDT 24
Peak memory 249276 kb
Host smart-3d51cc00-cd9b-413e-a986-d9df977e09c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46567
0743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.465670743
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.263477690
Short name T36
Test name
Test status
Simulation time 116491516 ps
CPU time 8.99 seconds
Started Jun 29 05:51:44 PM PDT 24
Finished Jun 29 05:51:53 PM PDT 24
Peak memory 254320 kb
Host smart-b7cabeda-ad44-4c69-9e1d-e304c6d76a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26347
7690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.263477690
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2270378441
Short name T427
Test name
Test status
Simulation time 72750959 ps
CPU time 3.07 seconds
Started Jun 29 05:51:49 PM PDT 24
Finished Jun 29 05:51:53 PM PDT 24
Peak memory 240608 kb
Host smart-59c3b9a2-0f4f-42ee-ad16-555db91d9549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22703
78441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2270378441
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2480011092
Short name T422
Test name
Test status
Simulation time 224127783 ps
CPU time 25.69 seconds
Started Jun 29 05:51:39 PM PDT 24
Finished Jun 29 05:52:06 PM PDT 24
Peak memory 256996 kb
Host smart-e096efea-ee45-4cdf-892f-010caeb6cc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24800
11092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2480011092
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1366434817
Short name T59
Test name
Test status
Simulation time 75274609538 ps
CPU time 1764.22 seconds
Started Jun 29 05:51:48 PM PDT 24
Finished Jun 29 06:21:12 PM PDT 24
Peak memory 290380 kb
Host smart-e36c2420-3d8e-4def-b124-a57d4ad90604
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366434817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1366434817
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3075024357
Short name T205
Test name
Test status
Simulation time 14649322 ps
CPU time 2.76 seconds
Started Jun 29 05:52:48 PM PDT 24
Finished Jun 29 05:52:51 PM PDT 24
Peak memory 249540 kb
Host smart-856b89c4-0242-4b00-aad3-6707cd90bafd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3075024357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3075024357
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2742561920
Short name T449
Test name
Test status
Simulation time 173644611563 ps
CPU time 2956.57 seconds
Started Jun 29 05:52:53 PM PDT 24
Finished Jun 29 06:42:10 PM PDT 24
Peak memory 290244 kb
Host smart-ea081bdd-c476-4b45-883c-28f51740bdbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742561920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2742561920
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2060764352
Short name T362
Test name
Test status
Simulation time 870596286 ps
CPU time 16.38 seconds
Started Jun 29 05:52:48 PM PDT 24
Finished Jun 29 05:53:05 PM PDT 24
Peak memory 249208 kb
Host smart-97360a30-5460-4ce6-a81c-587706d44137
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2060764352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2060764352
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2148889442
Short name T409
Test name
Test status
Simulation time 1186258031 ps
CPU time 66.14 seconds
Started Jun 29 05:52:41 PM PDT 24
Finished Jun 29 05:53:47 PM PDT 24
Peak memory 248992 kb
Host smart-fcce928e-b3f2-4c64-8985-ef536577e58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21488
89442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2148889442
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.421120883
Short name T444
Test name
Test status
Simulation time 1350086612 ps
CPU time 47.17 seconds
Started Jun 29 05:52:38 PM PDT 24
Finished Jun 29 05:53:26 PM PDT 24
Peak memory 256992 kb
Host smart-464cda6f-db14-464e-a5ec-2bee8512e785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42112
0883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.421120883
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2210293093
Short name T315
Test name
Test status
Simulation time 21929799018 ps
CPU time 1486.28 seconds
Started Jun 29 05:52:38 PM PDT 24
Finished Jun 29 06:17:26 PM PDT 24
Peak memory 273932 kb
Host smart-90490a4d-8076-4134-b7bd-85b1ede6742d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210293093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2210293093
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1864332257
Short name T598
Test name
Test status
Simulation time 48237604186 ps
CPU time 1419.92 seconds
Started Jun 29 05:52:46 PM PDT 24
Finished Jun 29 06:16:26 PM PDT 24
Peak memory 289392 kb
Host smart-33927f0e-6b02-49d3-bbee-df1262fab60b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864332257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1864332257
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.4198774926
Short name T225
Test name
Test status
Simulation time 6024672437 ps
CPU time 245.56 seconds
Started Jun 29 05:52:38 PM PDT 24
Finished Jun 29 05:56:45 PM PDT 24
Peak memory 249396 kb
Host smart-671b672f-5435-4814-b18b-ed85ee6ae6d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198774926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.4198774926
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2511473720
Short name T227
Test name
Test status
Simulation time 6559946658 ps
CPU time 76.2 seconds
Started Jun 29 05:52:40 PM PDT 24
Finished Jun 29 05:53:57 PM PDT 24
Peak memory 249436 kb
Host smart-04ea26ca-b6b1-42d9-9aa9-a35b7abac5d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25114
73720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2511473720
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3259149071
Short name T470
Test name
Test status
Simulation time 130683508 ps
CPU time 6.02 seconds
Started Jun 29 05:52:38 PM PDT 24
Finished Jun 29 05:52:45 PM PDT 24
Peak memory 248732 kb
Host smart-89a19b34-df8a-4177-b275-01e518be7b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32591
49071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3259149071
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1171981725
Short name T586
Test name
Test status
Simulation time 3023491807 ps
CPU time 15.91 seconds
Started Jun 29 05:52:38 PM PDT 24
Finished Jun 29 05:52:55 PM PDT 24
Peak memory 257228 kb
Host smart-47033d7c-ced9-4f1f-93bf-81d3aac218c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11719
81725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1171981725
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.180392084
Short name T648
Test name
Test status
Simulation time 451113134 ps
CPU time 57.49 seconds
Started Jun 29 05:52:46 PM PDT 24
Finished Jun 29 05:53:44 PM PDT 24
Peak memory 257428 kb
Host smart-10bb0e9e-ca07-4583-830a-648791de0e39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180392084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.180392084
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2589047524
Short name T287
Test name
Test status
Simulation time 198669802860 ps
CPU time 4322.59 seconds
Started Jun 29 05:52:48 PM PDT 24
Finished Jun 29 07:04:51 PM PDT 24
Peak memory 349612 kb
Host smart-1f9c6383-e8aa-4284-9666-401eaf1d9d7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589047524 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2589047524
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2643888009
Short name T371
Test name
Test status
Simulation time 29568738456 ps
CPU time 1882.3 seconds
Started Jun 29 05:52:55 PM PDT 24
Finished Jun 29 06:24:18 PM PDT 24
Peak memory 287216 kb
Host smart-792cd2d7-8c37-4d96-a61d-5c174d9cfb7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643888009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2643888009
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2143705468
Short name T536
Test name
Test status
Simulation time 239778938 ps
CPU time 11.82 seconds
Started Jun 29 05:52:54 PM PDT 24
Finished Jun 29 05:53:07 PM PDT 24
Peak memory 249240 kb
Host smart-8ef8956c-7295-4bb4-905b-4cc8479d7356
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2143705468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2143705468
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.350348168
Short name T417
Test name
Test status
Simulation time 1333268947 ps
CPU time 78.06 seconds
Started Jun 29 05:52:47 PM PDT 24
Finished Jun 29 05:54:06 PM PDT 24
Peak memory 257024 kb
Host smart-336ca130-9164-43bb-82f6-0a2f78518936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35034
8168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.350348168
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3542925351
Short name T436
Test name
Test status
Simulation time 612200557 ps
CPU time 13.61 seconds
Started Jun 29 05:52:55 PM PDT 24
Finished Jun 29 05:53:09 PM PDT 24
Peak memory 249252 kb
Host smart-fe23a3b7-6b54-4aa1-b7e8-c182bf56c2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35429
25351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3542925351
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1599574598
Short name T292
Test name
Test status
Simulation time 18073092580 ps
CPU time 743 seconds
Started Jun 29 05:52:54 PM PDT 24
Finished Jun 29 06:05:18 PM PDT 24
Peak memory 273312 kb
Host smart-6520107b-b9ea-4063-8ee7-e3eb412c683a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599574598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1599574598
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.545898558
Short name T224
Test name
Test status
Simulation time 65911522656 ps
CPU time 1933.19 seconds
Started Jun 29 05:52:56 PM PDT 24
Finished Jun 29 06:25:09 PM PDT 24
Peak memory 284160 kb
Host smart-488769a4-a6fc-4e93-b34d-39cabd0b3552
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545898558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.545898558
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1422583264
Short name T672
Test name
Test status
Simulation time 2180057146 ps
CPU time 41.39 seconds
Started Jun 29 05:52:53 PM PDT 24
Finished Jun 29 05:53:35 PM PDT 24
Peak memory 256840 kb
Host smart-20e9a39d-f1d8-46df-8836-08122b525070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14225
83264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1422583264
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.352697979
Short name T487
Test name
Test status
Simulation time 127595879 ps
CPU time 6.34 seconds
Started Jun 29 05:52:55 PM PDT 24
Finished Jun 29 05:53:02 PM PDT 24
Peak memory 255508 kb
Host smart-f4a1a436-947c-4e3a-88a3-1885c70c5afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35269
7979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.352697979
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2021050710
Short name T688
Test name
Test status
Simulation time 58823110 ps
CPU time 10.7 seconds
Started Jun 29 05:52:54 PM PDT 24
Finished Jun 29 05:53:05 PM PDT 24
Peak memory 248756 kb
Host smart-9d798fa9-aa16-4c4c-af38-50134dbfb650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20210
50710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2021050710
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3608009080
Short name T35
Test name
Test status
Simulation time 74469451 ps
CPU time 5.32 seconds
Started Jun 29 05:52:48 PM PDT 24
Finished Jun 29 05:52:53 PM PDT 24
Peak memory 252116 kb
Host smart-a8ad636e-2334-4905-8c8c-af1f8aad2d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36080
09080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3608009080
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1058331414
Short name T565
Test name
Test status
Simulation time 182530537129 ps
CPU time 2806.2 seconds
Started Jun 29 05:53:06 PM PDT 24
Finished Jun 29 06:39:52 PM PDT 24
Peak memory 290092 kb
Host smart-78157a17-3f45-4942-be63-e16d7523007a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058331414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1058331414
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.4048317426
Short name T238
Test name
Test status
Simulation time 172735309 ps
CPU time 9.78 seconds
Started Jun 29 05:53:04 PM PDT 24
Finished Jun 29 05:53:14 PM PDT 24
Peak memory 249280 kb
Host smart-5bf433a0-e38c-40d3-9e0c-65681b0b403d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4048317426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.4048317426
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.926247113
Short name T520
Test name
Test status
Simulation time 651173572 ps
CPU time 53.65 seconds
Started Jun 29 05:52:54 PM PDT 24
Finished Jun 29 05:53:48 PM PDT 24
Peak memory 257020 kb
Host smart-e2cd8dab-0848-4ea2-8072-e734d26087d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92624
7113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.926247113
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.113151621
Short name T90
Test name
Test status
Simulation time 320676051 ps
CPU time 29.98 seconds
Started Jun 29 05:52:54 PM PDT 24
Finished Jun 29 05:53:25 PM PDT 24
Peak memory 249232 kb
Host smart-80ecb170-dca1-41f0-8348-355add72de40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11315
1621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.113151621
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3182374236
Short name T663
Test name
Test status
Simulation time 108336778566 ps
CPU time 1705.53 seconds
Started Jun 29 05:53:05 PM PDT 24
Finished Jun 29 06:21:31 PM PDT 24
Peak memory 273988 kb
Host smart-55a130cd-2d1c-406b-8f2a-b8100577875c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182374236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3182374236
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.727653226
Short name T316
Test name
Test status
Simulation time 5254522528 ps
CPU time 231.69 seconds
Started Jun 29 05:53:06 PM PDT 24
Finished Jun 29 05:56:58 PM PDT 24
Peak memory 249360 kb
Host smart-8c7d7127-fa6c-422c-905d-db5594381434
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727653226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.727653226
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.135709737
Short name T85
Test name
Test status
Simulation time 95400500 ps
CPU time 7.02 seconds
Started Jun 29 05:52:54 PM PDT 24
Finished Jun 29 05:53:01 PM PDT 24
Peak memory 249280 kb
Host smart-b424053d-7c74-40c2-b773-d1628a4aee0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13570
9737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.135709737
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2951023189
Short name T286
Test name
Test status
Simulation time 849444760 ps
CPU time 20.9 seconds
Started Jun 29 05:52:55 PM PDT 24
Finished Jun 29 05:53:16 PM PDT 24
Peak memory 257420 kb
Host smart-3a3fa64f-0de9-4e3e-8ae3-76e62e441301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29510
23189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2951023189
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.139557556
Short name T264
Test name
Test status
Simulation time 1203315770 ps
CPU time 18.75 seconds
Started Jun 29 05:52:56 PM PDT 24
Finished Jun 29 05:53:15 PM PDT 24
Peak memory 255992 kb
Host smart-9863da6e-2114-4dc5-8d0a-3e29ab99ace6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13955
7556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.139557556
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3389079145
Short name T475
Test name
Test status
Simulation time 1557363729 ps
CPU time 34.76 seconds
Started Jun 29 05:52:54 PM PDT 24
Finished Jun 29 05:53:30 PM PDT 24
Peak memory 257224 kb
Host smart-f7066470-0794-4824-b557-2bb67a6e08b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33890
79145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3389079145
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1195178447
Short name T208
Test name
Test status
Simulation time 31920325 ps
CPU time 2.73 seconds
Started Jun 29 05:53:13 PM PDT 24
Finished Jun 29 05:53:16 PM PDT 24
Peak memory 249576 kb
Host smart-654d5978-29d0-415c-ae88-3f3417bd712a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1195178447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1195178447
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1661079023
Short name T413
Test name
Test status
Simulation time 46867976545 ps
CPU time 2653.35 seconds
Started Jun 29 05:53:24 PM PDT 24
Finished Jun 29 06:37:38 PM PDT 24
Peak memory 282040 kb
Host smart-c726a134-4fd3-4191-9eba-2aecd91b1adf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661079023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1661079023
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1270996876
Short name T557
Test name
Test status
Simulation time 83029071 ps
CPU time 7.02 seconds
Started Jun 29 05:53:12 PM PDT 24
Finished Jun 29 05:53:19 PM PDT 24
Peak memory 249208 kb
Host smart-23d9a7c6-31d8-4885-8201-4018b831df4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1270996876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1270996876
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2890208738
Short name T471
Test name
Test status
Simulation time 3507438929 ps
CPU time 192.33 seconds
Started Jun 29 05:53:24 PM PDT 24
Finished Jun 29 05:56:37 PM PDT 24
Peak memory 257092 kb
Host smart-a1285878-8d7e-4598-9943-063cc0f17da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28902
08738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2890208738
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2009964983
Short name T673
Test name
Test status
Simulation time 469644152 ps
CPU time 21.01 seconds
Started Jun 29 05:53:14 PM PDT 24
Finished Jun 29 05:53:35 PM PDT 24
Peak memory 249292 kb
Host smart-e7296e8b-83dc-426c-9c9a-dec1cd126b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20099
64983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2009964983
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2295650034
Short name T503
Test name
Test status
Simulation time 56222503199 ps
CPU time 1359.6 seconds
Started Jun 29 05:53:24 PM PDT 24
Finished Jun 29 06:16:04 PM PDT 24
Peak memory 290304 kb
Host smart-876e9f2b-add7-43f6-9bb4-d1cedf4f6569
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295650034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2295650034
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2860946309
Short name T539
Test name
Test status
Simulation time 10379255696 ps
CPU time 1429.96 seconds
Started Jun 29 05:53:25 PM PDT 24
Finished Jun 29 06:17:15 PM PDT 24
Peak memory 287912 kb
Host smart-f07183cb-b666-4736-ac44-bbb72cc3ca29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860946309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2860946309
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.465742702
Short name T603
Test name
Test status
Simulation time 409947851 ps
CPU time 34.41 seconds
Started Jun 29 05:53:12 PM PDT 24
Finished Jun 29 05:53:46 PM PDT 24
Peak memory 256684 kb
Host smart-8a43aa97-9a19-4f4f-bded-70e337069d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46574
2702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.465742702
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3919554364
Short name T404
Test name
Test status
Simulation time 778909231 ps
CPU time 28.9 seconds
Started Jun 29 05:53:12 PM PDT 24
Finished Jun 29 05:53:41 PM PDT 24
Peak memory 256820 kb
Host smart-3f4aae26-91c1-4e91-b562-23a6525c7b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39195
54364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3919554364
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1527851458
Short name T454
Test name
Test status
Simulation time 204323134 ps
CPU time 14.26 seconds
Started Jun 29 05:53:12 PM PDT 24
Finished Jun 29 05:53:27 PM PDT 24
Peak memory 248788 kb
Host smart-f31d55a0-00f6-44a7-843a-f4f872267ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15278
51458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1527851458
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.194309413
Short name T34
Test name
Test status
Simulation time 1379335194 ps
CPU time 21.21 seconds
Started Jun 29 05:53:25 PM PDT 24
Finished Jun 29 05:53:46 PM PDT 24
Peak memory 254052 kb
Host smart-8953f4eb-eb56-4d8e-be50-7ac7c7b5c47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19430
9413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.194309413
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.4043965543
Short name T61
Test name
Test status
Simulation time 222642692 ps
CPU time 3.85 seconds
Started Jun 29 05:53:23 PM PDT 24
Finished Jun 29 05:53:27 PM PDT 24
Peak memory 249576 kb
Host smart-098edb41-fecf-4826-80a6-6082f7b554a7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4043965543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.4043965543
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.369425567
Short name T689
Test name
Test status
Simulation time 7596785401 ps
CPU time 788.67 seconds
Started Jun 29 05:53:13 PM PDT 24
Finished Jun 29 06:06:22 PM PDT 24
Peak memory 273504 kb
Host smart-59a335bd-be73-40e9-835a-3ed627ce249d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369425567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.369425567
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2759891429
Short name T424
Test name
Test status
Simulation time 99916049 ps
CPU time 6.61 seconds
Started Jun 29 05:53:22 PM PDT 24
Finished Jun 29 05:53:28 PM PDT 24
Peak memory 249280 kb
Host smart-a0b8f3ac-d0c4-43f0-b189-6a4be1b8c866
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2759891429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2759891429
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.4265499354
Short name T573
Test name
Test status
Simulation time 948396032 ps
CPU time 38.11 seconds
Started Jun 29 05:53:12 PM PDT 24
Finished Jun 29 05:53:51 PM PDT 24
Peak memory 250332 kb
Host smart-43c5cf1a-72e1-4e83-8948-9e9879f1cf97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42654
99354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.4265499354
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1559849658
Short name T86
Test name
Test status
Simulation time 428225970 ps
CPU time 10.58 seconds
Started Jun 29 05:53:24 PM PDT 24
Finished Jun 29 05:53:35 PM PDT 24
Peak memory 253640 kb
Host smart-8fb0abf4-3f12-4b64-8421-fe174f5e8caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15598
49658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1559849658
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2471536290
Short name T323
Test name
Test status
Simulation time 29533305137 ps
CPU time 1873.15 seconds
Started Jun 29 05:53:20 PM PDT 24
Finished Jun 29 06:24:34 PM PDT 24
Peak memory 284636 kb
Host smart-ab49ceff-a791-4683-8ea3-5d627b454d10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471536290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2471536290
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2203389894
Short name T636
Test name
Test status
Simulation time 26699959142 ps
CPU time 1447.4 seconds
Started Jun 29 05:53:21 PM PDT 24
Finished Jun 29 06:17:29 PM PDT 24
Peak memory 273876 kb
Host smart-5407ee8c-7721-454c-8b01-601acf44a331
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203389894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2203389894
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2126143394
Short name T624
Test name
Test status
Simulation time 7656658158 ps
CPU time 325.38 seconds
Started Jun 29 05:53:22 PM PDT 24
Finished Jun 29 05:58:48 PM PDT 24
Peak memory 255736 kb
Host smart-15ebd06f-4a0d-43f5-aff2-4b0c01391b71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126143394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2126143394
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.988380074
Short name T46
Test name
Test status
Simulation time 612445879 ps
CPU time 19.23 seconds
Started Jun 29 05:53:13 PM PDT 24
Finished Jun 29 05:53:33 PM PDT 24
Peak memory 257352 kb
Host smart-c110d887-4045-4c75-a2c1-9f1caa40d09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98838
0074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.988380074
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.4271124341
Short name T27
Test name
Test status
Simulation time 996468869 ps
CPU time 32.66 seconds
Started Jun 29 05:53:13 PM PDT 24
Finished Jun 29 05:53:46 PM PDT 24
Peak memory 256168 kb
Host smart-b2dcb3bf-de03-47f8-8d9c-1ec1a017c8f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42711
24341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.4271124341
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1151105439
Short name T528
Test name
Test status
Simulation time 117474852 ps
CPU time 14.92 seconds
Started Jun 29 05:53:24 PM PDT 24
Finished Jun 29 05:53:39 PM PDT 24
Peak memory 256612 kb
Host smart-f43e7ff1-cf28-44ae-854c-b18ccd6496ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11511
05439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1151105439
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1179869779
Short name T589
Test name
Test status
Simulation time 1047580015 ps
CPU time 63.19 seconds
Started Jun 29 05:53:14 PM PDT 24
Finished Jun 29 05:54:17 PM PDT 24
Peak memory 249260 kb
Host smart-022b2b3e-c3b6-4b22-b64f-2aaf708cd5ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11798
69779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1179869779
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1493915193
Short name T585
Test name
Test status
Simulation time 146371527296 ps
CPU time 1179.19 seconds
Started Jun 29 05:53:21 PM PDT 24
Finished Jun 29 06:13:01 PM PDT 24
Peak memory 273100 kb
Host smart-4b8b9c79-3ff2-40b7-84cd-2cba62ce6a42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493915193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1493915193
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3188339620
Short name T231
Test name
Test status
Simulation time 17218926855 ps
CPU time 1201.88 seconds
Started Jun 29 05:53:22 PM PDT 24
Finished Jun 29 06:13:24 PM PDT 24
Peak memory 267988 kb
Host smart-7710109d-f0b5-491c-a3bc-f8a786251dbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188339620 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3188339620
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.774372780
Short name T220
Test name
Test status
Simulation time 111625310 ps
CPU time 2.65 seconds
Started Jun 29 05:53:30 PM PDT 24
Finished Jun 29 05:53:33 PM PDT 24
Peak memory 249596 kb
Host smart-bee2d746-e445-40d4-8b70-11ea667f84f3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=774372780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.774372780
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.657580369
Short name T531
Test name
Test status
Simulation time 9162957842 ps
CPU time 1182.58 seconds
Started Jun 29 05:53:30 PM PDT 24
Finished Jun 29 06:13:12 PM PDT 24
Peak memory 287232 kb
Host smart-327de2e1-91f5-40fa-8c7c-7cf51d0b61f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657580369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.657580369
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3966501005
Short name T483
Test name
Test status
Simulation time 8604821612 ps
CPU time 264.51 seconds
Started Jun 29 05:53:21 PM PDT 24
Finished Jun 29 05:57:46 PM PDT 24
Peak memory 257612 kb
Host smart-93ac336c-501a-4ffe-a62e-2d0947441783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39665
01005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3966501005
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1877521381
Short name T415
Test name
Test status
Simulation time 65491244 ps
CPU time 7.3 seconds
Started Jun 29 05:53:22 PM PDT 24
Finished Jun 29 05:53:29 PM PDT 24
Peak memory 249240 kb
Host smart-2e63d84e-f159-4a11-9107-d14d8dccf548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18775
21381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1877521381
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1496238105
Short name T466
Test name
Test status
Simulation time 171513760706 ps
CPU time 2799.12 seconds
Started Jun 29 05:53:31 PM PDT 24
Finished Jun 29 06:40:10 PM PDT 24
Peak memory 289644 kb
Host smart-add487af-8172-486d-bf6d-2ad14b6a5797
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496238105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1496238105
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2324801876
Short name T406
Test name
Test status
Simulation time 54030811424 ps
CPU time 1707.02 seconds
Started Jun 29 05:53:30 PM PDT 24
Finished Jun 29 06:21:57 PM PDT 24
Peak memory 290272 kb
Host smart-bff5e48e-b380-4e33-9c9d-b53a50542eee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324801876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2324801876
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2621206178
Short name T530
Test name
Test status
Simulation time 11720515959 ps
CPU time 139.19 seconds
Started Jun 29 05:53:29 PM PDT 24
Finished Jun 29 05:55:48 PM PDT 24
Peak memory 255976 kb
Host smart-c8fbffb1-32d6-461b-b620-1093528938b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621206178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2621206178
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1586153149
Short name T554
Test name
Test status
Simulation time 366261575 ps
CPU time 18.11 seconds
Started Jun 29 05:53:22 PM PDT 24
Finished Jun 29 05:53:41 PM PDT 24
Peak memory 256808 kb
Host smart-04e70a6d-393b-42a2-b912-7ee1663a00c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15861
53149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1586153149
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.36314654
Short name T575
Test name
Test status
Simulation time 2997206906 ps
CPU time 43.3 seconds
Started Jun 29 05:53:21 PM PDT 24
Finished Jun 29 05:54:05 PM PDT 24
Peak memory 249324 kb
Host smart-78ee4bb2-988a-436b-ac33-04b375404028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36314
654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.36314654
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2157523086
Short name T390
Test name
Test status
Simulation time 74391256 ps
CPU time 3.5 seconds
Started Jun 29 05:53:21 PM PDT 24
Finished Jun 29 05:53:25 PM PDT 24
Peak memory 240620 kb
Host smart-89bbf93f-b50f-478a-889f-e7945a638926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21575
23086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2157523086
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1068103718
Short name T659
Test name
Test status
Simulation time 435530250 ps
CPU time 36.62 seconds
Started Jun 29 05:53:21 PM PDT 24
Finished Jun 29 05:53:58 PM PDT 24
Peak memory 257356 kb
Host smart-f58ac492-3da2-4c68-964e-fd0777c3bbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10681
03718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1068103718
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3579179717
Short name T221
Test name
Test status
Simulation time 65560887 ps
CPU time 2.19 seconds
Started Jun 29 05:53:47 PM PDT 24
Finished Jun 29 05:53:49 PM PDT 24
Peak memory 249596 kb
Host smart-1f666e9c-e3a8-4330-810d-5df1715902a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3579179717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3579179717
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1196261544
Short name T377
Test name
Test status
Simulation time 39722573494 ps
CPU time 1231.05 seconds
Started Jun 29 05:53:36 PM PDT 24
Finished Jun 29 06:14:08 PM PDT 24
Peak memory 289444 kb
Host smart-3df77afa-9bee-4bac-bcbb-d58cf5e4d447
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196261544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1196261544
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2886093949
Short name T680
Test name
Test status
Simulation time 2321782877 ps
CPU time 21.38 seconds
Started Jun 29 05:53:46 PM PDT 24
Finished Jun 29 05:54:08 PM PDT 24
Peak memory 249424 kb
Host smart-5b8be390-1613-48a3-8f40-ba08e4279bb7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2886093949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2886093949
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3627876645
Short name T374
Test name
Test status
Simulation time 4631364317 ps
CPU time 217.11 seconds
Started Jun 29 05:53:37 PM PDT 24
Finished Jun 29 05:57:15 PM PDT 24
Peak memory 257128 kb
Host smart-936c5834-0003-4be1-a84e-b574b7752ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36278
76645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3627876645
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.315514476
Short name T400
Test name
Test status
Simulation time 2854095156 ps
CPU time 46.2 seconds
Started Jun 29 05:53:37 PM PDT 24
Finished Jun 29 05:54:24 PM PDT 24
Peak memory 257496 kb
Host smart-ac771d9d-e539-4661-bcef-d67ca1e50f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31551
4476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.315514476
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2301140094
Short name T339
Test name
Test status
Simulation time 47557892122 ps
CPU time 1777.43 seconds
Started Jun 29 05:53:36 PM PDT 24
Finished Jun 29 06:23:14 PM PDT 24
Peak memory 273896 kb
Host smart-8c16fc4b-d4bf-4c10-b0b8-cdd9ab761fce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301140094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2301140094
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2126631873
Short name T385
Test name
Test status
Simulation time 101660863479 ps
CPU time 1638.73 seconds
Started Jun 29 05:53:36 PM PDT 24
Finished Jun 29 06:20:55 PM PDT 24
Peak memory 274020 kb
Host smart-1d6375b2-27f5-46bc-b431-4ba4346acfbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126631873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2126631873
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1220545313
Short name T93
Test name
Test status
Simulation time 1412868398 ps
CPU time 71.92 seconds
Started Jun 29 05:53:35 PM PDT 24
Finished Jun 29 05:54:47 PM PDT 24
Peak memory 257396 kb
Host smart-04f73d4b-7507-45b2-b5fe-8b1121010f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12205
45313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1220545313
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3643210676
Short name T56
Test name
Test status
Simulation time 895177227 ps
CPU time 64.12 seconds
Started Jun 29 05:53:39 PM PDT 24
Finished Jun 29 05:54:43 PM PDT 24
Peak memory 250336 kb
Host smart-ad613567-2bb0-40cd-bfcf-72b7a2b51058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36432
10676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3643210676
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3042780679
Short name T249
Test name
Test status
Simulation time 535543920 ps
CPU time 36.59 seconds
Started Jun 29 05:53:37 PM PDT 24
Finished Jun 29 05:54:14 PM PDT 24
Peak memory 249308 kb
Host smart-7fcb056e-e058-4f3a-b48f-b58553ef4246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30427
80679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3042780679
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3248109273
Short name T623
Test name
Test status
Simulation time 1767289853 ps
CPU time 36.37 seconds
Started Jun 29 05:53:38 PM PDT 24
Finished Jun 29 05:54:14 PM PDT 24
Peak memory 257224 kb
Host smart-fe4b878e-0e11-4cb8-935e-54ce1a8d27ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32481
09273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3248109273
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2320980758
Short name T515
Test name
Test status
Simulation time 122162675255 ps
CPU time 3084.99 seconds
Started Jun 29 05:53:45 PM PDT 24
Finished Jun 29 06:45:11 PM PDT 24
Peak memory 300380 kb
Host smart-6d295e25-5d53-4538-998e-3e84de97d306
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320980758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2320980758
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1837555227
Short name T213
Test name
Test status
Simulation time 211239295 ps
CPU time 4.01 seconds
Started Jun 29 05:53:53 PM PDT 24
Finished Jun 29 05:53:57 PM PDT 24
Peak memory 249528 kb
Host smart-1da220b4-a1d4-4be7-83d1-3a95718524cf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1837555227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1837555227
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3944660659
Short name T434
Test name
Test status
Simulation time 5527945465 ps
CPU time 64.19 seconds
Started Jun 29 05:53:54 PM PDT 24
Finished Jun 29 05:54:58 PM PDT 24
Peak memory 249352 kb
Host smart-357de32e-514d-4e07-a9ee-c8f0c33040f3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3944660659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3944660659
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.159515774
Short name T660
Test name
Test status
Simulation time 3659724753 ps
CPU time 54.44 seconds
Started Jun 29 05:53:44 PM PDT 24
Finished Jun 29 05:54:39 PM PDT 24
Peak memory 256940 kb
Host smart-0b8235b0-00a5-45df-9e44-5f1b68c9f013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15951
5774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.159515774
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1108649778
Short name T667
Test name
Test status
Simulation time 38702346 ps
CPU time 5.26 seconds
Started Jun 29 05:53:44 PM PDT 24
Finished Jun 29 05:53:50 PM PDT 24
Peak memory 252812 kb
Host smart-df1b3d98-16ff-49cc-8235-2269e1d21093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11086
49778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1108649778
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3687261125
Short name T333
Test name
Test status
Simulation time 9923089768 ps
CPU time 822.33 seconds
Started Jun 29 05:53:53 PM PDT 24
Finished Jun 29 06:07:36 PM PDT 24
Peak memory 274000 kb
Host smart-b7d0d3fd-3791-4439-bf49-e6d25dc1cdc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687261125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3687261125
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3454663955
Short name T109
Test name
Test status
Simulation time 25675281515 ps
CPU time 1356.23 seconds
Started Jun 29 05:53:56 PM PDT 24
Finished Jun 29 06:16:32 PM PDT 24
Peak memory 289240 kb
Host smart-27c126ba-01ba-49e3-a682-63e89302ddc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454663955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3454663955
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1867732413
Short name T321
Test name
Test status
Simulation time 24780197562 ps
CPU time 540.73 seconds
Started Jun 29 05:53:55 PM PDT 24
Finished Jun 29 06:02:56 PM PDT 24
Peak memory 256108 kb
Host smart-67bc4679-9443-4926-8213-c8a4c62bd81c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867732413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1867732413
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3168983046
Short name T386
Test name
Test status
Simulation time 161161040 ps
CPU time 18.63 seconds
Started Jun 29 05:53:46 PM PDT 24
Finished Jun 29 05:54:05 PM PDT 24
Peak memory 257084 kb
Host smart-9bffe48b-c956-4063-9ec2-aa09b0a586c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31689
83046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3168983046
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3504730749
Short name T567
Test name
Test status
Simulation time 199044625 ps
CPU time 5.5 seconds
Started Jun 29 05:53:55 PM PDT 24
Finished Jun 29 05:54:01 PM PDT 24
Peak memory 240576 kb
Host smart-12c02523-776b-4718-82f7-44d1675f9f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35047
30749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3504730749
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3014179003
Short name T653
Test name
Test status
Simulation time 829428381 ps
CPU time 25.26 seconds
Started Jun 29 05:53:49 PM PDT 24
Finished Jun 29 05:54:14 PM PDT 24
Peak memory 256364 kb
Host smart-20d8cf4e-bc1b-4da7-b1bc-8dbc46a40582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30141
79003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3014179003
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2825065467
Short name T258
Test name
Test status
Simulation time 136428946538 ps
CPU time 3548.58 seconds
Started Jun 29 05:53:54 PM PDT 24
Finished Jun 29 06:53:03 PM PDT 24
Peak memory 319796 kb
Host smart-ff70bc43-92df-4885-83c0-bbe9a47afbd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825065467 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2825065467
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.923207987
Short name T587
Test name
Test status
Simulation time 17557043484 ps
CPU time 1368.38 seconds
Started Jun 29 05:54:06 PM PDT 24
Finished Jun 29 06:16:55 PM PDT 24
Peak memory 289412 kb
Host smart-81da7a58-ef25-4905-8e01-47bc2bc4c803
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923207987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.923207987
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2393630785
Short name T229
Test name
Test status
Simulation time 1330758964 ps
CPU time 30.83 seconds
Started Jun 29 05:54:05 PM PDT 24
Finished Jun 29 05:54:36 PM PDT 24
Peak memory 249280 kb
Host smart-fd14c2e8-aeb0-4a6d-bcf2-529b4e50fb1e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2393630785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2393630785
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.671610154
Short name T501
Test name
Test status
Simulation time 1694837135 ps
CPU time 24.82 seconds
Started Jun 29 05:53:55 PM PDT 24
Finished Jun 29 05:54:20 PM PDT 24
Peak memory 256288 kb
Host smart-ea440733-698c-48bf-b8bf-17afc714dc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67161
0154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.671610154
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2334430312
Short name T639
Test name
Test status
Simulation time 86946458 ps
CPU time 4.94 seconds
Started Jun 29 05:53:55 PM PDT 24
Finished Jun 29 05:54:00 PM PDT 24
Peak memory 240588 kb
Host smart-f9b952f5-b0c2-4b5c-8cab-ffbbf2ce4fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23344
30312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2334430312
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.92631986
Short name T507
Test name
Test status
Simulation time 54688849490 ps
CPU time 2217.84 seconds
Started Jun 29 05:54:01 PM PDT 24
Finished Jun 29 06:30:59 PM PDT 24
Peak memory 288324 kb
Host smart-09746a8b-f603-4682-a997-5f526a530e12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92631986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.92631986
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2944180769
Short name T408
Test name
Test status
Simulation time 32986525534 ps
CPU time 1952.4 seconds
Started Jun 29 05:54:01 PM PDT 24
Finished Jun 29 06:26:34 PM PDT 24
Peak memory 273912 kb
Host smart-cc1ecd9e-207d-4607-915e-67727178202f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944180769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2944180769
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.4123164209
Short name T301
Test name
Test status
Simulation time 12895866965 ps
CPU time 457.22 seconds
Started Jun 29 05:54:03 PM PDT 24
Finished Jun 29 06:01:41 PM PDT 24
Peak memory 256200 kb
Host smart-ff08c332-9d33-4d40-b9ca-a86d6d0f6a02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123164209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.4123164209
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3209703869
Short name T270
Test name
Test status
Simulation time 2093561221 ps
CPU time 26.61 seconds
Started Jun 29 05:53:53 PM PDT 24
Finished Jun 29 05:54:20 PM PDT 24
Peak memory 256708 kb
Host smart-2ef2fd5b-b60f-4143-b1c8-8b409f045946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32097
03869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3209703869
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3261575709
Short name T684
Test name
Test status
Simulation time 484392394 ps
CPU time 15.82 seconds
Started Jun 29 05:53:54 PM PDT 24
Finished Jun 29 05:54:10 PM PDT 24
Peak memory 248740 kb
Host smart-17192d7f-68c2-4fdd-8e0d-aa795a01ba4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32615
75709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3261575709
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2125875321
Short name T605
Test name
Test status
Simulation time 120650346 ps
CPU time 8.5 seconds
Started Jun 29 05:54:01 PM PDT 24
Finished Jun 29 05:54:10 PM PDT 24
Peak memory 251760 kb
Host smart-5d5a3801-ce01-42ae-b01d-af4fc55a0a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21258
75321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2125875321
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.47094197
Short name T661
Test name
Test status
Simulation time 4040139754 ps
CPU time 58.62 seconds
Started Jun 29 05:53:54 PM PDT 24
Finished Jun 29 05:54:53 PM PDT 24
Peak memory 257300 kb
Host smart-651d200d-9299-4f37-a958-87ac32886340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47094
197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.47094197
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3437445923
Short name T243
Test name
Test status
Simulation time 9761483632 ps
CPU time 794.01 seconds
Started Jun 29 05:54:01 PM PDT 24
Finished Jun 29 06:07:15 PM PDT 24
Peak memory 273600 kb
Host smart-78c7d8d8-7166-4b71-9444-513498c15206
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437445923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3437445923
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2776857321
Short name T212
Test name
Test status
Simulation time 74387319 ps
CPU time 3.7 seconds
Started Jun 29 05:54:19 PM PDT 24
Finished Jun 29 05:54:23 PM PDT 24
Peak memory 249484 kb
Host smart-24076ced-bde5-4709-b1b5-4050a7a08b7a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2776857321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2776857321
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3307338988
Short name T122
Test name
Test status
Simulation time 49408184536 ps
CPU time 2739.93 seconds
Started Jun 29 05:54:10 PM PDT 24
Finished Jun 29 06:39:51 PM PDT 24
Peak memory 290136 kb
Host smart-50480e9e-3a81-4444-89f9-0b35d05f80e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307338988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3307338988
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3196980851
Short name T114
Test name
Test status
Simulation time 92529980 ps
CPU time 6.57 seconds
Started Jun 29 05:54:09 PM PDT 24
Finished Jun 29 05:54:16 PM PDT 24
Peak memory 249208 kb
Host smart-2375f218-0940-4c6a-8ada-bf95c2836f83
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3196980851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3196980851
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3884733609
Short name T359
Test name
Test status
Simulation time 1648174386 ps
CPU time 87.44 seconds
Started Jun 29 05:54:10 PM PDT 24
Finished Jun 29 05:55:38 PM PDT 24
Peak memory 250336 kb
Host smart-34a14c30-110d-4c31-abd2-5d4355d136bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38847
33609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3884733609
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.4223483293
Short name T633
Test name
Test status
Simulation time 2190390722 ps
CPU time 65.02 seconds
Started Jun 29 05:54:09 PM PDT 24
Finished Jun 29 05:55:14 PM PDT 24
Peak memory 248896 kb
Host smart-58e8b59d-2d4e-4cc3-ba5a-40684c4b325a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42234
83293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.4223483293
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3931321835
Short name T310
Test name
Test status
Simulation time 27379266884 ps
CPU time 1938.09 seconds
Started Jun 29 05:54:09 PM PDT 24
Finished Jun 29 06:26:28 PM PDT 24
Peak memory 273988 kb
Host smart-0b0fd78d-e398-4dde-aac0-5df5f91f2974
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931321835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3931321835
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3809791271
Short name T380
Test name
Test status
Simulation time 24577423464 ps
CPU time 1512.6 seconds
Started Jun 29 05:54:10 PM PDT 24
Finished Jun 29 06:19:23 PM PDT 24
Peak memory 273620 kb
Host smart-9ccbaa7a-d072-4f7a-9253-79af0876dbec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809791271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3809791271
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1991904831
Short name T239
Test name
Test status
Simulation time 125004381 ps
CPU time 13.76 seconds
Started Jun 29 05:54:09 PM PDT 24
Finished Jun 29 05:54:23 PM PDT 24
Peak memory 255804 kb
Host smart-a484a0f6-2900-4420-aad9-5c7d8936313d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19919
04831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1991904831
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3961202582
Short name T464
Test name
Test status
Simulation time 3371664937 ps
CPU time 33.21 seconds
Started Jun 29 05:54:11 PM PDT 24
Finished Jun 29 05:54:45 PM PDT 24
Peak memory 249324 kb
Host smart-26c7b826-4198-4d86-a679-d3c01edf69b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39612
02582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3961202582
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.987765934
Short name T431
Test name
Test status
Simulation time 626986010 ps
CPU time 35.91 seconds
Started Jun 29 05:54:11 PM PDT 24
Finished Jun 29 05:54:47 PM PDT 24
Peak memory 256492 kb
Host smart-2f3612f0-5cf4-4675-b7e5-45332afb4a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98776
5934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.987765934
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1849251994
Short name T500
Test name
Test status
Simulation time 11057939613 ps
CPU time 787.77 seconds
Started Jun 29 05:54:19 PM PDT 24
Finished Jun 29 06:07:27 PM PDT 24
Peak memory 271028 kb
Host smart-9f6535b3-0abb-440e-89cd-bb5fb133e2e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849251994 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1849251994
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3582897567
Short name T16
Test name
Test status
Simulation time 23091543 ps
CPU time 2.53 seconds
Started Jun 29 05:51:48 PM PDT 24
Finished Jun 29 05:51:51 PM PDT 24
Peak memory 249560 kb
Host smart-e3c9b0fd-e800-49e7-957d-d94111ce8600
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3582897567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3582897567
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1954703125
Short name T682
Test name
Test status
Simulation time 46262791374 ps
CPU time 956.08 seconds
Started Jun 29 05:51:50 PM PDT 24
Finished Jun 29 06:07:46 PM PDT 24
Peak memory 271868 kb
Host smart-8b963d61-56b6-443a-b923-1a88a8a9ea8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954703125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1954703125
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.116649490
Short name T533
Test name
Test status
Simulation time 541265584 ps
CPU time 11.95 seconds
Started Jun 29 05:51:49 PM PDT 24
Finished Jun 29 05:52:02 PM PDT 24
Peak memory 249300 kb
Host smart-e977ddbd-9cbf-4c53-b15f-1e3d56bc753c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=116649490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.116649490
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1812437661
Short name T418
Test name
Test status
Simulation time 1551464190 ps
CPU time 24.48 seconds
Started Jun 29 05:51:50 PM PDT 24
Finished Jun 29 05:52:15 PM PDT 24
Peak memory 255932 kb
Host smart-511647cd-7cc1-487e-bf2f-38716c9d4b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18124
37661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1812437661
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1186508535
Short name T357
Test name
Test status
Simulation time 113242872 ps
CPU time 15.41 seconds
Started Jun 29 05:51:48 PM PDT 24
Finished Jun 29 05:52:04 PM PDT 24
Peak memory 249240 kb
Host smart-42e78832-b646-4509-b65d-2d8e51cd33fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11865
08535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1186508535
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.4190140190
Short name T335
Test name
Test status
Simulation time 70535996588 ps
CPU time 1842.1 seconds
Started Jun 29 05:51:50 PM PDT 24
Finished Jun 29 06:22:33 PM PDT 24
Peak memory 290088 kb
Host smart-7af425a1-a8c2-4968-a945-b4ea28571f2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190140190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.4190140190
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3396432818
Short name T600
Test name
Test status
Simulation time 73235148832 ps
CPU time 2600.48 seconds
Started Jun 29 05:51:48 PM PDT 24
Finished Jun 29 06:35:09 PM PDT 24
Peak memory 290276 kb
Host smart-7eb388c3-db18-4e73-ada7-87e55a346287
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396432818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3396432818
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.587873619
Short name T26
Test name
Test status
Simulation time 263739020 ps
CPU time 5.19 seconds
Started Jun 29 05:51:50 PM PDT 24
Finished Jun 29 05:51:55 PM PDT 24
Peak memory 241040 kb
Host smart-81d28988-6777-43be-a8c6-eaa0f1f79936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58787
3619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.587873619
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2757133902
Short name T547
Test name
Test status
Simulation time 126311627 ps
CPU time 6.97 seconds
Started Jun 29 05:51:49 PM PDT 24
Finished Jun 29 05:51:57 PM PDT 24
Peak memory 249312 kb
Host smart-25a89a97-c4bb-4e98-9fcf-c6e22375a835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27571
33902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2757133902
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3915261791
Short name T10
Test name
Test status
Simulation time 858048617 ps
CPU time 34.76 seconds
Started Jun 29 05:51:55 PM PDT 24
Finished Jun 29 05:52:30 PM PDT 24
Peak memory 271464 kb
Host smart-7da769af-5a06-48cc-965c-7db6d09d2827
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3915261791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3915261791
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.724735890
Short name T460
Test name
Test status
Simulation time 3063874696 ps
CPU time 48.41 seconds
Started Jun 29 05:51:49 PM PDT 24
Finished Jun 29 05:52:38 PM PDT 24
Peak memory 257124 kb
Host smart-6b3b6a4c-0ee6-466e-9c2c-d63494f81b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72473
5890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.724735890
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2260783355
Short name T526
Test name
Test status
Simulation time 1502563316 ps
CPU time 49.83 seconds
Started Jun 29 05:51:48 PM PDT 24
Finished Jun 29 05:52:38 PM PDT 24
Peak memory 257460 kb
Host smart-f8452354-b4fa-4e42-9f19-db009c8da9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22607
83355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2260783355
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2657355230
Short name T50
Test name
Test status
Simulation time 15796980343 ps
CPU time 1744.7 seconds
Started Jun 29 05:51:48 PM PDT 24
Finished Jun 29 06:20:53 PM PDT 24
Peak memory 306488 kb
Host smart-d3b953e1-a014-4545-a92c-579ba9ec3e65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657355230 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2657355230
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.185869807
Short name T108
Test name
Test status
Simulation time 29364280661 ps
CPU time 1786.13 seconds
Started Jun 29 05:54:19 PM PDT 24
Finished Jun 29 06:24:05 PM PDT 24
Peak memory 286924 kb
Host smart-90fcdead-8199-4ce1-9681-c8f08e1aaddf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185869807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.185869807
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3731935342
Short name T542
Test name
Test status
Simulation time 3598911178 ps
CPU time 223.43 seconds
Started Jun 29 05:54:19 PM PDT 24
Finished Jun 29 05:58:03 PM PDT 24
Peak memory 257016 kb
Host smart-577e451b-6eda-4c9f-b7e5-d8be8d3fc806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37319
35342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3731935342
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.792435065
Short name T383
Test name
Test status
Simulation time 181804825 ps
CPU time 11.28 seconds
Started Jun 29 05:54:17 PM PDT 24
Finished Jun 29 05:54:29 PM PDT 24
Peak memory 249856 kb
Host smart-7b431695-5c3a-4e86-8b57-3cef59772856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79243
5065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.792435065
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1820075031
Short name T6
Test name
Test status
Simulation time 86187493451 ps
CPU time 1431.1 seconds
Started Jun 29 05:54:27 PM PDT 24
Finished Jun 29 06:18:19 PM PDT 24
Peak memory 273276 kb
Host smart-633e5800-59ad-444d-9719-d9c75becb9e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820075031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1820075031
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3738058271
Short name T429
Test name
Test status
Simulation time 42143395523 ps
CPU time 1136.16 seconds
Started Jun 29 05:54:26 PM PDT 24
Finished Jun 29 06:13:23 PM PDT 24
Peak memory 282008 kb
Host smart-1446d6ef-f323-42a0-a336-4b8b212d27f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738058271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3738058271
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1582673542
Short name T273
Test name
Test status
Simulation time 4898258581 ps
CPU time 63.16 seconds
Started Jun 29 05:54:20 PM PDT 24
Finished Jun 29 05:55:24 PM PDT 24
Peak memory 257748 kb
Host smart-6dc29ea1-7f79-4d60-a798-e628113f6633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15826
73542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1582673542
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1463202430
Short name T447
Test name
Test status
Simulation time 511008458 ps
CPU time 28.26 seconds
Started Jun 29 05:54:16 PM PDT 24
Finished Jun 29 05:54:45 PM PDT 24
Peak memory 248908 kb
Host smart-4a4ffa17-0cb3-4ca7-a9b5-33010fb4afbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14632
02430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1463202430
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3332025524
Short name T248
Test name
Test status
Simulation time 1212484011 ps
CPU time 22.38 seconds
Started Jun 29 05:54:17 PM PDT 24
Finished Jun 29 05:54:39 PM PDT 24
Peak memory 256972 kb
Host smart-f097581f-e139-439e-ae12-67e5c18d937e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33320
25524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3332025524
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3452688077
Short name T674
Test name
Test status
Simulation time 2249260115 ps
CPU time 40.49 seconds
Started Jun 29 05:54:17 PM PDT 24
Finished Jun 29 05:54:58 PM PDT 24
Peak memory 256636 kb
Host smart-887831c8-f88a-48e4-91fa-49f8065966e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34526
88077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3452688077
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3619381766
Short name T97
Test name
Test status
Simulation time 35381476217 ps
CPU time 2438.9 seconds
Started Jun 29 05:54:25 PM PDT 24
Finished Jun 29 06:35:04 PM PDT 24
Peak memory 290268 kb
Host smart-44c1267e-ae54-45e5-8e99-8d6d27794ffa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619381766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3619381766
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3637828119
Short name T601
Test name
Test status
Simulation time 36985985846 ps
CPU time 2473.18 seconds
Started Jun 29 05:54:35 PM PDT 24
Finished Jun 29 06:35:49 PM PDT 24
Peak memory 290332 kb
Host smart-65a7ad2a-99f6-4597-bdad-fcdfd0b48fda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637828119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3637828119
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1126833264
Short name T439
Test name
Test status
Simulation time 4689731159 ps
CPU time 84.34 seconds
Started Jun 29 05:54:35 PM PDT 24
Finished Jun 29 05:56:00 PM PDT 24
Peak memory 257616 kb
Host smart-c7e9cf69-9b85-48c0-b440-6312918332c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11268
33264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1126833264
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1889547523
Short name T329
Test name
Test status
Simulation time 12668754670 ps
CPU time 974.28 seconds
Started Jun 29 05:54:37 PM PDT 24
Finished Jun 29 06:10:52 PM PDT 24
Peak memory 273984 kb
Host smart-d6343187-6f96-46c2-b937-f237ecc4c52b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889547523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1889547523
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.423322609
Short name T474
Test name
Test status
Simulation time 53383085207 ps
CPU time 3097.32 seconds
Started Jun 29 05:54:37 PM PDT 24
Finished Jun 29 06:46:15 PM PDT 24
Peak memory 290320 kb
Host smart-943337ad-9c21-4d7e-9a22-4b036e3e6c10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423322609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.423322609
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.465851311
Short name T308
Test name
Test status
Simulation time 39606621730 ps
CPU time 405.09 seconds
Started Jun 29 05:54:34 PM PDT 24
Finished Jun 29 06:01:20 PM PDT 24
Peak memory 256408 kb
Host smart-a2a8a7de-f702-430b-a9ce-e016b9a44294
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465851311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.465851311
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2629134047
Short name T608
Test name
Test status
Simulation time 1003083319 ps
CPU time 59.3 seconds
Started Jun 29 05:54:26 PM PDT 24
Finished Jun 29 05:55:26 PM PDT 24
Peak memory 256536 kb
Host smart-7ee9b53f-7f97-4d28-81e1-3844f156e99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26291
34047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2629134047
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2845330607
Short name T626
Test name
Test status
Simulation time 4526066592 ps
CPU time 64.91 seconds
Started Jun 29 05:54:26 PM PDT 24
Finished Jun 29 05:55:32 PM PDT 24
Peak memory 257524 kb
Host smart-4ce1f867-fd6b-42a1-a7a6-a594757c225f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28453
30607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2845330607
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2140942164
Short name T698
Test name
Test status
Simulation time 3707963701 ps
CPU time 26.08 seconds
Started Jun 29 05:54:26 PM PDT 24
Finished Jun 29 05:54:53 PM PDT 24
Peak memory 257256 kb
Host smart-244cec81-921d-4e5f-ab37-3fbf8124e5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21409
42164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2140942164
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1465725642
Short name T679
Test name
Test status
Simulation time 41682869259 ps
CPU time 2461.92 seconds
Started Jun 29 05:54:33 PM PDT 24
Finished Jun 29 06:35:35 PM PDT 24
Peak memory 289756 kb
Host smart-12c5394c-b544-4325-804c-02d7233acb5b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465725642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1465725642
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2964171415
Short name T51
Test name
Test status
Simulation time 36799793257 ps
CPU time 1363.78 seconds
Started Jun 29 05:54:35 PM PDT 24
Finished Jun 29 06:17:20 PM PDT 24
Peak memory 287156 kb
Host smart-d46a2ea3-5d36-48ab-8fc0-a48f9aa1cbf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964171415 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2964171415
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.60953150
Short name T22
Test name
Test status
Simulation time 43489815147 ps
CPU time 2714.66 seconds
Started Jun 29 05:54:41 PM PDT 24
Finished Jun 29 06:39:57 PM PDT 24
Peak memory 290260 kb
Host smart-1b148786-8879-49c4-a942-c4446dbaa318
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60953150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.60953150
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.929285611
Short name T43
Test name
Test status
Simulation time 5812660620 ps
CPU time 112.61 seconds
Started Jun 29 05:54:41 PM PDT 24
Finished Jun 29 05:56:34 PM PDT 24
Peak memory 257604 kb
Host smart-680a62d1-b528-47f8-a402-e2c425cab60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92928
5611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.929285611
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2398715729
Short name T426
Test name
Test status
Simulation time 121858642 ps
CPU time 12.85 seconds
Started Jun 29 05:54:41 PM PDT 24
Finished Jun 29 05:54:54 PM PDT 24
Peak memory 249216 kb
Host smart-27707efa-a71b-48ba-a210-a7b4ea8f3c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23987
15729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2398715729
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3246709229
Short name T302
Test name
Test status
Simulation time 182212336360 ps
CPU time 2983.4 seconds
Started Jun 29 05:54:43 PM PDT 24
Finished Jun 29 06:44:27 PM PDT 24
Peak memory 289696 kb
Host smart-5ef4944d-bf81-4e12-8a10-b89b7680ea35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246709229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3246709229
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1911465560
Short name T40
Test name
Test status
Simulation time 90186607119 ps
CPU time 2845.27 seconds
Started Jun 29 05:54:43 PM PDT 24
Finished Jun 29 06:42:09 PM PDT 24
Peak memory 290136 kb
Host smart-1247ff14-7b77-4268-adb9-315b510f2237
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911465560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1911465560
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.455613217
Short name T309
Test name
Test status
Simulation time 47266953569 ps
CPU time 582.73 seconds
Started Jun 29 05:54:41 PM PDT 24
Finished Jun 29 06:04:24 PM PDT 24
Peak memory 249276 kb
Host smart-e9b6f274-e65a-4866-9d84-c74d7cc310a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455613217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.455613217
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1534708006
Short name T236
Test name
Test status
Simulation time 1133643302 ps
CPU time 29.74 seconds
Started Jun 29 05:54:43 PM PDT 24
Finished Jun 29 05:55:14 PM PDT 24
Peak memory 256712 kb
Host smart-0c401e1b-2c46-4e8a-9fb0-3ae9c73ff430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15347
08006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1534708006
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.545590833
Short name T476
Test name
Test status
Simulation time 391577075 ps
CPU time 16.53 seconds
Started Jun 29 05:54:44 PM PDT 24
Finished Jun 29 05:55:01 PM PDT 24
Peak memory 248828 kb
Host smart-ff6d00d9-eaca-4b78-ad72-562b930adf6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54559
0833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.545590833
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.833011587
Short name T622
Test name
Test status
Simulation time 775339723 ps
CPU time 56.33 seconds
Started Jun 29 05:54:43 PM PDT 24
Finished Jun 29 05:55:40 PM PDT 24
Peak memory 257508 kb
Host smart-822cccee-ea6e-4fd6-a222-7dfd954c85ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83301
1587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.833011587
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3816701088
Short name T599
Test name
Test status
Simulation time 591913566 ps
CPU time 38.48 seconds
Started Jun 29 05:54:42 PM PDT 24
Finished Jun 29 05:55:21 PM PDT 24
Peak memory 256912 kb
Host smart-9bf21bbf-b125-464c-a681-bf61724702cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38167
01088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3816701088
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3196470093
Short name T242
Test name
Test status
Simulation time 187744690418 ps
CPU time 2931.81 seconds
Started Jun 29 05:54:50 PM PDT 24
Finished Jun 29 06:43:42 PM PDT 24
Peak memory 290248 kb
Host smart-d262c78b-b165-4f40-8d60-d855baef0cb6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196470093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3196470093
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3258764139
Short name T518
Test name
Test status
Simulation time 30921565552 ps
CPU time 1501.84 seconds
Started Jun 29 05:54:58 PM PDT 24
Finished Jun 29 06:20:01 PM PDT 24
Peak memory 281732 kb
Host smart-8b927ef4-3719-4889-85a8-91f928c9f473
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258764139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3258764139
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1551499208
Short name T126
Test name
Test status
Simulation time 1310836473 ps
CPU time 28.76 seconds
Started Jun 29 05:54:52 PM PDT 24
Finished Jun 29 05:55:21 PM PDT 24
Peak memory 257036 kb
Host smart-5953d160-fe8a-4100-8825-545a07c558f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15514
99208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1551499208
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.414756891
Short name T20
Test name
Test status
Simulation time 3057862602 ps
CPU time 51 seconds
Started Jun 29 05:54:51 PM PDT 24
Finished Jun 29 05:55:42 PM PDT 24
Peak memory 257108 kb
Host smart-86e8c81e-4563-48af-9f8e-060a883e33c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41475
6891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.414756891
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1132378873
Short name T341
Test name
Test status
Simulation time 144649291533 ps
CPU time 2052.8 seconds
Started Jun 29 05:54:59 PM PDT 24
Finished Jun 29 06:29:12 PM PDT 24
Peak memory 273268 kb
Host smart-fc6607ff-4997-44bd-bdb4-284e8066dd60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132378873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1132378873
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2683627513
Short name T360
Test name
Test status
Simulation time 397301934031 ps
CPU time 2526.5 seconds
Started Jun 29 05:54:58 PM PDT 24
Finished Jun 29 06:37:06 PM PDT 24
Peak memory 285964 kb
Host smart-dcf31448-485e-46fe-a058-e09211c7aca4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683627513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2683627513
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2340571741
Short name T297
Test name
Test status
Simulation time 13603854848 ps
CPU time 557.42 seconds
Started Jun 29 05:54:59 PM PDT 24
Finished Jun 29 06:04:17 PM PDT 24
Peak memory 249356 kb
Host smart-8849a211-eaf1-4326-8716-897353e7f958
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340571741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2340571741
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.219286155
Short name T353
Test name
Test status
Simulation time 704314812 ps
CPU time 44.08 seconds
Started Jun 29 05:54:50 PM PDT 24
Finished Jun 29 05:55:35 PM PDT 24
Peak memory 257412 kb
Host smart-aea1b3c9-1980-4cfc-81a1-c7602a479ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21928
6155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.219286155
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1678881701
Short name T41
Test name
Test status
Simulation time 654394698 ps
CPU time 42.01 seconds
Started Jun 29 05:54:49 PM PDT 24
Finished Jun 29 05:55:32 PM PDT 24
Peak memory 248792 kb
Host smart-684d9850-4be8-4ff6-bcc1-331fa536bb97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16788
81701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1678881701
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.779397775
Short name T640
Test name
Test status
Simulation time 428456438 ps
CPU time 26.84 seconds
Started Jun 29 05:54:52 PM PDT 24
Finished Jun 29 05:55:19 PM PDT 24
Peak memory 256992 kb
Host smart-74841dcf-7602-45f1-b3dc-6ebfe9f57634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77939
7775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.779397775
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3111714541
Short name T372
Test name
Test status
Simulation time 760079111 ps
CPU time 26.25 seconds
Started Jun 29 05:54:51 PM PDT 24
Finished Jun 29 05:55:18 PM PDT 24
Peak memory 257256 kb
Host smart-3b896921-8aca-4023-ad17-74c57d1db98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31117
14541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3111714541
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3780724515
Short name T411
Test name
Test status
Simulation time 32348023850 ps
CPU time 2152.94 seconds
Started Jun 29 05:55:08 PM PDT 24
Finished Jun 29 06:31:01 PM PDT 24
Peak memory 285320 kb
Host smart-3b718040-12c5-4973-b7fc-23242cfaf7ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780724515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3780724515
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.4236792268
Short name T379
Test name
Test status
Simulation time 4355592644 ps
CPU time 116.22 seconds
Started Jun 29 05:55:08 PM PDT 24
Finished Jun 29 05:57:05 PM PDT 24
Peak memory 256896 kb
Host smart-e0a97c2a-2422-4718-b172-2bbbf968f1e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42367
92268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.4236792268
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2403495318
Short name T553
Test name
Test status
Simulation time 287437648 ps
CPU time 10.35 seconds
Started Jun 29 05:55:09 PM PDT 24
Finished Jun 29 05:55:20 PM PDT 24
Peak memory 248840 kb
Host smart-4f37ad84-2543-4686-9598-fc9e06a5ec61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24034
95318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2403495318
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1681754049
Short name T630
Test name
Test status
Simulation time 41890261336 ps
CPU time 2451.63 seconds
Started Jun 29 05:55:08 PM PDT 24
Finished Jun 29 06:36:00 PM PDT 24
Peak memory 283672 kb
Host smart-67b4a250-7660-465c-a495-6738d0a6cac1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681754049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1681754049
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1549846198
Short name T678
Test name
Test status
Simulation time 53458863065 ps
CPU time 829.59 seconds
Started Jun 29 05:55:17 PM PDT 24
Finished Jun 29 06:09:07 PM PDT 24
Peak memory 273920 kb
Host smart-24cd6805-71a2-4232-b0cd-42622ba291ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549846198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1549846198
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3524282304
Short name T611
Test name
Test status
Simulation time 5718254990 ps
CPU time 242.18 seconds
Started Jun 29 05:55:08 PM PDT 24
Finished Jun 29 05:59:11 PM PDT 24
Peak memory 255932 kb
Host smart-dc5699ab-940d-4d4a-8607-23c089799240
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524282304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3524282304
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1278606434
Short name T621
Test name
Test status
Simulation time 999462954 ps
CPU time 59.21 seconds
Started Jun 29 05:54:58 PM PDT 24
Finished Jun 29 05:55:58 PM PDT 24
Peak memory 256816 kb
Host smart-81144486-c399-4bac-a0d8-d4ded3f3bd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12786
06434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1278606434
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2440148884
Short name T597
Test name
Test status
Simulation time 131235921 ps
CPU time 9.21 seconds
Started Jun 29 05:54:58 PM PDT 24
Finished Jun 29 05:55:08 PM PDT 24
Peak memory 248820 kb
Host smart-7952ea18-108d-4dce-baaf-48b0cf508163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24401
48884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2440148884
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1926642334
Short name T256
Test name
Test status
Simulation time 382529633 ps
CPU time 7 seconds
Started Jun 29 05:55:10 PM PDT 24
Finished Jun 29 05:55:17 PM PDT 24
Peak memory 248472 kb
Host smart-cf80fb99-98be-48b6-a6cf-428b2357dfa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19266
42334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1926642334
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3717405220
Short name T364
Test name
Test status
Simulation time 285807408 ps
CPU time 22.74 seconds
Started Jun 29 05:55:01 PM PDT 24
Finished Jun 29 05:55:24 PM PDT 24
Peak memory 256744 kb
Host smart-7eb40eef-9419-468e-a7c0-f96c27eb0f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37174
05220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3717405220
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2994842945
Short name T48
Test name
Test status
Simulation time 56727761437 ps
CPU time 3029.43 seconds
Started Jun 29 05:55:18 PM PDT 24
Finished Jun 29 06:45:48 PM PDT 24
Peak memory 289728 kb
Host smart-fd8f52a5-569f-4f64-a703-0f64e7cd01d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994842945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2994842945
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.4061845251
Short name T430
Test name
Test status
Simulation time 130935813197 ps
CPU time 2061.14 seconds
Started Jun 29 05:55:24 PM PDT 24
Finished Jun 29 06:29:46 PM PDT 24
Peak memory 287724 kb
Host smart-8d8077f1-1ca0-482e-a131-f13464baafdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061845251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4061845251
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3063544227
Short name T543
Test name
Test status
Simulation time 1960245768 ps
CPU time 174.67 seconds
Started Jun 29 05:55:19 PM PDT 24
Finished Jun 29 05:58:14 PM PDT 24
Peak memory 256740 kb
Host smart-bf39f87b-b3c2-4ec2-a10c-d4fb1091c177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30635
44227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3063544227
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2822333631
Short name T228
Test name
Test status
Simulation time 1186966295 ps
CPU time 34.34 seconds
Started Jun 29 05:55:17 PM PDT 24
Finished Jun 29 05:55:52 PM PDT 24
Peak memory 257352 kb
Host smart-5c3adc32-e8ba-48df-95d4-d858c03e979b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28223
33631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2822333631
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.4043881525
Short name T618
Test name
Test status
Simulation time 126463557853 ps
CPU time 1609.83 seconds
Started Jun 29 05:55:25 PM PDT 24
Finished Jun 29 06:22:16 PM PDT 24
Peak memory 273932 kb
Host smart-82ae784a-3ba7-4f9a-b17c-2846c65cb0f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043881525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.4043881525
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.864720765
Short name T562
Test name
Test status
Simulation time 36938823341 ps
CPU time 882.92 seconds
Started Jun 29 05:55:25 PM PDT 24
Finished Jun 29 06:10:08 PM PDT 24
Peak memory 268736 kb
Host smart-c1bd429e-c9a8-4ba5-a588-5d57408ad94a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864720765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.864720765
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2734468467
Short name T73
Test name
Test status
Simulation time 4863406744 ps
CPU time 101.93 seconds
Started Jun 29 05:55:25 PM PDT 24
Finished Jun 29 05:57:07 PM PDT 24
Peak memory 249448 kb
Host smart-c9e43a1c-10ab-4e85-a1f1-0baa5a058734
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734468467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2734468467
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1884184916
Short name T614
Test name
Test status
Simulation time 1776793107 ps
CPU time 49.37 seconds
Started Jun 29 05:55:17 PM PDT 24
Finished Jun 29 05:56:06 PM PDT 24
Peak memory 257424 kb
Host smart-6b54574b-69d2-4557-927d-e989faa10ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18841
84916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1884184916
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2821262573
Short name T115
Test name
Test status
Simulation time 1419537222 ps
CPU time 26.26 seconds
Started Jun 29 05:55:18 PM PDT 24
Finished Jun 29 05:55:44 PM PDT 24
Peak memory 256176 kb
Host smart-444b78a0-390f-4729-9f06-de441b9201e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28212
62573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2821262573
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3393660562
Short name T128
Test name
Test status
Simulation time 1485667200 ps
CPU time 25.64 seconds
Started Jun 29 05:55:24 PM PDT 24
Finished Jun 29 05:55:50 PM PDT 24
Peak memory 256980 kb
Host smart-f2735b67-5cb6-4200-a987-5c1cb91d1534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33936
60562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3393660562
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.176613885
Short name T384
Test name
Test status
Simulation time 582412675 ps
CPU time 18.97 seconds
Started Jun 29 05:55:18 PM PDT 24
Finished Jun 29 05:55:37 PM PDT 24
Peak memory 256448 kb
Host smart-e4d3cddc-b5c3-423a-a6b2-b014691e00f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17661
3885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.176613885
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2498045823
Short name T675
Test name
Test status
Simulation time 49830040084 ps
CPU time 1516.27 seconds
Started Jun 29 05:55:26 PM PDT 24
Finished Jun 29 06:20:42 PM PDT 24
Peak memory 290148 kb
Host smart-81fde16b-d583-4fd5-a690-9e283a2408bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498045823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2498045823
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2758539253
Short name T546
Test name
Test status
Simulation time 31796440186 ps
CPU time 1919.7 seconds
Started Jun 29 05:55:32 PM PDT 24
Finished Jun 29 06:27:32 PM PDT 24
Peak memory 272608 kb
Host smart-8941fb1a-9fde-443a-a49c-efa738bed13a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758539253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2758539253
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.908680201
Short name T381
Test name
Test status
Simulation time 4257477470 ps
CPU time 77.38 seconds
Started Jun 29 05:55:25 PM PDT 24
Finished Jun 29 05:56:43 PM PDT 24
Peak memory 257584 kb
Host smart-2a487561-4128-4cd8-8083-7630d85e81e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90868
0201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.908680201
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.101894181
Short name T499
Test name
Test status
Simulation time 1112061752 ps
CPU time 28.13 seconds
Started Jun 29 05:55:26 PM PDT 24
Finished Jun 29 05:55:55 PM PDT 24
Peak memory 248684 kb
Host smart-01eb6f59-5ae1-49dd-9b9a-6b69d959c6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10189
4181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.101894181
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.378303361
Short name T293
Test name
Test status
Simulation time 11488029237 ps
CPU time 973.47 seconds
Started Jun 29 05:55:33 PM PDT 24
Finished Jun 29 06:11:47 PM PDT 24
Peak memory 273520 kb
Host smart-f19abe6b-f30b-413e-945a-0b2c0bcada50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378303361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.378303361
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3453892761
Short name T274
Test name
Test status
Simulation time 33377284688 ps
CPU time 2005.01 seconds
Started Jun 29 05:55:34 PM PDT 24
Finished Jun 29 06:28:59 PM PDT 24
Peak memory 283884 kb
Host smart-b5d95500-78e4-45d3-9f9d-825bd9b23b85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453892761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3453892761
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2268946211
Short name T317
Test name
Test status
Simulation time 2304056729 ps
CPU time 97.97 seconds
Started Jun 29 05:55:34 PM PDT 24
Finished Jun 29 05:57:12 PM PDT 24
Peak memory 249396 kb
Host smart-56bc2fd0-b34f-44cf-ad2c-0f918681c106
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268946211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2268946211
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.4255129516
Short name T448
Test name
Test status
Simulation time 915543478 ps
CPU time 64.29 seconds
Started Jun 29 05:55:24 PM PDT 24
Finished Jun 29 05:56:28 PM PDT 24
Peak memory 249244 kb
Host smart-3d128f94-22dc-444f-962f-a51914743d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42551
29516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.4255129516
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2867210995
Short name T537
Test name
Test status
Simulation time 432141863 ps
CPU time 27.43 seconds
Started Jun 29 05:55:26 PM PDT 24
Finished Jun 29 05:55:54 PM PDT 24
Peak memory 248828 kb
Host smart-45596bcc-b114-4264-9a67-000d2a8428c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28672
10995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2867210995
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3528240187
Short name T549
Test name
Test status
Simulation time 1622894177 ps
CPU time 37.13 seconds
Started Jun 29 05:55:26 PM PDT 24
Finished Jun 29 05:56:03 PM PDT 24
Peak memory 248684 kb
Host smart-e580eeaf-cf6d-48c6-b598-f892256eb705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35282
40187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3528240187
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3360115054
Short name T462
Test name
Test status
Simulation time 863770725 ps
CPU time 18.17 seconds
Started Jun 29 05:55:24 PM PDT 24
Finished Jun 29 05:55:43 PM PDT 24
Peak memory 249220 kb
Host smart-c5155b8f-c3c6-4013-b11c-43c7743b284c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33601
15054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3360115054
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3254044179
Short name T119
Test name
Test status
Simulation time 25534086677 ps
CPU time 1025.93 seconds
Started Jun 29 05:55:40 PM PDT 24
Finished Jun 29 06:12:46 PM PDT 24
Peak memory 284288 kb
Host smart-3bbaed19-2d53-46ef-981e-e287b5f9e03e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254044179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3254044179
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3240736159
Short name T467
Test name
Test status
Simulation time 1605340594 ps
CPU time 104.55 seconds
Started Jun 29 05:55:44 PM PDT 24
Finished Jun 29 05:57:29 PM PDT 24
Peak memory 257272 kb
Host smart-ef79dd06-a8e6-4b48-b9a5-2c92716fb3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32407
36159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3240736159
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.438121423
Short name T685
Test name
Test status
Simulation time 361294160 ps
CPU time 38.8 seconds
Started Jun 29 05:55:43 PM PDT 24
Finished Jun 29 05:56:23 PM PDT 24
Peak memory 249096 kb
Host smart-ef2fd676-68cb-4b7d-baf5-c722859defa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43812
1423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.438121423
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.4168750957
Short name T332
Test name
Test status
Simulation time 19326633163 ps
CPU time 1504.93 seconds
Started Jun 29 05:55:47 PM PDT 24
Finished Jun 29 06:20:53 PM PDT 24
Peak memory 288840 kb
Host smart-efa81a85-fd3a-406d-b010-0cf81cc7f5c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168750957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.4168750957
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1342106287
Short name T550
Test name
Test status
Simulation time 33317445075 ps
CPU time 2041.29 seconds
Started Jun 29 05:55:50 PM PDT 24
Finished Jun 29 06:29:52 PM PDT 24
Peak memory 274000 kb
Host smart-e7ceda02-5814-4fe4-a18e-4f7c8576af95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342106287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1342106287
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2743390100
Short name T312
Test name
Test status
Simulation time 19646954032 ps
CPU time 217.33 seconds
Started Jun 29 05:55:48 PM PDT 24
Finished Jun 29 05:59:26 PM PDT 24
Peak memory 248456 kb
Host smart-7092b646-ff40-4072-9e25-d885093da8c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743390100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2743390100
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2035569852
Short name T285
Test name
Test status
Simulation time 138954183 ps
CPU time 10.48 seconds
Started Jun 29 05:55:42 PM PDT 24
Finished Jun 29 05:55:52 PM PDT 24
Peak memory 249228 kb
Host smart-490f8448-4abb-4fe7-98c4-e52c485fea0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20355
69852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2035569852
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.951043704
Short name T556
Test name
Test status
Simulation time 1210653819 ps
CPU time 19.65 seconds
Started Jun 29 05:55:41 PM PDT 24
Finished Jun 29 05:56:01 PM PDT 24
Peak memory 255052 kb
Host smart-6593e9d0-8d97-47fd-af28-1d9b7d7f7a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95104
3704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.951043704
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.459872138
Short name T604
Test name
Test status
Simulation time 324726602 ps
CPU time 17.02 seconds
Started Jun 29 05:55:40 PM PDT 24
Finished Jun 29 05:55:58 PM PDT 24
Peak memory 256284 kb
Host smart-4ffc93ff-aaae-4407-99a5-41ae15f9f728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45987
2138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.459872138
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3594916488
Short name T130
Test name
Test status
Simulation time 2544431804 ps
CPU time 37.92 seconds
Started Jun 29 05:55:44 PM PDT 24
Finished Jun 29 05:56:22 PM PDT 24
Peak memory 257340 kb
Host smart-b926bb2a-49ea-46c2-9256-1bd399205b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35949
16488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3594916488
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.158956286
Short name T465
Test name
Test status
Simulation time 16292846405 ps
CPU time 1384.22 seconds
Started Jun 29 05:55:46 PM PDT 24
Finished Jun 29 06:18:51 PM PDT 24
Peak memory 289616 kb
Host smart-848e0a31-f616-4894-8c11-dbe95646bc7b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158956286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.158956286
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3898087604
Short name T527
Test name
Test status
Simulation time 17921036993 ps
CPU time 1739.72 seconds
Started Jun 29 05:55:55 PM PDT 24
Finished Jun 29 06:24:56 PM PDT 24
Peak memory 290108 kb
Host smart-748ee26d-846b-44e7-84d3-cc43bf599818
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898087604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3898087604
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1262969651
Short name T588
Test name
Test status
Simulation time 3616292466 ps
CPU time 52.61 seconds
Started Jun 29 05:55:57 PM PDT 24
Finished Jun 29 05:56:50 PM PDT 24
Peak memory 248968 kb
Host smart-0d744186-c57b-49fe-bbd4-8300fb477240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12629
69651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1262969651
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.4139255514
Short name T363
Test name
Test status
Simulation time 954412190 ps
CPU time 25.68 seconds
Started Jun 29 05:55:57 PM PDT 24
Finished Jun 29 05:56:23 PM PDT 24
Peak memory 248964 kb
Host smart-43187827-5b56-4b25-8a3c-e0804bf8793a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41392
55514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.4139255514
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.4048540561
Short name T620
Test name
Test status
Simulation time 25398433497 ps
CPU time 1388.18 seconds
Started Jun 29 05:55:59 PM PDT 24
Finished Jun 29 06:19:08 PM PDT 24
Peak memory 274124 kb
Host smart-1650728f-7000-4b07-92be-bc709ed3989a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048540561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.4048540561
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1760165457
Short name T590
Test name
Test status
Simulation time 44022083527 ps
CPU time 2520.1 seconds
Started Jun 29 05:55:56 PM PDT 24
Finished Jun 29 06:37:57 PM PDT 24
Peak memory 284172 kb
Host smart-4cbfe23d-f736-4189-b98b-a07ba7bc585e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760165457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1760165457
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2525087174
Short name T99
Test name
Test status
Simulation time 164174820920 ps
CPU time 343.33 seconds
Started Jun 29 05:55:57 PM PDT 24
Finished Jun 29 06:01:41 PM PDT 24
Peak memory 256368 kb
Host smart-9be818bc-a228-43d4-8391-7b68d63b37b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525087174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2525087174
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.782747037
Short name T392
Test name
Test status
Simulation time 546418181 ps
CPU time 34.6 seconds
Started Jun 29 05:55:58 PM PDT 24
Finished Jun 29 05:56:33 PM PDT 24
Peak memory 249332 kb
Host smart-fa238268-e0c7-4d66-937e-e2c77087301e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78274
7037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.782747037
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3520823445
Short name T665
Test name
Test status
Simulation time 1879541087 ps
CPU time 43.32 seconds
Started Jun 29 05:55:55 PM PDT 24
Finished Jun 29 05:56:39 PM PDT 24
Peak memory 250328 kb
Host smart-49a4a318-dd1a-43f6-a9f9-bab27c3cddcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35208
23445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3520823445
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.101665544
Short name T668
Test name
Test status
Simulation time 949164606 ps
CPU time 28.54 seconds
Started Jun 29 05:55:56 PM PDT 24
Finished Jun 29 05:56:25 PM PDT 24
Peak memory 256800 kb
Host smart-d8838767-ee90-4c47-a450-8577b8a29a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10166
5544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.101665544
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3945964586
Short name T33
Test name
Test status
Simulation time 705088243 ps
CPU time 35.07 seconds
Started Jun 29 05:55:55 PM PDT 24
Finished Jun 29 05:56:31 PM PDT 24
Peak memory 257128 kb
Host smart-0eb07924-b9cd-4fb1-8ee7-aa6059b73b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39459
64586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3945964586
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3679290044
Short name T112
Test name
Test status
Simulation time 33401722528 ps
CPU time 1690.74 seconds
Started Jun 29 05:56:05 PM PDT 24
Finished Jun 29 06:24:16 PM PDT 24
Peak memory 290324 kb
Host smart-2570c85e-7b5c-43f9-85be-d977eb917d15
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679290044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3679290044
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3155829780
Short name T479
Test name
Test status
Simulation time 5197961590 ps
CPU time 53.35 seconds
Started Jun 29 05:56:03 PM PDT 24
Finished Jun 29 05:56:56 PM PDT 24
Peak memory 257376 kb
Host smart-bf531b57-6731-4539-8e4f-49a23a1a22e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31558
29780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3155829780
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.4093914482
Short name T532
Test name
Test status
Simulation time 246526127 ps
CPU time 7.98 seconds
Started Jun 29 05:56:04 PM PDT 24
Finished Jun 29 05:56:12 PM PDT 24
Peak memory 248844 kb
Host smart-634eef35-9854-4c4c-b632-7b7585bf14eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40939
14482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4093914482
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1216412178
Short name T331
Test name
Test status
Simulation time 73775253526 ps
CPU time 1657.95 seconds
Started Jun 29 05:56:12 PM PDT 24
Finished Jun 29 06:23:51 PM PDT 24
Peak memory 289928 kb
Host smart-a6fbdc6d-5e4b-4371-9b8c-e28440f5e03d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216412178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1216412178
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3993773668
Short name T579
Test name
Test status
Simulation time 12420503623 ps
CPU time 1437.33 seconds
Started Jun 29 05:56:12 PM PDT 24
Finished Jun 29 06:20:09 PM PDT 24
Peak memory 290180 kb
Host smart-1481b7a9-e27b-44f3-a847-9a5bf5b1c786
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993773668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3993773668
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1938706212
Short name T696
Test name
Test status
Simulation time 15301110442 ps
CPU time 178.81 seconds
Started Jun 29 05:56:12 PM PDT 24
Finished Jun 29 05:59:11 PM PDT 24
Peak memory 249392 kb
Host smart-2e65bbfa-8a0e-46bd-95e5-7d22fad08d50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938706212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1938706212
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3967299234
Short name T510
Test name
Test status
Simulation time 553868944 ps
CPU time 37.51 seconds
Started Jun 29 05:56:03 PM PDT 24
Finished Jun 29 05:56:41 PM PDT 24
Peak memory 257224 kb
Host smart-315b7c28-f6db-40dc-ac2a-7225a7ff1d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39672
99234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3967299234
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2075927986
Short name T529
Test name
Test status
Simulation time 1967705618 ps
CPU time 43.4 seconds
Started Jun 29 05:56:04 PM PDT 24
Finished Jun 29 05:56:48 PM PDT 24
Peak memory 256688 kb
Host smart-59982137-62fa-4770-91d5-18191b87fe26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20759
27986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2075927986
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.475726316
Short name T53
Test name
Test status
Simulation time 936796469 ps
CPU time 19.99 seconds
Started Jun 29 05:56:07 PM PDT 24
Finished Jun 29 05:56:27 PM PDT 24
Peak memory 248612 kb
Host smart-2328b2e5-4447-4f5e-8f8c-689346507057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47572
6316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.475726316
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3501660701
Short name T535
Test name
Test status
Simulation time 1129915610 ps
CPU time 61.71 seconds
Started Jun 29 05:56:04 PM PDT 24
Finished Jun 29 05:57:06 PM PDT 24
Peak memory 249304 kb
Host smart-84e1b022-4a1d-430c-8e2e-0d5d28a17330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35016
60701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3501660701
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3023424297
Short name T263
Test name
Test status
Simulation time 19869029891 ps
CPU time 1152.31 seconds
Started Jun 29 05:56:13 PM PDT 24
Finished Jun 29 06:15:26 PM PDT 24
Peak memory 282812 kb
Host smart-5436c6d3-caf4-42ca-bea7-472d33758c17
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023424297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3023424297
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.448175827
Short name T232
Test name
Test status
Simulation time 36030498062 ps
CPU time 2350.95 seconds
Started Jun 29 05:56:18 PM PDT 24
Finished Jun 29 06:35:30 PM PDT 24
Peak memory 287236 kb
Host smart-96a481a5-ee53-4367-8ef9-1583720f1aa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448175827 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.448175827
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.340517575
Short name T206
Test name
Test status
Simulation time 112602082 ps
CPU time 3.55 seconds
Started Jun 29 05:51:55 PM PDT 24
Finished Jun 29 05:51:59 PM PDT 24
Peak memory 249532 kb
Host smart-1ff2ef0a-aafa-446c-9fea-1aef0da2ee9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=340517575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.340517575
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3141567909
Short name T635
Test name
Test status
Simulation time 513333671771 ps
CPU time 2298.92 seconds
Started Jun 29 05:51:56 PM PDT 24
Finished Jun 29 06:30:16 PM PDT 24
Peak memory 284964 kb
Host smart-4de22d8d-c961-4d8d-9579-be82a3793c3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141567909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3141567909
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3538941871
Short name T516
Test name
Test status
Simulation time 545613149 ps
CPU time 9.52 seconds
Started Jun 29 05:51:55 PM PDT 24
Finished Jun 29 05:52:05 PM PDT 24
Peak memory 249220 kb
Host smart-ba4cf92c-583a-437f-8dc5-738770700340
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3538941871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3538941871
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.454929301
Short name T619
Test name
Test status
Simulation time 5253118343 ps
CPU time 296.02 seconds
Started Jun 29 05:51:56 PM PDT 24
Finished Jun 29 05:56:52 PM PDT 24
Peak memory 257124 kb
Host smart-718f4d67-30a0-4576-b9db-ba6d94bc92cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45492
9301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.454929301
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.682249241
Short name T262
Test name
Test status
Simulation time 1617301285 ps
CPU time 22.57 seconds
Started Jun 29 05:51:57 PM PDT 24
Finished Jun 29 05:52:19 PM PDT 24
Peak memory 248920 kb
Host smart-8ae0fc42-8c88-4f4e-94de-ccb640eadf6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68224
9241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.682249241
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.4224082678
Short name T68
Test name
Test status
Simulation time 57471942643 ps
CPU time 3535.3 seconds
Started Jun 29 05:51:59 PM PDT 24
Finished Jun 29 06:50:55 PM PDT 24
Peak memory 290376 kb
Host smart-b89f2f7e-06a8-4308-a9f8-aabcb7a7d0be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224082678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4224082678
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.891759741
Short name T303
Test name
Test status
Simulation time 14584104821 ps
CPU time 322.64 seconds
Started Jun 29 05:51:58 PM PDT 24
Finished Jun 29 05:57:21 PM PDT 24
Peak memory 249380 kb
Host smart-39ac7928-09c0-49a7-ab7b-d3e8a698320c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891759741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.891759741
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.745877850
Short name T664
Test name
Test status
Simulation time 95672359 ps
CPU time 7.16 seconds
Started Jun 29 05:51:59 PM PDT 24
Finished Jun 29 05:52:06 PM PDT 24
Peak memory 249288 kb
Host smart-06548836-2e4c-4431-878a-ab70c2547454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74587
7850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.745877850
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2386442112
Short name T365
Test name
Test status
Simulation time 1452470209 ps
CPU time 21.17 seconds
Started Jun 29 05:51:56 PM PDT 24
Finished Jun 29 05:52:18 PM PDT 24
Peak memory 249308 kb
Host smart-7f571d44-bfa2-4969-8f49-9551a2e01b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23864
42112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2386442112
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2075813500
Short name T31
Test name
Test status
Simulation time 353757552 ps
CPU time 11.7 seconds
Started Jun 29 05:51:57 PM PDT 24
Finished Jun 29 05:52:09 PM PDT 24
Peak memory 272240 kb
Host smart-200cb16a-e5cf-4166-a496-18eeabb96f9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2075813500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2075813500
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.365460191
Short name T265
Test name
Test status
Simulation time 481462165 ps
CPU time 17.36 seconds
Started Jun 29 05:51:59 PM PDT 24
Finished Jun 29 05:52:17 PM PDT 24
Peak memory 256692 kb
Host smart-1a2c2f20-80a8-4f05-b2ea-b7cfb2970cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36546
0191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.365460191
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2620396767
Short name T519
Test name
Test status
Simulation time 1201360190 ps
CPU time 25.97 seconds
Started Jun 29 05:51:59 PM PDT 24
Finished Jun 29 05:52:25 PM PDT 24
Peak memory 257476 kb
Host smart-2c7bc4e0-2541-4df3-a7f7-b9cc3ea44e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26203
96767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2620396767
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2666314764
Short name T521
Test name
Test status
Simulation time 61075993 ps
CPU time 6.12 seconds
Started Jun 29 05:51:58 PM PDT 24
Finished Jun 29 05:52:04 PM PDT 24
Peak memory 253184 kb
Host smart-51ad853d-f107-4792-a11a-59ccf6cbc224
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666314764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2666314764
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.841400929
Short name T484
Test name
Test status
Simulation time 189711529007 ps
CPU time 2337.11 seconds
Started Jun 29 05:56:19 PM PDT 24
Finished Jun 29 06:35:17 PM PDT 24
Peak memory 272964 kb
Host smart-84f7787d-afc0-4fba-b8d6-4f61ae8a13fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841400929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.841400929
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2983536440
Short name T504
Test name
Test status
Simulation time 6866726791 ps
CPU time 143.36 seconds
Started Jun 29 05:56:19 PM PDT 24
Finished Jun 29 05:58:43 PM PDT 24
Peak memory 257620 kb
Host smart-6380c254-0c92-426e-91ed-8f7bce58c496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29835
36440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2983536440
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1957259373
Short name T401
Test name
Test status
Simulation time 761529437 ps
CPU time 46.65 seconds
Started Jun 29 05:56:19 PM PDT 24
Finished Jun 29 05:57:06 PM PDT 24
Peak memory 256940 kb
Host smart-c5fe6b21-a6c6-437c-8717-bd15408a7ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19572
59373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1957259373
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.734130265
Short name T450
Test name
Test status
Simulation time 6642699034 ps
CPU time 717.98 seconds
Started Jun 29 05:56:19 PM PDT 24
Finished Jun 29 06:08:18 PM PDT 24
Peak memory 273196 kb
Host smart-2d333bfd-50c3-4cab-895d-dc1d9f58be3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734130265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.734130265
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3976969354
Short name T489
Test name
Test status
Simulation time 90368569411 ps
CPU time 1654.27 seconds
Started Jun 29 05:56:19 PM PDT 24
Finished Jun 29 06:23:54 PM PDT 24
Peak memory 273348 kb
Host smart-4f1f659f-dfa4-4cac-8008-6cf5daed5830
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976969354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3976969354
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2143479897
Short name T29
Test name
Test status
Simulation time 37747082249 ps
CPU time 492.18 seconds
Started Jun 29 05:56:20 PM PDT 24
Finished Jun 29 06:04:32 PM PDT 24
Peak memory 249132 kb
Host smart-dc28769e-5249-4f6e-99c2-d85c788e6b2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143479897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2143479897
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3559943700
Short name T279
Test name
Test status
Simulation time 567098007 ps
CPU time 33.37 seconds
Started Jun 29 05:56:18 PM PDT 24
Finished Jun 29 05:56:52 PM PDT 24
Peak memory 256604 kb
Host smart-f1f884ee-49ef-4ef1-b0cb-31c3afe977ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35599
43700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3559943700
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2396222147
Short name T581
Test name
Test status
Simulation time 505931897 ps
CPU time 17.72 seconds
Started Jun 29 05:56:21 PM PDT 24
Finished Jun 29 05:56:39 PM PDT 24
Peak memory 249328 kb
Host smart-b58d8a05-edc9-4f16-97ef-f6edd3d92dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23962
22147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2396222147
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2022047081
Short name T491
Test name
Test status
Simulation time 197437240 ps
CPU time 6.54 seconds
Started Jun 29 05:56:22 PM PDT 24
Finished Jun 29 05:56:29 PM PDT 24
Peak memory 252132 kb
Host smart-593b6a79-723e-4985-9883-7d19de0e1394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20220
47081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2022047081
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.210671522
Short name T60
Test name
Test status
Simulation time 17404699285 ps
CPU time 1638.14 seconds
Started Jun 29 05:56:19 PM PDT 24
Finished Jun 29 06:23:37 PM PDT 24
Peak memory 289628 kb
Host smart-2fb86a79-462b-4791-bf6d-fd686d94d2c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210671522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.210671522
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3509850495
Short name T245
Test name
Test status
Simulation time 226722523785 ps
CPU time 4030.64 seconds
Started Jun 29 05:56:28 PM PDT 24
Finished Jun 29 07:03:39 PM PDT 24
Peak memory 306004 kb
Host smart-2d2a7eed-d23b-43ed-8161-f1bca1b5c49c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509850495 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3509850495
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3010648534
Short name T405
Test name
Test status
Simulation time 26882853022 ps
CPU time 1632.76 seconds
Started Jun 29 05:56:35 PM PDT 24
Finished Jun 29 06:23:48 PM PDT 24
Peak memory 273844 kb
Host smart-b94d265e-58e3-4e77-b955-67a22d6db38d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010648534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3010648534
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2867852757
Short name T607
Test name
Test status
Simulation time 1135975102 ps
CPU time 96.89 seconds
Started Jun 29 05:56:35 PM PDT 24
Finished Jun 29 05:58:13 PM PDT 24
Peak memory 256988 kb
Host smart-2346b58f-a47b-46fb-83e4-53d221a3cbf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28678
52757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2867852757
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3214342501
Short name T512
Test name
Test status
Simulation time 987796488 ps
CPU time 34.32 seconds
Started Jun 29 05:56:28 PM PDT 24
Finished Jun 29 05:57:03 PM PDT 24
Peak memory 249148 kb
Host smart-d163057a-df74-4e35-bbfe-747155e1d666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32143
42501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3214342501
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.201849885
Short name T325
Test name
Test status
Simulation time 17494529952 ps
CPU time 1315.16 seconds
Started Jun 29 05:56:36 PM PDT 24
Finished Jun 29 06:18:32 PM PDT 24
Peak memory 285584 kb
Host smart-d0ae1fa8-e54d-4500-8261-6e6c64761a11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201849885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.201849885
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1297653995
Short name T440
Test name
Test status
Simulation time 28775864557 ps
CPU time 1706.61 seconds
Started Jun 29 05:56:35 PM PDT 24
Finished Jun 29 06:25:02 PM PDT 24
Peak memory 269904 kb
Host smart-17c37776-3a08-4379-be64-c87ef30c34cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297653995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1297653995
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.409887518
Short name T298
Test name
Test status
Simulation time 13199148800 ps
CPU time 548.23 seconds
Started Jun 29 05:56:37 PM PDT 24
Finished Jun 29 06:05:45 PM PDT 24
Peak memory 255772 kb
Host smart-501e7807-4992-4e8a-8ff2-596bb68566bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409887518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.409887518
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2979956252
Short name T563
Test name
Test status
Simulation time 2226024188 ps
CPU time 76.32 seconds
Started Jun 29 05:56:29 PM PDT 24
Finished Jun 29 05:57:45 PM PDT 24
Peak memory 256976 kb
Host smart-b6726ce7-9bc8-412b-a607-ff6de4492b90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29799
56252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2979956252
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3746007267
Short name T552
Test name
Test status
Simulation time 636081186 ps
CPU time 7.54 seconds
Started Jun 29 05:56:27 PM PDT 24
Finished Jun 29 05:56:35 PM PDT 24
Peak memory 249316 kb
Host smart-a7257a96-ba23-4be5-9229-a824eb20f373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37460
07267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3746007267
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3031522873
Short name T419
Test name
Test status
Simulation time 792263523 ps
CPU time 52.73 seconds
Started Jun 29 05:56:27 PM PDT 24
Finished Jun 29 05:57:20 PM PDT 24
Peak memory 249260 kb
Host smart-b57c4c6b-4fcd-45fe-b7a8-3cc1723227ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30315
22873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3031522873
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2285676761
Short name T508
Test name
Test status
Simulation time 26603398794 ps
CPU time 1686.53 seconds
Started Jun 29 05:56:50 PM PDT 24
Finished Jun 29 06:24:57 PM PDT 24
Peak memory 289260 kb
Host smart-897aa063-3c04-402c-b78a-233b4c1f2978
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285676761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2285676761
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3975662229
Short name T393
Test name
Test status
Simulation time 5337168538 ps
CPU time 114.5 seconds
Started Jun 29 05:56:44 PM PDT 24
Finished Jun 29 05:58:39 PM PDT 24
Peak memory 257616 kb
Host smart-23926889-cb33-4b13-bf41-39653c2f970f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39756
62229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3975662229
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1729395086
Short name T253
Test name
Test status
Simulation time 307899551 ps
CPU time 19.67 seconds
Started Jun 29 05:56:43 PM PDT 24
Finished Jun 29 05:57:03 PM PDT 24
Peak memory 257496 kb
Host smart-31e060e2-52bf-4b49-9e7d-d4b9828b71d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17293
95086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1729395086
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.251258304
Short name T691
Test name
Test status
Simulation time 12292178845 ps
CPU time 1046.39 seconds
Started Jun 29 05:56:58 PM PDT 24
Finished Jun 29 06:14:24 PM PDT 24
Peak memory 290268 kb
Host smart-519ade4c-8c7d-4b75-90ed-2bcf917e9ad4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251258304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.251258304
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.338198615
Short name T355
Test name
Test status
Simulation time 68582821385 ps
CPU time 2163.47 seconds
Started Jun 29 05:56:59 PM PDT 24
Finished Jun 29 06:33:04 PM PDT 24
Peak memory 273920 kb
Host smart-ef639264-e189-497b-8759-1c42913f9e42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338198615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.338198615
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1764200873
Short name T5
Test name
Test status
Simulation time 33310893295 ps
CPU time 387.5 seconds
Started Jun 29 05:56:50 PM PDT 24
Finished Jun 29 06:03:18 PM PDT 24
Peak memory 249124 kb
Host smart-28c19571-ac8a-4b5f-8a0c-875d11615a75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764200873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1764200873
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1898180579
Short name T578
Test name
Test status
Simulation time 448039631 ps
CPU time 5.44 seconds
Started Jun 29 05:56:39 PM PDT 24
Finished Jun 29 05:56:45 PM PDT 24
Peak memory 241248 kb
Host smart-34650759-3b8a-496d-ac97-7f8d6b715a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18981
80579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1898180579
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2040991495
Short name T468
Test name
Test status
Simulation time 1074257663 ps
CPU time 69.87 seconds
Started Jun 29 05:56:43 PM PDT 24
Finished Jun 29 05:57:54 PM PDT 24
Peak memory 249356 kb
Host smart-752d7fc5-fd71-4330-b658-f99ef9eab68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20409
91495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2040991495
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2287742780
Short name T541
Test name
Test status
Simulation time 1639709176 ps
CPU time 41.2 seconds
Started Jun 29 05:56:51 PM PDT 24
Finished Jun 29 05:57:32 PM PDT 24
Peak memory 249076 kb
Host smart-8a4794bf-38bf-4773-b80f-3eda91c83b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22877
42780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2287742780
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3133744746
Short name T509
Test name
Test status
Simulation time 124768192 ps
CPU time 18.44 seconds
Started Jun 29 05:56:39 PM PDT 24
Finished Jun 29 05:56:57 PM PDT 24
Peak memory 256828 kb
Host smart-dfbbebaa-0bdb-426a-a319-cfa548c86150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31337
44746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3133744746
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3928128153
Short name T100
Test name
Test status
Simulation time 77537897903 ps
CPU time 3424.4 seconds
Started Jun 29 05:57:10 PM PDT 24
Finished Jun 29 06:54:15 PM PDT 24
Peak memory 300148 kb
Host smart-2a61f1b4-faf7-4ca2-bb9b-e1a4e86bb3c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928128153 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3928128153
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1251610973
Short name T443
Test name
Test status
Simulation time 38765849464 ps
CPU time 1259.23 seconds
Started Jun 29 05:57:10 PM PDT 24
Finished Jun 29 06:18:10 PM PDT 24
Peak memory 273916 kb
Host smart-8c4d77b4-2ee0-4874-b062-662de0a37e40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251610973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1251610973
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3325625320
Short name T375
Test name
Test status
Simulation time 396564574 ps
CPU time 27.16 seconds
Started Jun 29 05:57:10 PM PDT 24
Finished Jun 29 05:57:37 PM PDT 24
Peak memory 256548 kb
Host smart-12818059-3427-4fac-9f7b-d959a52c7974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33256
25320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3325625320
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.720233788
Short name T670
Test name
Test status
Simulation time 266853212 ps
CPU time 8.88 seconds
Started Jun 29 05:56:59 PM PDT 24
Finished Jun 29 05:57:09 PM PDT 24
Peak memory 249312 kb
Host smart-b51cd4f6-c94b-44c7-b9a1-0c675bec61f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72023
3788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.720233788
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.537427202
Short name T652
Test name
Test status
Simulation time 74013363505 ps
CPU time 1749.07 seconds
Started Jun 29 05:57:10 PM PDT 24
Finished Jun 29 06:26:19 PM PDT 24
Peak memory 274248 kb
Host smart-6d605731-9973-41d4-986c-24b596c1df09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537427202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.537427202
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3834626656
Short name T616
Test name
Test status
Simulation time 11255972410 ps
CPU time 473.59 seconds
Started Jun 29 05:57:11 PM PDT 24
Finished Jun 29 06:05:05 PM PDT 24
Peak memory 256056 kb
Host smart-47356230-a471-427e-8d9b-bca095ce3706
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834626656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3834626656
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2049949581
Short name T486
Test name
Test status
Simulation time 212775160 ps
CPU time 16.02 seconds
Started Jun 29 05:57:07 PM PDT 24
Finished Jun 29 05:57:23 PM PDT 24
Peak memory 254296 kb
Host smart-f98dc68e-0215-44f7-bb96-6e63907cb09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20499
49581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2049949581
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2108370586
Short name T421
Test name
Test status
Simulation time 697475660 ps
CPU time 23.02 seconds
Started Jun 29 05:57:08 PM PDT 24
Finished Jun 29 05:57:31 PM PDT 24
Peak memory 256192 kb
Host smart-5c2333a5-b779-4910-89e1-ad4830d18cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21083
70586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2108370586
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.522772667
Short name T566
Test name
Test status
Simulation time 723669156 ps
CPU time 47.48 seconds
Started Jun 29 05:57:09 PM PDT 24
Finished Jun 29 05:57:57 PM PDT 24
Peak memory 249320 kb
Host smart-f1dae6f0-37fa-4d13-ab66-c1f6d2eb242e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52277
2667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.522772667
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1886051633
Short name T395
Test name
Test status
Simulation time 4089357451 ps
CPU time 28.52 seconds
Started Jun 29 05:56:59 PM PDT 24
Finished Jun 29 05:57:28 PM PDT 24
Peak memory 249624 kb
Host smart-4d984ff6-726f-4611-b6e5-4e123d72ee90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18860
51633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1886051633
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.929339938
Short name T261
Test name
Test status
Simulation time 6749287248 ps
CPU time 350.84 seconds
Started Jun 29 05:57:10 PM PDT 24
Finished Jun 29 06:03:01 PM PDT 24
Peak memory 257620 kb
Host smart-2f5e50d3-1a6b-4b3d-b954-6c9eaf454c75
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929339938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.929339938
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.4133975402
Short name T559
Test name
Test status
Simulation time 40533350907 ps
CPU time 2475.92 seconds
Started Jun 29 05:57:17 PM PDT 24
Finished Jun 29 06:38:34 PM PDT 24
Peak memory 290176 kb
Host smart-8edbd9f9-a43f-4f2a-a95a-0a78626c4296
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133975402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.4133975402
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3295299320
Short name T398
Test name
Test status
Simulation time 300223306 ps
CPU time 40.81 seconds
Started Jun 29 05:57:17 PM PDT 24
Finished Jun 29 05:57:58 PM PDT 24
Peak memory 257008 kb
Host smart-9eaf0cd3-637e-495d-86f0-1e6cf26c6925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32952
99320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3295299320
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1136890683
Short name T564
Test name
Test status
Simulation time 793153461 ps
CPU time 48.09 seconds
Started Jun 29 05:57:19 PM PDT 24
Finished Jun 29 05:58:07 PM PDT 24
Peak memory 256944 kb
Host smart-f35074e3-34e5-40e7-a7c8-eefc31caf8d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11368
90683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1136890683
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.957068593
Short name T69
Test name
Test status
Simulation time 96469142013 ps
CPU time 1494.22 seconds
Started Jun 29 05:57:18 PM PDT 24
Finished Jun 29 06:22:12 PM PDT 24
Peak memory 290100 kb
Host smart-2a5c5025-f186-4ed6-bf8b-957293a4f5c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957068593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.957068593
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3838049254
Short name T456
Test name
Test status
Simulation time 23397444982 ps
CPU time 137.59 seconds
Started Jun 29 05:57:19 PM PDT 24
Finished Jun 29 05:59:37 PM PDT 24
Peak memory 255212 kb
Host smart-90ba081c-a9ee-4a1a-8034-bb30d6d7344d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838049254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3838049254
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2723044018
Short name T37
Test name
Test status
Simulation time 4155446415 ps
CPU time 60.82 seconds
Started Jun 29 05:57:16 PM PDT 24
Finished Jun 29 05:58:17 PM PDT 24
Peak memory 249436 kb
Host smart-fe85b3bb-cb08-4f54-ac8c-6c35a9cfcb89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27230
44018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2723044018
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3258509549
Short name T55
Test name
Test status
Simulation time 602776475 ps
CPU time 44.85 seconds
Started Jun 29 05:57:20 PM PDT 24
Finished Jun 29 05:58:05 PM PDT 24
Peak memory 249308 kb
Host smart-179656f8-59af-41a2-b541-c998f234a3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32585
09549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3258509549
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.327129331
Short name T613
Test name
Test status
Simulation time 545154580 ps
CPU time 27.6 seconds
Started Jun 29 05:57:17 PM PDT 24
Finished Jun 29 05:57:45 PM PDT 24
Peak memory 257096 kb
Host smart-f0453481-9ee6-4ef7-ac81-20515bc0eb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32712
9331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.327129331
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.804301455
Short name T32
Test name
Test status
Simulation time 232893279 ps
CPU time 8.71 seconds
Started Jun 29 05:57:11 PM PDT 24
Finished Jun 29 05:57:20 PM PDT 24
Peak memory 249228 kb
Host smart-be716836-348e-4e38-860b-f8c418ac8de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80430
1455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.804301455
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.4039691013
Short name T102
Test name
Test status
Simulation time 11380159718 ps
CPU time 402.64 seconds
Started Jun 29 05:57:28 PM PDT 24
Finished Jun 29 06:04:11 PM PDT 24
Peak memory 257516 kb
Host smart-153eb3c3-3aad-4d61-9960-fb6946ae9bfe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039691013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.4039691013
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1647486299
Short name T233
Test name
Test status
Simulation time 59515328494 ps
CPU time 2069.67 seconds
Started Jun 29 05:57:26 PM PDT 24
Finished Jun 29 06:31:56 PM PDT 24
Peak memory 289580 kb
Host smart-f4c2a7da-1619-4e68-882c-112bb7befdd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647486299 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1647486299
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1637596917
Short name T482
Test name
Test status
Simulation time 168768695545 ps
CPU time 2657.31 seconds
Started Jun 29 05:57:26 PM PDT 24
Finished Jun 29 06:41:44 PM PDT 24
Peak memory 282180 kb
Host smart-80d52535-ee06-48eb-8cda-b770177d8ff0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637596917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1637596917
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.973733496
Short name T414
Test name
Test status
Simulation time 12624308812 ps
CPU time 116.51 seconds
Started Jun 29 05:57:30 PM PDT 24
Finished Jun 29 05:59:27 PM PDT 24
Peak memory 256728 kb
Host smart-5d84fcd5-dbae-4f52-bcbd-28d4647c1877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97373
3496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.973733496
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3030290506
Short name T65
Test name
Test status
Simulation time 161539366 ps
CPU time 18.85 seconds
Started Jun 29 05:57:25 PM PDT 24
Finished Jun 29 05:57:45 PM PDT 24
Peak memory 249888 kb
Host smart-968209c3-d5fc-4a4e-8ce0-59c320c22524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30302
90506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3030290506
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3055509761
Short name T511
Test name
Test status
Simulation time 197327617728 ps
CPU time 1666.86 seconds
Started Jun 29 05:57:28 PM PDT 24
Finished Jun 29 06:25:15 PM PDT 24
Peak memory 273880 kb
Host smart-6e2ab72b-2611-43ed-81fe-39b282b26744
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055509761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3055509761
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.465092663
Short name T495
Test name
Test status
Simulation time 25736129662 ps
CPU time 1862.77 seconds
Started Jun 29 05:57:30 PM PDT 24
Finished Jun 29 06:28:33 PM PDT 24
Peak memory 283524 kb
Host smart-30c0301d-749f-427c-8df3-72702f6fe9d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465092663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.465092663
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2781466559
Short name T655
Test name
Test status
Simulation time 39491042182 ps
CPU time 396.58 seconds
Started Jun 29 05:57:28 PM PDT 24
Finished Jun 29 06:04:05 PM PDT 24
Peak memory 248224 kb
Host smart-44c77610-b58a-4a96-b865-d63af42a4a22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781466559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2781466559
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3864724580
Short name T131
Test name
Test status
Simulation time 704754771 ps
CPU time 8.47 seconds
Started Jun 29 05:57:26 PM PDT 24
Finished Jun 29 05:57:35 PM PDT 24
Peak memory 249284 kb
Host smart-eb643ee2-6a2e-4217-bd12-1af6440cd1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38647
24580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3864724580
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3432818551
Short name T389
Test name
Test status
Simulation time 1024398179 ps
CPU time 28.57 seconds
Started Jun 29 05:57:25 PM PDT 24
Finished Jun 29 05:57:54 PM PDT 24
Peak memory 249316 kb
Host smart-690c7da0-0621-4ee2-92d7-c74e8f2d7dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34328
18551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3432818551
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2306588927
Short name T71
Test name
Test status
Simulation time 1546146783 ps
CPU time 29.1 seconds
Started Jun 29 05:57:25 PM PDT 24
Finished Jun 29 05:57:55 PM PDT 24
Peak memory 249316 kb
Host smart-7dbcfa9e-6bce-4d10-abd0-d4a36e5a295f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23065
88927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2306588927
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1085781554
Short name T657
Test name
Test status
Simulation time 650875250 ps
CPU time 38.67 seconds
Started Jun 29 05:57:26 PM PDT 24
Finished Jun 29 05:58:05 PM PDT 24
Peak memory 256560 kb
Host smart-ddb54320-814b-48fa-9b2c-29ede5458f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10857
81554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1085781554
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1948541718
Short name T492
Test name
Test status
Simulation time 4236958359 ps
CPU time 422.63 seconds
Started Jun 29 05:57:27 PM PDT 24
Finished Jun 29 06:04:30 PM PDT 24
Peak memory 257632 kb
Host smart-ce4ae609-5f2a-43c6-aa92-6e29c1af79e5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948541718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1948541718
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3951519918
Short name T117
Test name
Test status
Simulation time 73791987998 ps
CPU time 1579.75 seconds
Started Jun 29 05:57:33 PM PDT 24
Finished Jun 29 06:23:54 PM PDT 24
Peak memory 289632 kb
Host smart-219da6b2-0da8-4842-a224-38b64fdb6675
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951519918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3951519918
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1116697829
Short name T280
Test name
Test status
Simulation time 1073863271 ps
CPU time 44.61 seconds
Started Jun 29 05:57:32 PM PDT 24
Finished Jun 29 05:58:17 PM PDT 24
Peak memory 257492 kb
Host smart-5fc4fe62-9948-4037-8d34-a937171af24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11166
97829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1116697829
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3465809501
Short name T627
Test name
Test status
Simulation time 859323675 ps
CPU time 51.77 seconds
Started Jun 29 05:57:32 PM PDT 24
Finished Jun 29 05:58:24 PM PDT 24
Peak memory 249640 kb
Host smart-d7d9fd5a-2a76-4b62-abff-baeb045f1d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34658
09501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3465809501
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.269528100
Short name T342
Test name
Test status
Simulation time 21902743858 ps
CPU time 1320.5 seconds
Started Jun 29 05:57:34 PM PDT 24
Finished Jun 29 06:19:35 PM PDT 24
Peak memory 273292 kb
Host smart-5c0a9f5a-cb2c-4e69-ac66-2172e069a494
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269528100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.269528100
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3023101711
Short name T361
Test name
Test status
Simulation time 12769421612 ps
CPU time 786.25 seconds
Started Jun 29 05:57:42 PM PDT 24
Finished Jun 29 06:10:48 PM PDT 24
Peak memory 273724 kb
Host smart-9f0cebff-ea4f-425d-89a0-4c6e055ef686
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023101711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3023101711
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2667295096
Short name T21
Test name
Test status
Simulation time 106509732 ps
CPU time 11.03 seconds
Started Jun 29 05:57:28 PM PDT 24
Finished Jun 29 05:57:39 PM PDT 24
Peak memory 249244 kb
Host smart-ac0e404e-498e-4d8f-8f48-d5b9d9ee669a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26672
95096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2667295096
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.226776650
Short name T70
Test name
Test status
Simulation time 1494042863 ps
CPU time 24.88 seconds
Started Jun 29 05:57:32 PM PDT 24
Finished Jun 29 05:57:57 PM PDT 24
Peak memory 249208 kb
Host smart-9a931ade-6955-4fbc-b641-2924647d4da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22677
6650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.226776650
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3996368293
Short name T132
Test name
Test status
Simulation time 350208224 ps
CPU time 27.14 seconds
Started Jun 29 05:57:32 PM PDT 24
Finished Jun 29 05:57:59 PM PDT 24
Peak memory 248360 kb
Host smart-a79a09a5-b5b7-43ed-8daa-f8e9b9e1ad7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39963
68293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3996368293
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.4054823755
Short name T671
Test name
Test status
Simulation time 757811096 ps
CPU time 14.96 seconds
Started Jun 29 05:57:30 PM PDT 24
Finished Jun 29 05:57:45 PM PDT 24
Peak memory 249224 kb
Host smart-fcbd0ad1-4ccb-48d4-ba67-9cd3eec54848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40548
23755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.4054823755
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3747793464
Short name T282
Test name
Test status
Simulation time 51886036451 ps
CPU time 2942.11 seconds
Started Jun 29 05:57:40 PM PDT 24
Finished Jun 29 06:46:42 PM PDT 24
Peak memory 288900 kb
Host smart-d51ca7da-079a-4e9f-a810-c99d0303c796
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747793464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3747793464
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.931035569
Short name T28
Test name
Test status
Simulation time 12029119067 ps
CPU time 976.42 seconds
Started Jun 29 05:57:41 PM PDT 24
Finished Jun 29 06:13:58 PM PDT 24
Peak memory 283344 kb
Host smart-5c035c94-e293-48f9-9890-eb2cff6c9d33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931035569 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.931035569
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.10344216
Short name T13
Test name
Test status
Simulation time 122124922925 ps
CPU time 1121.59 seconds
Started Jun 29 05:57:48 PM PDT 24
Finished Jun 29 06:16:30 PM PDT 24
Peak memory 265728 kb
Host smart-23fbc107-5d62-460f-8f70-3b9bde214dc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10344216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.10344216
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3362982714
Short name T576
Test name
Test status
Simulation time 18515220112 ps
CPU time 124.54 seconds
Started Jun 29 05:57:41 PM PDT 24
Finished Jun 29 05:59:45 PM PDT 24
Peak memory 257144 kb
Host smart-ce95efed-bbde-4a4a-a9d3-7b52543e1acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33629
82714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3362982714
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3016091065
Short name T76
Test name
Test status
Simulation time 382179552 ps
CPU time 13.31 seconds
Started Jun 29 05:57:41 PM PDT 24
Finished Jun 29 05:57:55 PM PDT 24
Peak memory 248840 kb
Host smart-44992c20-09f7-42dd-84b5-8d9b1d9ca930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30160
91065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3016091065
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1323893254
Short name T463
Test name
Test status
Simulation time 9818841580 ps
CPU time 1179.82 seconds
Started Jun 29 05:57:55 PM PDT 24
Finished Jun 29 06:17:36 PM PDT 24
Peak memory 273988 kb
Host smart-a9fd7681-8335-4392-bb7e-6f8a87328abd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323893254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1323893254
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1613635133
Short name T324
Test name
Test status
Simulation time 17665691819 ps
CPU time 171.96 seconds
Started Jun 29 05:57:49 PM PDT 24
Finished Jun 29 06:00:41 PM PDT 24
Peak memory 249396 kb
Host smart-fb0fd1ff-b1ff-4c33-a0c4-90d8b5cfdd01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613635133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1613635133
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.4168662168
Short name T548
Test name
Test status
Simulation time 3311294580 ps
CPU time 47.51 seconds
Started Jun 29 05:57:41 PM PDT 24
Finished Jun 29 05:58:29 PM PDT 24
Peak memory 257088 kb
Host smart-9f96b648-375e-4be9-a4af-d7b3abc3ad63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41686
62168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.4168662168
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.879207155
Short name T695
Test name
Test status
Simulation time 1664869705 ps
CPU time 36.98 seconds
Started Jun 29 05:57:41 PM PDT 24
Finished Jun 29 05:58:18 PM PDT 24
Peak memory 249304 kb
Host smart-a6c9f526-6ffa-4efb-8854-0e000befa4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87920
7155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.879207155
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3758110417
Short name T18
Test name
Test status
Simulation time 43377668 ps
CPU time 4.25 seconds
Started Jun 29 05:57:41 PM PDT 24
Finished Jun 29 05:57:46 PM PDT 24
Peak memory 240616 kb
Host smart-74e20704-c354-436e-91c6-c2916d7a4e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37581
10417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3758110417
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3463172042
Short name T485
Test name
Test status
Simulation time 1746461071 ps
CPU time 22.68 seconds
Started Jun 29 05:57:41 PM PDT 24
Finished Jun 29 05:58:04 PM PDT 24
Peak memory 256136 kb
Host smart-9e02bc14-d7ac-4742-942a-94e5d49fffd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34631
72042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3463172042
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1466900895
Short name T62
Test name
Test status
Simulation time 623119913 ps
CPU time 41.9 seconds
Started Jun 29 05:57:57 PM PDT 24
Finished Jun 29 05:58:39 PM PDT 24
Peak memory 257400 kb
Host smart-e6462ae5-7858-4447-9954-de35122b4243
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466900895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1466900895
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.425668006
Short name T410
Test name
Test status
Simulation time 29224405233 ps
CPU time 1443.13 seconds
Started Jun 29 05:58:04 PM PDT 24
Finished Jun 29 06:22:08 PM PDT 24
Peak memory 290364 kb
Host smart-719ef14b-d0bc-400f-a402-2187ccf720ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425668006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.425668006
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.4172301253
Short name T19
Test name
Test status
Simulation time 3593785049 ps
CPU time 242.13 seconds
Started Jun 29 05:58:04 PM PDT 24
Finished Jun 29 06:02:07 PM PDT 24
Peak memory 257544 kb
Host smart-e6731dac-7399-497d-b09e-4aacfb62f0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41723
01253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.4172301253
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.4059381841
Short name T642
Test name
Test status
Simulation time 1312529059 ps
CPU time 24.76 seconds
Started Jun 29 05:58:07 PM PDT 24
Finished Jun 29 05:58:32 PM PDT 24
Peak memory 249444 kb
Host smart-d8fd304a-88b5-4d52-b457-b8828ba89154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40593
81841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.4059381841
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.4142866527
Short name T692
Test name
Test status
Simulation time 31722383988 ps
CPU time 2133.6 seconds
Started Jun 29 05:58:03 PM PDT 24
Finished Jun 29 06:33:37 PM PDT 24
Peak memory 282112 kb
Host smart-8c85a644-9e48-4a4e-b5f1-6126a831beca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142866527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.4142866527
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.198289596
Short name T289
Test name
Test status
Simulation time 22473052566 ps
CPU time 466.33 seconds
Started Jun 29 05:58:04 PM PDT 24
Finished Jun 29 06:05:51 PM PDT 24
Peak memory 256416 kb
Host smart-d54fcb9a-9799-4c8e-9e23-abb90b1a6190
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198289596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.198289596
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.646926228
Short name T127
Test name
Test status
Simulation time 293557310 ps
CPU time 9.04 seconds
Started Jun 29 05:57:57 PM PDT 24
Finished Jun 29 05:58:06 PM PDT 24
Peak memory 249284 kb
Host smart-fae19db0-635e-462b-a264-be514b8b6f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64692
6228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.646926228
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2943525577
Short name T544
Test name
Test status
Simulation time 12370106047 ps
CPU time 66.16 seconds
Started Jun 29 05:58:05 PM PDT 24
Finished Jun 29 05:59:11 PM PDT 24
Peak memory 257208 kb
Host smart-c5573ae2-6ed9-4130-96fa-3db8bfdf88c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29435
25577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2943525577
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.4078181668
Short name T241
Test name
Test status
Simulation time 88253854 ps
CPU time 8.99 seconds
Started Jun 29 05:58:03 PM PDT 24
Finished Jun 29 05:58:12 PM PDT 24
Peak memory 253936 kb
Host smart-39b31369-60b2-4524-8dff-c4de45677ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40781
81668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.4078181668
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1023166915
Short name T435
Test name
Test status
Simulation time 3491533092 ps
CPU time 56.91 seconds
Started Jun 29 05:57:56 PM PDT 24
Finished Jun 29 05:58:53 PM PDT 24
Peak memory 257564 kb
Host smart-2fc25362-5e08-4a52-acdb-45d76045d63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10231
66915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1023166915
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.631665605
Short name T98
Test name
Test status
Simulation time 64263466734 ps
CPU time 1089.07 seconds
Started Jun 29 05:58:11 PM PDT 24
Finished Jun 29 06:16:20 PM PDT 24
Peak memory 286872 kb
Host smart-f1019447-99ff-4131-a8e9-b0f0a2f2820a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631665605 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.631665605
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1470961679
Short name T382
Test name
Test status
Simulation time 182464034547 ps
CPU time 2828.83 seconds
Started Jun 29 05:58:19 PM PDT 24
Finished Jun 29 06:45:29 PM PDT 24
Peak memory 286768 kb
Host smart-5a2e6ed0-0629-4607-be86-91279b0a86da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470961679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1470961679
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2842753858
Short name T513
Test name
Test status
Simulation time 5118711654 ps
CPU time 153.19 seconds
Started Jun 29 05:58:19 PM PDT 24
Finished Jun 29 06:00:52 PM PDT 24
Peak memory 257568 kb
Host smart-ac0e1987-40d5-4855-b6f6-b68cd636474e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28427
53858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2842753858
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3448565114
Short name T88
Test name
Test status
Simulation time 1812520374 ps
CPU time 39.2 seconds
Started Jun 29 05:58:15 PM PDT 24
Finished Jun 29 05:58:54 PM PDT 24
Peak memory 248808 kb
Host smart-d4906597-ebf1-4dbb-a9fb-978e493b7611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34485
65114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3448565114
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3362166766
Short name T120
Test name
Test status
Simulation time 56640966947 ps
CPU time 1235.26 seconds
Started Jun 29 05:58:20 PM PDT 24
Finished Jun 29 06:18:55 PM PDT 24
Peak memory 285536 kb
Host smart-2c141ddc-2179-42c4-92f4-466ad9900327
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362166766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3362166766
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3237558386
Short name T121
Test name
Test status
Simulation time 18919097258 ps
CPU time 1293.38 seconds
Started Jun 29 05:58:20 PM PDT 24
Finished Jun 29 06:19:54 PM PDT 24
Peak memory 284272 kb
Host smart-901b889e-df85-466a-9725-a9debd4e40d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237558386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3237558386
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1652369414
Short name T313
Test name
Test status
Simulation time 9268973778 ps
CPU time 408.47 seconds
Started Jun 29 05:58:19 PM PDT 24
Finished Jun 29 06:05:08 PM PDT 24
Peak memory 255856 kb
Host smart-c9634cdf-278d-4f20-b7be-02ffd6ac5141
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652369414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1652369414
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2274242208
Short name T52
Test name
Test status
Simulation time 1391415694 ps
CPU time 37.24 seconds
Started Jun 29 05:58:13 PM PDT 24
Finished Jun 29 05:58:51 PM PDT 24
Peak memory 256480 kb
Host smart-82bbd620-ddc3-42fb-a647-1c72e8f1b639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22742
42208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2274242208
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1228590426
Short name T118
Test name
Test status
Simulation time 71257167 ps
CPU time 6.18 seconds
Started Jun 29 05:58:12 PM PDT 24
Finished Jun 29 05:58:19 PM PDT 24
Peak memory 251808 kb
Host smart-dc98c0bc-0255-4fc3-83b3-cdaca6964eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12285
90426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1228590426
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1266724635
Short name T561
Test name
Test status
Simulation time 638849844 ps
CPU time 25.73 seconds
Started Jun 29 05:58:18 PM PDT 24
Finished Jun 29 05:58:45 PM PDT 24
Peak memory 249244 kb
Host smart-8cf40811-dda6-41f0-b2a6-6df985c48f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12667
24635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1266724635
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2511905875
Short name T290
Test name
Test status
Simulation time 624549525 ps
CPU time 33.93 seconds
Started Jun 29 05:58:12 PM PDT 24
Finished Jun 29 05:58:46 PM PDT 24
Peak memory 256532 kb
Host smart-87ee734e-8255-427f-9ef7-c23bde5db940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25119
05875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2511905875
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2236364925
Short name T584
Test name
Test status
Simulation time 91312419660 ps
CPU time 2678.82 seconds
Started Jun 29 05:58:21 PM PDT 24
Finished Jun 29 06:43:00 PM PDT 24
Peak memory 290216 kb
Host smart-9cc3b409-deb1-4980-8ca6-811b651779f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236364925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2236364925
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1406489144
Short name T217
Test name
Test status
Simulation time 99422834 ps
CPU time 4.53 seconds
Started Jun 29 05:52:05 PM PDT 24
Finished Jun 29 05:52:10 PM PDT 24
Peak memory 249588 kb
Host smart-7a3b8dc7-e267-4bca-89aa-3dbaf00378f8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1406489144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1406489144
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1840535480
Short name T628
Test name
Test status
Simulation time 88311995179 ps
CPU time 1606.71 seconds
Started Jun 29 05:51:56 PM PDT 24
Finished Jun 29 06:18:43 PM PDT 24
Peak memory 273048 kb
Host smart-41b5b75c-0e83-4212-b99e-fd0581970622
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840535480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1840535480
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.601241387
Short name T506
Test name
Test status
Simulation time 213932327 ps
CPU time 7.61 seconds
Started Jun 29 05:52:05 PM PDT 24
Finished Jun 29 05:52:13 PM PDT 24
Peak memory 249256 kb
Host smart-888ac59c-5648-4810-9cd6-123218f5c22f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=601241387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.601241387
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1051120802
Short name T354
Test name
Test status
Simulation time 1853870992 ps
CPU time 66.89 seconds
Started Jun 29 05:51:57 PM PDT 24
Finished Jun 29 05:53:04 PM PDT 24
Peak memory 256432 kb
Host smart-38a4fd7f-d960-4142-8e42-db8561554d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10511
20802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1051120802
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1334553295
Short name T80
Test name
Test status
Simulation time 2489558990 ps
CPU time 43.06 seconds
Started Jun 29 05:51:58 PM PDT 24
Finished Jun 29 05:52:42 PM PDT 24
Peak memory 250076 kb
Host smart-06c2960c-6216-45d9-9c16-f021edf06b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13345
53295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1334553295
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.950326874
Short name T334
Test name
Test status
Simulation time 40765047004 ps
CPU time 2293.66 seconds
Started Jun 29 05:52:06 PM PDT 24
Finished Jun 29 06:30:20 PM PDT 24
Peak memory 282184 kb
Host smart-70352911-301b-46cd-9150-aab0c6b93935
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950326874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.950326874
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.733098149
Short name T570
Test name
Test status
Simulation time 13207754897 ps
CPU time 1236.76 seconds
Started Jun 29 05:52:05 PM PDT 24
Finished Jun 29 06:12:42 PM PDT 24
Peak memory 289512 kb
Host smart-e8cda031-e77f-4df8-9df4-fab3c98d667e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733098149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.733098149
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3026146929
Short name T412
Test name
Test status
Simulation time 1337047861 ps
CPU time 29.77 seconds
Started Jun 29 05:51:57 PM PDT 24
Finished Jun 29 05:52:27 PM PDT 24
Peak memory 249208 kb
Host smart-c0f121ce-a147-41ad-a49e-34ebd49aacb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30261
46929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3026146929
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2991442982
Short name T38
Test name
Test status
Simulation time 261310620 ps
CPU time 32.72 seconds
Started Jun 29 05:51:57 PM PDT 24
Finished Jun 29 05:52:30 PM PDT 24
Peak memory 257496 kb
Host smart-c7d44e71-7e0a-40d2-802d-17a72f332011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29914
42982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2991442982
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3366386919
Short name T30
Test name
Test status
Simulation time 418757103 ps
CPU time 26.18 seconds
Started Jun 29 05:52:05 PM PDT 24
Finished Jun 29 05:52:31 PM PDT 24
Peak memory 277484 kb
Host smart-a926131a-1ffe-4d55-a106-9ac54ef7d12f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3366386919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3366386919
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3728150952
Short name T250
Test name
Test status
Simulation time 2810468294 ps
CPU time 43.42 seconds
Started Jun 29 05:51:57 PM PDT 24
Finished Jun 29 05:52:41 PM PDT 24
Peak memory 249360 kb
Host smart-cecd16ab-6124-4306-91f9-56ec235d33bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37281
50952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3728150952
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3321861436
Short name T514
Test name
Test status
Simulation time 7625630707 ps
CPU time 74.69 seconds
Started Jun 29 05:51:56 PM PDT 24
Finished Jun 29 05:53:11 PM PDT 24
Peak memory 257448 kb
Host smart-160ed2c6-c766-4394-976e-60990c59c451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33218
61436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3321861436
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1547830533
Short name T366
Test name
Test status
Simulation time 6893895732 ps
CPU time 320.19 seconds
Started Jun 29 05:52:04 PM PDT 24
Finished Jun 29 05:57:24 PM PDT 24
Peak memory 257620 kb
Host smart-bf40c526-cbb9-4faa-8e57-8edbafdf6543
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547830533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1547830533
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3048525771
Short name T57
Test name
Test status
Simulation time 8090350157 ps
CPU time 904.08 seconds
Started Jun 29 05:58:35 PM PDT 24
Finished Jun 29 06:13:40 PM PDT 24
Peak memory 267808 kb
Host smart-b51a45f8-b3c7-4cc4-bcb8-05676e8c9e55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048525771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3048525771
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3396386351
Short name T391
Test name
Test status
Simulation time 1801336205 ps
CPU time 127.37 seconds
Started Jun 29 05:58:29 PM PDT 24
Finished Jun 29 06:00:37 PM PDT 24
Peak memory 256548 kb
Host smart-e84bd89b-7aed-476a-8646-bc7177e2206e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33963
86351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3396386351
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1361221164
Short name T373
Test name
Test status
Simulation time 2218095241 ps
CPU time 31 seconds
Started Jun 29 05:58:26 PM PDT 24
Finished Jun 29 05:58:58 PM PDT 24
Peak memory 249360 kb
Host smart-a476a359-01ce-4326-8764-9a959d10b8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13612
21164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1361221164
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1140618039
Short name T461
Test name
Test status
Simulation time 31916630340 ps
CPU time 1129.52 seconds
Started Jun 29 05:58:35 PM PDT 24
Finished Jun 29 06:17:25 PM PDT 24
Peak memory 272828 kb
Host smart-f6eda7ac-0507-4aac-8b9f-eb3ac27271f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140618039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1140618039
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.696554768
Short name T304
Test name
Test status
Simulation time 14177219916 ps
CPU time 296.23 seconds
Started Jun 29 05:58:35 PM PDT 24
Finished Jun 29 06:03:32 PM PDT 24
Peak memory 249344 kb
Host smart-1e2fd48e-af74-4b97-a87a-889dee18f363
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696554768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.696554768
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2949918066
Short name T78
Test name
Test status
Simulation time 2618147886 ps
CPU time 78.39 seconds
Started Jun 29 05:58:27 PM PDT 24
Finished Jun 29 05:59:46 PM PDT 24
Peak memory 249436 kb
Host smart-c4884a95-6fef-452e-b87d-ee2902da5ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29499
18066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2949918066
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.354538399
Short name T658
Test name
Test status
Simulation time 3691604001 ps
CPU time 72.85 seconds
Started Jun 29 05:58:27 PM PDT 24
Finished Jun 29 05:59:40 PM PDT 24
Peak memory 257140 kb
Host smart-97b3fca7-bd41-4a19-ba49-3364ba2d2a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35453
8399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.354538399
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2653484905
Short name T681
Test name
Test status
Simulation time 563424966 ps
CPU time 42.69 seconds
Started Jun 29 05:58:26 PM PDT 24
Finished Jun 29 05:59:10 PM PDT 24
Peak memory 248788 kb
Host smart-fd6e62b1-af3b-47a2-8627-91321b89d8bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26534
84905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2653484905
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.955296294
Short name T399
Test name
Test status
Simulation time 52331866 ps
CPU time 4.33 seconds
Started Jun 29 05:58:29 PM PDT 24
Finished Jun 29 05:58:33 PM PDT 24
Peak memory 251844 kb
Host smart-7b1ae0bc-97e9-4555-82bd-64b20191e5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95529
6294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.955296294
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1582855052
Short name T481
Test name
Test status
Simulation time 3061119032 ps
CPU time 335.04 seconds
Started Jun 29 05:58:35 PM PDT 24
Finished Jun 29 06:04:11 PM PDT 24
Peak memory 257632 kb
Host smart-44012a17-5b64-4217-b91a-24f10b90fd96
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582855052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1582855052
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3314988502
Short name T195
Test name
Test status
Simulation time 51221022095 ps
CPU time 3783.37 seconds
Started Jun 29 05:58:34 PM PDT 24
Finished Jun 29 07:01:39 PM PDT 24
Peak memory 331464 kb
Host smart-2d17df08-1c46-487c-8b29-91d9fc12f031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314988502 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3314988502
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2957603067
Short name T113
Test name
Test status
Simulation time 138355736821 ps
CPU time 2644.74 seconds
Started Jun 29 05:58:42 PM PDT 24
Finished Jun 29 06:42:48 PM PDT 24
Peak memory 289544 kb
Host smart-734a4443-fab9-443c-aa3c-67d335c7c31d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957603067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2957603067
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1470750543
Short name T662
Test name
Test status
Simulation time 648085495 ps
CPU time 13.57 seconds
Started Jun 29 05:58:42 PM PDT 24
Finished Jun 29 05:58:56 PM PDT 24
Peak memory 255296 kb
Host smart-b9820afb-0aaa-4b69-9f45-613cad7ffc28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14707
50543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1470750543
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3499356747
Short name T571
Test name
Test status
Simulation time 393376006 ps
CPU time 27.54 seconds
Started Jun 29 05:58:42 PM PDT 24
Finished Jun 29 05:59:10 PM PDT 24
Peak memory 256524 kb
Host smart-a6b13657-dcc7-4b97-9e8e-869d95faa4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34993
56747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3499356747
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.392705277
Short name T328
Test name
Test status
Simulation time 57691662337 ps
CPU time 1800.65 seconds
Started Jun 29 05:58:42 PM PDT 24
Finished Jun 29 06:28:44 PM PDT 24
Peak memory 290292 kb
Host smart-7764acf8-a560-450f-8bf2-79079aad1a26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392705277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.392705277
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3979361036
Short name T402
Test name
Test status
Simulation time 111766941055 ps
CPU time 1827.26 seconds
Started Jun 29 05:58:52 PM PDT 24
Finished Jun 29 06:29:20 PM PDT 24
Peak memory 281552 kb
Host smart-15117557-fa35-4dac-acd2-5455895e47d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979361036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3979361036
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.132953912
Short name T656
Test name
Test status
Simulation time 3044559023 ps
CPU time 31.27 seconds
Started Jun 29 05:58:42 PM PDT 24
Finished Jun 29 05:59:14 PM PDT 24
Peak memory 257368 kb
Host smart-fff85525-2122-43cf-860b-cfa8460d2968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13295
3912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.132953912
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.4081831919
Short name T107
Test name
Test status
Simulation time 608160045 ps
CPU time 41.34 seconds
Started Jun 29 05:58:43 PM PDT 24
Finished Jun 29 05:59:25 PM PDT 24
Peak memory 248744 kb
Host smart-5c91b396-f635-4c06-8a6a-320e21993a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40818
31919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.4081831919
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1285856856
Short name T615
Test name
Test status
Simulation time 630478715 ps
CPU time 31.45 seconds
Started Jun 29 05:58:34 PM PDT 24
Finished Jun 29 05:59:06 PM PDT 24
Peak memory 257452 kb
Host smart-0bd1000c-fb3c-43dd-a231-2e0f6fcb513c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12858
56856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1285856856
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3552594576
Short name T77
Test name
Test status
Simulation time 60869487 ps
CPU time 9.12 seconds
Started Jun 29 05:58:51 PM PDT 24
Finished Jun 29 05:59:00 PM PDT 24
Peak memory 255968 kb
Host smart-1c74c16b-6445-4e4c-80e6-588126783354
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552594576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3552594576
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.314129791
Short name T222
Test name
Test status
Simulation time 41758875567 ps
CPU time 1472.14 seconds
Started Jun 29 05:58:59 PM PDT 24
Finished Jun 29 06:23:32 PM PDT 24
Peak memory 273972 kb
Host smart-3d666514-a832-4cc9-a56f-341ea6a19af5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314129791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.314129791
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.4173309648
Short name T693
Test name
Test status
Simulation time 5461083894 ps
CPU time 317.01 seconds
Started Jun 29 05:59:00 PM PDT 24
Finished Jun 29 06:04:17 PM PDT 24
Peak memory 252492 kb
Host smart-1b501919-acf0-4229-8231-4a4a5ef44ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41733
09648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4173309648
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.230775117
Short name T644
Test name
Test status
Simulation time 1473907962 ps
CPU time 30.23 seconds
Started Jun 29 05:58:59 PM PDT 24
Finished Jun 29 05:59:29 PM PDT 24
Peak memory 249688 kb
Host smart-cbca04bf-fd2a-439e-8f8a-2731ee62e7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23077
5117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.230775117
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2018944146
Short name T690
Test name
Test status
Simulation time 8748621529 ps
CPU time 811.97 seconds
Started Jun 29 05:59:07 PM PDT 24
Finished Jun 29 06:12:40 PM PDT 24
Peak memory 273736 kb
Host smart-a30fa127-4c3c-494a-a00b-0cefcb332bdc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018944146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2018944146
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.559517822
Short name T129
Test name
Test status
Simulation time 75476631793 ps
CPU time 2740.65 seconds
Started Jun 29 05:59:08 PM PDT 24
Finished Jun 29 06:44:49 PM PDT 24
Peak memory 286836 kb
Host smart-adf1c137-f7f1-42ef-a28a-ee9e6f51b6b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559517822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.559517822
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1447018247
Short name T596
Test name
Test status
Simulation time 6508332040 ps
CPU time 263.31 seconds
Started Jun 29 05:59:08 PM PDT 24
Finished Jun 29 06:03:31 PM PDT 24
Peak memory 249384 kb
Host smart-656b6cc6-a9aa-4841-a656-ae8398673f9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447018247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1447018247
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2651035289
Short name T387
Test name
Test status
Simulation time 280671383 ps
CPU time 23.97 seconds
Started Jun 29 05:58:51 PM PDT 24
Finished Jun 29 05:59:15 PM PDT 24
Peak memory 256560 kb
Host smart-d6805cc1-d64a-45b0-a3d8-96e3a8875e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26510
35289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2651035289
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2101208651
Short name T396
Test name
Test status
Simulation time 172673625 ps
CPU time 12.89 seconds
Started Jun 29 05:59:00 PM PDT 24
Finished Jun 29 05:59:13 PM PDT 24
Peak memory 248780 kb
Host smart-db772b34-7c87-4eed-b0b2-94df75c3a31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21012
08651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2101208651
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2424441125
Short name T433
Test name
Test status
Simulation time 160077252 ps
CPU time 3.98 seconds
Started Jun 29 05:58:58 PM PDT 24
Finished Jun 29 05:59:02 PM PDT 24
Peak memory 241044 kb
Host smart-a5d7a8f2-06fa-4157-814c-a40d958c8ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24244
41125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2424441125
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.103698753
Short name T378
Test name
Test status
Simulation time 1506040609 ps
CPU time 48.77 seconds
Started Jun 29 05:58:51 PM PDT 24
Finished Jun 29 05:59:40 PM PDT 24
Peak memory 256564 kb
Host smart-e39d813a-16a7-4f0f-95db-ab0eba7f84cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10369
8753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.103698753
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2637489492
Short name T551
Test name
Test status
Simulation time 43801260845 ps
CPU time 1277.14 seconds
Started Jun 29 05:59:07 PM PDT 24
Finished Jun 29 06:20:25 PM PDT 24
Peak memory 286848 kb
Host smart-39ad5faf-8680-47c0-ada5-bb89e2b4307c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637489492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2637489492
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.139411741
Short name T123
Test name
Test status
Simulation time 152760505133 ps
CPU time 9141.63 seconds
Started Jun 29 05:59:07 PM PDT 24
Finished Jun 29 08:31:30 PM PDT 24
Peak memory 372188 kb
Host smart-ca97b4d2-09ec-429a-86fb-fc5fb08e62a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139411741 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.139411741
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.264332262
Short name T105
Test name
Test status
Simulation time 21476996293 ps
CPU time 936.4 seconds
Started Jun 29 05:59:14 PM PDT 24
Finished Jun 29 06:14:51 PM PDT 24
Peak memory 270032 kb
Host smart-e6f36bb2-0250-4b40-b20d-fbda8ecd6823
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264332262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.264332262
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3650133666
Short name T617
Test name
Test status
Simulation time 1148557370 ps
CPU time 111.42 seconds
Started Jun 29 05:59:17 PM PDT 24
Finished Jun 29 06:01:09 PM PDT 24
Peak memory 251252 kb
Host smart-b9867a43-82d3-4c2d-b49c-823c3f57c6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36501
33666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3650133666
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1147768424
Short name T686
Test name
Test status
Simulation time 3992235683 ps
CPU time 63.23 seconds
Started Jun 29 05:59:17 PM PDT 24
Finished Jun 29 06:00:21 PM PDT 24
Peak memory 249384 kb
Host smart-6a88861b-9c8e-4700-99c9-a2603cf954ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11477
68424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1147768424
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2049471122
Short name T522
Test name
Test status
Simulation time 22952078716 ps
CPU time 971.98 seconds
Started Jun 29 05:59:23 PM PDT 24
Finished Jun 29 06:15:35 PM PDT 24
Peak memory 273996 kb
Host smart-668f9b47-c929-4b59-b6ec-da1ab74aeb59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049471122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2049471122
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.35741285
Short name T275
Test name
Test status
Simulation time 29333367326 ps
CPU time 1655.61 seconds
Started Jun 29 05:59:25 PM PDT 24
Finished Jun 29 06:27:01 PM PDT 24
Peak memory 273808 kb
Host smart-4b18ec70-51b8-4726-a19a-839291daa287
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35741285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.35741285
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3471421208
Short name T574
Test name
Test status
Simulation time 227419992 ps
CPU time 21.3 seconds
Started Jun 29 05:59:15 PM PDT 24
Finished Jun 29 05:59:37 PM PDT 24
Peak memory 249172 kb
Host smart-65142ddf-6d3f-43de-af98-9dc81c5a9ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34714
21208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3471421208
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3951827882
Short name T569
Test name
Test status
Simulation time 20205307 ps
CPU time 3.56 seconds
Started Jun 29 05:59:17 PM PDT 24
Finished Jun 29 05:59:21 PM PDT 24
Peak memory 240588 kb
Host smart-5471642d-a459-488a-894a-6968cf30c3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39518
27882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3951827882
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2811209103
Short name T79
Test name
Test status
Simulation time 792828884 ps
CPU time 18.96 seconds
Started Jun 29 05:59:14 PM PDT 24
Finished Jun 29 05:59:33 PM PDT 24
Peak memory 248732 kb
Host smart-9c7df398-bcbc-447f-97ab-ee371d8d523c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28112
09103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2811209103
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1154281744
Short name T352
Test name
Test status
Simulation time 993052799 ps
CPU time 15.23 seconds
Started Jun 29 05:59:18 PM PDT 24
Finished Jun 29 05:59:33 PM PDT 24
Peak memory 249416 kb
Host smart-6c59db55-0a13-4ea7-a6f0-dd421b138ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11542
81744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1154281744
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.4055747029
Short name T634
Test name
Test status
Simulation time 60969598230 ps
CPU time 1328.13 seconds
Started Jun 29 05:59:24 PM PDT 24
Finished Jun 29 06:21:33 PM PDT 24
Peak memory 289988 kb
Host smart-b5008dcf-ebf2-4446-b1ea-2c99d154041b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055747029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.4055747029
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.615590147
Short name T583
Test name
Test status
Simulation time 5579344324 ps
CPU time 639.49 seconds
Started Jun 29 05:59:34 PM PDT 24
Finished Jun 29 06:10:13 PM PDT 24
Peak memory 273496 kb
Host smart-4712060e-3a37-4122-a840-35936d8bf842
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615590147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.615590147
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2731128171
Short name T237
Test name
Test status
Simulation time 5046935822 ps
CPU time 295.55 seconds
Started Jun 29 05:59:31 PM PDT 24
Finished Jun 29 06:04:27 PM PDT 24
Peak memory 256888 kb
Host smart-6572c4fb-5b30-41e4-932e-6f3dea3b2dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27311
28171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2731128171
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.557700233
Short name T643
Test name
Test status
Simulation time 352487659 ps
CPU time 32.25 seconds
Started Jun 29 05:59:34 PM PDT 24
Finished Jun 29 06:00:06 PM PDT 24
Peak memory 257380 kb
Host smart-15cef3c7-1b5c-45e2-94ba-cc7f8c6ab4f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55770
0233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.557700233
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2856962371
Short name T337
Test name
Test status
Simulation time 13044781930 ps
CPU time 1542.82 seconds
Started Jun 29 05:59:31 PM PDT 24
Finished Jun 29 06:25:15 PM PDT 24
Peak memory 282088 kb
Host smart-cc9c3a26-6d75-4f83-ba3b-2e1ea6f1176c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856962371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2856962371
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2465501185
Short name T606
Test name
Test status
Simulation time 15751914772 ps
CPU time 1288.31 seconds
Started Jun 29 05:59:32 PM PDT 24
Finished Jun 29 06:21:01 PM PDT 24
Peak memory 289172 kb
Host smart-8921fc9a-3956-4be6-997f-e9d6c9b08d27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465501185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2465501185
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1273640478
Short name T318
Test name
Test status
Simulation time 18956363722 ps
CPU time 362.24 seconds
Started Jun 29 05:59:34 PM PDT 24
Finished Jun 29 06:05:36 PM PDT 24
Peak memory 255984 kb
Host smart-295b491e-415d-4147-850a-0be9d6b0f5b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273640478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1273640478
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.200706509
Short name T697
Test name
Test status
Simulation time 664855211 ps
CPU time 12.81 seconds
Started Jun 29 05:59:33 PM PDT 24
Finished Jun 29 05:59:46 PM PDT 24
Peak memory 255284 kb
Host smart-3127c3f0-87cd-47f3-825c-022f48905487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20070
6509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.200706509
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.877715963
Short name T694
Test name
Test status
Simulation time 238402053 ps
CPU time 33.32 seconds
Started Jun 29 05:59:31 PM PDT 24
Finished Jun 29 06:00:05 PM PDT 24
Peak memory 249320 kb
Host smart-88dedcf5-11ec-4347-a275-fe42f06e8293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87771
5963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.877715963
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2609593360
Short name T269
Test name
Test status
Simulation time 1014789752 ps
CPU time 56.96 seconds
Started Jun 29 05:59:23 PM PDT 24
Finished Jun 29 06:00:21 PM PDT 24
Peak memory 256520 kb
Host smart-3e990570-9eab-4ec4-aea4-04e9cd653c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26095
93360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2609593360
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2420403402
Short name T244
Test name
Test status
Simulation time 161194838482 ps
CPU time 2357.27 seconds
Started Jun 29 05:59:32 PM PDT 24
Finished Jun 29 06:38:49 PM PDT 24
Peak memory 288828 kb
Host smart-feb964ce-6754-4097-a21c-95a7b104eaa7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420403402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2420403402
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1811049479
Short name T646
Test name
Test status
Simulation time 11758574471 ps
CPU time 993.34 seconds
Started Jun 29 05:59:31 PM PDT 24
Finished Jun 29 06:16:05 PM PDT 24
Peak memory 271024 kb
Host smart-be2379e5-9d1a-4fa4-a33f-e5855ecc53fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811049479 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1811049479
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1499163643
Short name T12
Test name
Test status
Simulation time 56439068258 ps
CPU time 2032.53 seconds
Started Jun 29 05:59:47 PM PDT 24
Finished Jun 29 06:33:40 PM PDT 24
Peak memory 289712 kb
Host smart-b7aae052-d364-4e98-9828-8b74a22c863c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499163643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1499163643
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3284431218
Short name T538
Test name
Test status
Simulation time 297671538 ps
CPU time 21.22 seconds
Started Jun 29 05:59:39 PM PDT 24
Finished Jun 29 06:00:01 PM PDT 24
Peak memory 256984 kb
Host smart-07f3a139-ae10-4563-9630-864aac562b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32844
31218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3284431218
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2592536711
Short name T592
Test name
Test status
Simulation time 304965258 ps
CPU time 28.32 seconds
Started Jun 29 05:59:39 PM PDT 24
Finished Jun 29 06:00:08 PM PDT 24
Peak memory 249244 kb
Host smart-bb54384e-550d-4f1d-acf4-e31feb502439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25925
36711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2592536711
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.876515970
Short name T294
Test name
Test status
Simulation time 55515148203 ps
CPU time 1602.66 seconds
Started Jun 29 05:59:48 PM PDT 24
Finished Jun 29 06:26:31 PM PDT 24
Peak memory 289668 kb
Host smart-e2310c69-031f-4be8-bf31-ba9a3a8c25e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876515970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.876515970
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1943580316
Short name T455
Test name
Test status
Simulation time 15200644240 ps
CPU time 1319.14 seconds
Started Jun 29 05:59:48 PM PDT 24
Finished Jun 29 06:21:47 PM PDT 24
Peak memory 288228 kb
Host smart-18e511c2-0216-42b3-b2a8-55d992c01f77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943580316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1943580316
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.24460440
Short name T299
Test name
Test status
Simulation time 30138038871 ps
CPU time 595.17 seconds
Started Jun 29 05:59:48 PM PDT 24
Finished Jun 29 06:09:44 PM PDT 24
Peak memory 249192 kb
Host smart-03cc7472-a5b5-460c-8a18-0405339fb0ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24460440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.24460440
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.4198060005
Short name T423
Test name
Test status
Simulation time 2999451716 ps
CPU time 35.64 seconds
Started Jun 29 05:59:38 PM PDT 24
Finished Jun 29 06:00:14 PM PDT 24
Peak memory 257208 kb
Host smart-ff00dcfa-4e53-4448-bd34-6abfa5aca9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41980
60005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.4198060005
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2449030812
Short name T44
Test name
Test status
Simulation time 2392803314 ps
CPU time 40.42 seconds
Started Jun 29 05:59:39 PM PDT 24
Finished Jun 29 06:00:20 PM PDT 24
Peak memory 248636 kb
Host smart-494fb238-43f1-4456-8382-364528d1dc42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24490
30812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2449030812
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.750823935
Short name T438
Test name
Test status
Simulation time 210571122 ps
CPU time 27.67 seconds
Started Jun 29 05:59:48 PM PDT 24
Finished Jun 29 06:00:16 PM PDT 24
Peak memory 249800 kb
Host smart-3f95b297-b386-45ac-a15e-ad7492f44c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75082
3935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.750823935
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3796044254
Short name T437
Test name
Test status
Simulation time 313635952 ps
CPU time 16.39 seconds
Started Jun 29 05:59:39 PM PDT 24
Finished Jun 29 05:59:55 PM PDT 24
Peak memory 256544 kb
Host smart-1da54c18-50ad-447b-8ee9-a973a74d026d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37960
44254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3796044254
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1005484264
Short name T95
Test name
Test status
Simulation time 26477907488 ps
CPU time 519.72 seconds
Started Jun 29 05:59:47 PM PDT 24
Finished Jun 29 06:08:27 PM PDT 24
Peak memory 265704 kb
Host smart-45028106-e60f-4af4-8897-2c833e6eae16
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005484264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1005484264
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3172116960
Short name T647
Test name
Test status
Simulation time 26276445572 ps
CPU time 1129.31 seconds
Started Jun 29 06:00:03 PM PDT 24
Finished Jun 29 06:18:53 PM PDT 24
Peak memory 282380 kb
Host smart-8db48024-4a86-4b83-b5ba-3c6e249e3d9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172116960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3172116960
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1938017687
Short name T388
Test name
Test status
Simulation time 2839359747 ps
CPU time 16.7 seconds
Started Jun 29 05:59:56 PM PDT 24
Finished Jun 29 06:00:13 PM PDT 24
Peak memory 255468 kb
Host smart-eb6c2eef-f365-4476-94b3-71f4e1e07006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19380
17687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1938017687
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.4049326637
Short name T473
Test name
Test status
Simulation time 141560023 ps
CPU time 10.42 seconds
Started Jun 29 05:59:57 PM PDT 24
Finished Jun 29 06:00:07 PM PDT 24
Peak memory 248612 kb
Host smart-6478722a-4019-4ba4-8ba8-802a96dae98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40493
26637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.4049326637
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3270775729
Short name T295
Test name
Test status
Simulation time 114966816114 ps
CPU time 1984.48 seconds
Started Jun 29 06:00:04 PM PDT 24
Finished Jun 29 06:33:09 PM PDT 24
Peak memory 273764 kb
Host smart-7b30f367-7e03-4d7a-b441-95d1f92b6b61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270775729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3270775729
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.4057248054
Short name T591
Test name
Test status
Simulation time 37958058604 ps
CPU time 2266.57 seconds
Started Jun 29 06:00:03 PM PDT 24
Finished Jun 29 06:37:50 PM PDT 24
Peak memory 282188 kb
Host smart-2f01a805-835b-48c8-a7e1-1af5984dca0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057248054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.4057248054
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1146765785
Short name T300
Test name
Test status
Simulation time 30368651186 ps
CPU time 357.66 seconds
Started Jun 29 06:00:07 PM PDT 24
Finished Jun 29 06:06:05 PM PDT 24
Peak memory 249416 kb
Host smart-c0d3d5cd-f6fc-4b90-803d-b7570d52f5f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146765785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1146765785
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.765391758
Short name T72
Test name
Test status
Simulation time 2200273018 ps
CPU time 44.81 seconds
Started Jun 29 05:59:55 PM PDT 24
Finished Jun 29 06:00:40 PM PDT 24
Peak memory 257544 kb
Host smart-4995cb46-4c58-4ccf-b098-9808adf0cbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76539
1758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.765391758
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1092293653
Short name T649
Test name
Test status
Simulation time 233063783 ps
CPU time 9.94 seconds
Started Jun 29 05:59:55 PM PDT 24
Finished Jun 29 06:00:05 PM PDT 24
Peak memory 255472 kb
Host smart-37b85b94-ba23-4606-8a09-1f71aa21f2a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10922
93653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1092293653
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3767430969
Short name T625
Test name
Test status
Simulation time 1593247913 ps
CPU time 27.45 seconds
Started Jun 29 05:59:55 PM PDT 24
Finished Jun 29 06:00:23 PM PDT 24
Peak memory 256840 kb
Host smart-6dd4be12-139c-4716-9c2c-296cd88567ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37674
30969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3767430969
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3739396240
Short name T629
Test name
Test status
Simulation time 1500039248 ps
CPU time 26.22 seconds
Started Jun 29 05:59:48 PM PDT 24
Finished Jun 29 06:00:15 PM PDT 24
Peak memory 249792 kb
Host smart-29b2dc41-e94e-4be2-a6c9-b3066621e798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37393
96240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3739396240
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.933338376
Short name T442
Test name
Test status
Simulation time 28342428433 ps
CPU time 3229.05 seconds
Started Jun 29 06:00:03 PM PDT 24
Finished Jun 29 06:53:52 PM PDT 24
Peak memory 321848 kb
Host smart-6ed44c67-615a-4463-a8df-a16b84701dda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933338376 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.933338376
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2012059711
Short name T577
Test name
Test status
Simulation time 44040951553 ps
CPU time 2383.91 seconds
Started Jun 29 06:00:17 PM PDT 24
Finished Jun 29 06:40:02 PM PDT 24
Peak memory 287900 kb
Host smart-1e46df44-6bba-4f08-b43a-c1d82f783b06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012059711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2012059711
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.574649674
Short name T654
Test name
Test status
Simulation time 14355742951 ps
CPU time 210.31 seconds
Started Jun 29 06:00:10 PM PDT 24
Finished Jun 29 06:03:41 PM PDT 24
Peak memory 256820 kb
Host smart-8fc7524f-bf66-479e-a7ce-9ad8c5d3d787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57464
9674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.574649674
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.685718358
Short name T560
Test name
Test status
Simulation time 649261497 ps
CPU time 51.65 seconds
Started Jun 29 06:00:10 PM PDT 24
Finished Jun 29 06:01:02 PM PDT 24
Peak memory 248768 kb
Host smart-8e6ccfa5-6368-4e0d-838e-1fd91a10b5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68571
8358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.685718358
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3680390095
Short name T420
Test name
Test status
Simulation time 36821265044 ps
CPU time 1160.51 seconds
Started Jun 29 06:00:21 PM PDT 24
Finished Jun 29 06:19:41 PM PDT 24
Peak memory 287048 kb
Host smart-888259f5-5f44-4751-8f61-8fc58ab2f9d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680390095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3680390095
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3338664025
Short name T307
Test name
Test status
Simulation time 45232639794 ps
CPU time 431.91 seconds
Started Jun 29 06:00:23 PM PDT 24
Finished Jun 29 06:07:36 PM PDT 24
Peak memory 249188 kb
Host smart-810f9a79-4450-4979-961d-2089f2af3901
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338664025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3338664025
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1949139380
Short name T472
Test name
Test status
Simulation time 842233459 ps
CPU time 15.69 seconds
Started Jun 29 06:00:07 PM PDT 24
Finished Jun 29 06:00:23 PM PDT 24
Peak memory 256680 kb
Host smart-2b71b326-df1b-4750-b63d-d28e99eacf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19491
39380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1949139380
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2587871901
Short name T469
Test name
Test status
Simulation time 160469444 ps
CPU time 20.9 seconds
Started Jun 29 06:00:10 PM PDT 24
Finished Jun 29 06:00:31 PM PDT 24
Peak memory 249316 kb
Host smart-d52a0557-baf9-4e30-9f71-db971efad7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25878
71901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2587871901
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3224967350
Short name T251
Test name
Test status
Simulation time 1903726020 ps
CPU time 37.88 seconds
Started Jun 29 06:00:10 PM PDT 24
Finished Jun 29 06:00:49 PM PDT 24
Peak memory 256780 kb
Host smart-9f0852fb-698b-4df7-97bd-475501a7cb41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32249
67350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3224967350
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.372803065
Short name T407
Test name
Test status
Simulation time 465501053 ps
CPU time 11.34 seconds
Started Jun 29 06:00:02 PM PDT 24
Finished Jun 29 06:00:14 PM PDT 24
Peak memory 253208 kb
Host smart-ca66bb10-a331-4e67-8a0d-fe2b54bc8b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37280
3065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.372803065
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2346418207
Short name T284
Test name
Test status
Simulation time 31925414832 ps
CPU time 1381.77 seconds
Started Jun 29 06:00:21 PM PDT 24
Finished Jun 29 06:23:23 PM PDT 24
Peak memory 290060 kb
Host smart-5ee38645-6a3d-41ab-b8a1-dfa28e960c0f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346418207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2346418207
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.4188673313
Short name T645
Test name
Test status
Simulation time 7513884475 ps
CPU time 712.78 seconds
Started Jun 29 06:00:25 PM PDT 24
Finished Jun 29 06:12:19 PM PDT 24
Peak memory 273560 kb
Host smart-61461b22-9d87-4997-8f08-2f87a677dee5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188673313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.4188673313
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1974117128
Short name T594
Test name
Test status
Simulation time 7772311295 ps
CPU time 164.23 seconds
Started Jun 29 06:00:25 PM PDT 24
Finished Jun 29 06:03:10 PM PDT 24
Peak memory 257532 kb
Host smart-bba2bc16-2794-447d-b8ac-cbf1dd6b41af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19741
17128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1974117128
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.634819105
Short name T497
Test name
Test status
Simulation time 313369035 ps
CPU time 26.32 seconds
Started Jun 29 06:00:31 PM PDT 24
Finished Jun 29 06:00:57 PM PDT 24
Peak memory 249680 kb
Host smart-fb69df1c-61f6-4b70-92bc-dc73a8d4665f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63481
9105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.634819105
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2135779523
Short name T2
Test name
Test status
Simulation time 118418707957 ps
CPU time 1974.6 seconds
Started Jun 29 06:00:34 PM PDT 24
Finished Jun 29 06:33:29 PM PDT 24
Peak memory 282972 kb
Host smart-9b0def65-ab02-48f7-8f0f-a200a1dfc9ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135779523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2135779523
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2846746440
Short name T451
Test name
Test status
Simulation time 97872595789 ps
CPU time 1490.57 seconds
Started Jun 29 06:00:33 PM PDT 24
Finished Jun 29 06:25:24 PM PDT 24
Peak memory 273484 kb
Host smart-e7704bb5-bc87-46a4-bef2-32a976ab151c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846746440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2846746440
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3477442220
Short name T490
Test name
Test status
Simulation time 2516715774 ps
CPU time 106.52 seconds
Started Jun 29 06:00:27 PM PDT 24
Finished Jun 29 06:02:14 PM PDT 24
Peak memory 255980 kb
Host smart-0118d080-55f8-4be8-a54a-e0f8b5e8593b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477442220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3477442220
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2904960560
Short name T369
Test name
Test status
Simulation time 284936487 ps
CPU time 26.69 seconds
Started Jun 29 06:00:31 PM PDT 24
Finished Jun 29 06:00:58 PM PDT 24
Peak memory 249308 kb
Host smart-5a3b56f7-03d1-440b-ae81-2ced72324607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29049
60560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2904960560
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.718994044
Short name T572
Test name
Test status
Simulation time 90037092 ps
CPU time 10.68 seconds
Started Jun 29 06:00:31 PM PDT 24
Finished Jun 29 06:00:42 PM PDT 24
Peak memory 254836 kb
Host smart-477a5c03-420d-43a0-937c-7a4dd5dd7e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71899
4044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.718994044
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.858776872
Short name T496
Test name
Test status
Simulation time 3357786168 ps
CPU time 67.71 seconds
Started Jun 29 06:00:25 PM PDT 24
Finished Jun 29 06:01:33 PM PDT 24
Peak memory 256680 kb
Host smart-f15a08d2-f44e-4f66-9e73-d57483530d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85877
6872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.858776872
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3724152601
Short name T677
Test name
Test status
Simulation time 1670519069 ps
CPU time 24.44 seconds
Started Jun 29 06:00:25 PM PDT 24
Finished Jun 29 06:00:50 PM PDT 24
Peak memory 257092 kb
Host smart-f44aed6e-2d0b-458b-bb31-f05483bd8582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37241
52601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3724152601
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1400967906
Short name T247
Test name
Test status
Simulation time 99328887992 ps
CPU time 2511.1 seconds
Started Jun 29 06:00:34 PM PDT 24
Finished Jun 29 06:42:26 PM PDT 24
Peak memory 306832 kb
Host smart-5257466b-d6c4-40e7-b6a2-6f2d03f3ecf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400967906 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1400967906
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2680344889
Short name T505
Test name
Test status
Simulation time 101271774965 ps
CPU time 3017.85 seconds
Started Jun 29 06:00:50 PM PDT 24
Finished Jun 29 06:51:09 PM PDT 24
Peak memory 289668 kb
Host smart-32af1169-b485-47f8-acab-1e8252985d9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680344889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2680344889
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1449613627
Short name T568
Test name
Test status
Simulation time 5435902567 ps
CPU time 111.66 seconds
Started Jun 29 06:00:42 PM PDT 24
Finished Jun 29 06:02:34 PM PDT 24
Peak memory 256924 kb
Host smart-8c320f80-dde3-4401-9bda-88784dc39871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14496
13627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1449613627
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2827744123
Short name T452
Test name
Test status
Simulation time 301886893 ps
CPU time 20.6 seconds
Started Jun 29 06:00:43 PM PDT 24
Finished Jun 29 06:01:03 PM PDT 24
Peak memory 255768 kb
Host smart-bf6dda6d-9005-4919-8efe-8ef4817a60a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277
44123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2827744123
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1291138113
Short name T425
Test name
Test status
Simulation time 49247402638 ps
CPU time 1125.64 seconds
Started Jun 29 06:00:51 PM PDT 24
Finished Jun 29 06:19:37 PM PDT 24
Peak memory 274020 kb
Host smart-556dd235-5776-4c30-91f2-715ea1218d83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291138113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1291138113
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1684373853
Short name T358
Test name
Test status
Simulation time 303886501199 ps
CPU time 3256.03 seconds
Started Jun 29 06:00:50 PM PDT 24
Finished Jun 29 06:55:07 PM PDT 24
Peak memory 290124 kb
Host smart-b36d718c-11cd-48b0-b072-139083b1561d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684373853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1684373853
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2811685483
Short name T320
Test name
Test status
Simulation time 15105799288 ps
CPU time 325.98 seconds
Started Jun 29 06:00:52 PM PDT 24
Finished Jun 29 06:06:18 PM PDT 24
Peak memory 249396 kb
Host smart-c98dd2f5-1ea3-4b96-96f7-88400621d71a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811685483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2811685483
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.572157675
Short name T517
Test name
Test status
Simulation time 454538345 ps
CPU time 9.44 seconds
Started Jun 29 06:00:42 PM PDT 24
Finished Jun 29 06:00:51 PM PDT 24
Peak memory 249240 kb
Host smart-f1990853-69bf-4966-9cf7-2729ae6a539a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57215
7675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.572157675
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3269792622
Short name T39
Test name
Test status
Simulation time 1457870021 ps
CPU time 18.62 seconds
Started Jun 29 06:00:42 PM PDT 24
Finished Jun 29 06:01:01 PM PDT 24
Peak memory 253936 kb
Host smart-75ed478e-e408-469b-9491-0c84ba61b889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32697
92622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3269792622
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2550412562
Short name T523
Test name
Test status
Simulation time 218370253 ps
CPU time 24.39 seconds
Started Jun 29 06:00:50 PM PDT 24
Finished Jun 29 06:01:14 PM PDT 24
Peak memory 248792 kb
Host smart-64ec5175-37a0-4d4b-9f21-e051c6cf0ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25504
12562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2550412562
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1399111208
Short name T397
Test name
Test status
Simulation time 366686136 ps
CPU time 39.19 seconds
Started Jun 29 06:00:42 PM PDT 24
Finished Jun 29 06:01:22 PM PDT 24
Peak memory 256984 kb
Host smart-3cc7f043-fc20-43b6-8294-18220f05b42d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13991
11208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1399111208
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3519848407
Short name T638
Test name
Test status
Simulation time 15948573229 ps
CPU time 1401.03 seconds
Started Jun 29 06:00:52 PM PDT 24
Finished Jun 29 06:24:13 PM PDT 24
Peak memory 305816 kb
Host smart-87937345-a4fd-4112-948d-c1187802c72b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519848407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3519848407
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2736513248
Short name T215
Test name
Test status
Simulation time 53565357 ps
CPU time 2.63 seconds
Started Jun 29 05:52:13 PM PDT 24
Finished Jun 29 05:52:16 PM PDT 24
Peak memory 249528 kb
Host smart-5cc76482-e0c9-45bf-a8dd-9d25fcf9374e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2736513248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2736513248
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3337475214
Short name T494
Test name
Test status
Simulation time 21476272282 ps
CPU time 861.94 seconds
Started Jun 29 05:52:04 PM PDT 24
Finished Jun 29 06:06:27 PM PDT 24
Peak memory 273504 kb
Host smart-cea20cd6-5ab7-4e18-90c9-85a377d2b7c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337475214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3337475214
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1233714522
Short name T64
Test name
Test status
Simulation time 231966604 ps
CPU time 12.94 seconds
Started Jun 29 05:52:07 PM PDT 24
Finished Jun 29 05:52:20 PM PDT 24
Peak memory 249296 kb
Host smart-c6ce8122-fdf9-4d27-88e0-49d87c9635f6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1233714522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1233714522
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.743420183
Short name T42
Test name
Test status
Simulation time 6043149014 ps
CPU time 150.67 seconds
Started Jun 29 05:52:04 PM PDT 24
Finished Jun 29 05:54:35 PM PDT 24
Peak memory 257584 kb
Host smart-5e6aac13-372b-4ce4-a700-090ae02b7ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74342
0183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.743420183
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2074379768
Short name T370
Test name
Test status
Simulation time 1065359308 ps
CPU time 31.99 seconds
Started Jun 29 05:52:05 PM PDT 24
Finished Jun 29 05:52:38 PM PDT 24
Peak memory 249240 kb
Host smart-1f2b0564-6621-4f9d-ab20-55ffaefe3c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20743
79768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2074379768
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.337959791
Short name T291
Test name
Test status
Simulation time 41465096707 ps
CPU time 1091.71 seconds
Started Jun 29 05:52:06 PM PDT 24
Finished Jun 29 06:10:18 PM PDT 24
Peak memory 273944 kb
Host smart-c5562ca9-208b-4e12-8cc9-ea25b157a689
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337959791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.337959791
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.4122862423
Short name T84
Test name
Test status
Simulation time 5246764013 ps
CPU time 126.45 seconds
Started Jun 29 05:52:06 PM PDT 24
Finished Jun 29 05:54:12 PM PDT 24
Peak memory 249432 kb
Host smart-84e08d1d-6c2c-4ea1-b7da-cd7bd5249e79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122862423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.4122862423
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1756396778
Short name T25
Test name
Test status
Simulation time 75110089 ps
CPU time 5.47 seconds
Started Jun 29 05:52:05 PM PDT 24
Finished Jun 29 05:52:11 PM PDT 24
Peak memory 249276 kb
Host smart-034afb34-1ed6-450b-80d9-90073589a038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17563
96778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1756396778
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2239094084
Short name T493
Test name
Test status
Simulation time 2907188554 ps
CPU time 45.75 seconds
Started Jun 29 05:52:06 PM PDT 24
Finished Jun 29 05:52:52 PM PDT 24
Peak memory 248960 kb
Host smart-d613fdef-a0b3-4af2-a234-a59395311623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22390
94084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2239094084
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3528817654
Short name T595
Test name
Test status
Simulation time 3611984520 ps
CPU time 60.91 seconds
Started Jun 29 05:52:04 PM PDT 24
Finished Jun 29 05:53:06 PM PDT 24
Peak memory 249360 kb
Host smart-b4ab5e13-3319-4775-ba6a-31851be989ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35288
17654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3528817654
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3707157752
Short name T610
Test name
Test status
Simulation time 51399241 ps
CPU time 2.65 seconds
Started Jun 29 05:52:04 PM PDT 24
Finished Jun 29 05:52:07 PM PDT 24
Peak memory 251312 kb
Host smart-d7f99363-5eb0-4ed5-add3-ee9a860eec1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37071
57752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3707157752
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1210930805
Short name T216
Test name
Test status
Simulation time 18815332 ps
CPU time 2.58 seconds
Started Jun 29 05:52:14 PM PDT 24
Finished Jun 29 05:52:17 PM PDT 24
Peak memory 249524 kb
Host smart-0467a459-a402-4e6e-9936-0469f35173ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1210930805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1210930805
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2352340492
Short name T116
Test name
Test status
Simulation time 30199312161 ps
CPU time 1726.33 seconds
Started Jun 29 05:52:14 PM PDT 24
Finished Jun 29 06:21:01 PM PDT 24
Peak memory 273700 kb
Host smart-acc7c6bc-de51-410d-bf95-e2cefef842ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352340492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2352340492
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.798582713
Short name T4
Test name
Test status
Simulation time 1129126083 ps
CPU time 13.65 seconds
Started Jun 29 05:52:14 PM PDT 24
Finished Jun 29 05:52:28 PM PDT 24
Peak memory 249288 kb
Host smart-374b7795-9687-447f-a187-6ff8e277e274
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=798582713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.798582713
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.141171410
Short name T445
Test name
Test status
Simulation time 5614222264 ps
CPU time 123.44 seconds
Started Jun 29 05:52:14 PM PDT 24
Finished Jun 29 05:54:18 PM PDT 24
Peak memory 257532 kb
Host smart-1fb3d10d-dd7c-4b31-8164-f5f56838f008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14117
1410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.141171410
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1962576965
Short name T637
Test name
Test status
Simulation time 3507470060 ps
CPU time 55.55 seconds
Started Jun 29 05:52:15 PM PDT 24
Finished Jun 29 05:53:11 PM PDT 24
Peak memory 249356 kb
Host smart-32a512f4-8a06-41a2-8e36-6323383bbc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19625
76965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1962576965
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2467886015
Short name T650
Test name
Test status
Simulation time 53733507139 ps
CPU time 966.08 seconds
Started Jun 29 05:52:17 PM PDT 24
Finished Jun 29 06:08:23 PM PDT 24
Peak memory 273832 kb
Host smart-56838ef0-40c7-4cba-8ac6-880cdfee6721
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467886015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2467886015
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1595042951
Short name T235
Test name
Test status
Simulation time 96507663046 ps
CPU time 1752.94 seconds
Started Jun 29 05:52:16 PM PDT 24
Finished Jun 29 06:21:29 PM PDT 24
Peak memory 273788 kb
Host smart-1f396a62-3031-45fe-8526-ff7c1987e13a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595042951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1595042951
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1806816928
Short name T305
Test name
Test status
Simulation time 30616356532 ps
CPU time 308.89 seconds
Started Jun 29 05:52:18 PM PDT 24
Finished Jun 29 05:57:28 PM PDT 24
Peak memory 249428 kb
Host smart-2376cae2-442d-457f-a79d-3bb88cb1e552
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806816928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1806816928
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1296273247
Short name T641
Test name
Test status
Simulation time 171476386 ps
CPU time 18 seconds
Started Jun 29 05:52:17 PM PDT 24
Finished Jun 29 05:52:35 PM PDT 24
Peak memory 256584 kb
Host smart-1855c54d-6d27-40a3-bd54-c38be5deec0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12962
73247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1296273247
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.263460459
Short name T651
Test name
Test status
Simulation time 4025049427 ps
CPU time 59.49 seconds
Started Jun 29 05:52:18 PM PDT 24
Finished Jun 29 05:53:18 PM PDT 24
Peak memory 257124 kb
Host smart-7de489a4-d88a-4934-a6c4-e0805df147ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26346
0459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.263460459
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1023448641
Short name T631
Test name
Test status
Simulation time 759542511 ps
CPU time 25.86 seconds
Started Jun 29 05:52:13 PM PDT 24
Finished Jun 29 05:52:39 PM PDT 24
Peak memory 249292 kb
Host smart-a637ef57-9027-4eb2-9361-f24e653f6238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10234
48641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1023448641
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.348309962
Short name T368
Test name
Test status
Simulation time 3305532865 ps
CPU time 55.44 seconds
Started Jun 29 05:52:14 PM PDT 24
Finished Jun 29 05:53:10 PM PDT 24
Peak memory 257564 kb
Host smart-77aa8d2c-c845-4e56-8782-13244fb3fd84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34830
9962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.348309962
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.800859997
Short name T81
Test name
Test status
Simulation time 1449567382 ps
CPU time 22.46 seconds
Started Jun 29 05:52:16 PM PDT 24
Finished Jun 29 05:52:38 PM PDT 24
Peak memory 249004 kb
Host smart-59f073fb-8482-4178-b077-e91a364aa25d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800859997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.800859997
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2498381482
Short name T54
Test name
Test status
Simulation time 75555414624 ps
CPU time 7166.43 seconds
Started Jun 29 05:52:14 PM PDT 24
Finished Jun 29 07:51:42 PM PDT 24
Peak memory 355552 kb
Host smart-33338eb2-dfd4-416b-ba45-c5ffc9c68b03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498381482 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2498381482
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.611308132
Short name T218
Test name
Test status
Simulation time 57058132 ps
CPU time 3.45 seconds
Started Jun 29 05:52:25 PM PDT 24
Finished Jun 29 05:52:29 PM PDT 24
Peak memory 249532 kb
Host smart-12cd81d7-cbef-42d3-9369-aa08c27b8dd3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=611308132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.611308132
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2307211483
Short name T545
Test name
Test status
Simulation time 129382521877 ps
CPU time 2097.09 seconds
Started Jun 29 05:52:13 PM PDT 24
Finished Jun 29 06:27:11 PM PDT 24
Peak memory 288300 kb
Host smart-8236a60f-5af1-47fd-b89e-d6e424741971
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307211483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2307211483
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2066022716
Short name T683
Test name
Test status
Simulation time 782060610 ps
CPU time 11.14 seconds
Started Jun 29 05:52:24 PM PDT 24
Finished Jun 29 05:52:35 PM PDT 24
Peak memory 249208 kb
Host smart-059df319-47d4-4414-aa24-c9307dae0731
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2066022716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2066022716
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.609423440
Short name T458
Test name
Test status
Simulation time 8458539219 ps
CPU time 258.89 seconds
Started Jun 29 05:52:13 PM PDT 24
Finished Jun 29 05:56:33 PM PDT 24
Peak memory 257136 kb
Host smart-aa7209da-a14d-44dd-a4ee-762bc91bbca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60942
3440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.609423440
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1702648332
Short name T82
Test name
Test status
Simulation time 378867156 ps
CPU time 10.87 seconds
Started Jun 29 05:52:13 PM PDT 24
Finished Jun 29 05:52:24 PM PDT 24
Peak memory 255524 kb
Host smart-f08cc5d0-d397-4cd5-8203-6dcf9510ab4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17026
48332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1702648332
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3056712306
Short name T338
Test name
Test status
Simulation time 529589640033 ps
CPU time 2395.6 seconds
Started Jun 29 05:52:22 PM PDT 24
Finished Jun 29 06:32:18 PM PDT 24
Peak memory 289608 kb
Host smart-c214e468-953d-4a68-85d3-eeb6fd8cce1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056712306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3056712306
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1915790581
Short name T106
Test name
Test status
Simulation time 37852424218 ps
CPU time 2354.16 seconds
Started Jun 29 05:52:23 PM PDT 24
Finished Jun 29 06:31:38 PM PDT 24
Peak memory 288804 kb
Host smart-f98c646d-f567-4a1c-ad14-f080253b9e52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915790581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1915790581
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.726663232
Short name T459
Test name
Test status
Simulation time 12337742153 ps
CPU time 536.08 seconds
Started Jun 29 05:52:13 PM PDT 24
Finished Jun 29 06:01:09 PM PDT 24
Peak memory 249396 kb
Host smart-f96668ab-eb7a-42f0-a506-7bed0b032bc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726663232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.726663232
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1134011028
Short name T66
Test name
Test status
Simulation time 1625983176 ps
CPU time 27.93 seconds
Started Jun 29 05:52:12 PM PDT 24
Finished Jun 29 05:52:40 PM PDT 24
Peak memory 257184 kb
Host smart-75cfc63c-8736-4808-a9b3-b104cd3108bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11340
11028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1134011028
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3515416141
Short name T441
Test name
Test status
Simulation time 2475158584 ps
CPU time 40.69 seconds
Started Jun 29 05:52:14 PM PDT 24
Finished Jun 29 05:52:55 PM PDT 24
Peak memory 249440 kb
Host smart-7cd91a14-1ca8-46d2-94f0-6bacc4fe3816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35154
16141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3515416141
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1546911363
Short name T58
Test name
Test status
Simulation time 168966374 ps
CPU time 19.85 seconds
Started Jun 29 05:52:14 PM PDT 24
Finished Jun 29 05:52:34 PM PDT 24
Peak memory 256944 kb
Host smart-6c13cefe-6617-4912-85f1-10d2f4040589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15469
11363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1546911363
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2587494802
Short name T416
Test name
Test status
Simulation time 776529413 ps
CPU time 31.04 seconds
Started Jun 29 05:52:13 PM PDT 24
Finished Jun 29 05:52:44 PM PDT 24
Peak memory 256756 kb
Host smart-d18b8573-a15d-4575-b46c-22b42b754b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25874
94802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2587494802
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1741857711
Short name T555
Test name
Test status
Simulation time 123349508516 ps
CPU time 1985.96 seconds
Started Jun 29 05:52:23 PM PDT 24
Finished Jun 29 06:25:30 PM PDT 24
Peak memory 286216 kb
Host smart-91ca6b71-96ed-432d-b8ed-5d5b625101ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741857711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1741857711
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.5517956
Short name T211
Test name
Test status
Simulation time 41639855 ps
CPU time 2.46 seconds
Started Jun 29 05:52:25 PM PDT 24
Finished Jun 29 05:52:28 PM PDT 24
Peak memory 249464 kb
Host smart-12a36613-f379-4e17-9a43-8de5f8006663
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=5517956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.5517956
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1351282367
Short name T582
Test name
Test status
Simulation time 84434403902 ps
CPU time 1488.45 seconds
Started Jun 29 05:52:25 PM PDT 24
Finished Jun 29 06:17:14 PM PDT 24
Peak memory 273496 kb
Host smart-ea86fa08-e8a6-40e0-8214-4047f6c109fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351282367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1351282367
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1294988315
Short name T367
Test name
Test status
Simulation time 167724835 ps
CPU time 11.2 seconds
Started Jun 29 05:52:23 PM PDT 24
Finished Jun 29 05:52:34 PM PDT 24
Peak memory 249256 kb
Host smart-5bb65d77-c32f-4811-b42a-bee3894e43cd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1294988315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1294988315
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3571263692
Short name T394
Test name
Test status
Simulation time 417679922 ps
CPU time 43.89 seconds
Started Jun 29 05:52:25 PM PDT 24
Finished Jun 29 05:53:10 PM PDT 24
Peak memory 257400 kb
Host smart-4d5445b5-f32a-4e0e-a942-2246f85baf71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35712
63692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3571263692
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3204753184
Short name T457
Test name
Test status
Simulation time 1154803849 ps
CPU time 23.86 seconds
Started Jun 29 05:52:22 PM PDT 24
Finished Jun 29 05:52:47 PM PDT 24
Peak memory 255720 kb
Host smart-0e121631-f0c9-4c6a-8143-5ef258c1a8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047
53184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3204753184
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.569575601
Short name T376
Test name
Test status
Simulation time 86458367324 ps
CPU time 2713.9 seconds
Started Jun 29 05:52:23 PM PDT 24
Finished Jun 29 06:37:38 PM PDT 24
Peak memory 289776 kb
Host smart-05b08c84-2153-4f07-9734-3abe22810523
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569575601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.569575601
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.581745722
Short name T502
Test name
Test status
Simulation time 39752482942 ps
CPU time 429.49 seconds
Started Jun 29 05:52:23 PM PDT 24
Finished Jun 29 05:59:33 PM PDT 24
Peak memory 249396 kb
Host smart-9af3fe18-d252-4aaf-80a8-99535cfdbee1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581745722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.581745722
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3597141430
Short name T602
Test name
Test status
Simulation time 2070982312 ps
CPU time 16.37 seconds
Started Jun 29 05:52:23 PM PDT 24
Finished Jun 29 05:52:40 PM PDT 24
Peak memory 255884 kb
Host smart-c4b53805-157a-424e-84cd-4cc29237ab18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35971
41430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3597141430
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3153249216
Short name T111
Test name
Test status
Simulation time 84483017 ps
CPU time 10.57 seconds
Started Jun 29 05:52:24 PM PDT 24
Finished Jun 29 05:52:35 PM PDT 24
Peak memory 248840 kb
Host smart-c64aa52d-d6d3-49ad-af1a-ed8f29bb4375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31532
49216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3153249216
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3038502984
Short name T283
Test name
Test status
Simulation time 1384776306 ps
CPU time 50.73 seconds
Started Jun 29 05:52:23 PM PDT 24
Finished Jun 29 05:53:14 PM PDT 24
Peak memory 248824 kb
Host smart-6ab0f6e0-f293-4ecd-82ed-d89f6d58e4ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30385
02984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3038502984
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1954017559
Short name T687
Test name
Test status
Simulation time 173119112 ps
CPU time 4.37 seconds
Started Jun 29 05:52:23 PM PDT 24
Finished Jun 29 05:52:28 PM PDT 24
Peak memory 251372 kb
Host smart-8296f201-0bf9-4aa4-966b-8fee71f61340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19540
17559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1954017559
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1244893127
Short name T125
Test name
Test status
Simulation time 64948823956 ps
CPU time 3907.73 seconds
Started Jun 29 05:52:22 PM PDT 24
Finished Jun 29 06:57:30 PM PDT 24
Peak memory 305340 kb
Host smart-261377cc-bc56-4435-ba7e-2dfef0dcbc4a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244893127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1244893127
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.754095426
Short name T210
Test name
Test status
Simulation time 35813372 ps
CPU time 2.09 seconds
Started Jun 29 05:52:30 PM PDT 24
Finished Jun 29 05:52:33 PM PDT 24
Peak memory 249472 kb
Host smart-006b315b-5ce5-4763-9b9c-a1cad7178a7c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=754095426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.754095426
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.160748375
Short name T498
Test name
Test status
Simulation time 35239684196 ps
CPU time 680.63 seconds
Started Jun 29 05:52:37 PM PDT 24
Finished Jun 29 06:03:59 PM PDT 24
Peak memory 273972 kb
Host smart-b9764cb9-43dc-4da7-93bb-a3e1fc6eeb0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160748375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.160748375
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2219729321
Short name T432
Test name
Test status
Simulation time 14421801038 ps
CPU time 58.03 seconds
Started Jun 29 05:52:32 PM PDT 24
Finished Jun 29 05:53:30 PM PDT 24
Peak memory 249428 kb
Host smart-effac065-422a-484d-9974-d5fe7f36a69c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2219729321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2219729321
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.780000489
Short name T666
Test name
Test status
Simulation time 27128164 ps
CPU time 4.66 seconds
Started Jun 29 05:52:31 PM PDT 24
Finished Jun 29 05:52:36 PM PDT 24
Peak memory 251948 kb
Host smart-b25049a1-e7ea-4704-b0dc-6cd2a7a04436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78000
0489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.780000489
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3586588229
Short name T446
Test name
Test status
Simulation time 157026012 ps
CPU time 12.18 seconds
Started Jun 29 05:52:32 PM PDT 24
Finished Jun 29 05:52:44 PM PDT 24
Peak memory 256952 kb
Host smart-846ef896-aa0a-4ebf-94a0-124a06368557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35865
88229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3586588229
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2685788135
Short name T327
Test name
Test status
Simulation time 27283480963 ps
CPU time 1263.34 seconds
Started Jun 29 05:52:40 PM PDT 24
Finished Jun 29 06:13:44 PM PDT 24
Peak memory 288216 kb
Host smart-aa9a91a4-e44f-45bc-af06-7788d8c1bdc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685788135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2685788135
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2028773328
Short name T480
Test name
Test status
Simulation time 9015872315 ps
CPU time 1109.96 seconds
Started Jun 29 05:52:30 PM PDT 24
Finished Jun 29 06:11:00 PM PDT 24
Peak memory 284776 kb
Host smart-fccb3c0e-22f3-431a-98d2-898e8f6aa918
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028773328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2028773328
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3223248081
Short name T558
Test name
Test status
Simulation time 21971504879 ps
CPU time 435.79 seconds
Started Jun 29 05:52:31 PM PDT 24
Finished Jun 29 05:59:47 PM PDT 24
Peak memory 249400 kb
Host smart-a94875b9-7092-4082-9fe1-cea92f34a288
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223248081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3223248081
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3126109113
Short name T356
Test name
Test status
Simulation time 328745615 ps
CPU time 17.59 seconds
Started Jun 29 05:52:32 PM PDT 24
Finished Jun 29 05:52:50 PM PDT 24
Peak memory 256736 kb
Host smart-12bf348f-ad55-47c1-8d3f-2c2c8ab28c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31261
09113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3126109113
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3173606733
Short name T540
Test name
Test status
Simulation time 262209819 ps
CPU time 5.34 seconds
Started Jun 29 05:52:32 PM PDT 24
Finished Jun 29 05:52:37 PM PDT 24
Peak memory 240416 kb
Host smart-129a0775-d80b-4c4b-af97-d8b2167d675e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31736
06733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3173606733
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.468068055
Short name T124
Test name
Test status
Simulation time 2646072294 ps
CPU time 48.42 seconds
Started Jun 29 05:52:33 PM PDT 24
Finished Jun 29 05:53:21 PM PDT 24
Peak memory 256904 kb
Host smart-768b9c60-b3bb-4d18-9e72-2a34e2680ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46806
8055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.468068055
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2962799461
Short name T477
Test name
Test status
Simulation time 305194919 ps
CPU time 23.32 seconds
Started Jun 29 05:52:46 PM PDT 24
Finished Jun 29 05:53:09 PM PDT 24
Peak memory 256468 kb
Host smart-cfe47eb7-4391-4858-93ba-2c73e7bd687c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29627
99461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2962799461
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.4026565704
Short name T24
Test name
Test status
Simulation time 68899634015 ps
CPU time 5332.02 seconds
Started Jun 29 05:52:39 PM PDT 24
Finished Jun 29 07:21:32 PM PDT 24
Peak memory 330840 kb
Host smart-e56625cb-f2ec-4737-8423-75fdc369dda0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026565704 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.4026565704
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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