Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	79085	1			T4	24		T14	26		T8	3
class_i[0x1]	54870	1			T4	10		T6	1		T14	4
class_i[0x2]	70237	1			T4	4602		T6	9		T8	9
class_i[0x3]	62299	1			T6	36		T15	4963		T9	3

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	68673	1			T4	1162		T6	18		T14	10
alert[0x1]	62933	1			T4	1251		T6	13		T14	14
alert[0x2]	68519	1			T4	1095		T6	11		T14	4
alert[0x3]	66366	1			T4	1128		T6	4		T14	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

266200

1

T4

4636

T6

46

T14

30

esc_ping_fail

291

1

T8

9

T9

6

T10

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	68585	1			T4	1162		T6	18		T14	10
esc_integrity_fail	alert[0x1]	62862	1			T4	1251		T6	13		T14	14
esc_integrity_fail	alert[0x2]	68453	1			T4	1095		T6	11		T14	4
esc_integrity_fail	alert[0x3]	66300	1			T4	1128		T6	4		T14	2
esc_ping_fail	alert[0x0]	88	1			T8	2		T9	2		T10	1
esc_ping_fail	alert[0x1]	71	1			T8	2		T9	1		T275	2
esc_ping_fail	alert[0x2]	66	1			T8	2		T9	2		T10	1
esc_ping_fail	alert[0x3]	66	1			T8	3		T9	1		T275	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	79032	1			T4	24		T14	26		T8	3
esc_integrity_fail	class_i[0x1]	54768	1			T4	10		T6	1		T14	4
esc_integrity_fail	class_i[0x2]	70146	1			T4	4602		T6	9		T9	7
esc_integrity_fail	class_i[0x3]	62254	1			T6	36		T15	4963		T9	2
esc_ping_fail	class_i[0x0]	53	1			T9	5		T286	1		T283	1
esc_ping_fail	class_i[0x1]	102	1			T275	8		T281	8		T278	3
esc_ping_fail	class_i[0x2]	91	1			T8	9		T10	2		T286	2
esc_ping_fail	class_i[0x3]	45	1			T9	1		T286	1		T287	3