Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	192	1			T8	1		T15	1		T21	1
index[0x1]	192	1			T1	1		T14	1		T43	2
index[0x2]	165	1			T4	2		T5	1		T7	1
index[0x3]	173	1			T4	2		T6	1		T8	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	255	1			T4	2		T5	1		T7	1
lens_less_than_1000[1]	119	1			T4	1		T43	1		T27	1
lens_less_than_1000[2]	106	1			T4	1		T8	1		T15	2
lens_less_than_1000[3]	88	1			T1	1		T63	2		T25	1
lens_less_than_1000[4]	50	1			T8	1		T15	1		T43	1
lens_less_than_1000[5]	28	1			T22	1		T68	1		T70	1
lens_less_than_1000[6]	19	1			T248	1		T81	1		T90	1
lens_less_than_1000[7]	16	1			T47	1		T26	1		T249	1
lens_less_than_1000[8]	19	1			T26	1		T52	2		T249	1
lens_less_than_1000[9]	6	1			T52	1		T250	2		T251	2
len_2	16	1			T6	1		T25	1		T32	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x3]]	[lens_less_than_1000[6]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	62	1			T21	1		T27	1		T68	1
index[0x0]	lens_less_than_1000[1]	35	1			T28	1		T47	1		T64	1
index[0x0]	lens_less_than_1000[2]	28	1			T15	1		T252	1		T253	1
index[0x0]	lens_less_than_1000[3]	22	1			T25	1		T42	1		T76	2
index[0x0]	lens_less_than_1000[4]	14	1			T8	1		T254	1		T192	1
index[0x0]	lens_less_than_1000[5]	8	1			T81	1		T255	1		T256	1
index[0x0]	lens_less_than_1000[6]	12	1			T81	1		T90	1		T257	1
index[0x0]	lens_less_than_1000[7]	4	1			T249	1		T58	1		T258	1
index[0x0]	lens_less_than_1000[8]	6	1			T259	2		T81	1		T91	1
index[0x0]	len_2	1	1			T260	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	71	1			T14	1		T27	1		T80	2
index[0x1]	lens_less_than_1000[1]	32	1			T43	1		T27	1		T47	1
index[0x1]	lens_less_than_1000[2]	26	1			T43	1		T23	1		T42	1
index[0x1]	lens_less_than_1000[3]	26	1			T1	1		T63	2		T26	1
index[0x1]	lens_less_than_1000[4]	8	1			T47	1		T81	1		T242	1
index[0x1]	lens_less_than_1000[5]	8	1			T23	1		T51	1		T249	1
index[0x1]	lens_less_than_1000[6]	4	1			T248	1		T261	1		T225	1
index[0x1]	lens_less_than_1000[7]	7	1			T26	1		T105	1		T235	1
index[0x1]	lens_less_than_1000[8]	5	1			T81	1		T90	1		T262	3
index[0x1]	lens_less_than_1000[9]	3	1			T52	1		T250	2		-	-
index[0x1]	len_2	2	1			T187	1		T263	1		-	-
index[0x2]	lens_less_than_1000[0]	66	1			T4	1		T5	1		T7	1
index[0x2]	lens_less_than_1000[1]	30	1			T4	1		T28	1		T264	1
index[0x2]	lens_less_than_1000[2]	20	1			T47	1		T220	1		T26	1
index[0x2]	lens_less_than_1000[3]	16	1			T265	1		T266	1		T57	1
index[0x2]	lens_less_than_1000[4]	9	1			T15	1		T43	1		T267	1
index[0x2]	lens_less_than_1000[5]	8	1			T22	1		T68	1		T32	1
index[0x2]	lens_less_than_1000[6]	3	1			T105	1		T268	2		-	-
index[0x2]	lens_less_than_1000[7]	2	1			T78	1		T213	1		-	-
index[0x2]	lens_less_than_1000[8]	5	1			T52	1		T249	1		T235	1
index[0x2]	lens_less_than_1000[9]	2	1			T251	2		-	-		-	-
index[0x2]	len_2	4	1			T25	1		T32	1		T260	2
index[0x3]	lens_less_than_1000[0]	56	1			T4	1		T47	1		T64	1
index[0x3]	lens_less_than_1000[1]	22	1			T48	1		T25	1		T269	1
index[0x3]	lens_less_than_1000[2]	32	1			T4	1		T8	1		T15	1
index[0x3]	lens_less_than_1000[3]	24	1			T49	5		T26	1		T174	2
index[0x3]	lens_less_than_1000[4]	19	1			T270	1		T81	1		T85	1
index[0x3]	lens_less_than_1000[5]	4	1			T70	1		T255	1		T94	1
index[0x3]	lens_less_than_1000[7]	3	1			T47	1		T245	1		T213	1
index[0x3]	lens_less_than_1000[8]	3	1			T26	1		T52	1		T271	1
index[0x3]	lens_less_than_1000[9]	1	1			T260	1		-	-		-	-
index[0x3]	len_2	9	1			T6	1		T58	6		T272	1