Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	68	1			T21	1		T60	1		T25	2
class_index[0x1]	50	1			T1	1		T21	1		T27	1
class_index[0x2]	60	1			T22	1		T27	1		T68	1
class_index[0x3]	66	1			T43	1		T21	1		T69	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	94	1			T1	1		T21	3		T27	1
intr_timeout_cnt[1]	49	1			T47	1		T70	1		T25	1
intr_timeout_cnt[2]	27	1			T68	1		T69	1		T190	1
intr_timeout_cnt[3]	18	1			T43	1		T108	1		T76	1
intr_timeout_cnt[4]	20	1			T22	1		T25	2		T74	1
intr_timeout_cnt[5]	7	1			T27	1		T85	1		T227	1
intr_timeout_cnt[6]	10	1			T25	1		T81	1		T85	1
intr_timeout_cnt[7]	8	1			T85	2		T228	1		T229	1
intr_timeout_cnt[8]	7	1			T26	2		T90	1		T230	1
intr_timeout_cnt[9]	4	1			T230	1		T91	1		T231	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[3]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	29	1			T21	1		T60	1		T25	2
class_index[0x0]	intr_timeout_cnt[1]	19	1			T77	1		T81	1		T82	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T190	1		T232	1		T233	2
class_index[0x0]	intr_timeout_cnt[3]	3	1			T57	1		T234	1		T231	1
class_index[0x0]	intr_timeout_cnt[4]	5	1			T74	1		T53	1		T235	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T24	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T228	1		T191	1		T236	1
class_index[0x0]	intr_timeout_cnt[8]	2	1			T230	1		T237	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	19	1			T1	1		T21	1		T28	1
class_index[0x1]	intr_timeout_cnt[1]	11	1			T47	1		T25	1		T30	1
class_index[0x1]	intr_timeout_cnt[2]	9	1			T238	2		T58	2		T239	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T230	2		T234	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	2	1			T27	1		T85	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T25	1		T240	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T26	1		T241	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T231	1		T215	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	13	1			T27	1		T23	1		T78	1
class_index[0x2]	intr_timeout_cnt[1]	12	1			T70	1		T57	1		T82	1
class_index[0x2]	intr_timeout_cnt[2]	6	1			T68	1		T242	1		T243	1
class_index[0x2]	intr_timeout_cnt[3]	8	1			T76	1		T81	1		T238	1
class_index[0x2]	intr_timeout_cnt[4]	7	1			T22	1		T25	1		T230	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T240	1		T244	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	6	1			T81	1		T229	1		T245	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T85	1		T187	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T26	1		T90	1		T215	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T91	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	33	1			T21	1		T49	5		T23	1
class_index[0x3]	intr_timeout_cnt[1]	7	1			T109	1		T97	1		T235	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T69	1		T103	1		T246	1
class_index[0x3]	intr_timeout_cnt[3]	7	1			T43	1		T108	1		T233	3
class_index[0x3]	intr_timeout_cnt[4]	5	1			T25	1		T228	1		T244	3
class_index[0x3]	intr_timeout_cnt[5]	2	1			T227	1		T24	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T85	1		T247	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	3	1			T85	1		T229	1		T247	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T230	1		-	-		-	-