Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	362182	1			T1	23		T2	13		T3	13
all_values[1]	362182	1			T1	23		T2	13		T3	13
all_values[2]	362182	1			T1	23		T2	13		T3	13
all_values[3]	362182	1			T1	23		T2	13		T3	13

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

720899

1

T1

46

T2

21

T3

20

auto[1]

727829

1

T1

46

T2

31

T3

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

861775

1

T1

48

T2

48

T3

28

auto[1]

586953

1

T1

44

T2

4

T3

24

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104310	1			T1	6		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	76234	1			T1	6		T2	2		T3	2
all_values[0]	auto[1]	auto[0]	105440	1			T1	6		T2	7		T3	5
all_values[0]	auto[1]	auto[1]	76198	1			T1	5		T2	2		T3	4
all_values[1]	auto[0]	auto[0]	107462	1			T1	6		T2	7		T3	4
all_values[1]	auto[0]	auto[1]	72706	1			T1	5		T3	4		T4	658
all_values[1]	auto[1]	auto[0]	108963	1			T1	6		T2	6		T3	3
all_values[1]	auto[1]	auto[1]	73051	1			T1	6		T3	2		T4	608
all_values[2]	auto[0]	auto[0]	107368	1			T1	8		T2	6		T3	3
all_values[2]	auto[0]	auto[1]	72357	1			T1	7		T3	3		T4	661
all_values[2]	auto[1]	auto[0]	109463	1			T1	4		T2	7		T3	4
all_values[2]	auto[1]	auto[1]	72994	1			T1	4		T3	3		T4	685
all_values[3]	auto[0]	auto[0]	108952	1			T1	4		T2	4		T3	1
all_values[3]	auto[0]	auto[1]	71510	1			T1	4		T3	1		T4	651
all_values[3]	auto[1]	auto[0]	109817	1			T1	8		T2	9		T3	6
all_values[3]	auto[1]	auto[1]	71903	1			T1	7		T3	5		T4	658