Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	362182	1			T1	23		T2	13		T3	13
all_pins[1]	362182	1			T1	23		T2	13		T3	13
all_pins[2]	362182	1			T1	23		T2	13		T3	13
all_pins[3]	362182	1			T1	23		T2	13		T3	13

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1154582	1			T1	70		T2	50		T3	38
values[0x1]	294146	1			T1	22		T2	2		T3	14
transitions[0x0=>0x1]	195093	1			T1	15		T2	2		T3	8
transitions[0x1=>0x0]	195361	1			T1	16		T2	2		T3	8

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	285984	1			T1	18		T2	11		T3	9
all_pins[0]	values[0x1]	76198	1			T1	5		T2	2		T3	4
all_pins[0]	transitions[0x0=>0x1]	75508	1			T1	4		T2	2		T3	4
all_pins[0]	transitions[0x1=>0x0]	71481	1			T1	7		T3	5		T4	656
all_pins[1]	values[0x0]	289131	1			T1	17		T2	13		T3	11
all_pins[1]	values[0x1]	73051	1			T1	6		T3	2		T4	608
all_pins[1]	transitions[0x0=>0x1]	40319	1			T1	4		T4	367		T5	128
all_pins[1]	transitions[0x1=>0x0]	43466	1			T1	3		T2	2		T3	2
all_pins[2]	values[0x0]	289188	1			T1	19		T2	13		T3	10
all_pins[2]	values[0x1]	72994	1			T1	4		T3	3		T4	685
all_pins[2]	transitions[0x0=>0x1]	39911	1			T1	2		T3	2		T4	374
all_pins[2]	transitions[0x1=>0x0]	39968	1			T1	4		T3	1		T4	297
all_pins[3]	values[0x0]	290279	1			T1	16		T2	13		T3	8
all_pins[3]	values[0x1]	71903	1			T1	7		T3	5		T4	658
all_pins[3]	transitions[0x0=>0x1]	39355	1			T1	5		T3	2		T4	339
all_pins[3]	transitions[0x1=>0x0]	40446	1			T1	2		T4	366		T5	154