Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	100854	1			T4	787		T5	235		T6	633
accum_cnt_1000	244001	1			T4	2623		T5	1406		T6	702
accum_cnt_100	28798	1			T4	267		T5	82		T6	35
accum_cnt_50	68431	1			T1	28		T4	1667		T5	975
accum_cnt_10	191636	1			T1	32		T2	11		T3	15
accum_cnt_0	384705	1			T1	28		T2	33		T3	33

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	267330	1			T1	22		T2	11		T3	12
class_index[0x1]	267330	1			T1	22		T2	11		T3	12
class_index[0x2]	267330	1			T1	22		T2	11		T3	12
class_index[0x3]	267330	1			T1	22		T2	11		T3	12

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	28355	1			T5	235		T14	189		T15	681
class_index[0x0]	accum_cnt_1000	70773	1			T4	1405		T5	600		T14	774
class_index[0x0]	accum_cnt_100	9144	1			T4	121		T5	36		T14	46
class_index[0x0]	accum_cnt_50	18757	1			T1	2		T4	165		T5	26
class_index[0x0]	accum_cnt_10	45944	1			T1	16		T2	11		T3	3
class_index[0x0]	accum_cnt_0	79950	1			T1	4		T3	9		T4	125
class_index[0x1]	accum_cnt_2000	24674	1			T4	625		T14	497		T17	609
class_index[0x1]	accum_cnt_1000	54700	1			T4	805		T14	506		T43	65
class_index[0x1]	accum_cnt_100	6000	1			T4	70		T14	25		T43	13
class_index[0x1]	accum_cnt_50	17581	1			T1	12		T4	55		T5	904
class_index[0x1]	accum_cnt_10	48317	1			T1	9		T3	6		T4	32
class_index[0x1]	accum_cnt_0	106382	1			T1	1		T2	11		T3	6
class_index[0x2]	accum_cnt_2000	23846	1			T14	483		T15	455		T28	68
class_index[0x2]	accum_cnt_1000	61762	1			T4	87		T5	806		T7	1161
class_index[0x2]	accum_cnt_100	6201	1			T4	52		T5	46		T7	151
class_index[0x2]	accum_cnt_50	19321	1			T1	14		T4	1419		T5	45
class_index[0x2]	accum_cnt_10	45578	1			T1	7		T4	27		T5	6
class_index[0x2]	accum_cnt_0	96271	1			T1	1		T2	11		T3	12
class_index[0x3]	accum_cnt_2000	23979	1			T4	162		T6	633		T14	510
class_index[0x3]	accum_cnt_1000	56766	1			T4	326		T6	702		T14	480
class_index[0x3]	accum_cnt_100	7453	1			T4	24		T6	35		T14	21
class_index[0x3]	accum_cnt_50	12772	1			T4	28		T6	18		T14	25
class_index[0x3]	accum_cnt_10	51797	1			T3	6		T4	118		T5	899
class_index[0x3]	accum_cnt_0	102102	1			T1	22		T2	11		T3	6