Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5897	1			T9	1		T17	38		T68	925
alert[0x1]	9672	1			T4	2		T5	34		T8	1
alert[0x2]	2442	1			T14	2		T15	42		T27	1
alert[0x3]	4443	1			T8	1		T15	103		T80	323
alert[0x4]	2466	1			T5	277		T15	152		T28	195
alert[0x5]	9121	1			T14	6		T28	19		T26	3
alert[0x6]	10497	1			T4	2584		T80	5		T68	45
alert[0x7]	6867	1			T80	18		T28	45		T47	1
alert[0x8]	3510	1			T5	17		T7	1		T8	1
alert[0x9]	11713	1			T4	96		T15	420		T22	2
alert[0xa]	6733	1			T5	15		T14	1		T80	419
alert[0xb]	3329	1			T5	10		T8	1		T28	91
alert[0xc]	3906	1			T4	1111		T5	51		T9	1
alert[0xd]	2867	1			T5	3		T8	1		T15	84
alert[0xe]	7204	1			T4	237		T15	236		T22	8
alert[0xf]	6243	1			T28	688		T69	3		T25	1035
alert[0x10]	11099	1			T5	24		T8	2		T15	970
alert[0x11]	2802	1			T5	29		T15	92		T68	1
alert[0x12]	4027	1			T4	372		T5	19		T15	82
alert[0x13]	3971	1			T4	25		T8	1		T15	7
alert[0x14]	4819	1			T27	76		T80	159		T47	15
alert[0x15]	7449	1			T80	496		T68	20		T47	120
alert[0x16]	6630	1			T8	1		T15	1397		T80	138
alert[0x17]	6507	1			T15	31		T104	249		T275	1
alert[0x18]	7417	1			T15	672		T27	1		T80	129
alert[0x19]	7098	1			T8	1		T15	7		T9	1
alert[0x1a]	8647	1			T4	72		T8	2		T9	1
alert[0x1b]	3971	1			T8	1		T15	64		T22	5
alert[0x1c]	6215	1			T5	1519		T6	1		T22	3
alert[0x1d]	4561	1			T5	1		T14	19		T8	2
alert[0x1e]	6212	1			T15	528		T80	127		T68	324
alert[0x1f]	10350	1			T5	20		T68	729		T98	1
alert[0x20]	11084	1			T14	3		T22	92		T28	110
alert[0x21]	11051	1			T15	325		T9	1		T22	1
alert[0x22]	11394	1			T4	217		T6	10		T14	4
alert[0x23]	6851	1			T15	140		T27	37		T47	27
alert[0x24]	9726	1			T8	1		T15	25		T27	1
alert[0x25]	9988	1			T8	1		T15	609		T9	1
alert[0x26]	5058	1			T4	3		T5	31		T15	6
alert[0x27]	5002	1			T4	3		T15	369		T68	3
alert[0x28]	3491	1			T4	46		T27	1		T68	198
alert[0x29]	11183	1			T5	15		T14	3		T9	1
alert[0x2a]	16721	1			T5	62		T8	1		T80	80
alert[0x2b]	7932	1			T15	323		T68	14		T28	208
alert[0x2c]	11337	1			T4	66		T5	273		T15	1001
alert[0x2d]	3980	1			T6	5		T68	1251		T47	210
alert[0x2e]	8118	1			T4	5		T5	10		T14	1
alert[0x2f]	6333	1			T5	2802		T6	1		T22	1
alert[0x30]	3159	1			T5	553		T80	20		T68	65
alert[0x31]	9245	1			T5	4		T15	16		T22	2
alert[0x32]	3580	1			T5	64		T80	5		T10	1
alert[0x33]	5321	1			T4	33		T6	1		T15	131
alert[0x34]	14597	1			T4	1733		T5	1		T8	1
alert[0x35]	2425	1			T5	3		T14	3		T15	106
alert[0x36]	5356	1			T80	290		T68	6		T28	50
alert[0x37]	9022	1			T14	3		T27	1		T80	470
alert[0x38]	9168	1			T6	2		T15	12		T80	44
alert[0x39]	5081	1			T4	602		T5	56		T80	212
alert[0x3a]	10518	1			T4	38		T10	1		T47	173
alert[0x3b]	5711	1			T15	339		T22	4		T68	20
alert[0x3c]	7083	1			T4	1012		T68	862		T28	37
alert[0x3d]	15870	1			T4	2		T8	1		T15	82
alert[0x3e]	17532	1			T4	18		T8	1		T68	81
alert[0x3f]	13650	1			T80	349		T64	1		T25	4006
alert[0x40]	10385	1			T4	2		T5	491		T15	47

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	166167	1			T4	14		T6	12		T7	1
class_i[0x1]	127590	1			T4	21		T5	6384		T14	16
class_i[0x2]	75826	1			T4	7		T6	8		T8	1
class_i[0x3]	116054	1			T4	8237		T14	29		T15	14213

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

484899

1

T4

8279

T5

6384

T6

20

alert_ping_fail

738

1

T7

1

T8

21

T9

10

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5885	1			T17	38		T68	925		T104	122
alert_integrity_fail	alert[0x1]	9662	1			T4	2		T5	34		T22	1
alert_integrity_fail	alert[0x2]	2432	1			T14	2		T15	42		T27	1
alert_integrity_fail	alert[0x3]	4422	1			T15	103		T80	323		T68	1418
alert_integrity_fail	alert[0x4]	2456	1			T5	277		T15	152		T28	195
alert_integrity_fail	alert[0x5]	9109	1			T14	6		T28	19		T26	3
alert_integrity_fail	alert[0x6]	10488	1			T4	2584		T80	5		T68	45
alert_integrity_fail	alert[0x7]	6852	1			T80	18		T28	45		T47	1
alert_integrity_fail	alert[0x8]	3491	1			T5	17		T15	370		T28	32
alert_integrity_fail	alert[0x9]	11702	1			T4	96		T15	420		T22	2
alert_integrity_fail	alert[0xa]	6714	1			T5	15		T14	1		T80	419
alert_integrity_fail	alert[0xb]	3316	1			T5	10		T28	91		T25	133
alert_integrity_fail	alert[0xc]	3896	1			T4	1111		T5	51		T80	647
alert_integrity_fail	alert[0xd]	2859	1			T5	3		T15	84		T22	1
alert_integrity_fail	alert[0xe]	7193	1			T4	237		T15	236		T22	8
alert_integrity_fail	alert[0xf]	6234	1			T28	688		T69	3		T25	1035
alert_integrity_fail	alert[0x10]	11089	1			T5	24		T15	970		T80	4
alert_integrity_fail	alert[0x11]	2797	1			T5	29		T15	92		T68	1
alert_integrity_fail	alert[0x12]	4019	1			T4	372		T5	19		T15	82
alert_integrity_fail	alert[0x13]	3955	1			T4	25		T15	7		T80	4
alert_integrity_fail	alert[0x14]	4804	1			T27	76		T80	159		T47	15
alert_integrity_fail	alert[0x15]	7434	1			T80	496		T68	20		T47	120
alert_integrity_fail	alert[0x16]	6614	1			T15	1397		T80	138		T68	6
alert_integrity_fail	alert[0x17]	6494	1			T15	31		T104	249		T276	3
alert_integrity_fail	alert[0x18]	7403	1			T15	672		T27	1		T80	129
alert_integrity_fail	alert[0x19]	7084	1			T15	7		T68	319		T47	28
alert_integrity_fail	alert[0x1a]	8632	1			T4	72		T80	2		T68	78
alert_integrity_fail	alert[0x1b]	3957	1			T15	64		T22	5		T80	141
alert_integrity_fail	alert[0x1c]	6208	1			T5	1519		T6	1		T22	3
alert_integrity_fail	alert[0x1d]	4552	1			T5	1		T14	19		T15	1152
alert_integrity_fail	alert[0x1e]	6202	1			T15	528		T80	127		T68	324
alert_integrity_fail	alert[0x1f]	10340	1			T5	20		T68	729		T28	34
alert_integrity_fail	alert[0x20]	11076	1			T14	3		T22	92		T28	110
alert_integrity_fail	alert[0x21]	11042	1			T15	325		T22	1		T17	1
alert_integrity_fail	alert[0x22]	11380	1			T4	217		T6	10		T14	4
alert_integrity_fail	alert[0x23]	6839	1			T15	140		T27	37		T47	27
alert_integrity_fail	alert[0x24]	9716	1			T15	25		T27	1		T28	134
alert_integrity_fail	alert[0x25]	9973	1			T15	609		T68	377		T42	21
alert_integrity_fail	alert[0x26]	5051	1			T4	3		T5	31		T15	6
alert_integrity_fail	alert[0x27]	4991	1			T4	3		T15	369		T68	3
alert_integrity_fail	alert[0x28]	3481	1			T4	46		T27	1		T68	198
alert_integrity_fail	alert[0x29]	11168	1			T5	15		T14	3		T28	619
alert_integrity_fail	alert[0x2a]	16704	1			T5	62		T80	80		T68	666
alert_integrity_fail	alert[0x2b]	7923	1			T15	323		T68	14		T28	208
alert_integrity_fail	alert[0x2c]	11322	1			T4	66		T5	273		T15	1001
alert_integrity_fail	alert[0x2d]	3965	1			T6	5		T68	1251		T47	210
alert_integrity_fail	alert[0x2e]	8107	1			T4	5		T5	10		T14	1
alert_integrity_fail	alert[0x2f]	6321	1			T5	2802		T6	1		T22	1
alert_integrity_fail	alert[0x30]	3149	1			T5	553		T80	20		T68	65
alert_integrity_fail	alert[0x31]	9237	1			T5	4		T15	16		T22	2
alert_integrity_fail	alert[0x32]	3571	1			T5	64		T80	5		T47	26
alert_integrity_fail	alert[0x33]	5311	1			T4	33		T6	1		T15	131
alert_integrity_fail	alert[0x34]	14591	1			T4	1733		T5	1		T15	4229
alert_integrity_fail	alert[0x35]	2415	1			T5	3		T14	3		T15	106
alert_integrity_fail	alert[0x36]	5347	1			T80	290		T68	6		T28	50
alert_integrity_fail	alert[0x37]	9008	1			T14	3		T27	1		T80	470
alert_integrity_fail	alert[0x38]	9160	1			T6	2		T15	12		T80	44
alert_integrity_fail	alert[0x39]	5074	1			T4	602		T5	56		T80	212
alert_integrity_fail	alert[0x3a]	10501	1			T4	38		T47	173		T64	3
alert_integrity_fail	alert[0x3b]	5706	1			T15	339		T22	4		T68	20
alert_integrity_fail	alert[0x3c]	7075	1			T4	1012		T68	862		T28	37
alert_integrity_fail	alert[0x3d]	15859	1			T4	2		T15	82		T80	480
alert_integrity_fail	alert[0x3e]	17521	1			T4	18		T68	81		T28	10
alert_integrity_fail	alert[0x3f]	13645	1			T80	349		T64	1		T25	4006
alert_integrity_fail	alert[0x40]	10375	1			T4	2		T5	491		T15	47
alert_ping_fail	alert[0x0]	12	1			T9	1		T277	1		T278	1
alert_ping_fail	alert[0x1]	10	1			T8	1		T9	1		T275	1
alert_ping_fail	alert[0x2]	10	1			T275	1		T279	1		T280	1
alert_ping_fail	alert[0x3]	21	1			T8	1		T10	1		T275	1
alert_ping_fail	alert[0x4]	10	1			T281	1		T279	2		T282	1
alert_ping_fail	alert[0x5]	12	1			T283	1		T279	1		T256	1
alert_ping_fail	alert[0x6]	9	1			T221	2		T256	1		T280	1
alert_ping_fail	alert[0x7]	15	1			T275	1		T284	1		T285	1
alert_ping_fail	alert[0x8]	19	1			T7	1		T8	1		T286	1
alert_ping_fail	alert[0x9]	11	1			T287	1		T283	1		T277	1
alert_ping_fail	alert[0xa]	19	1			T98	2		T10	1		T254	1
alert_ping_fail	alert[0xb]	13	1			T8	1		T281	2		T256	1
alert_ping_fail	alert[0xc]	10	1			T9	1		T275	1		T288	1
alert_ping_fail	alert[0xd]	8	1			T8	1		T275	1		T286	1
alert_ping_fail	alert[0xe]	11	1			T275	1		T284	1		T288	1
alert_ping_fail	alert[0xf]	9	1			T275	1		T289	1		T290	1
alert_ping_fail	alert[0x10]	10	1			T8	2		T281	1		T291	1
alert_ping_fail	alert[0x11]	5	1			T283	1		T290	1		T292	1
alert_ping_fail	alert[0x12]	8	1			T279	1		T293	1		T294	1
alert_ping_fail	alert[0x13]	16	1			T8	1		T221	1		T285	1
alert_ping_fail	alert[0x14]	15	1			T286	2		T295	1		T281	1
alert_ping_fail	alert[0x15]	15	1			T275	1		T265	1		T283	1
alert_ping_fail	alert[0x16]	16	1			T8	1		T275	2		T254	1
alert_ping_fail	alert[0x17]	13	1			T275	1		T296	1		T288	1
alert_ping_fail	alert[0x18]	14	1			T275	1		T286	1		T289	1
alert_ping_fail	alert[0x19]	14	1			T8	1		T9	1		T286	1
alert_ping_fail	alert[0x1a]	15	1			T8	2		T9	1		T281	1
alert_ping_fail	alert[0x1b]	14	1			T8	1		T284	1		T279	2
alert_ping_fail	alert[0x1c]	7	1			T283	1		T297	1		T279	1
alert_ping_fail	alert[0x1d]	9	1			T8	2		T289	3		T298	1
alert_ping_fail	alert[0x1e]	10	1			T275	1		T289	1		T256	1
alert_ping_fail	alert[0x1f]	10	1			T98	1		T275	1		T299	1
alert_ping_fail	alert[0x20]	8	1			T275	1		T94	1		T300	1
alert_ping_fail	alert[0x21]	9	1			T9	1		T283	1		T290	1
alert_ping_fail	alert[0x22]	14	1			T98	3		T63	1		T275	1
alert_ping_fail	alert[0x23]	12	1			T284	1		T289	1		T291	2
alert_ping_fail	alert[0x24]	10	1			T8	1		T281	1		T291	2
alert_ping_fail	alert[0x25]	15	1			T8	1		T9	1		T283	1
alert_ping_fail	alert[0x26]	7	1			T9	1		T279	1		T301	1
alert_ping_fail	alert[0x27]	11	1			T281	1		T292	1		T293	1
alert_ping_fail	alert[0x28]	10	1			T221	1		T278	1		T288	1
alert_ping_fail	alert[0x29]	15	1			T9	1		T275	1		T283	1
alert_ping_fail	alert[0x2a]	17	1			T8	1		T98	2		T281	1
alert_ping_fail	alert[0x2b]	9	1			T297	1		T302	1		T303	1
alert_ping_fail	alert[0x2c]	15	1			T36	1		T283	1		T304	2
alert_ping_fail	alert[0x2d]	15	1			T305	1		T292	1		T288	1
alert_ping_fail	alert[0x2e]	11	1			T10	1		T277	1		T281	1
alert_ping_fail	alert[0x2f]	12	1			T300	1		T282	1		T292	1
alert_ping_fail	alert[0x30]	10	1			T284	1		T282	1		T256	1
alert_ping_fail	alert[0x31]	8	1			T283	2		T306	1		T307	1
alert_ping_fail	alert[0x32]	9	1			T10	1		T291	1		T282	2
alert_ping_fail	alert[0x33]	10	1			T9	1		T275	1		T281	1
alert_ping_fail	alert[0x34]	6	1			T8	1		T278	1		T288	1
alert_ping_fail	alert[0x35]	10	1			T281	1		T289	1		T291	1
alert_ping_fail	alert[0x36]	9	1			T275	1		T292	1		T308	1
alert_ping_fail	alert[0x37]	14	1			T284	1		T291	2		T256	1
alert_ping_fail	alert[0x38]	8	1			T283	1		T256	1		T292	1
alert_ping_fail	alert[0x39]	7	1			T290	1		T292	2		T309	1
alert_ping_fail	alert[0x3a]	17	1			T10	1		T275	1		T287	1
alert_ping_fail	alert[0x3b]	5	1			T284	1		T291	1		T279	1
alert_ping_fail	alert[0x3c]	8	1			T286	1		T281	1		T291	1
alert_ping_fail	alert[0x3d]	11	1			T8	1		T287	1		T283	1
alert_ping_fail	alert[0x3e]	11	1			T8	1		T283	2		T284	1
alert_ping_fail	alert[0x3f]	5	1			T310	1		T308	1		T301	1
alert_ping_fail	alert[0x40]	10	1			T281	4		T279	1		T311	2

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	165989	1			T4	14		T6	12		T80	3
alert_integrity_fail	class_i[0x1]	127427	1			T4	21		T5	6384		T14	16
alert_integrity_fail	class_i[0x2]	75683	1			T4	7		T6	8		T22	6
alert_integrity_fail	class_i[0x3]	115800	1			T4	8237		T14	29		T15	14213
alert_ping_fail	class_i[0x0]	178	1			T7	1		T8	2		T98	8
alert_ping_fail	class_i[0x1]	163	1			T8	18		T9	7		T10	1
alert_ping_fail	class_i[0x2]	143	1			T8	1		T9	2		T275	20
alert_ping_fail	class_i[0x3]	254	1			T9	1		T10	4		T286	2