Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.72 99.97 100.00 100.00 99.38 99.48


Total test records in report: 834
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T775 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3335961940 Jul 01 11:01:27 AM PDT 24 Jul 01 11:01:32 AM PDT 24 59418765 ps
T776 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.726666012 Jul 01 11:01:51 AM PDT 24 Jul 01 11:01:53 AM PDT 24 11466646 ps
T119 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3542513746 Jul 01 11:01:31 AM PDT 24 Jul 01 11:03:09 AM PDT 24 1656164641 ps
T139 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3776930567 Jul 01 11:01:49 AM PDT 24 Jul 01 11:06:27 AM PDT 24 2314329377 ps
T777 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3092141762 Jul 01 11:01:25 AM PDT 24 Jul 01 11:01:31 AM PDT 24 63012788 ps
T140 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1302268421 Jul 01 11:01:28 AM PDT 24 Jul 01 11:03:45 AM PDT 24 3337558550 ps
T778 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4156606973 Jul 01 11:01:50 AM PDT 24 Jul 01 11:01:55 AM PDT 24 228968588 ps
T779 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2683477735 Jul 01 11:01:13 AM PDT 24 Jul 01 11:01:57 AM PDT 24 4113191627 ps
T130 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.524356802 Jul 01 11:01:49 AM PDT 24 Jul 01 11:13:05 AM PDT 24 15782205696 ps
T780 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.531817687 Jul 01 11:01:14 AM PDT 24 Jul 01 11:01:17 AM PDT 24 8462341 ps
T781 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3439163124 Jul 01 11:01:34 AM PDT 24 Jul 01 11:01:36 AM PDT 24 11393346 ps
T782 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.757378525 Jul 01 11:01:15 AM PDT 24 Jul 01 11:01:28 AM PDT 24 339567356 ps
T783 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3531365778 Jul 01 11:01:44 AM PDT 24 Jul 01 11:01:46 AM PDT 24 13948365 ps
T784 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1549452954 Jul 01 11:01:28 AM PDT 24 Jul 01 11:01:59 AM PDT 24 602576568 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3886532715 Jul 01 11:01:38 AM PDT 24 Jul 01 11:04:18 AM PDT 24 4582157243 ps
T786 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.815709154 Jul 01 11:01:55 AM PDT 24 Jul 01 11:01:58 AM PDT 24 12380178 ps
T135 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2747691827 Jul 01 11:01:38 AM PDT 24 Jul 01 11:20:09 AM PDT 24 16877751362 ps
T787 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2011618307 Jul 01 11:01:39 AM PDT 24 Jul 01 11:01:41 AM PDT 24 8827410 ps
T788 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.660278921 Jul 01 11:01:23 AM PDT 24 Jul 01 11:01:33 AM PDT 24 461259717 ps
T789 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.795620828 Jul 01 11:01:34 AM PDT 24 Jul 01 11:01:43 AM PDT 24 622335530 ps
T790 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3314219786 Jul 01 11:01:26 AM PDT 24 Jul 01 11:01:32 AM PDT 24 234607511 ps
T791 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.362978366 Jul 01 11:01:28 AM PDT 24 Jul 01 11:01:33 AM PDT 24 243905243 ps
T792 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3831370606 Jul 01 11:01:15 AM PDT 24 Jul 01 11:01:30 AM PDT 24 208839948 ps
T793 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4109647199 Jul 01 11:01:42 AM PDT 24 Jul 01 11:01:49 AM PDT 24 233296620 ps
T794 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3341151571 Jul 01 11:01:15 AM PDT 24 Jul 01 11:03:00 AM PDT 24 1641038600 ps
T795 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3686387093 Jul 01 11:01:35 AM PDT 24 Jul 01 11:01:37 AM PDT 24 10456298 ps
T132 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1027502625 Jul 01 11:01:11 AM PDT 24 Jul 01 11:06:10 AM PDT 24 4484048337 ps
T136 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2862798982 Jul 01 11:01:53 AM PDT 24 Jul 01 11:10:05 AM PDT 24 99142494792 ps
T796 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2168338482 Jul 01 11:01:26 AM PDT 24 Jul 01 11:03:21 AM PDT 24 7662935966 ps
T797 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1147789432 Jul 01 11:01:48 AM PDT 24 Jul 01 11:02:02 AM PDT 24 183679957 ps
T798 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1566581883 Jul 01 11:01:20 AM PDT 24 Jul 01 11:01:29 AM PDT 24 94285736 ps
T146 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2695861507 Jul 01 11:01:22 AM PDT 24 Jul 01 11:06:13 AM PDT 24 2190316380 ps
T799 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1921878627 Jul 01 11:01:08 AM PDT 24 Jul 01 11:01:14 AM PDT 24 10867559 ps
T143 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1214493456 Jul 01 11:01:47 AM PDT 24 Jul 01 11:17:07 AM PDT 24 13960711753 ps
T800 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1137222297 Jul 01 11:01:25 AM PDT 24 Jul 01 11:01:49 AM PDT 24 338465596 ps
T801 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3985378640 Jul 01 11:01:54 AM PDT 24 Jul 01 11:01:58 AM PDT 24 19631187 ps
T802 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3206338915 Jul 01 11:01:30 AM PDT 24 Jul 01 11:01:33 AM PDT 24 13721992 ps
T803 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2608289916 Jul 01 11:01:25 AM PDT 24 Jul 01 11:01:32 AM PDT 24 40712814 ps
T145 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1587126280 Jul 01 11:01:53 AM PDT 24 Jul 01 11:09:57 AM PDT 24 26193017736 ps
T804 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1386866320 Jul 01 11:01:25 AM PDT 24 Jul 01 11:03:11 AM PDT 24 1079354897 ps
T166 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3625886778 Jul 01 11:01:17 AM PDT 24 Jul 01 11:02:28 AM PDT 24 1160696896 ps
T137 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2153661501 Jul 01 11:01:26 AM PDT 24 Jul 01 11:10:59 AM PDT 24 7410315166 ps
T155 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2521595385 Jul 01 11:01:37 AM PDT 24 Jul 01 11:02:24 AM PDT 24 597476362 ps
T805 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3384588976 Jul 01 11:01:30 AM PDT 24 Jul 01 11:01:36 AM PDT 24 112858907 ps
T806 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.81423304 Jul 01 11:01:12 AM PDT 24 Jul 01 11:04:16 AM PDT 24 11406042802 ps
T807 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1037997649 Jul 01 11:01:54 AM PDT 24 Jul 01 11:01:57 AM PDT 24 10720004 ps
T808 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2384585089 Jul 01 11:01:50 AM PDT 24 Jul 01 11:02:09 AM PDT 24 281049408 ps
T809 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.543751636 Jul 01 11:01:52 AM PDT 24 Jul 01 11:01:57 AM PDT 24 28973182 ps
T810 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2530411829 Jul 01 11:01:10 AM PDT 24 Jul 01 11:03:25 AM PDT 24 6644057256 ps
T134 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3124105487 Jul 01 11:01:52 AM PDT 24 Jul 01 11:17:22 AM PDT 24 49177881000 ps
T138 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.710677183 Jul 01 11:01:39 AM PDT 24 Jul 01 11:05:27 AM PDT 24 3411416003 ps
T811 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3343354210 Jul 01 11:01:07 AM PDT 24 Jul 01 11:01:22 AM PDT 24 290122650 ps
T812 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3125098511 Jul 01 11:01:11 AM PDT 24 Jul 01 11:02:46 AM PDT 24 3027722024 ps
T147 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.605683817 Jul 01 11:01:52 AM PDT 24 Jul 01 11:03:17 AM PDT 24 3114702385 ps
T813 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1151398808 Jul 01 11:01:26 AM PDT 24 Jul 01 11:01:28 AM PDT 24 9954773 ps
T814 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3950756911 Jul 01 11:01:31 AM PDT 24 Jul 01 11:01:38 AM PDT 24 75666936 ps
T815 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2960304350 Jul 01 11:01:34 AM PDT 24 Jul 01 11:01:39 AM PDT 24 173922775 ps
T816 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.65593105 Jul 01 11:02:00 AM PDT 24 Jul 01 11:02:01 AM PDT 24 9748150 ps
T817 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.609160129 Jul 01 11:01:51 AM PDT 24 Jul 01 11:01:58 AM PDT 24 189349363 ps
T818 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3651019999 Jul 01 11:01:28 AM PDT 24 Jul 01 11:01:51 AM PDT 24 664115367 ps
T819 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2378201826 Jul 01 11:01:19 AM PDT 24 Jul 01 11:01:23 AM PDT 24 219545752 ps
T820 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1744541151 Jul 01 11:01:45 AM PDT 24 Jul 01 11:01:57 AM PDT 24 210748498 ps
T821 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1350851124 Jul 01 11:01:57 AM PDT 24 Jul 01 11:01:59 AM PDT 24 18533541 ps
T822 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3316393 Jul 01 11:01:29 AM PDT 24 Jul 01 11:02:10 AM PDT 24 505709116 ps
T141 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.845508133 Jul 01 11:01:46 AM PDT 24 Jul 01 11:04:22 AM PDT 24 2675092412 ps
T144 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.512728064 Jul 01 11:01:48 AM PDT 24 Jul 01 11:04:56 AM PDT 24 10855922568 ps
T823 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3864997390 Jul 01 11:01:54 AM PDT 24 Jul 01 11:02:32 AM PDT 24 1885768544 ps
T336 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1884982275 Jul 01 11:01:15 AM PDT 24 Jul 01 11:06:41 AM PDT 24 8773411564 ps
T824 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.473009532 Jul 01 11:01:40 AM PDT 24 Jul 01 11:02:03 AM PDT 24 1042461541 ps
T825 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1486739021 Jul 01 11:01:42 AM PDT 24 Jul 01 11:01:44 AM PDT 24 39661864 ps
T826 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3698931121 Jul 01 11:01:14 AM PDT 24 Jul 01 11:01:19 AM PDT 24 21812643 ps
T165 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1948186468 Jul 01 11:01:22 AM PDT 24 Jul 01 11:01:25 AM PDT 24 31100456 ps
T827 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1942828236 Jul 01 11:01:39 AM PDT 24 Jul 01 11:01:53 AM PDT 24 1443483339 ps
T828 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.58227908 Jul 01 11:01:53 AM PDT 24 Jul 01 11:01:57 AM PDT 24 6783925 ps
T829 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2503538957 Jul 01 11:01:21 AM PDT 24 Jul 01 11:01:28 AM PDT 24 330269170 ps
T142 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1445334238 Jul 01 11:01:28 AM PDT 24 Jul 01 11:04:12 AM PDT 24 2066136327 ps
T830 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3669074296 Jul 01 11:01:26 AM PDT 24 Jul 01 11:01:28 AM PDT 24 8734894 ps
T831 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2073256261 Jul 01 11:01:38 AM PDT 24 Jul 01 11:01:44 AM PDT 24 287414532 ps
T157 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.271054911 Jul 01 11:01:34 AM PDT 24 Jul 01 11:01:37 AM PDT 24 28613710 ps
T832 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2505703347 Jul 01 11:01:53 AM PDT 24 Jul 01 11:02:16 AM PDT 24 3280941823 ps
T169 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1229718570 Jul 01 11:01:37 AM PDT 24 Jul 01 11:01:43 AM PDT 24 80473725 ps
T833 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.117480724 Jul 01 11:01:51 AM PDT 24 Jul 01 11:02:04 AM PDT 24 175508906 ps
T158 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1265476575 Jul 01 11:01:26 AM PDT 24 Jul 01 11:01:30 AM PDT 24 170717475 ps
T834 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2045432312 Jul 01 11:01:12 AM PDT 24 Jul 01 11:01:18 AM PDT 24 179831198 ps

Test location /workspace/coverage/default/1.alert_handler_stress_all.3402281937
Short name T4
Test name
Test status
Simulation time 59311219172 ps
CPU time 3466.08 seconds
Started Jul 01 11:24:06 AM PDT 24
Finished Jul 01 12:21:56 PM PDT 24
Peak memory 305324 kb
Host smart-70bf7598-8924-414f-bf88-af942afcc12b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402281937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3402281937
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2181881675
Short name T28
Test name
Test status
Simulation time 61959115801 ps
CPU time 5741.7 seconds
Started Jul 01 11:24:46 AM PDT 24
Finished Jul 01 01:00:29 PM PDT 24
Peak memory 331436 kb
Host smart-303b6c0b-5a4c-4eca-b4b3-68099e506839
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181881675 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2181881675
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1729896360
Short name T11
Test name
Test status
Simulation time 437635138 ps
CPU time 23.32 seconds
Started Jul 01 11:24:08 AM PDT 24
Finished Jul 01 11:24:36 AM PDT 24
Peak memory 267456 kb
Host smart-db32a407-ede4-4c11-b668-cb2c42095d82
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1729896360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1729896360
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.918986632
Short name T148
Test name
Test status
Simulation time 4979486162 ps
CPU time 88.89 seconds
Started Jul 01 11:01:32 AM PDT 24
Finished Jul 01 11:03:02 AM PDT 24
Peak memory 240616 kb
Host smart-d5c773f1-ab12-400b-8b3f-0ff18584d217
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=918986632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.918986632
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2239694022
Short name T25
Test name
Test status
Simulation time 238623503802 ps
CPU time 4712.97 seconds
Started Jul 01 11:25:22 AM PDT 24
Finished Jul 01 12:43:59 PM PDT 24
Peak memory 321428 kb
Host smart-3e6dd4a6-6082-4568-b733-b6957c09ac77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239694022 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2239694022
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2758923472
Short name T88
Test name
Test status
Simulation time 15580491028 ps
CPU time 1731.73 seconds
Started Jul 01 11:25:44 AM PDT 24
Finished Jul 01 11:54:38 AM PDT 24
Peak memory 306144 kb
Host smart-9ec94b7d-4080-4307-8b2c-bf126d219123
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758923472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2758923472
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3663429835
Short name T15
Test name
Test status
Simulation time 351943140102 ps
CPU time 3101.6 seconds
Started Jul 01 11:24:45 AM PDT 24
Finished Jul 01 12:16:28 PM PDT 24
Peak memory 289796 kb
Host smart-0834f0b4-76d6-433d-ae33-a4122c0d81fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663429835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3663429835
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2124643062
Short name T115
Test name
Test status
Simulation time 25237353255 ps
CPU time 988.85 seconds
Started Jul 01 11:01:16 AM PDT 24
Finished Jul 01 11:17:47 AM PDT 24
Peak memory 265420 kb
Host smart-ff7cab45-add5-494e-915b-7674086e5ee4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124643062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2124643062
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3497739861
Short name T98
Test name
Test status
Simulation time 91734467347 ps
CPU time 2615.68 seconds
Started Jul 01 11:24:25 AM PDT 24
Finished Jul 01 12:08:03 PM PDT 24
Peak memory 285252 kb
Host smart-981ec9c7-fe0a-470b-8e02-dcc4fa79a0fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497739861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3497739861
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.592851672
Short name T91
Test name
Test status
Simulation time 237923842828 ps
CPU time 1217.44 seconds
Started Jul 01 11:25:53 AM PDT 24
Finished Jul 01 11:46:12 AM PDT 24
Peak memory 289592 kb
Host smart-b8e4e716-a003-4695-b3e9-ef1806e0ab79
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592851672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.592851672
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.589204837
Short name T92
Test name
Test status
Simulation time 26643073776 ps
CPU time 1506.97 seconds
Started Jul 01 11:24:37 AM PDT 24
Finished Jul 01 11:49:45 AM PDT 24
Peak memory 273656 kb
Host smart-8ae01768-4a5c-4028-aec2-cfcd82dfcb2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589204837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.589204837
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1974602760
Short name T114
Test name
Test status
Simulation time 17587139389 ps
CPU time 624.17 seconds
Started Jul 01 11:01:17 AM PDT 24
Finished Jul 01 11:11:43 AM PDT 24
Peak memory 265436 kb
Host smart-14100cc5-4a2f-4f75-bf12-14c2e6ac08f7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974602760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1974602760
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1027502625
Short name T132
Test name
Test status
Simulation time 4484048337 ps
CPU time 295.98 seconds
Started Jul 01 11:01:11 AM PDT 24
Finished Jul 01 11:06:10 AM PDT 24
Peak memory 265528 kb
Host smart-5eb555cf-83b3-46e7-acfe-5bad6429140d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1027502625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1027502625
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.50674522
Short name T213
Test name
Test status
Simulation time 9559549934 ps
CPU time 410.71 seconds
Started Jul 01 11:26:06 AM PDT 24
Finished Jul 01 11:32:58 AM PDT 24
Peak memory 249400 kb
Host smart-83229332-5501-4492-9e2e-448494b15072
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50674522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.50674522
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.654574880
Short name T122
Test name
Test status
Simulation time 23832501319 ps
CPU time 912.36 seconds
Started Jul 01 11:01:25 AM PDT 24
Finished Jul 01 11:16:38 AM PDT 24
Peak memory 265420 kb
Host smart-5abbc7a3-8e54-45e1-b655-70893b893147
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654574880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.654574880
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2079522467
Short name T320
Test name
Test status
Simulation time 72662061255 ps
CPU time 1382.34 seconds
Started Jul 01 11:24:50 AM PDT 24
Finished Jul 01 11:47:54 AM PDT 24
Peak memory 274088 kb
Host smart-0f813137-c49a-43bd-9648-3950bc5606d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079522467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2079522467
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.501902806
Short name T329
Test name
Test status
Simulation time 10212868 ps
CPU time 1.7 seconds
Started Jul 01 11:01:43 AM PDT 24
Finished Jul 01 11:01:46 AM PDT 24
Peak memory 236684 kb
Host smart-c13b5d57-5c60-4ce1-b9b4-874710b7fd82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=501902806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.501902806
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3706033331
Short name T8
Test name
Test status
Simulation time 56418163145 ps
CPU time 592.83 seconds
Started Jul 01 11:24:58 AM PDT 24
Finished Jul 01 11:34:55 AM PDT 24
Peak memory 249136 kb
Host smart-8c66160b-e8ca-462f-a33c-a354408533ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706033331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3706033331
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.710677183
Short name T138
Test name
Test status
Simulation time 3411416003 ps
CPU time 226.58 seconds
Started Jul 01 11:01:39 AM PDT 24
Finished Jul 01 11:05:27 AM PDT 24
Peak memory 265436 kb
Host smart-e8e7b1ba-f277-4f7a-962e-cec3c3e06660
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=710677183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.710677183
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2495413823
Short name T285
Test name
Test status
Simulation time 40413160106 ps
CPU time 2524.84 seconds
Started Jul 01 11:25:57 AM PDT 24
Finished Jul 01 12:08:03 PM PDT 24
Peak memory 290276 kb
Host smart-10984f37-8162-4326-800f-e5916cde5903
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495413823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2495413823
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3081072333
Short name T62
Test name
Test status
Simulation time 151301963 ps
CPU time 9.26 seconds
Started Jul 01 11:24:06 AM PDT 24
Finished Jul 01 11:24:18 AM PDT 24
Peak memory 249292 kb
Host smart-e46720aa-f0df-4d1f-a114-d36ede8a8fa8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3081072333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3081072333
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3377157683
Short name T110
Test name
Test status
Simulation time 26115552071 ps
CPU time 511.17 seconds
Started Jul 01 11:01:34 AM PDT 24
Finished Jul 01 11:10:06 AM PDT 24
Peak memory 265424 kb
Host smart-64833ae2-d159-41e0-bc14-b5b0acd8c398
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377157683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3377157683
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.524356802
Short name T130
Test name
Test status
Simulation time 15782205696 ps
CPU time 674.91 seconds
Started Jul 01 11:01:49 AM PDT 24
Finished Jul 01 11:13:05 AM PDT 24
Peak memory 272704 kb
Host smart-3b69ca06-e3e8-45c2-b4e2-69e5d9b6dd61
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524356802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.524356802
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.4109416034
Short name T81
Test name
Test status
Simulation time 490701400007 ps
CPU time 2045 seconds
Started Jul 01 11:24:08 AM PDT 24
Finished Jul 01 11:58:18 AM PDT 24
Peak memory 290356 kb
Host smart-e93fc089-f680-40b5-b719-8dea2e4025c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109416034 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.4109416034
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2895197951
Short name T292
Test name
Test status
Simulation time 14419489376 ps
CPU time 589.22 seconds
Started Jul 01 11:24:07 AM PDT 24
Finished Jul 01 11:34:00 AM PDT 24
Peak memory 255700 kb
Host smart-06d8436e-b05b-43b9-9106-4a55ac1cb6e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895197951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2895197951
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2539646547
Short name T36
Test name
Test status
Simulation time 63176084592 ps
CPU time 1686.13 seconds
Started Jul 01 11:26:24 AM PDT 24
Finished Jul 01 11:54:32 AM PDT 24
Peak memory 273872 kb
Host smart-58458e10-901d-493e-8bbb-5c9cbc30a842
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539646547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2539646547
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1653268789
Short name T112
Test name
Test status
Simulation time 13669955940 ps
CPU time 303.57 seconds
Started Jul 01 11:01:21 AM PDT 24
Finished Jul 01 11:06:25 AM PDT 24
Peak memory 265456 kb
Host smart-40537a9b-4c25-4e89-a5ec-b70ee9806769
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1653268789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1653268789
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.222515617
Short name T275
Test name
Test status
Simulation time 15334770038 ps
CPU time 640.17 seconds
Started Jul 01 11:24:41 AM PDT 24
Finished Jul 01 11:35:23 AM PDT 24
Peak memory 249412 kb
Host smart-b0a71fc2-822f-4be5-89e3-1311004abd10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222515617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.222515617
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1724301716
Short name T297
Test name
Test status
Simulation time 47354965037 ps
CPU time 2659.41 seconds
Started Jul 01 11:25:02 AM PDT 24
Finished Jul 01 12:09:27 PM PDT 24
Peak memory 289808 kb
Host smart-bde1e787-fe6c-406e-a50d-917598f64aaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724301716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1724301716
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2538004531
Short name T23
Test name
Test status
Simulation time 21400892110 ps
CPU time 1952.4 seconds
Started Jul 01 11:25:35 AM PDT 24
Finished Jul 01 11:58:10 AM PDT 24
Peak memory 302676 kb
Host smart-7e14de9e-4d86-4633-bd04-92d51eefd265
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538004531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2538004531
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1423791072
Short name T26
Test name
Test status
Simulation time 1104036178650 ps
CPU time 4272.05 seconds
Started Jul 01 11:25:45 AM PDT 24
Finished Jul 01 12:36:59 PM PDT 24
Peak memory 323016 kb
Host smart-e5228309-b0e6-45b9-814e-6e425f891419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423791072 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1423791072
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2696612542
Short name T120
Test name
Test status
Simulation time 13665262416 ps
CPU time 280.15 seconds
Started Jul 01 11:01:35 AM PDT 24
Finished Jul 01 11:06:16 AM PDT 24
Peak memory 273176 kb
Host smart-a2df36fa-1eb8-4751-9c07-629bb8bcb8b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2696612542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2696612542
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1800056481
Short name T85
Test name
Test status
Simulation time 167587249999 ps
CPU time 5033.27 seconds
Started Jul 01 11:24:35 AM PDT 24
Finished Jul 01 12:48:31 PM PDT 24
Peak memory 305256 kb
Host smart-af7f9670-f1e8-4365-8c63-40a92e773e3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800056481 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1800056481
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.524596929
Short name T279
Test name
Test status
Simulation time 27545294412 ps
CPU time 549.64 seconds
Started Jul 01 11:24:19 AM PDT 24
Finished Jul 01 11:33:32 AM PDT 24
Peak memory 256340 kb
Host smart-2032a5eb-08be-4b57-870b-cdd12ccafb03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524596929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.524596929
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.702742028
Short name T222
Test name
Test status
Simulation time 8410148 ps
CPU time 1.44 seconds
Started Jul 01 11:01:21 AM PDT 24
Finished Jul 01 11:01:23 AM PDT 24
Peak memory 236644 kb
Host smart-40d1d561-9390-42fe-b9cc-6bb6b991d588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=702742028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.702742028
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1668965739
Short name T260
Test name
Test status
Simulation time 89998078012 ps
CPU time 1507.79 seconds
Started Jul 01 11:25:12 AM PDT 24
Finished Jul 01 11:50:23 AM PDT 24
Peak memory 290332 kb
Host smart-14dd10df-6e77-43c3-a149-6f8812300968
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668965739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1668965739
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.4265759682
Short name T313
Test name
Test status
Simulation time 162621077970 ps
CPU time 1771.72 seconds
Started Jul 01 11:25:42 AM PDT 24
Finished Jul 01 11:55:15 AM PDT 24
Peak memory 273744 kb
Host smart-0499e87d-b0ff-41b4-acd7-542d142282e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265759682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4265759682
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.478264129
Short name T639
Test name
Test status
Simulation time 56591089984 ps
CPU time 594.62 seconds
Started Jul 01 11:24:31 AM PDT 24
Finished Jul 01 11:34:27 AM PDT 24
Peak memory 249392 kb
Host smart-3931f33f-10b4-4f49-adbb-1d6acd51b043
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478264129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.478264129
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3586468391
Short name T22
Test name
Test status
Simulation time 2695950956 ps
CPU time 60.86 seconds
Started Jul 01 11:24:43 AM PDT 24
Finished Jul 01 11:25:46 AM PDT 24
Peak memory 250648 kb
Host smart-44e5eb36-3174-4c45-8bbf-171dbdbc8838
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586468391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3586468391
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3069809505
Short name T127
Test name
Test status
Simulation time 6147657141 ps
CPU time 478.25 seconds
Started Jul 01 11:01:49 AM PDT 24
Finished Jul 01 11:09:48 AM PDT 24
Peak memory 269476 kb
Host smart-f465ad1e-b910-468c-a08c-29c0a95ac4b5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069809505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3069809505
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3364069533
Short name T57
Test name
Test status
Simulation time 1536170912 ps
CPU time 140.43 seconds
Started Jul 01 11:24:36 AM PDT 24
Finished Jul 01 11:26:58 AM PDT 24
Peak memory 253440 kb
Host smart-f3080f9d-4db9-47ff-9257-c53d4e03cd4a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364069533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3364069533
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2685158414
Short name T230
Test name
Test status
Simulation time 2886798153 ps
CPU time 39.44 seconds
Started Jul 01 11:24:33 AM PDT 24
Finished Jul 01 11:25:14 AM PDT 24
Peak memory 249136 kb
Host smart-de9379bd-9c99-4c6c-b613-49e3f789d37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26851
58414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2685158414
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2448772045
Short name T240
Test name
Test status
Simulation time 360994426347 ps
CPU time 6297.9 seconds
Started Jul 01 11:24:55 AM PDT 24
Finished Jul 01 01:09:57 PM PDT 24
Peak memory 306848 kb
Host smart-b91a1339-c038-4a83-8478-acb7289046c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448772045 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2448772045
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1581889110
Short name T688
Test name
Test status
Simulation time 61543593682 ps
CPU time 1844.84 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:55:54 AM PDT 24
Peak memory 282188 kb
Host smart-c01f561f-e036-4e93-be2e-9b38fe4f5dfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581889110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1581889110
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2857089099
Short name T299
Test name
Test status
Simulation time 96754596095 ps
CPU time 2241.82 seconds
Started Jul 01 11:25:00 AM PDT 24
Finished Jul 01 12:02:28 PM PDT 24
Peak memory 290260 kb
Host smart-95cf23a6-1d5a-4da2-87cc-aed32cab91aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857089099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2857089099
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2776312877
Short name T58
Test name
Test status
Simulation time 147677580472 ps
CPU time 4918.52 seconds
Started Jul 01 11:25:10 AM PDT 24
Finished Jul 01 12:47:12 PM PDT 24
Peak memory 300960 kb
Host smart-d425b32b-97e4-42ce-852f-2b90cab337cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776312877 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2776312877
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.927084468
Short name T309
Test name
Test status
Simulation time 12292269234 ps
CPU time 537.11 seconds
Started Jul 01 11:25:10 AM PDT 24
Finished Jul 01 11:34:10 AM PDT 24
Peak memory 249576 kb
Host smart-0225c762-b901-4114-a2dc-80c3ed1cec4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927084468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.927084468
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.858924831
Short name T156
Test name
Test status
Simulation time 23299686 ps
CPU time 2.52 seconds
Started Jul 01 11:01:16 AM PDT 24
Finished Jul 01 11:01:20 AM PDT 24
Peak memory 237720 kb
Host smart-46c9a134-2eb0-4c1a-a632-8b429cb2e750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=858924831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.858924831
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3069672163
Short name T149
Test name
Test status
Simulation time 157975667 ps
CPU time 20.52 seconds
Started Jul 01 11:01:30 AM PDT 24
Finished Jul 01 11:01:51 AM PDT 24
Peak memory 240512 kb
Host smart-0bb85769-3d25-4705-a77d-b05a34dc0780
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3069672163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3069672163
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.515203956
Short name T24
Test name
Test status
Simulation time 589141964 ps
CPU time 33.86 seconds
Started Jul 01 11:24:40 AM PDT 24
Finished Jul 01 11:25:16 AM PDT 24
Peak memory 249308 kb
Host smart-5499f5a6-1790-434f-94ac-90c849ea68ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51520
3956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.515203956
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.341786006
Short name T206
Test name
Test status
Simulation time 38993243 ps
CPU time 3.69 seconds
Started Jul 01 11:24:03 AM PDT 24
Finished Jul 01 11:24:10 AM PDT 24
Peak memory 249588 kb
Host smart-e8a8696a-5906-4d6a-a858-a36d4e757899
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=341786006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.341786006
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.278939608
Short name T208
Test name
Test status
Simulation time 21390534 ps
CPU time 2.27 seconds
Started Jul 01 11:24:32 AM PDT 24
Finished Jul 01 11:24:37 AM PDT 24
Peak memory 249596 kb
Host smart-d10e4bc6-5969-4478-80e2-6ac7b7dd909e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=278939608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.278939608
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3458842934
Short name T197
Test name
Test status
Simulation time 47883375 ps
CPU time 2.49 seconds
Started Jul 01 11:24:23 AM PDT 24
Finished Jul 01 11:24:28 AM PDT 24
Peak memory 249536 kb
Host smart-69336f4f-1361-46a4-87bd-8533834cb444
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3458842934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3458842934
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.4485201
Short name T207
Test name
Test status
Simulation time 91097642 ps
CPU time 3.87 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:24:22 AM PDT 24
Peak memory 249520 kb
Host smart-0522d033-dc5f-4ffd-8c27-9f7f1437acd7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4485201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.4485201
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1130447274
Short name T225
Test name
Test status
Simulation time 43169648763 ps
CPU time 1151.02 seconds
Started Jul 01 11:24:05 AM PDT 24
Finished Jul 01 11:43:19 AM PDT 24
Peak memory 271792 kb
Host smart-09b2f7ce-5501-4e9d-aaa8-6b0479b45b98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130447274 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1130447274
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1855250975
Short name T231
Test name
Test status
Simulation time 7900233455 ps
CPU time 46.07 seconds
Started Jul 01 11:24:37 AM PDT 24
Finished Jul 01 11:25:25 AM PDT 24
Peak memory 248680 kb
Host smart-845d53d9-d59e-4d79-9425-4f1df402fa72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18552
50975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1855250975
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3818896820
Short name T80
Test name
Test status
Simulation time 141719717467 ps
CPU time 2190.1 seconds
Started Jul 01 11:25:19 AM PDT 24
Finished Jul 01 12:01:53 PM PDT 24
Peak memory 282168 kb
Host smart-b4f744a0-f012-4e14-81f8-f2a41a3cdfb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818896820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3818896820
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1345443589
Short name T124
Test name
Test status
Simulation time 2059818183 ps
CPU time 144.22 seconds
Started Jul 01 11:01:06 AM PDT 24
Finished Jul 01 11:03:35 AM PDT 24
Peak memory 265356 kb
Host smart-9598cb2d-0839-435c-a1df-d1d8c7b14232
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1345443589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1345443589
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1733811573
Short name T111
Test name
Test status
Simulation time 4757299934 ps
CPU time 113.42 seconds
Started Jul 01 11:01:30 AM PDT 24
Finished Jul 01 11:03:24 AM PDT 24
Peak memory 265460 kb
Host smart-a177ee48-215c-4cab-abaa-9919892065c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1733811573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1733811573
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2695861507
Short name T146
Test name
Test status
Simulation time 2190316380 ps
CPU time 290.96 seconds
Started Jul 01 11:01:22 AM PDT 24
Finished Jul 01 11:06:13 AM PDT 24
Peak memory 270188 kb
Host smart-f3e387b2-cde0-45bf-bf7a-d38d5651c278
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695861507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2695861507
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2728507966
Short name T121
Test name
Test status
Simulation time 4947111436 ps
CPU time 87.71 seconds
Started Jul 01 11:01:42 AM PDT 24
Finished Jul 01 11:03:11 AM PDT 24
Peak memory 265424 kb
Host smart-ed75bb04-5208-421f-a436-a21465289677
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2728507966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2728507966
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1608232647
Short name T250
Test name
Test status
Simulation time 10525716505 ps
CPU time 195.27 seconds
Started Jul 01 11:24:08 AM PDT 24
Finished Jul 01 11:27:28 AM PDT 24
Peak memory 251496 kb
Host smart-21e71054-c2eb-4635-b41b-d7e15ae61edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16082
32647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1608232647
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3400963761
Short name T191
Test name
Test status
Simulation time 345482499675 ps
CPU time 10049.3 seconds
Started Jul 01 11:24:33 AM PDT 24
Finished Jul 01 02:12:06 PM PDT 24
Peak memory 388132 kb
Host smart-85f00789-e5df-4902-a13d-f991515050b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400963761 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3400963761
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3449049322
Short name T477
Test name
Test status
Simulation time 36335926174 ps
CPU time 2324.31 seconds
Started Jul 01 11:24:26 AM PDT 24
Finished Jul 01 12:03:12 PM PDT 24
Peak memory 290216 kb
Host smart-b4b7dc9b-d86d-48ba-b487-ac00932a60f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449049322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3449049322
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.793927566
Short name T287
Test name
Test status
Simulation time 3381212147 ps
CPU time 136.75 seconds
Started Jul 01 11:24:48 AM PDT 24
Finished Jul 01 11:27:07 AM PDT 24
Peak memory 249432 kb
Host smart-9b22d595-042a-4a43-8db3-1c2a7ccd0756
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793927566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.793927566
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.539412919
Short name T251
Test name
Test status
Simulation time 49304319064 ps
CPU time 976.31 seconds
Started Jul 01 11:25:00 AM PDT 24
Finished Jul 01 11:41:22 AM PDT 24
Peak memory 273460 kb
Host smart-acbf3d96-5d0e-47a3-822f-c48622ee2884
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539412919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.539412919
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3163282823
Short name T105
Test name
Test status
Simulation time 17663008669 ps
CPU time 532.6 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:34:01 AM PDT 24
Peak memory 265820 kb
Host smart-2af21acc-0503-4bef-8814-03e1b04010c2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163282823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3163282823
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3324877364
Short name T74
Test name
Test status
Simulation time 158175146 ps
CPU time 6.63 seconds
Started Jul 01 11:24:58 AM PDT 24
Finished Jul 01 11:25:09 AM PDT 24
Peak memory 252140 kb
Host smart-29f346b8-4ee6-4463-b966-f2a4387cd000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33248
77364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3324877364
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.952953868
Short name T212
Test name
Test status
Simulation time 225705136849 ps
CPU time 3278.75 seconds
Started Jul 01 11:25:11 AM PDT 24
Finished Jul 01 12:19:53 PM PDT 24
Peak memory 290084 kb
Host smart-aac1431f-e149-4dd5-b6bd-dcb83322e861
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952953868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.952953868
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.294729694
Short name T263
Test name
Test status
Simulation time 419740975934 ps
CPU time 2274.9 seconds
Started Jul 01 11:25:38 AM PDT 24
Finished Jul 01 12:03:36 PM PDT 24
Peak memory 286652 kb
Host smart-9d7136ba-b7b7-42b3-85a9-9ec601bc7652
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294729694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.294729694
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2521595385
Short name T155
Test name
Test status
Simulation time 597476362 ps
CPU time 45.79 seconds
Started Jul 01 11:01:37 AM PDT 24
Finished Jul 01 11:02:24 AM PDT 24
Peak memory 248572 kb
Host smart-14365f13-e16c-43b0-8821-8a5c96a30bc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2521595385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2521595385
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1265476575
Short name T158
Test name
Test status
Simulation time 170717475 ps
CPU time 3.61 seconds
Started Jul 01 11:01:26 AM PDT 24
Finished Jul 01 11:01:30 AM PDT 24
Peak memory 236612 kb
Host smart-ce3936fc-8e01-445a-95f1-074bc4495f3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1265476575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1265476575
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3808419700
Short name T131
Test name
Test status
Simulation time 10513823728 ps
CPU time 103.85 seconds
Started Jul 01 11:01:13 AM PDT 24
Finished Jul 01 11:02:58 AM PDT 24
Peak memory 266812 kb
Host smart-1bdfa288-2b9c-4f2c-abfc-c0d8756af1c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3808419700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3808419700
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3710847101
Short name T163
Test name
Test status
Simulation time 181317757 ps
CPU time 3.9 seconds
Started Jul 01 11:01:50 AM PDT 24
Finished Jul 01 11:01:54 AM PDT 24
Peak memory 238632 kb
Host smart-427cfe32-f356-4965-a767-e14121bda00f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3710847101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3710847101
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2570726373
Short name T160
Test name
Test status
Simulation time 271070418 ps
CPU time 4.03 seconds
Started Jul 01 11:01:28 AM PDT 24
Finished Jul 01 11:01:33 AM PDT 24
Peak memory 236632 kb
Host smart-ec95ac14-5891-4c19-88b7-95e9457c4564
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2570726373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2570726373
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1057180525
Short name T162
Test name
Test status
Simulation time 350105614 ps
CPU time 41.3 seconds
Started Jul 01 11:01:10 AM PDT 24
Finished Jul 01 11:01:54 AM PDT 24
Peak memory 240540 kb
Host smart-53fe9945-86d4-45a1-95be-99643b2f7183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1057180525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1057180525
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1881241824
Short name T164
Test name
Test status
Simulation time 3156887917 ps
CPU time 42.32 seconds
Started Jul 01 11:01:35 AM PDT 24
Finished Jul 01 11:02:18 AM PDT 24
Peak memory 240600 kb
Host smart-b21f31d7-24c1-4d65-b13a-98e48cda06e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1881241824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1881241824
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2090400922
Short name T154
Test name
Test status
Simulation time 455281850 ps
CPU time 37.33 seconds
Started Jul 01 11:01:25 AM PDT 24
Finished Jul 01 11:02:03 AM PDT 24
Peak memory 237676 kb
Host smart-7b45822f-bb6a-4473-8120-eef631b38043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2090400922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2090400922
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2649467618
Short name T159
Test name
Test status
Simulation time 78757753 ps
CPU time 4.27 seconds
Started Jul 01 11:01:54 AM PDT 24
Finished Jul 01 11:02:00 AM PDT 24
Peak memory 237592 kb
Host smart-5706c4a0-4253-49f9-987e-c103ba0ec25d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2649467618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2649467618
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3247440336
Short name T150
Test name
Test status
Simulation time 1263906468 ps
CPU time 43.13 seconds
Started Jul 01 11:01:31 AM PDT 24
Finished Jul 01 11:02:15 AM PDT 24
Peak memory 240516 kb
Host smart-8c4a3ebb-ad3e-42ce-857e-3e1776849f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3247440336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3247440336
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1229718570
Short name T169
Test name
Test status
Simulation time 80473725 ps
CPU time 4.92 seconds
Started Jul 01 11:01:37 AM PDT 24
Finished Jul 01 11:01:43 AM PDT 24
Peak memory 236568 kb
Host smart-d7e06175-4d31-46ab-91e1-d00023365de9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1229718570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1229718570
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3625886778
Short name T166
Test name
Test status
Simulation time 1160696896 ps
CPU time 70.31 seconds
Started Jul 01 11:01:17 AM PDT 24
Finished Jul 01 11:02:28 AM PDT 24
Peak memory 240552 kb
Host smart-989547b2-2a7d-44e2-ae73-3f1ab3ff155a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3625886778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3625886778
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.271054911
Short name T157
Test name
Test status
Simulation time 28613710 ps
CPU time 2.74 seconds
Started Jul 01 11:01:34 AM PDT 24
Finished Jul 01 11:01:37 AM PDT 24
Peak memory 237872 kb
Host smart-cae6c2d9-774e-41df-8cc7-7c3fc0bf4ff1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=271054911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.271054911
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1948186468
Short name T165
Test name
Test status
Simulation time 31100456 ps
CPU time 2.25 seconds
Started Jul 01 11:01:22 AM PDT 24
Finished Jul 01 11:01:25 AM PDT 24
Peak memory 237796 kb
Host smart-2d885159-8417-458c-9c10-f68a1f632e09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1948186468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1948186468
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.4122313604
Short name T186
Test name
Test status
Simulation time 2113733483 ps
CPU time 123.97 seconds
Started Jul 01 11:01:15 AM PDT 24
Finished Jul 01 11:03:21 AM PDT 24
Peak memory 237608 kb
Host smart-61f252d2-36d0-4b50-99c3-425bb3d3fcc8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4122313604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.4122313604
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1210719594
Short name T754
Test name
Test status
Simulation time 1925006540 ps
CPU time 163.31 seconds
Started Jul 01 11:01:31 AM PDT 24
Finished Jul 01 11:04:15 AM PDT 24
Peak memory 240496 kb
Host smart-2c137c1b-61e9-444b-9374-3982e0643b4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1210719594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1210719594
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3566124877
Short name T756
Test name
Test status
Simulation time 39650961 ps
CPU time 6.03 seconds
Started Jul 01 11:01:22 AM PDT 24
Finished Jul 01 11:01:29 AM PDT 24
Peak memory 248740 kb
Host smart-c5eb568e-3307-4b91-886f-6c74a947f15e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3566124877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3566124877
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1128989426
Short name T189
Test name
Test status
Simulation time 285844141 ps
CPU time 6.72 seconds
Started Jul 01 11:01:15 AM PDT 24
Finished Jul 01 11:01:23 AM PDT 24
Peak memory 239712 kb
Host smart-20bfc606-0f0c-4fc9-b332-6b0fb8e60704
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128989426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1128989426
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2224176172
Short name T724
Test name
Test status
Simulation time 79551197 ps
CPU time 6.56 seconds
Started Jul 01 11:01:15 AM PDT 24
Finished Jul 01 11:01:23 AM PDT 24
Peak memory 237604 kb
Host smart-8892803d-c729-469b-a438-136dd9617e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2224176172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2224176172
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1921878627
Short name T799
Test name
Test status
Simulation time 10867559 ps
CPU time 1.23 seconds
Started Jul 01 11:01:08 AM PDT 24
Finished Jul 01 11:01:14 AM PDT 24
Peak memory 237612 kb
Host smart-959195f9-8fa0-4abc-a16e-d5977ca7af0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1921878627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1921878627
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3831370606
Short name T792
Test name
Test status
Simulation time 208839948 ps
CPU time 13.8 seconds
Started Jul 01 11:01:15 AM PDT 24
Finished Jul 01 11:01:30 AM PDT 24
Peak memory 240236 kb
Host smart-8232363f-9ba2-46ac-9849-e6f29eaec454
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3831370606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3831370606
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1884982275
Short name T336
Test name
Test status
Simulation time 8773411564 ps
CPU time 324.12 seconds
Started Jul 01 11:01:15 AM PDT 24
Finished Jul 01 11:06:41 AM PDT 24
Peak memory 265432 kb
Host smart-7247975f-3191-4227-b054-fb67b12d62e1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884982275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1884982275
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3343354210
Short name T811
Test name
Test status
Simulation time 290122650 ps
CPU time 10.73 seconds
Started Jul 01 11:01:07 AM PDT 24
Finished Jul 01 11:01:22 AM PDT 24
Peak memory 255892 kb
Host smart-c91e0dd9-d91d-45c6-94ff-4a5be5d2bcea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3343354210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3343354210
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2530411829
Short name T810
Test name
Test status
Simulation time 6644057256 ps
CPU time 131.53 seconds
Started Jul 01 11:01:10 AM PDT 24
Finished Jul 01 11:03:25 AM PDT 24
Peak memory 240600 kb
Host smart-21b52c1a-be8f-47e0-b1ba-81fb19d0d049
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2530411829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2530411829
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3125098511
Short name T812
Test name
Test status
Simulation time 3027722024 ps
CPU time 92.52 seconds
Started Jul 01 11:01:11 AM PDT 24
Finished Jul 01 11:02:46 AM PDT 24
Peak memory 236684 kb
Host smart-9da825c1-d694-4b0f-a4e4-91c5a2cd74a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3125098511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3125098511
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3698931121
Short name T826
Test name
Test status
Simulation time 21812643 ps
CPU time 3.98 seconds
Started Jul 01 11:01:14 AM PDT 24
Finished Jul 01 11:01:19 AM PDT 24
Peak memory 248800 kb
Host smart-e01a398a-2e54-4e0e-a4f5-12304d6d9df8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3698931121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3698931121
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3198989715
Short name T757
Test name
Test status
Simulation time 38921892 ps
CPU time 5.19 seconds
Started Jul 01 11:01:18 AM PDT 24
Finished Jul 01 11:01:25 AM PDT 24
Peak memory 241192 kb
Host smart-075075ca-b94a-48f5-9103-76dd562b7e5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198989715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3198989715
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2045432312
Short name T834
Test name
Test status
Simulation time 179831198 ps
CPU time 4.37 seconds
Started Jul 01 11:01:12 AM PDT 24
Finished Jul 01 11:01:18 AM PDT 24
Peak memory 237588 kb
Host smart-fa85654b-de87-4e26-8193-607975474ab5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2045432312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2045432312
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1448841268
Short name T773
Test name
Test status
Simulation time 12100189 ps
CPU time 1.51 seconds
Started Jul 01 11:01:10 AM PDT 24
Finished Jul 01 11:01:15 AM PDT 24
Peak memory 237556 kb
Host smart-28dbaef2-0c48-4adc-b6c1-36282a056e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1448841268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1448841268
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2743125380
Short name T723
Test name
Test status
Simulation time 563855649 ps
CPU time 19.6 seconds
Started Jul 01 11:01:48 AM PDT 24
Finished Jul 01 11:02:08 AM PDT 24
Peak memory 245756 kb
Host smart-7d27f7a2-7274-4cc7-a0ab-057e48bd86dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2743125380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2743125380
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3976846764
Short name T126
Test name
Test status
Simulation time 3632398700 ps
CPU time 131.24 seconds
Started Jul 01 11:01:37 AM PDT 24
Finished Jul 01 11:03:49 AM PDT 24
Peak memory 257280 kb
Host smart-3c7b4617-6f26-4342-a6af-887340f108fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3976846764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3976846764
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3513794658
Short name T125
Test name
Test status
Simulation time 89540317562 ps
CPU time 1089.85 seconds
Started Jul 01 11:01:07 AM PDT 24
Finished Jul 01 11:19:22 AM PDT 24
Peak memory 265512 kb
Host smart-588d409c-f9f0-4fe6-81a6-bab3912e217c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513794658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3513794658
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1274133989
Short name T734
Test name
Test status
Simulation time 127547414 ps
CPU time 9.2 seconds
Started Jul 01 11:01:15 AM PDT 24
Finished Jul 01 11:01:26 AM PDT 24
Peak memory 248332 kb
Host smart-be5bd223-8af5-4cf2-9b5d-f68b951ed1a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1274133989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1274133989
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1785811018
Short name T161
Test name
Test status
Simulation time 45945429 ps
CPU time 3.36 seconds
Started Jul 01 11:01:36 AM PDT 24
Finished Jul 01 11:01:40 AM PDT 24
Peak memory 238004 kb
Host smart-2b908ad4-7d04-4271-86a2-0b1209edf7e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1785811018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1785811018
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2503538957
Short name T829
Test name
Test status
Simulation time 330269170 ps
CPU time 6.67 seconds
Started Jul 01 11:01:21 AM PDT 24
Finished Jul 01 11:01:28 AM PDT 24
Peak memory 240580 kb
Host smart-11674f69-c09b-4f3e-8f48-9614eda8df4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503538957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2503538957
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3590740816
Short name T766
Test name
Test status
Simulation time 356566199 ps
CPU time 8.07 seconds
Started Jul 01 11:01:26 AM PDT 24
Finished Jul 01 11:01:34 AM PDT 24
Peak memory 237532 kb
Host smart-af5dc3d7-2421-47e6-9927-febca7102a37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3590740816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3590740816
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.820893443
Short name T740
Test name
Test status
Simulation time 85040319 ps
CPU time 11.18 seconds
Started Jul 01 11:01:51 AM PDT 24
Finished Jul 01 11:02:03 AM PDT 24
Peak memory 240476 kb
Host smart-a6c3ea09-ad35-4fed-adfd-b9e0b7ccbc8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=820893443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.820893443
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2711539639
Short name T733
Test name
Test status
Simulation time 1501923768 ps
CPU time 23.46 seconds
Started Jul 01 11:01:50 AM PDT 24
Finished Jul 01 11:02:14 AM PDT 24
Peak memory 248876 kb
Host smart-55b67272-7ec0-4691-8699-31dd4d4ee277
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2711539639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2711539639
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1445422181
Short name T768
Test name
Test status
Simulation time 409652545 ps
CPU time 7.68 seconds
Started Jul 01 11:01:28 AM PDT 24
Finished Jul 01 11:01:36 AM PDT 24
Peak memory 238044 kb
Host smart-91b27c9a-1df0-4523-be13-f68a0e290dd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445422181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1445422181
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3335961940
Short name T775
Test name
Test status
Simulation time 59418765 ps
CPU time 4.72 seconds
Started Jul 01 11:01:27 AM PDT 24
Finished Jul 01 11:01:32 AM PDT 24
Peak memory 236640 kb
Host smart-8ba6f823-9525-498e-9b5f-59c25d11cff2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3335961940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3335961940
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.58227908
Short name T828
Test name
Test status
Simulation time 6783925 ps
CPU time 1.34 seconds
Started Jul 01 11:01:53 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 235712 kb
Host smart-bd3af57f-714a-4055-a86a-28fddb356e1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=58227908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.58227908
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3651019999
Short name T818
Test name
Test status
Simulation time 664115367 ps
CPU time 22.42 seconds
Started Jul 01 11:01:28 AM PDT 24
Finished Jul 01 11:01:51 AM PDT 24
Peak memory 248748 kb
Host smart-946cfbbc-33de-4905-a85d-68e047e01f5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3651019999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3651019999
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3839159968
Short name T129
Test name
Test status
Simulation time 809185388 ps
CPU time 94.63 seconds
Started Jul 01 11:01:29 AM PDT 24
Finished Jul 01 11:03:04 AM PDT 24
Peak memory 265384 kb
Host smart-59205de3-326a-436d-867a-241aa860c365
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3839159968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3839159968
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.4091014315
Short name T758
Test name
Test status
Simulation time 372094776 ps
CPU time 8.97 seconds
Started Jul 01 11:01:52 AM PDT 24
Finished Jul 01 11:02:02 AM PDT 24
Peak memory 248816 kb
Host smart-a6ebe2b7-67c5-416a-9579-03b0b891f27a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4091014315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.4091014315
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.449811115
Short name T335
Test name
Test status
Simulation time 1014863103 ps
CPU time 11.2 seconds
Started Jul 01 11:01:40 AM PDT 24
Finished Jul 01 11:01:52 AM PDT 24
Peak memory 257000 kb
Host smart-faa6f862-3beb-49a0-9825-8ef75f84f6c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449811115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.449811115
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2054579305
Short name T719
Test name
Test status
Simulation time 66485171 ps
CPU time 3.15 seconds
Started Jul 01 11:01:29 AM PDT 24
Finished Jul 01 11:01:33 AM PDT 24
Peak memory 236636 kb
Host smart-cf3e7192-fd2e-4007-8470-fb2a61c0bed0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2054579305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2054579305
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3875348312
Short name T753
Test name
Test status
Simulation time 27389744 ps
CPU time 2.15 seconds
Started Jul 01 11:01:49 AM PDT 24
Finished Jul 01 11:01:52 AM PDT 24
Peak memory 235616 kb
Host smart-c7e2678a-d1c8-48df-8aaa-fe0d46af1984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3875348312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3875348312
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3316393
Short name T822
Test name
Test status
Simulation time 505709116 ps
CPU time 40.43 seconds
Started Jul 01 11:01:29 AM PDT 24
Finished Jul 01 11:02:10 AM PDT 24
Peak memory 245800 kb
Host smart-6cd25cc9-e675-43d7-b0f3-aad4244d8a2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3316393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outst
anding.3316393
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1302268421
Short name T140
Test name
Test status
Simulation time 3337558550 ps
CPU time 135.91 seconds
Started Jul 01 11:01:28 AM PDT 24
Finished Jul 01 11:03:45 AM PDT 24
Peak memory 266144 kb
Host smart-796395d9-b2d6-41d7-a044-748ea9112dba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1302268421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1302268421
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1744541151
Short name T820
Test name
Test status
Simulation time 210748498 ps
CPU time 10.83 seconds
Started Jul 01 11:01:45 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 254984 kb
Host smart-4afd6b7b-c111-42bc-9279-a267bdb14a20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1744541151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1744541151
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.116018845
Short name T188
Test name
Test status
Simulation time 35727567 ps
CPU time 2.09 seconds
Started Jul 01 11:01:54 AM PDT 24
Finished Jul 01 11:01:58 AM PDT 24
Peak memory 237864 kb
Host smart-eb0dd333-c526-4c59-b89d-90e0e13bab45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=116018845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.116018845
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2577708056
Short name T732
Test name
Test status
Simulation time 141329948 ps
CPU time 11.28 seconds
Started Jul 01 11:01:30 AM PDT 24
Finished Jul 01 11:01:41 AM PDT 24
Peak memory 250856 kb
Host smart-c2e2e5ef-4f60-4cfb-9fa4-6132fd2c94fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577708056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2577708056
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3360458957
Short name T745
Test name
Test status
Simulation time 44144987 ps
CPU time 3.54 seconds
Started Jul 01 11:01:52 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 237600 kb
Host smart-c2af3f01-644f-43ab-b31b-a4dbd0612f32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3360458957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3360458957
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3416440454
Short name T765
Test name
Test status
Simulation time 10698839 ps
CPU time 1.66 seconds
Started Jul 01 11:01:51 AM PDT 24
Finished Jul 01 11:01:53 AM PDT 24
Peak memory 237596 kb
Host smart-55c23e43-fce6-4769-9c21-4924b39fcf34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3416440454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3416440454
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1241673195
Short name T771
Test name
Test status
Simulation time 1099539860 ps
CPU time 45.48 seconds
Started Jul 01 11:01:28 AM PDT 24
Finished Jul 01 11:02:14 AM PDT 24
Peak memory 245820 kb
Host smart-b48b4967-9655-438d-a577-6cf5c709caf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1241673195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1241673195
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1445334238
Short name T142
Test name
Test status
Simulation time 2066136327 ps
CPU time 163.12 seconds
Started Jul 01 11:01:28 AM PDT 24
Finished Jul 01 11:04:12 AM PDT 24
Peak memory 265064 kb
Host smart-fa2f219b-ac0d-452d-8556-e23fd977a4af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1445334238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1445334238
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3776930567
Short name T139
Test name
Test status
Simulation time 2314329377 ps
CPU time 276.6 seconds
Started Jul 01 11:01:49 AM PDT 24
Finished Jul 01 11:06:27 AM PDT 24
Peak memory 268932 kb
Host smart-78101789-c97b-4bed-b4dc-4d8a4fd599df
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776930567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3776930567
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1383133974
Short name T713
Test name
Test status
Simulation time 864465118 ps
CPU time 13.83 seconds
Started Jul 01 11:01:54 AM PDT 24
Finished Jul 01 11:02:10 AM PDT 24
Peak memory 248036 kb
Host smart-7c8a8c6c-11b8-4df5-9217-9c91367c4f5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1383133974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1383133974
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3950756911
Short name T814
Test name
Test status
Simulation time 75666936 ps
CPU time 6.58 seconds
Started Jul 01 11:01:31 AM PDT 24
Finished Jul 01 11:01:38 AM PDT 24
Peak memory 239560 kb
Host smart-f92279d7-120d-4529-8ced-c8d4eaf6e255
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950756911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3950756911
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.543751636
Short name T809
Test name
Test status
Simulation time 28973182 ps
CPU time 3.36 seconds
Started Jul 01 11:01:52 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 237556 kb
Host smart-2a3063de-1062-4929-922a-019718eb9476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=543751636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.543751636
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4264399861
Short name T715
Test name
Test status
Simulation time 11001183 ps
CPU time 1.59 seconds
Started Jul 01 11:02:00 AM PDT 24
Finished Jul 01 11:02:02 AM PDT 24
Peak memory 236716 kb
Host smart-e58ddcda-efb5-436f-a3f6-257c3602fb5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4264399861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4264399861
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.28757471
Short name T179
Test name
Test status
Simulation time 547491890 ps
CPU time 17.58 seconds
Started Jul 01 11:01:51 AM PDT 24
Finished Jul 01 11:02:10 AM PDT 24
Peak memory 244860 kb
Host smart-d6ee062d-48a0-4c94-9a4f-cc6dd3070dbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=28757471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outs
tanding.28757471
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2862798982
Short name T136
Test name
Test status
Simulation time 99142494792 ps
CPU time 489.53 seconds
Started Jul 01 11:01:53 AM PDT 24
Finished Jul 01 11:10:05 AM PDT 24
Peak memory 265412 kb
Host smart-3e680875-65e1-4853-a777-27900b70397b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862798982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2862798982
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1549452954
Short name T784
Test name
Test status
Simulation time 602576568 ps
CPU time 30.47 seconds
Started Jul 01 11:01:28 AM PDT 24
Finished Jul 01 11:01:59 AM PDT 24
Peak memory 248496 kb
Host smart-a8a0347b-5750-40b0-9bd6-17eeaba4853a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1549452954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1549452954
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3461615234
Short name T759
Test name
Test status
Simulation time 737269204 ps
CPU time 37.67 seconds
Started Jul 01 11:01:33 AM PDT 24
Finished Jul 01 11:02:11 AM PDT 24
Peak memory 246088 kb
Host smart-187319db-5d13-4932-b38f-ded45e87de3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3461615234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3461615234
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3492387977
Short name T755
Test name
Test status
Simulation time 60210535 ps
CPU time 8.6 seconds
Started Jul 01 11:01:54 AM PDT 24
Finished Jul 01 11:02:04 AM PDT 24
Peak memory 252708 kb
Host smart-78b12eee-b616-46a4-9836-d6952ebcb4c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492387977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3492387977
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.608744622
Short name T722
Test name
Test status
Simulation time 131073736 ps
CPU time 9.76 seconds
Started Jul 01 11:01:47 AM PDT 24
Finished Jul 01 11:01:58 AM PDT 24
Peak memory 237580 kb
Host smart-b922d118-7e68-4b23-8a1a-d4909d6bff80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=608744622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.608744622
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3206338915
Short name T802
Test name
Test status
Simulation time 13721992 ps
CPU time 1.72 seconds
Started Jul 01 11:01:30 AM PDT 24
Finished Jul 01 11:01:33 AM PDT 24
Peak memory 237600 kb
Host smart-d549b7a4-d328-44d4-84e5-e7d3d4bf8ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3206338915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3206338915
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2384585089
Short name T808
Test name
Test status
Simulation time 281049408 ps
CPU time 17.88 seconds
Started Jul 01 11:01:50 AM PDT 24
Finished Jul 01 11:02:09 AM PDT 24
Peak memory 244836 kb
Host smart-9ae32cd7-dbb1-40dd-9d3b-78155e08c5d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2384585089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2384585089
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3121812157
Short name T128
Test name
Test status
Simulation time 1537192229 ps
CPU time 98.32 seconds
Started Jul 01 11:01:55 AM PDT 24
Finished Jul 01 11:03:35 AM PDT 24
Peak memory 257236 kb
Host smart-f852369a-cb95-4512-be42-aecedfbf1fe6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3121812157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3121812157
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1587126280
Short name T145
Test name
Test status
Simulation time 26193017736 ps
CPU time 482.74 seconds
Started Jul 01 11:01:53 AM PDT 24
Finished Jul 01 11:09:57 AM PDT 24
Peak memory 265356 kb
Host smart-b670e9b8-df7e-4050-8621-e675c5d7bf6c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587126280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1587126280
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.260983545
Short name T727
Test name
Test status
Simulation time 39839532 ps
CPU time 5.6 seconds
Started Jul 01 11:01:30 AM PDT 24
Finished Jul 01 11:01:36 AM PDT 24
Peak memory 249864 kb
Host smart-5691d8a9-cb91-40c0-8dfd-5866005bea40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=260983545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.260983545
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3888870415
Short name T334
Test name
Test status
Simulation time 62242385 ps
CPU time 8.94 seconds
Started Jul 01 11:01:53 AM PDT 24
Finished Jul 01 11:02:03 AM PDT 24
Peak memory 253156 kb
Host smart-9816cd51-3a95-4c1c-b7a7-3bde9fc90849
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888870415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3888870415
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2960304350
Short name T815
Test name
Test status
Simulation time 173922775 ps
CPU time 4.7 seconds
Started Jul 01 11:01:34 AM PDT 24
Finished Jul 01 11:01:39 AM PDT 24
Peak memory 240528 kb
Host smart-7ce2129a-b59e-46a9-b637-c484617d0f8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2960304350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2960304350
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2205308917
Short name T772
Test name
Test status
Simulation time 7450967 ps
CPU time 1.47 seconds
Started Jul 01 11:01:53 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 237612 kb
Host smart-da654cbc-f935-4542-9e3e-429501b1c13f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2205308917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2205308917
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3726294773
Short name T180
Test name
Test status
Simulation time 3026154041 ps
CPU time 19.54 seconds
Started Jul 01 11:01:54 AM PDT 24
Finished Jul 01 11:02:15 AM PDT 24
Peak memory 245632 kb
Host smart-3359007a-095d-4e97-bbb0-ba3cb6cbb017
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3726294773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3726294773
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3542513746
Short name T119
Test name
Test status
Simulation time 1656164641 ps
CPU time 97.58 seconds
Started Jul 01 11:01:31 AM PDT 24
Finished Jul 01 11:03:09 AM PDT 24
Peak memory 265324 kb
Host smart-631778a4-2877-44ab-83ee-e7321da21be4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3542513746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3542513746
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3124105487
Short name T134
Test name
Test status
Simulation time 49177881000 ps
CPU time 928.43 seconds
Started Jul 01 11:01:52 AM PDT 24
Finished Jul 01 11:17:22 AM PDT 24
Peak memory 265628 kb
Host smart-9bdb93a8-2b4b-4e32-a789-d71609b85244
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124105487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3124105487
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.609160129
Short name T817
Test name
Test status
Simulation time 189349363 ps
CPU time 6.21 seconds
Started Jul 01 11:01:51 AM PDT 24
Finished Jul 01 11:01:58 AM PDT 24
Peak memory 248492 kb
Host smart-16870b92-7ccb-498c-a6a1-baedfba8ac73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=609160129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.609160129
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.117480724
Short name T833
Test name
Test status
Simulation time 175508906 ps
CPU time 11.76 seconds
Started Jul 01 11:01:51 AM PDT 24
Finished Jul 01 11:02:04 AM PDT 24
Peak memory 256112 kb
Host smart-8b0621ad-027e-4768-9db9-4228852a7c42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117480724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.117480724
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.587016002
Short name T184
Test name
Test status
Simulation time 33686003 ps
CPU time 5.25 seconds
Started Jul 01 11:01:51 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 237624 kb
Host smart-1797fd55-ca17-43e1-9b94-aa0d1715f5b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=587016002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.587016002
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3439163124
Short name T781
Test name
Test status
Simulation time 11393346 ps
CPU time 1.68 seconds
Started Jul 01 11:01:34 AM PDT 24
Finished Jul 01 11:01:36 AM PDT 24
Peak memory 237600 kb
Host smart-8656b709-31af-4cea-a2e9-9494f13eeb9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3439163124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3439163124
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3864997390
Short name T823
Test name
Test status
Simulation time 1885768544 ps
CPU time 35.7 seconds
Started Jul 01 11:01:54 AM PDT 24
Finished Jul 01 11:02:32 AM PDT 24
Peak memory 248768 kb
Host smart-6648ba04-e703-4e48-954e-6455f94ef69a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3864997390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3864997390
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.605683817
Short name T147
Test name
Test status
Simulation time 3114702385 ps
CPU time 82.83 seconds
Started Jul 01 11:01:52 AM PDT 24
Finished Jul 01 11:03:17 AM PDT 24
Peak memory 267592 kb
Host smart-3ef0c7a6-9446-4077-8d72-053234eb1dab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=605683817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.605683817
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3252185231
Short name T133
Test name
Test status
Simulation time 6875073826 ps
CPU time 481.71 seconds
Started Jul 01 11:01:32 AM PDT 24
Finished Jul 01 11:09:34 AM PDT 24
Peak memory 269368 kb
Host smart-ddff7612-1b8f-4b8d-b3eb-8ff4c5a9ac7e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252185231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3252185231
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.818135502
Short name T714
Test name
Test status
Simulation time 175186254 ps
CPU time 12.79 seconds
Started Jul 01 11:01:37 AM PDT 24
Finished Jul 01 11:01:50 AM PDT 24
Peak memory 254900 kb
Host smart-505ebbd0-ba8d-494b-ab02-38969b0625ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=818135502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.818135502
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2073256261
Short name T831
Test name
Test status
Simulation time 287414532 ps
CPU time 5.32 seconds
Started Jul 01 11:01:38 AM PDT 24
Finished Jul 01 11:01:44 AM PDT 24
Peak memory 240612 kb
Host smart-38169df2-c1c8-40ca-9275-f973b218a16f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073256261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2073256261
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1193847627
Short name T752
Test name
Test status
Simulation time 482563441 ps
CPU time 7.74 seconds
Started Jul 01 11:01:50 AM PDT 24
Finished Jul 01 11:01:58 AM PDT 24
Peak memory 237620 kb
Host smart-fe52bec8-e640-4397-b818-b146af7f3baa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1193847627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1193847627
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.4059647491
Short name T741
Test name
Test status
Simulation time 9114206 ps
CPU time 1.6 seconds
Started Jul 01 11:01:36 AM PDT 24
Finished Jul 01 11:01:38 AM PDT 24
Peak memory 237620 kb
Host smart-602263a6-2069-4ec2-a143-b3706a9ac064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4059647491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.4059647491
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2505703347
Short name T832
Test name
Test status
Simulation time 3280941823 ps
CPU time 20.69 seconds
Started Jul 01 11:01:53 AM PDT 24
Finished Jul 01 11:02:16 AM PDT 24
Peak memory 244776 kb
Host smart-d4dbe6c6-2b76-47e0-aeb8-d0faca1b8d0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2505703347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2505703347
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.845508133
Short name T141
Test name
Test status
Simulation time 2675092412 ps
CPU time 155.85 seconds
Started Jul 01 11:01:46 AM PDT 24
Finished Jul 01 11:04:22 AM PDT 24
Peak memory 256808 kb
Host smart-d031272f-559a-4b76-86b8-4e9a5866fc74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=845508133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.845508133
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.963482983
Short name T743
Test name
Test status
Simulation time 68799637 ps
CPU time 7.91 seconds
Started Jul 01 11:01:41 AM PDT 24
Finished Jul 01 11:01:50 AM PDT 24
Peak memory 254652 kb
Host smart-9518d608-6bb0-48ca-a114-bc4b397e48a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=963482983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.963482983
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1942828236
Short name T827
Test name
Test status
Simulation time 1443483339 ps
CPU time 13.65 seconds
Started Jul 01 11:01:39 AM PDT 24
Finished Jul 01 11:01:53 AM PDT 24
Peak memory 243696 kb
Host smart-e60d8c40-a9b2-4405-b06b-d1a9a7249c40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942828236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1942828236
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4156606973
Short name T778
Test name
Test status
Simulation time 228968588 ps
CPU time 4.36 seconds
Started Jul 01 11:01:50 AM PDT 24
Finished Jul 01 11:01:55 AM PDT 24
Peak memory 239448 kb
Host smart-4a5d5e38-ce8e-484b-8375-874e9417e123
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4156606973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.4156606973
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3717521901
Short name T153
Test name
Test status
Simulation time 18326596 ps
CPU time 1.38 seconds
Started Jul 01 11:01:54 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 237612 kb
Host smart-07c1f8cd-04e5-4481-b37c-04690a7e1de5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3717521901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3717521901
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.473009532
Short name T824
Test name
Test status
Simulation time 1042461541 ps
CPU time 21.98 seconds
Started Jul 01 11:01:40 AM PDT 24
Finished Jul 01 11:02:03 AM PDT 24
Peak memory 245796 kb
Host smart-0de700ba-3aea-42c8-8d90-d4b32ba5fbbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=473009532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.473009532
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3410115092
Short name T117
Test name
Test status
Simulation time 23957491576 ps
CPU time 481.67 seconds
Started Jul 01 11:01:40 AM PDT 24
Finished Jul 01 11:09:43 AM PDT 24
Peak memory 265412 kb
Host smart-3b0fca60-0115-488e-a1ef-4ec3896660b5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410115092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3410115092
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4109647199
Short name T793
Test name
Test status
Simulation time 233296620 ps
CPU time 6.94 seconds
Started Jul 01 11:01:42 AM PDT 24
Finished Jul 01 11:01:49 AM PDT 24
Peak memory 253744 kb
Host smart-5574412f-7701-4bfd-8297-e0b6e2f3b53b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4109647199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4109647199
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2168338482
Short name T796
Test name
Test status
Simulation time 7662935966 ps
CPU time 114.72 seconds
Started Jul 01 11:01:26 AM PDT 24
Finished Jul 01 11:03:21 AM PDT 24
Peak memory 237688 kb
Host smart-51cfa902-9759-43b9-aca7-0cf2287325b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2168338482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2168338482
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.167606228
Short name T183
Test name
Test status
Simulation time 9606072949 ps
CPU time 208.65 seconds
Started Jul 01 11:01:18 AM PDT 24
Finished Jul 01 11:04:48 AM PDT 24
Peak memory 237604 kb
Host smart-c7cda0f8-8d4a-4f5c-9f5f-bed089119589
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=167606228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.167606228
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.186890818
Short name T731
Test name
Test status
Simulation time 396610493 ps
CPU time 8.66 seconds
Started Jul 01 11:01:27 AM PDT 24
Finished Jul 01 11:01:36 AM PDT 24
Peak memory 249160 kb
Host smart-34d75f2e-70a1-4149-88ad-2f4f21885c24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=186890818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.186890818
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1602402800
Short name T333
Test name
Test status
Simulation time 118071572 ps
CPU time 5.19 seconds
Started Jul 01 11:01:36 AM PDT 24
Finished Jul 01 11:01:42 AM PDT 24
Peak memory 241096 kb
Host smart-f19aa1f5-60b8-4c0b-8693-aacb00f93dbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602402800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1602402800
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.742839914
Short name T730
Test name
Test status
Simulation time 218943865 ps
CPU time 4.98 seconds
Started Jul 01 11:01:15 AM PDT 24
Finished Jul 01 11:01:21 AM PDT 24
Peak memory 236492 kb
Host smart-b7fff356-2ff3-4cc0-a63a-d41a8c46e10a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=742839914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.742839914
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2011618307
Short name T787
Test name
Test status
Simulation time 8827410 ps
CPU time 1.66 seconds
Started Jul 01 11:01:39 AM PDT 24
Finished Jul 01 11:01:41 AM PDT 24
Peak memory 237564 kb
Host smart-764a4861-8a68-45ec-839b-f27f3c4d0cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2011618307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2011618307
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2683477735
Short name T779
Test name
Test status
Simulation time 4113191627 ps
CPU time 42.55 seconds
Started Jul 01 11:01:13 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 248824 kb
Host smart-e115ed99-08fa-4d19-93a7-4cf07867787c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2683477735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2683477735
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2747691827
Short name T135
Test name
Test status
Simulation time 16877751362 ps
CPU time 1109.27 seconds
Started Jul 01 11:01:38 AM PDT 24
Finished Jul 01 11:20:09 AM PDT 24
Peak memory 265428 kb
Host smart-981d8757-e0e3-4259-a2a7-912242174f9f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747691827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2747691827
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.269574550
Short name T712
Test name
Test status
Simulation time 59269919 ps
CPU time 6.69 seconds
Started Jul 01 11:01:39 AM PDT 24
Finished Jul 01 11:01:46 AM PDT 24
Peak memory 248700 kb
Host smart-4ae53625-667f-4b00-bd2b-b0af684a3516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=269574550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.269574550
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1037997649
Short name T807
Test name
Test status
Simulation time 10720004 ps
CPU time 1.31 seconds
Started Jul 01 11:01:54 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 236672 kb
Host smart-4fa83da6-6359-48fc-a947-1d3a9c61a3cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1037997649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1037997649
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.953691588
Short name T764
Test name
Test status
Simulation time 8688187 ps
CPU time 1.44 seconds
Started Jul 01 11:01:54 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 236668 kb
Host smart-6fae3af5-586f-4846-abf9-da061cd81da1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=953691588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.953691588
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1577564439
Short name T718
Test name
Test status
Simulation time 17678286 ps
CPU time 1.45 seconds
Started Jul 01 11:01:41 AM PDT 24
Finished Jul 01 11:01:43 AM PDT 24
Peak memory 237632 kb
Host smart-8394fc1e-d515-4099-8f89-83bfc98bb319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1577564439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1577564439
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1329407944
Short name T737
Test name
Test status
Simulation time 16790597 ps
CPU time 1.41 seconds
Started Jul 01 11:01:47 AM PDT 24
Finished Jul 01 11:01:49 AM PDT 24
Peak memory 237632 kb
Host smart-4b562d07-8118-4a39-bd74-a5bd23683a70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1329407944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1329407944
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2015988402
Short name T151
Test name
Test status
Simulation time 10772734 ps
CPU time 1.62 seconds
Started Jul 01 11:01:52 AM PDT 24
Finished Jul 01 11:01:55 AM PDT 24
Peak memory 237612 kb
Host smart-791caac9-2318-4cf4-971f-c9a45d841bde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2015988402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2015988402
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1131591885
Short name T331
Test name
Test status
Simulation time 11047809 ps
CPU time 1.32 seconds
Started Jul 01 11:01:54 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 236624 kb
Host smart-22f00cc4-4b50-4526-b48a-7123056823c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1131591885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1131591885
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1495645534
Short name T725
Test name
Test status
Simulation time 6535762 ps
CPU time 1.51 seconds
Started Jul 01 11:01:56 AM PDT 24
Finished Jul 01 11:01:59 AM PDT 24
Peak memory 236784 kb
Host smart-7fac1188-9b86-4dcc-968c-3cc4cf167bfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1495645534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1495645534
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.815709154
Short name T786
Test name
Test status
Simulation time 12380178 ps
CPU time 1.43 seconds
Started Jul 01 11:01:55 AM PDT 24
Finished Jul 01 11:01:58 AM PDT 24
Peak memory 236664 kb
Host smart-32c8685b-b137-47f8-9c95-638e3032243f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=815709154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.815709154
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.726666012
Short name T776
Test name
Test status
Simulation time 11466646 ps
CPU time 1.27 seconds
Started Jul 01 11:01:51 AM PDT 24
Finished Jul 01 11:01:53 AM PDT 24
Peak memory 236540 kb
Host smart-19316802-d1c3-440d-b53f-11b4efce11c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=726666012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.726666012
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2057496766
Short name T330
Test name
Test status
Simulation time 8652524 ps
CPU time 1.5 seconds
Started Jul 01 11:01:43 AM PDT 24
Finished Jul 01 11:01:45 AM PDT 24
Peak memory 235724 kb
Host smart-d8cca4b8-0a38-40d5-85c6-5024d34b4e3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2057496766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2057496766
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3341151571
Short name T794
Test name
Test status
Simulation time 1641038600 ps
CPU time 103.59 seconds
Started Jul 01 11:01:15 AM PDT 24
Finished Jul 01 11:03:00 AM PDT 24
Peak memory 240440 kb
Host smart-b167131c-09fd-485a-a3ed-6acbb3d5a5a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3341151571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3341151571
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.81423304
Short name T806
Test name
Test status
Simulation time 11406042802 ps
CPU time 182.14 seconds
Started Jul 01 11:01:12 AM PDT 24
Finished Jul 01 11:04:16 AM PDT 24
Peak memory 240620 kb
Host smart-6572bc26-624f-40b9-a4b3-f7239e180b9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=81423304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.81423304
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.362978366
Short name T791
Test name
Test status
Simulation time 243905243 ps
CPU time 3.65 seconds
Started Jul 01 11:01:28 AM PDT 24
Finished Jul 01 11:01:33 AM PDT 24
Peak memory 248728 kb
Host smart-ef678aca-53b5-431a-b163-44ad553bdf04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=362978366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.362978366
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1147789432
Short name T797
Test name
Test status
Simulation time 183679957 ps
CPU time 13.18 seconds
Started Jul 01 11:01:48 AM PDT 24
Finished Jul 01 11:02:02 AM PDT 24
Peak memory 243900 kb
Host smart-e335b081-d1a3-499b-b8fe-c2a38df8532b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147789432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1147789432
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2124493727
Short name T721
Test name
Test status
Simulation time 35358182 ps
CPU time 5.03 seconds
Started Jul 01 11:01:35 AM PDT 24
Finished Jul 01 11:01:41 AM PDT 24
Peak memory 236644 kb
Host smart-31ff2ec5-d201-4fb1-a258-37f2c124ac5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2124493727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2124493727
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.531817687
Short name T780
Test name
Test status
Simulation time 8462341 ps
CPU time 1.33 seconds
Started Jul 01 11:01:14 AM PDT 24
Finished Jul 01 11:01:17 AM PDT 24
Peak memory 236636 kb
Host smart-5da316b3-7d5d-4b2c-8403-1ec8bb427399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=531817687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.531817687
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1050067343
Short name T182
Test name
Test status
Simulation time 516572503 ps
CPU time 13.24 seconds
Started Jul 01 11:01:11 AM PDT 24
Finished Jul 01 11:01:27 AM PDT 24
Peak memory 240540 kb
Host smart-89d5371f-c888-4382-98ab-84c41318d7a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1050067343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1050067343
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.4284156013
Short name T113
Test name
Test status
Simulation time 2089096078 ps
CPU time 159.89 seconds
Started Jul 01 11:01:18 AM PDT 24
Finished Jul 01 11:03:59 AM PDT 24
Peak memory 265388 kb
Host smart-fe006789-a976-4d7b-b841-0d2a7e36733e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4284156013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.4284156013
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1214493456
Short name T143
Test name
Test status
Simulation time 13960711753 ps
CPU time 918.5 seconds
Started Jul 01 11:01:47 AM PDT 24
Finished Jul 01 11:17:07 AM PDT 24
Peak memory 265460 kb
Host smart-7cec5b90-f96c-4447-88c5-6c1aed5a20da
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214493456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1214493456
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.447057055
Short name T720
Test name
Test status
Simulation time 342109190 ps
CPU time 24.83 seconds
Started Jul 01 11:01:16 AM PDT 24
Finished Jul 01 11:01:43 AM PDT 24
Peak memory 248348 kb
Host smart-6e74e531-3340-4c13-9b8d-1d384f24b80a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=447057055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.447057055
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.950604972
Short name T167
Test name
Test status
Simulation time 1288613926 ps
CPU time 83.7 seconds
Started Jul 01 11:01:16 AM PDT 24
Finished Jul 01 11:02:42 AM PDT 24
Peak memory 240504 kb
Host smart-50706f9b-e186-4fe2-88fd-2af74ccfec2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=950604972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.950604972
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3541236490
Short name T760
Test name
Test status
Simulation time 18348034 ps
CPU time 1.35 seconds
Started Jul 01 11:01:47 AM PDT 24
Finished Jul 01 11:01:49 AM PDT 24
Peak memory 237620 kb
Host smart-a1113df0-9537-48f0-a6a5-e596277d1fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3541236490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3541236490
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1488466871
Short name T774
Test name
Test status
Simulation time 6689789 ps
CPU time 1.48 seconds
Started Jul 01 11:02:00 AM PDT 24
Finished Jul 01 11:02:02 AM PDT 24
Peak memory 236736 kb
Host smart-1eb816e4-042e-4584-9674-48dc91d6e2af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1488466871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1488466871
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.65593105
Short name T816
Test name
Test status
Simulation time 9748150 ps
CPU time 1.22 seconds
Started Jul 01 11:02:00 AM PDT 24
Finished Jul 01 11:02:01 AM PDT 24
Peak memory 235548 kb
Host smart-a2d4f0d8-337f-4a80-9b43-3a009aa7a8c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=65593105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.65593105
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1106743544
Short name T328
Test name
Test status
Simulation time 11357649 ps
CPU time 1.45 seconds
Started Jul 01 11:01:46 AM PDT 24
Finished Jul 01 11:01:48 AM PDT 24
Peak memory 235684 kb
Host smart-228bd78d-9f96-42f7-b112-bb11e4827a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1106743544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1106743544
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3986358611
Short name T767
Test name
Test status
Simulation time 20591034 ps
CPU time 1.47 seconds
Started Jul 01 11:01:48 AM PDT 24
Finished Jul 01 11:01:50 AM PDT 24
Peak memory 237600 kb
Host smart-5b4ea635-0fdf-4555-a359-5e8c0a2b6951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3986358611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3986358611
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.4282049166
Short name T748
Test name
Test status
Simulation time 7544564 ps
CPU time 1.57 seconds
Started Jul 01 11:01:45 AM PDT 24
Finished Jul 01 11:01:47 AM PDT 24
Peak memory 236684 kb
Host smart-f6b74881-69d9-42a1-9a42-b8f7fa73a5a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4282049166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.4282049166
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3696621495
Short name T744
Test name
Test status
Simulation time 23936284 ps
CPU time 1.55 seconds
Started Jul 01 11:01:45 AM PDT 24
Finished Jul 01 11:01:47 AM PDT 24
Peak memory 237588 kb
Host smart-266e5c38-6451-40b5-9928-74958aa0d92e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3696621495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3696621495
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2214934181
Short name T746
Test name
Test status
Simulation time 21023534 ps
CPU time 1.45 seconds
Started Jul 01 11:02:00 AM PDT 24
Finished Jul 01 11:02:02 AM PDT 24
Peak memory 237604 kb
Host smart-5906f596-0ad2-43d6-9c43-2048b290e43e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2214934181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2214934181
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.268954331
Short name T742
Test name
Test status
Simulation time 8989579 ps
CPU time 1.45 seconds
Started Jul 01 11:01:43 AM PDT 24
Finished Jul 01 11:01:45 AM PDT 24
Peak memory 237588 kb
Host smart-9553f8b4-b9d2-47b5-83d8-a7be41b25670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=268954331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.268954331
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3886532715
Short name T785
Test name
Test status
Simulation time 4582157243 ps
CPU time 158.87 seconds
Started Jul 01 11:01:38 AM PDT 24
Finished Jul 01 11:04:18 AM PDT 24
Peak memory 240640 kb
Host smart-e301f5db-d4eb-4058-b4f2-8753ab75aa35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3886532715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3886532715
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1642586853
Short name T761
Test name
Test status
Simulation time 85556897059 ps
CPU time 485.56 seconds
Started Jul 01 11:01:15 AM PDT 24
Finished Jul 01 11:09:23 AM PDT 24
Peak memory 237628 kb
Host smart-6abda3ba-87d1-4693-aff2-5fdb2749ba20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1642586853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1642586853
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.219791273
Short name T770
Test name
Test status
Simulation time 1354109761 ps
CPU time 8.72 seconds
Started Jul 01 11:01:47 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 249208 kb
Host smart-480d2792-3638-40f4-a2ff-69f4d14cb098
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=219791273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.219791273
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3092141762
Short name T777
Test name
Test status
Simulation time 63012788 ps
CPU time 5.57 seconds
Started Jul 01 11:01:25 AM PDT 24
Finished Jul 01 11:01:31 AM PDT 24
Peak memory 254020 kb
Host smart-b466801a-7769-4de7-81ff-5de570acd8f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092141762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3092141762
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1566581883
Short name T798
Test name
Test status
Simulation time 94285736 ps
CPU time 8.22 seconds
Started Jul 01 11:01:20 AM PDT 24
Finished Jul 01 11:01:29 AM PDT 24
Peak memory 236656 kb
Host smart-ea529172-e092-4118-8ed9-50ef6891bd4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1566581883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1566581883
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1486739021
Short name T825
Test name
Test status
Simulation time 39661864 ps
CPU time 1.47 seconds
Started Jul 01 11:01:42 AM PDT 24
Finished Jul 01 11:01:44 AM PDT 24
Peak memory 236744 kb
Host smart-0cfd3c69-8571-48be-8584-4f92ed1402ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1486739021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1486739021
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1413334374
Short name T185
Test name
Test status
Simulation time 1055610969 ps
CPU time 21.43 seconds
Started Jul 01 11:01:33 AM PDT 24
Finished Jul 01 11:01:55 AM PDT 24
Peak memory 245768 kb
Host smart-810c93bf-4c72-4a65-a947-61556526655d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1413334374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1413334374
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1878038141
Short name T750
Test name
Test status
Simulation time 32454726 ps
CPU time 4.96 seconds
Started Jul 01 11:01:40 AM PDT 24
Finished Jul 01 11:01:46 AM PDT 24
Peak memory 252020 kb
Host smart-c3410840-005d-4ae2-9584-aca516d75e68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1878038141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1878038141
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3531365778
Short name T783
Test name
Test status
Simulation time 13948365 ps
CPU time 1.39 seconds
Started Jul 01 11:01:44 AM PDT 24
Finished Jul 01 11:01:46 AM PDT 24
Peak memory 235676 kb
Host smart-55ac2e0c-3f05-48ca-b6ad-347c97499fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3531365778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3531365778
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3985378640
Short name T801
Test name
Test status
Simulation time 19631187 ps
CPU time 1.43 seconds
Started Jul 01 11:01:54 AM PDT 24
Finished Jul 01 11:01:58 AM PDT 24
Peak memory 236628 kb
Host smart-d98a0ab1-7b61-46d2-865e-64b8d1eebc0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3985378640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3985378640
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1350851124
Short name T821
Test name
Test status
Simulation time 18533541 ps
CPU time 1.3 seconds
Started Jul 01 11:01:57 AM PDT 24
Finished Jul 01 11:01:59 AM PDT 24
Peak memory 237620 kb
Host smart-e2f29a6f-e493-4925-b673-afb908a1e9b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1350851124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1350851124
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2730703920
Short name T716
Test name
Test status
Simulation time 8543663 ps
CPU time 1.42 seconds
Started Jul 01 11:01:56 AM PDT 24
Finished Jul 01 11:01:58 AM PDT 24
Peak memory 237600 kb
Host smart-16640103-9c4c-4244-860c-6c0481c0093b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2730703920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2730703920
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4205203786
Short name T739
Test name
Test status
Simulation time 21908858 ps
CPU time 1.46 seconds
Started Jul 01 11:01:44 AM PDT 24
Finished Jul 01 11:01:46 AM PDT 24
Peak memory 237600 kb
Host smart-b3863f3a-5b05-452d-9048-122f601c5723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4205203786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4205203786
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2338061865
Short name T747
Test name
Test status
Simulation time 10959151 ps
CPU time 1.36 seconds
Started Jul 01 11:01:53 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 237540 kb
Host smart-f2771704-2eef-428a-aabe-b2aa7b48c4c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2338061865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2338061865
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1225532360
Short name T152
Test name
Test status
Simulation time 10143606 ps
CPU time 1.37 seconds
Started Jul 01 11:01:46 AM PDT 24
Finished Jul 01 11:01:48 AM PDT 24
Peak memory 236652 kb
Host smart-281f6b83-0328-4bba-8954-64e431283851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1225532360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1225532360
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.297117586
Short name T769
Test name
Test status
Simulation time 25641882 ps
CPU time 1.55 seconds
Started Jul 01 11:01:45 AM PDT 24
Finished Jul 01 11:01:47 AM PDT 24
Peak memory 236628 kb
Host smart-904c27c1-2961-4662-8f07-f1341c7cd518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=297117586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.297117586
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2604720989
Short name T736
Test name
Test status
Simulation time 8662039 ps
CPU time 1.51 seconds
Started Jul 01 11:02:11 AM PDT 24
Finished Jul 01 11:02:13 AM PDT 24
Peak memory 236612 kb
Host smart-4b6dd839-756b-4358-bfe4-54d45f770058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2604720989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2604720989
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4167371816
Short name T332
Test name
Test status
Simulation time 11910714 ps
CPU time 1.48 seconds
Started Jul 01 11:01:45 AM PDT 24
Finished Jul 01 11:01:47 AM PDT 24
Peak memory 237588 kb
Host smart-9f77f1f5-1485-454a-9f7a-7f18c5cb1275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4167371816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4167371816
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3590531978
Short name T726
Test name
Test status
Simulation time 33640804 ps
CPU time 4.74 seconds
Started Jul 01 11:01:35 AM PDT 24
Finished Jul 01 11:01:40 AM PDT 24
Peak memory 240572 kb
Host smart-2d8ef1e8-ffc1-4a57-975c-d44b4c6d1c30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590531978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3590531978
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3384588976
Short name T805
Test name
Test status
Simulation time 112858907 ps
CPU time 4.55 seconds
Started Jul 01 11:01:30 AM PDT 24
Finished Jul 01 11:01:36 AM PDT 24
Peak memory 236544 kb
Host smart-bf7e2ea8-39df-4e63-aff7-7231f3f1eeae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3384588976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3384588976
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1535916198
Short name T751
Test name
Test status
Simulation time 8885059 ps
CPU time 1.5 seconds
Started Jul 01 11:01:22 AM PDT 24
Finished Jul 01 11:01:24 AM PDT 24
Peak memory 237620 kb
Host smart-de25aab7-591f-4ac2-b462-3bda847dfd78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1535916198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1535916198
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1902079477
Short name T181
Test name
Test status
Simulation time 706040172 ps
CPU time 25.89 seconds
Started Jul 01 11:01:27 AM PDT 24
Finished Jul 01 11:01:54 AM PDT 24
Peak memory 245776 kb
Host smart-4fe36e98-4129-423d-abf3-9eed34457fae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1902079477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1902079477
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2818874052
Short name T116
Test name
Test status
Simulation time 2185392752 ps
CPU time 280.75 seconds
Started Jul 01 11:01:17 AM PDT 24
Finished Jul 01 11:05:59 AM PDT 24
Peak memory 266512 kb
Host smart-66c0509d-3264-4a89-b142-3957353bf11e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818874052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2818874052
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1058848157
Short name T763
Test name
Test status
Simulation time 95663617 ps
CPU time 12.25 seconds
Started Jul 01 11:01:17 AM PDT 24
Finished Jul 01 11:01:31 AM PDT 24
Peak memory 255844 kb
Host smart-fabb8cb6-38c5-4508-b424-409d96a89617
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1058848157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1058848157
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.795620828
Short name T789
Test name
Test status
Simulation time 622335530 ps
CPU time 7.99 seconds
Started Jul 01 11:01:34 AM PDT 24
Finished Jul 01 11:01:43 AM PDT 24
Peak memory 256884 kb
Host smart-0f8b3eb6-7cef-43bb-80f3-0416c1b720a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795620828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.alert_handler_csr_mem_rw_with_rand_reset.795620828
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2378201826
Short name T819
Test name
Test status
Simulation time 219545752 ps
CPU time 3.66 seconds
Started Jul 01 11:01:19 AM PDT 24
Finished Jul 01 11:01:23 AM PDT 24
Peak memory 237432 kb
Host smart-7840f08f-7a59-411f-bfdf-b0230cc46597
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2378201826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2378201826
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1151398808
Short name T813
Test name
Test status
Simulation time 9954773 ps
CPU time 1.55 seconds
Started Jul 01 11:01:26 AM PDT 24
Finished Jul 01 11:01:28 AM PDT 24
Peak memory 236736 kb
Host smart-12bbd782-a7b7-4e12-849c-5c075c153dec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1151398808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1151398808
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.767694946
Short name T170
Test name
Test status
Simulation time 641550691 ps
CPU time 21.11 seconds
Started Jul 01 11:01:32 AM PDT 24
Finished Jul 01 11:01:54 AM PDT 24
Peak memory 245820 kb
Host smart-1f4f7d9f-28dc-47a7-8133-39e33608d18f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=767694946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.767694946
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1306083623
Short name T118
Test name
Test status
Simulation time 2486819789 ps
CPU time 104.12 seconds
Started Jul 01 11:01:16 AM PDT 24
Finished Jul 01 11:03:02 AM PDT 24
Peak memory 265516 kb
Host smart-8b9a7450-6028-482e-ad2b-236827ccf4e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1306083623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1306083623
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.757378525
Short name T782
Test name
Test status
Simulation time 339567356 ps
CPU time 11.19 seconds
Started Jul 01 11:01:15 AM PDT 24
Finished Jul 01 11:01:28 AM PDT 24
Peak memory 248496 kb
Host smart-c10289cc-5c9d-4cfb-8e3e-6a11b9e4520f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=757378525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.757378525
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.660278921
Short name T788
Test name
Test status
Simulation time 461259717 ps
CPU time 9.48 seconds
Started Jul 01 11:01:23 AM PDT 24
Finished Jul 01 11:01:33 AM PDT 24
Peak memory 239340 kb
Host smart-bfa5987a-6aac-4aac-b533-23f9a5b554a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660278921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.660278921
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2608289916
Short name T803
Test name
Test status
Simulation time 40712814 ps
CPU time 6.44 seconds
Started Jul 01 11:01:25 AM PDT 24
Finished Jul 01 11:01:32 AM PDT 24
Peak memory 237620 kb
Host smart-45227381-c282-4173-adff-0b80671bbca4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2608289916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2608289916
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3686387093
Short name T795
Test name
Test status
Simulation time 10456298 ps
CPU time 1.57 seconds
Started Jul 01 11:01:35 AM PDT 24
Finished Jul 01 11:01:37 AM PDT 24
Peak memory 235680 kb
Host smart-3b525ec0-0003-4306-98db-1b9a38a74fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3686387093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3686387093
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.422732379
Short name T168
Test name
Test status
Simulation time 97465113 ps
CPU time 12.82 seconds
Started Jul 01 11:01:27 AM PDT 24
Finished Jul 01 11:01:40 AM PDT 24
Peak memory 245812 kb
Host smart-77a51630-3d53-465f-9056-e2a693984413
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=422732379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.422732379
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.592018936
Short name T123
Test name
Test status
Simulation time 6836523485 ps
CPU time 653.28 seconds
Started Jul 01 11:01:18 AM PDT 24
Finished Jul 01 11:12:12 AM PDT 24
Peak memory 265408 kb
Host smart-72b8a26a-9f38-4cf9-b39a-194abbdaf8ae
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592018936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.592018936
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2724282323
Short name T717
Test name
Test status
Simulation time 35942450 ps
CPU time 4.78 seconds
Started Jul 01 11:01:32 AM PDT 24
Finished Jul 01 11:01:38 AM PDT 24
Peak memory 250444 kb
Host smart-fe9a29a0-886f-4949-a84e-6fa54677eeff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2724282323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2724282323
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1893243074
Short name T337
Test name
Test status
Simulation time 157949692 ps
CPU time 13.26 seconds
Started Jul 01 11:01:21 AM PDT 24
Finished Jul 01 11:01:35 AM PDT 24
Peak memory 243656 kb
Host smart-8480f90b-9e87-4f83-ac1f-1298d58ab0ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893243074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1893243074
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3314219786
Short name T790
Test name
Test status
Simulation time 234607511 ps
CPU time 5.24 seconds
Started Jul 01 11:01:26 AM PDT 24
Finished Jul 01 11:01:32 AM PDT 24
Peak memory 237536 kb
Host smart-0a8705c6-1f58-45a6-917a-5ac8aa7539e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3314219786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3314219786
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3669074296
Short name T830
Test name
Test status
Simulation time 8734894 ps
CPU time 1.33 seconds
Started Jul 01 11:01:26 AM PDT 24
Finished Jul 01 11:01:28 AM PDT 24
Peak memory 237576 kb
Host smart-78dc5602-b663-4478-b0a3-717d2b13db10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3669074296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3669074296
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3562461242
Short name T735
Test name
Test status
Simulation time 282632950 ps
CPU time 19.38 seconds
Started Jul 01 11:01:48 AM PDT 24
Finished Jul 01 11:02:09 AM PDT 24
Peak memory 244880 kb
Host smart-b84cf07c-855c-43ef-b317-e1f7b44efab4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3562461242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3562461242
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1386866320
Short name T804
Test name
Test status
Simulation time 1079354897 ps
CPU time 105.13 seconds
Started Jul 01 11:01:25 AM PDT 24
Finished Jul 01 11:03:11 AM PDT 24
Peak memory 265276 kb
Host smart-c6efa51d-238b-4ce8-b033-5362db22fa37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1386866320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1386866320
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3988985960
Short name T729
Test name
Test status
Simulation time 244622577 ps
CPU time 6.36 seconds
Started Jul 01 11:01:25 AM PDT 24
Finished Jul 01 11:01:32 AM PDT 24
Peak memory 248676 kb
Host smart-d4097f2c-ecd0-4091-b094-b947f45e4fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3988985960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3988985960
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2713642912
Short name T749
Test name
Test status
Simulation time 80076447 ps
CPU time 6.47 seconds
Started Jul 01 11:01:48 AM PDT 24
Finished Jul 01 11:01:55 AM PDT 24
Peak memory 240620 kb
Host smart-95e899c9-ad69-4d7c-9abe-2783e77a8b3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713642912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2713642912
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.219895468
Short name T738
Test name
Test status
Simulation time 126535555 ps
CPU time 4.68 seconds
Started Jul 01 11:01:22 AM PDT 24
Finished Jul 01 11:01:27 AM PDT 24
Peak memory 240556 kb
Host smart-8f84c78d-4d03-4061-bfd6-28d12541a9e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=219895468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.219895468
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1603857495
Short name T762
Test name
Test status
Simulation time 7837087 ps
CPU time 1.29 seconds
Started Jul 01 11:01:54 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 237520 kb
Host smart-1def266d-dba2-4d4b-b4ad-055d2c6fbc6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1603857495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1603857495
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1137222297
Short name T800
Test name
Test status
Simulation time 338465596 ps
CPU time 24.01 seconds
Started Jul 01 11:01:25 AM PDT 24
Finished Jul 01 11:01:49 AM PDT 24
Peak memory 248776 kb
Host smart-f6ce29d3-5408-44ec-9c9e-73a8fae99e5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1137222297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1137222297
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.512728064
Short name T144
Test name
Test status
Simulation time 10855922568 ps
CPU time 187.68 seconds
Started Jul 01 11:01:48 AM PDT 24
Finished Jul 01 11:04:56 AM PDT 24
Peak memory 265416 kb
Host smart-b0d46138-bfe6-46c2-9d74-f9be248fc8d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=512728064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.512728064
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2153661501
Short name T137
Test name
Test status
Simulation time 7410315166 ps
CPU time 572.32 seconds
Started Jul 01 11:01:26 AM PDT 24
Finished Jul 01 11:10:59 AM PDT 24
Peak memory 268372 kb
Host smart-dc8d5a0e-ce56-41f2-9b44-b7fa9a66e270
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153661501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2153661501
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.604591711
Short name T728
Test name
Test status
Simulation time 116375947 ps
CPU time 8.83 seconds
Started Jul 01 11:01:26 AM PDT 24
Finished Jul 01 11:01:35 AM PDT 24
Peak memory 248904 kb
Host smart-bb82c762-1e68-4e51-a44f-aad0e062c200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=604591711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.604591711
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1451573467
Short name T697
Test name
Test status
Simulation time 26115024067 ps
CPU time 1065.33 seconds
Started Jul 01 11:24:07 AM PDT 24
Finished Jul 01 11:41:56 AM PDT 24
Peak memory 290352 kb
Host smart-dd77534f-46cd-415b-99c3-06cc1a7ffbb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451573467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1451573467
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.66504417
Short name T414
Test name
Test status
Simulation time 3453702767 ps
CPU time 35.92 seconds
Started Jul 01 11:24:06 AM PDT 24
Finished Jul 01 11:24:44 AM PDT 24
Peak memory 249280 kb
Host smart-d144f371-05e3-4452-a731-d6ae1544ddaf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=66504417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.66504417
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2989565291
Short name T578
Test name
Test status
Simulation time 162116676 ps
CPU time 5.61 seconds
Started Jul 01 11:24:06 AM PDT 24
Finished Jul 01 11:24:15 AM PDT 24
Peak memory 255468 kb
Host smart-94b18457-f025-41f0-9f15-659d80b2b8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29895
65291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2989565291
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1956672650
Short name T300
Test name
Test status
Simulation time 17975123663 ps
CPU time 1239.49 seconds
Started Jul 01 11:24:04 AM PDT 24
Finished Jul 01 11:44:46 AM PDT 24
Peak memory 273332 kb
Host smart-8e1c3ef7-ffd8-4316-b22b-2b1cec798b36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956672650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1956672650
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3382106681
Short name T415
Test name
Test status
Simulation time 147494122863 ps
CPU time 1896.34 seconds
Started Jul 01 11:24:07 AM PDT 24
Finished Jul 01 11:55:48 AM PDT 24
Peak memory 273980 kb
Host smart-2e76a192-2099-4701-8f44-54bf5ee7006f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382106681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3382106681
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3061710943
Short name T499
Test name
Test status
Simulation time 1247924573 ps
CPU time 54.74 seconds
Started Jul 01 11:24:04 AM PDT 24
Finished Jul 01 11:25:01 AM PDT 24
Peak memory 248128 kb
Host smart-4240fddc-fc7a-434f-a8ed-36b0aa5aeb8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061710943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3061710943
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1909259030
Short name T174
Test name
Test status
Simulation time 1794024141 ps
CPU time 21.46 seconds
Started Jul 01 11:24:10 AM PDT 24
Finished Jul 01 11:24:35 AM PDT 24
Peak memory 249272 kb
Host smart-17c07105-bd98-42f1-8031-c07fb8dc02bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19092
59030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1909259030
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2253140943
Short name T560
Test name
Test status
Simulation time 1544364459 ps
CPU time 69.13 seconds
Started Jul 01 11:24:04 AM PDT 24
Finished Jul 01 11:25:16 AM PDT 24
Peak memory 249496 kb
Host smart-ac9c82c2-89ed-43a0-bc0e-7471a72d0da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22531
40943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2253140943
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1418588449
Short name T12
Test name
Test status
Simulation time 865229574 ps
CPU time 22.67 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:24:41 AM PDT 24
Peak memory 278108 kb
Host smart-267f1ca2-2300-471a-b591-b6e2e98b9196
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1418588449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1418588449
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1481752
Short name T563
Test name
Test status
Simulation time 2954288320 ps
CPU time 33.07 seconds
Started Jul 01 11:24:05 AM PDT 24
Finished Jul 01 11:24:41 AM PDT 24
Peak memory 249392 kb
Host smart-e3d6dc34-6c52-4e2b-9c05-01f892910d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14817
52 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1481752
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.138077164
Short name T417
Test name
Test status
Simulation time 99839325 ps
CPU time 10.96 seconds
Started Jul 01 11:24:05 AM PDT 24
Finished Jul 01 11:24:19 AM PDT 24
Peak memory 257484 kb
Host smart-a1416754-27f0-47e8-903d-c05d77e257b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13807
7164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.138077164
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1698841271
Short name T261
Test name
Test status
Simulation time 87588972758 ps
CPU time 1663.67 seconds
Started Jul 01 11:24:04 AM PDT 24
Finished Jul 01 11:51:50 AM PDT 24
Peak memory 273992 kb
Host smart-e195de67-09ac-4374-958a-d59d62090ca1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698841271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1698841271
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3304878791
Short name T497
Test name
Test status
Simulation time 516059555389 ps
CPU time 2643.58 seconds
Started Jul 01 11:24:12 AM PDT 24
Finished Jul 01 12:08:20 PM PDT 24
Peak memory 288920 kb
Host smart-55f26c0b-ef2f-40ef-98fd-dceacb5e057e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304878791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3304878791
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2379419895
Short name T386
Test name
Test status
Simulation time 2362284648 ps
CPU time 130.09 seconds
Started Jul 01 11:24:03 AM PDT 24
Finished Jul 01 11:26:16 AM PDT 24
Peak memory 257208 kb
Host smart-f02a8940-6eac-4cb2-9ae8-2a2848b8fe0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23794
19895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2379419895
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.300153040
Short name T350
Test name
Test status
Simulation time 220284278 ps
CPU time 7.38 seconds
Started Jul 01 11:24:02 AM PDT 24
Finished Jul 01 11:24:13 AM PDT 24
Peak memory 248752 kb
Host smart-0db4605c-e0fd-42e9-b5c0-d074acf768c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30015
3040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.300153040
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.711280401
Short name T550
Test name
Test status
Simulation time 28980306468 ps
CPU time 1610.78 seconds
Started Jul 01 11:24:06 AM PDT 24
Finished Jul 01 11:51:00 AM PDT 24
Peak memory 273356 kb
Host smart-38b9a919-1eb9-45a5-8104-47da882f1b76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711280401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.711280401
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1569342556
Short name T376
Test name
Test status
Simulation time 37437125561 ps
CPU time 2389.18 seconds
Started Jul 01 11:24:02 AM PDT 24
Finished Jul 01 12:03:54 PM PDT 24
Peak memory 289464 kb
Host smart-20d1deb5-e942-4b71-9258-4855e8b7575e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569342556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1569342556
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1970407048
Short name T685
Test name
Test status
Simulation time 1524999290 ps
CPU time 12.37 seconds
Started Jul 01 11:24:25 AM PDT 24
Finished Jul 01 11:24:40 AM PDT 24
Peak memory 249300 kb
Host smart-f577f3db-90fb-4cf6-9d5a-3bd0a7b8fc96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19704
07048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1970407048
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3812322674
Short name T381
Test name
Test status
Simulation time 2865722653 ps
CPU time 31.38 seconds
Started Jul 01 11:24:06 AM PDT 24
Finished Jul 01 11:24:41 AM PDT 24
Peak memory 256936 kb
Host smart-4ceb8208-1305-4497-9856-66a004348daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38123
22674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3812322674
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2397089827
Short name T34
Test name
Test status
Simulation time 430657086 ps
CPU time 12.22 seconds
Started Jul 01 11:24:05 AM PDT 24
Finished Jul 01 11:24:20 AM PDT 24
Peak memory 267056 kb
Host smart-0a46f229-0378-4587-b294-3ec320cdf7ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2397089827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2397089827
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.674740184
Short name T96
Test name
Test status
Simulation time 2759584866 ps
CPU time 31.65 seconds
Started Jul 01 11:24:04 AM PDT 24
Finished Jul 01 11:24:38 AM PDT 24
Peak memory 256612 kb
Host smart-3925b079-2692-4859-a2bc-8d942e0004aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67474
0184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.674740184
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1234255203
Short name T396
Test name
Test status
Simulation time 751918576 ps
CPU time 40.76 seconds
Started Jul 01 11:24:06 AM PDT 24
Finished Jul 01 11:24:50 AM PDT 24
Peak memory 257280 kb
Host smart-0ce2aedf-94ea-4c4b-aeeb-0fcf2c6ea2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12342
55203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1234255203
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3521242274
Short name T508
Test name
Test status
Simulation time 6765553752 ps
CPU time 31.03 seconds
Started Jul 01 11:24:31 AM PDT 24
Finished Jul 01 11:25:04 AM PDT 24
Peak memory 249448 kb
Host smart-1daea89c-c6a7-49d7-8a51-19e2562a207e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3521242274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3521242274
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.370751196
Short name T385
Test name
Test status
Simulation time 4011882208 ps
CPU time 108.17 seconds
Started Jul 01 11:24:30 AM PDT 24
Finished Jul 01 11:26:19 AM PDT 24
Peak memory 257616 kb
Host smart-bb1bf2cc-61c0-472e-99d4-a83fa25674b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37075
1196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.370751196
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.445007892
Short name T672
Test name
Test status
Simulation time 1051492941 ps
CPU time 23.43 seconds
Started Jul 01 11:24:31 AM PDT 24
Finished Jul 01 11:24:56 AM PDT 24
Peak memory 257500 kb
Host smart-985200de-c46e-4b27-aa1f-ec764cf697bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44500
7892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.445007892
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.975546583
Short name T322
Test name
Test status
Simulation time 27828452153 ps
CPU time 1798.35 seconds
Started Jul 01 11:24:24 AM PDT 24
Finished Jul 01 11:54:25 AM PDT 24
Peak memory 282552 kb
Host smart-22ede2c0-9a22-4cce-bf64-8c5672e49c38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975546583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.975546583
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1851339300
Short name T248
Test name
Test status
Simulation time 78477358663 ps
CPU time 2242.65 seconds
Started Jul 01 11:24:33 AM PDT 24
Finished Jul 01 12:01:58 PM PDT 24
Peak memory 273892 kb
Host smart-454d23ad-018b-465f-9dd7-489bdcbe0d02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851339300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1851339300
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3484397642
Short name T620
Test name
Test status
Simulation time 11984404557 ps
CPU time 488.74 seconds
Started Jul 01 11:24:43 AM PDT 24
Finished Jul 01 11:32:53 AM PDT 24
Peak memory 249404 kb
Host smart-3c5c0572-76f1-4fbb-a595-aaf3c9d14b96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484397642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3484397642
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3768844281
Short name T349
Test name
Test status
Simulation time 152063447 ps
CPU time 10.94 seconds
Started Jul 01 11:24:33 AM PDT 24
Finished Jul 01 11:24:46 AM PDT 24
Peak memory 256740 kb
Host smart-3e87ee3a-67ce-4573-9d0a-a90fd797f9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37688
44281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3768844281
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3649657092
Short name T696
Test name
Test status
Simulation time 522294017 ps
CPU time 34.65 seconds
Started Jul 01 11:24:44 AM PDT 24
Finished Jul 01 11:25:20 AM PDT 24
Peak memory 256624 kb
Host smart-bbf82b8b-6f35-42a4-a08c-1e7b0b36939b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36496
57092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3649657092
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3460358288
Short name T244
Test name
Test status
Simulation time 469804701 ps
CPU time 25.81 seconds
Started Jul 01 11:24:23 AM PDT 24
Finished Jul 01 11:24:51 AM PDT 24
Peak memory 256424 kb
Host smart-c4c34ec1-0d03-4172-8ae1-848ae168e55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34603
58288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3460358288
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.4253861225
Short name T342
Test name
Test status
Simulation time 753437069 ps
CPU time 51.91 seconds
Started Jul 01 11:24:28 AM PDT 24
Finished Jul 01 11:25:21 AM PDT 24
Peak memory 257456 kb
Host smart-d80fa80e-9608-4aa1-af60-afb95ea86503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42538
61225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.4253861225
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2790255811
Short name T45
Test name
Test status
Simulation time 73063346 ps
CPU time 2.72 seconds
Started Jul 01 11:24:36 AM PDT 24
Finished Jul 01 11:24:41 AM PDT 24
Peak memory 249512 kb
Host smart-2a8cb623-2612-4848-9876-adc2d99ce980
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2790255811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2790255811
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3189310691
Short name T495
Test name
Test status
Simulation time 5693901367 ps
CPU time 35.52 seconds
Started Jul 01 11:24:28 AM PDT 24
Finished Jul 01 11:25:05 AM PDT 24
Peak memory 249336 kb
Host smart-36486eaf-5050-47e6-a7db-2ab5947dac76
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3189310691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3189310691
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2843771496
Short name T474
Test name
Test status
Simulation time 1054150311 ps
CPU time 86.53 seconds
Started Jul 01 11:24:39 AM PDT 24
Finished Jul 01 11:26:08 AM PDT 24
Peak memory 257504 kb
Host smart-8ad12a5f-8616-4544-81ff-326a3e3efc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28437
71496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2843771496
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2667196552
Short name T546
Test name
Test status
Simulation time 655151568 ps
CPU time 15.86 seconds
Started Jul 01 11:24:29 AM PDT 24
Finished Jul 01 11:24:46 AM PDT 24
Peak memory 249744 kb
Host smart-390d8c52-a10f-49a4-99b9-d55c1bda3f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26671
96552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2667196552
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1777867115
Short name T518
Test name
Test status
Simulation time 31744085798 ps
CPU time 1525.2 seconds
Started Jul 01 11:24:44 AM PDT 24
Finished Jul 01 11:50:11 AM PDT 24
Peak memory 290248 kb
Host smart-0eb376f2-91d7-4ddc-a8ac-4d855ce694d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777867115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1777867115
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.12277349
Short name T484
Test name
Test status
Simulation time 35296174005 ps
CPU time 814.9 seconds
Started Jul 01 11:24:41 AM PDT 24
Finished Jul 01 11:38:17 AM PDT 24
Peak memory 273780 kb
Host smart-9880df9c-9bba-4deb-a7ff-725197e1b25a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12277349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.12277349
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2022161998
Short name T482
Test name
Test status
Simulation time 1083375549 ps
CPU time 13.57 seconds
Started Jul 01 11:24:24 AM PDT 24
Finished Jul 01 11:24:40 AM PDT 24
Peak memory 249292 kb
Host smart-000930d3-9c2d-4c76-ab45-5c9977540866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20221
61998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2022161998
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.4237082213
Short name T416
Test name
Test status
Simulation time 3845400176 ps
CPU time 39.93 seconds
Started Jul 01 11:24:39 AM PDT 24
Finished Jul 01 11:25:21 AM PDT 24
Peak memory 248944 kb
Host smart-1e202c68-e8ad-44d3-80c5-ce95a935ea7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42370
82213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.4237082213
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1137696174
Short name T567
Test name
Test status
Simulation time 248556259 ps
CPU time 28.95 seconds
Started Jul 01 11:24:33 AM PDT 24
Finished Jul 01 11:25:04 AM PDT 24
Peak memory 248968 kb
Host smart-bab91f57-83ee-4198-8fea-ac0d031e8c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11376
96174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1137696174
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3438292292
Short name T604
Test name
Test status
Simulation time 907106364 ps
CPU time 21.44 seconds
Started Jul 01 11:24:25 AM PDT 24
Finished Jul 01 11:24:49 AM PDT 24
Peak memory 249520 kb
Host smart-23713965-6132-4387-9719-bcf025e6d532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34382
92292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3438292292
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3815988495
Short name T478
Test name
Test status
Simulation time 61335737065 ps
CPU time 3391.83 seconds
Started Jul 01 11:24:28 AM PDT 24
Finished Jul 01 12:21:01 PM PDT 24
Peak memory 301144 kb
Host smart-3bbb4fb8-5df3-438e-97fa-20a6a68c4c2f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815988495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3815988495
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1048773421
Short name T86
Test name
Test status
Simulation time 1641782692636 ps
CPU time 9111.5 seconds
Started Jul 01 11:24:47 AM PDT 24
Finished Jul 01 01:56:41 PM PDT 24
Peak memory 355756 kb
Host smart-c104c674-5d06-46a4-8a63-0498e103e15b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048773421 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1048773421
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.278667925
Short name T65
Test name
Test status
Simulation time 12608172 ps
CPU time 2.51 seconds
Started Jul 01 11:24:32 AM PDT 24
Finished Jul 01 11:24:37 AM PDT 24
Peak memory 249512 kb
Host smart-f17e803f-a244-47c7-8633-fe6291c997a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=278667925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.278667925
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1163016143
Short name T5
Test name
Test status
Simulation time 6789366050 ps
CPU time 679.15 seconds
Started Jul 01 11:24:49 AM PDT 24
Finished Jul 01 11:36:10 AM PDT 24
Peak memory 273984 kb
Host smart-e7893960-2431-4c4f-bf46-32d6671569a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163016143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1163016143
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2873631181
Short name T537
Test name
Test status
Simulation time 798298612 ps
CPU time 10.35 seconds
Started Jul 01 11:24:50 AM PDT 24
Finished Jul 01 11:25:02 AM PDT 24
Peak memory 249232 kb
Host smart-54d2fedd-2dc0-47d9-b454-5c8085fa04a7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2873631181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2873631181
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2528248212
Short name T521
Test name
Test status
Simulation time 1262157359 ps
CPU time 112.74 seconds
Started Jul 01 11:24:29 AM PDT 24
Finished Jul 01 11:26:23 AM PDT 24
Peak memory 256872 kb
Host smart-f5eb3e1b-acb2-44bc-be8a-a3e736d2b01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25282
48212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2528248212
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1194043169
Short name T425
Test name
Test status
Simulation time 453138091 ps
CPU time 8 seconds
Started Jul 01 11:24:46 AM PDT 24
Finished Jul 01 11:24:55 AM PDT 24
Peak memory 249256 kb
Host smart-cb0ce7ba-9897-47ed-9401-b395a418a07e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11940
43169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1194043169
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3175536720
Short name T528
Test name
Test status
Simulation time 87527649858 ps
CPU time 1210.52 seconds
Started Jul 01 11:24:36 AM PDT 24
Finished Jul 01 11:44:48 AM PDT 24
Peak memory 266828 kb
Host smart-c8e2f748-7fb3-412b-b46e-5a468c93cb04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175536720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3175536720
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1893384481
Short name T646
Test name
Test status
Simulation time 660468853 ps
CPU time 10.87 seconds
Started Jul 01 11:24:30 AM PDT 24
Finished Jul 01 11:24:42 AM PDT 24
Peak memory 257124 kb
Host smart-91d8f8ac-2186-4af1-b53b-ce0561649432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18933
84481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1893384481
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.204560299
Short name T553
Test name
Test status
Simulation time 2672028932 ps
CPU time 11.28 seconds
Started Jul 01 11:24:48 AM PDT 24
Finished Jul 01 11:25:01 AM PDT 24
Peak memory 253184 kb
Host smart-7f372a85-db99-4739-b4e7-8456ee12bb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20456
0299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.204560299
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.249986760
Short name T107
Test name
Test status
Simulation time 370385825 ps
CPU time 4.93 seconds
Started Jul 01 11:24:31 AM PDT 24
Finished Jul 01 11:24:38 AM PDT 24
Peak memory 240444 kb
Host smart-eca48d96-6259-4f6b-be20-de6a1df28cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24998
6760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.249986760
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2171769588
Short name T340
Test name
Test status
Simulation time 523823183 ps
CPU time 13.06 seconds
Started Jul 01 11:24:46 AM PDT 24
Finished Jul 01 11:25:00 AM PDT 24
Peak memory 255832 kb
Host smart-d4dd1220-9acc-4f5f-8844-5a49fc26a53b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21717
69588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2171769588
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.539411284
Short name T202
Test name
Test status
Simulation time 48182775 ps
CPU time 2.64 seconds
Started Jul 01 11:24:47 AM PDT 24
Finished Jul 01 11:24:51 AM PDT 24
Peak memory 249500 kb
Host smart-293d68e1-796d-4525-a1ed-a0ebb1e5d1f7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=539411284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.539411284
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.126236104
Short name T698
Test name
Test status
Simulation time 52546625989 ps
CPU time 1188.25 seconds
Started Jul 01 11:24:28 AM PDT 24
Finished Jul 01 11:44:18 AM PDT 24
Peak memory 290524 kb
Host smart-093c0544-d856-4b63-adaa-959787b56f9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126236104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.126236104
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3163783820
Short name T610
Test name
Test status
Simulation time 878478299 ps
CPU time 8.3 seconds
Started Jul 01 11:24:32 AM PDT 24
Finished Jul 01 11:24:43 AM PDT 24
Peak memory 249308 kb
Host smart-db5e8cc4-0aef-4f60-8e6d-deefb23dbb3b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3163783820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3163783820
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3327924006
Short name T348
Test name
Test status
Simulation time 126231819 ps
CPU time 15.32 seconds
Started Jul 01 11:24:31 AM PDT 24
Finished Jul 01 11:24:49 AM PDT 24
Peak memory 256980 kb
Host smart-4a38c5af-c510-437e-954a-c5a70c7a6f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33279
24006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3327924006
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.533991273
Short name T585
Test name
Test status
Simulation time 1704554881 ps
CPU time 31.32 seconds
Started Jul 01 11:24:31 AM PDT 24
Finished Jul 01 11:25:04 AM PDT 24
Peak memory 248948 kb
Host smart-37ae3999-d7ac-4685-a456-495e4ad2e610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53399
1273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.533991273
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3118084796
Short name T318
Test name
Test status
Simulation time 39631449006 ps
CPU time 1386.04 seconds
Started Jul 01 11:24:53 AM PDT 24
Finished Jul 01 11:48:02 AM PDT 24
Peak memory 273240 kb
Host smart-c46ccfe6-b2b8-4d6e-9c76-d632f679606b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118084796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3118084796
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2670687104
Short name T603
Test name
Test status
Simulation time 157428721274 ps
CPU time 1942.35 seconds
Started Jul 01 11:24:32 AM PDT 24
Finished Jul 01 11:56:57 AM PDT 24
Peak memory 285804 kb
Host smart-616307f4-758e-4271-806d-0a32d09a414f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670687104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2670687104
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1365348707
Short name T694
Test name
Test status
Simulation time 534415894 ps
CPU time 29.59 seconds
Started Jul 01 11:24:44 AM PDT 24
Finished Jul 01 11:25:15 AM PDT 24
Peak memory 257596 kb
Host smart-8f314958-5346-4dc0-90ff-701129194fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13653
48707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1365348707
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2553729684
Short name T702
Test name
Test status
Simulation time 616578369 ps
CPU time 10.97 seconds
Started Jul 01 11:24:49 AM PDT 24
Finished Jul 01 11:25:02 AM PDT 24
Peak memory 255160 kb
Host smart-5e31fbfd-ca6f-4866-97b4-e76b86cefef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25537
29684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2553729684
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1643560468
Short name T59
Test name
Test status
Simulation time 942120649 ps
CPU time 26.93 seconds
Started Jul 01 11:24:31 AM PDT 24
Finished Jul 01 11:25:01 AM PDT 24
Peak memory 249312 kb
Host smart-79359a6a-e789-4b53-bdef-ba9681e97aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16435
60468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1643560468
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.619603133
Short name T430
Test name
Test status
Simulation time 1319521676 ps
CPU time 52.48 seconds
Started Jul 01 11:24:49 AM PDT 24
Finished Jul 01 11:25:44 AM PDT 24
Peak memory 249264 kb
Host smart-e729bef7-99c6-454f-97b3-d40401653f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61960
3133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.619603133
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2175880745
Short name T640
Test name
Test status
Simulation time 17600067816 ps
CPU time 1663.17 seconds
Started Jul 01 11:24:51 AM PDT 24
Finished Jul 01 11:52:36 AM PDT 24
Peak memory 290396 kb
Host smart-f3f89437-2ec9-4add-93e1-f421de3aeb47
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175880745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2175880745
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3302082095
Short name T223
Test name
Test status
Simulation time 70076462411 ps
CPU time 1056.16 seconds
Started Jul 01 11:24:37 AM PDT 24
Finished Jul 01 11:42:16 AM PDT 24
Peak memory 282288 kb
Host smart-4cf3dea3-5a8e-4e85-bc03-93c5e32f8e7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302082095 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3302082095
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1983581547
Short name T201
Test name
Test status
Simulation time 22279841 ps
CPU time 2.25 seconds
Started Jul 01 11:24:51 AM PDT 24
Finished Jul 01 11:24:55 AM PDT 24
Peak memory 249572 kb
Host smart-8cfd2f2f-de1a-49d4-bc39-4792fa0c7817
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1983581547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1983581547
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1311669413
Short name T543
Test name
Test status
Simulation time 27546297487 ps
CPU time 1817.16 seconds
Started Jul 01 11:24:53 AM PDT 24
Finished Jul 01 11:55:13 AM PDT 24
Peak memory 273840 kb
Host smart-2fba71f7-d6ba-4f2a-a34f-c68de1fd1561
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311669413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1311669413
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1559401416
Short name T480
Test name
Test status
Simulation time 559214258 ps
CPU time 9.54 seconds
Started Jul 01 11:24:32 AM PDT 24
Finished Jul 01 11:24:44 AM PDT 24
Peak memory 249296 kb
Host smart-9ad6395e-424c-45c5-bfb1-1b168f1159b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1559401416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1559401416
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.144830464
Short name T438
Test name
Test status
Simulation time 495682330 ps
CPU time 14.29 seconds
Started Jul 01 11:24:49 AM PDT 24
Finished Jul 01 11:25:06 AM PDT 24
Peak memory 255664 kb
Host smart-0c8d2a1d-0f12-40f3-8d8d-2559b4af0d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14483
0464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.144830464
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2706288243
Short name T556
Test name
Test status
Simulation time 306780154 ps
CPU time 21.8 seconds
Started Jul 01 11:24:36 AM PDT 24
Finished Jul 01 11:25:00 AM PDT 24
Peak memory 256904 kb
Host smart-ea1e6eb8-ea23-4c3b-9ecf-8f218139318a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27062
88243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2706288243
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1199672949
Short name T325
Test name
Test status
Simulation time 116021315245 ps
CPU time 1338.09 seconds
Started Jul 01 11:24:53 AM PDT 24
Finished Jul 01 11:47:14 AM PDT 24
Peak memory 288136 kb
Host smart-3deeffbd-89ef-4297-8d6d-6614a935a644
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199672949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1199672949
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2924711465
Short name T566
Test name
Test status
Simulation time 45499412251 ps
CPU time 2563.34 seconds
Started Jul 01 11:24:33 AM PDT 24
Finished Jul 01 12:07:19 PM PDT 24
Peak memory 289768 kb
Host smart-b7500e68-9dc4-4a3c-b3c9-754578eb687f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924711465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2924711465
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3091322457
Short name T587
Test name
Test status
Simulation time 5085380716 ps
CPU time 193.35 seconds
Started Jul 01 11:24:37 AM PDT 24
Finished Jul 01 11:27:52 AM PDT 24
Peak memory 249424 kb
Host smart-cdc2c37b-c7eb-41b8-a4de-aec1c897b6ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091322457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3091322457
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1125784445
Short name T420
Test name
Test status
Simulation time 1793414391 ps
CPU time 47.39 seconds
Started Jul 01 11:24:47 AM PDT 24
Finished Jul 01 11:25:35 AM PDT 24
Peak memory 256640 kb
Host smart-7cddeec6-ec4a-4637-8d5e-267af6cd12f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11257
84445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1125784445
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3599508385
Short name T412
Test name
Test status
Simulation time 10351241947 ps
CPU time 40.2 seconds
Started Jul 01 11:24:34 AM PDT 24
Finished Jul 01 11:25:17 AM PDT 24
Peak memory 257216 kb
Host smart-e83ac9b0-6d26-4f44-8e2f-3d66859ba087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35995
08385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3599508385
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.977626381
Short name T616
Test name
Test status
Simulation time 161978328 ps
CPU time 7.01 seconds
Started Jul 01 11:24:54 AM PDT 24
Finished Jul 01 11:25:04 AM PDT 24
Peak memory 249240 kb
Host smart-de77ce6d-0fa1-4248-b1c2-69875a198e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97762
6381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.977626381
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1143382785
Short name T641
Test name
Test status
Simulation time 72221456304 ps
CPU time 2183.16 seconds
Started Jul 01 11:24:42 AM PDT 24
Finished Jul 01 12:01:07 PM PDT 24
Peak memory 289456 kb
Host smart-476dc730-77a9-405f-aab8-38eb47d204ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143382785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1143382785
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3677254261
Short name T18
Test name
Test status
Simulation time 74369539 ps
CPU time 2.99 seconds
Started Jul 01 11:24:38 AM PDT 24
Finished Jul 01 11:24:43 AM PDT 24
Peak memory 249608 kb
Host smart-ee8ac371-0cad-4f62-9f89-5980bbca204c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3677254261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3677254261
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3989203106
Short name T435
Test name
Test status
Simulation time 38129632742 ps
CPU time 1200.43 seconds
Started Jul 01 11:24:38 AM PDT 24
Finished Jul 01 11:44:41 AM PDT 24
Peak memory 273792 kb
Host smart-eef37bbb-88a3-4c19-b083-6a49e6b2f5a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989203106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3989203106
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2897940327
Short name T693
Test name
Test status
Simulation time 182274257 ps
CPU time 10.37 seconds
Started Jul 01 11:24:51 AM PDT 24
Finished Jul 01 11:25:03 AM PDT 24
Peak memory 249296 kb
Host smart-5cf40925-61ea-4512-95ca-e48439977f28
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2897940327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2897940327
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2660306392
Short name T370
Test name
Test status
Simulation time 15527815689 ps
CPU time 317.73 seconds
Started Jul 01 11:24:54 AM PDT 24
Finished Jul 01 11:30:15 AM PDT 24
Peak memory 257068 kb
Host smart-f36a4f22-0f78-4447-8399-70d4196ee8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26603
06392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2660306392
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.684533964
Short name T555
Test name
Test status
Simulation time 30242377 ps
CPU time 4.52 seconds
Started Jul 01 11:24:36 AM PDT 24
Finished Jul 01 11:24:42 AM PDT 24
Peak memory 252180 kb
Host smart-d122c896-91d6-455f-a214-fd8be052a81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68453
3964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.684533964
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1642224313
Short name T296
Test name
Test status
Simulation time 290335730809 ps
CPU time 3109.65 seconds
Started Jul 01 11:24:51 AM PDT 24
Finished Jul 01 12:16:43 PM PDT 24
Peak memory 290188 kb
Host smart-c92f4475-477c-4a60-bc90-d02b4712ff16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642224313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1642224313
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2862123891
Short name T551
Test name
Test status
Simulation time 142177513119 ps
CPU time 1473.44 seconds
Started Jul 01 11:24:44 AM PDT 24
Finished Jul 01 11:49:19 AM PDT 24
Peak memory 289272 kb
Host smart-d4ee9477-29df-45ae-94a8-57f80398260c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862123891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2862123891
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2422073417
Short name T288
Test name
Test status
Simulation time 48781131952 ps
CPU time 492.77 seconds
Started Jul 01 11:24:48 AM PDT 24
Finished Jul 01 11:33:03 AM PDT 24
Peak memory 249404 kb
Host smart-ba939daa-6098-4b99-97a9-ec24d6690f48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422073417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2422073417
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1501645513
Short name T475
Test name
Test status
Simulation time 4926127616 ps
CPU time 75.44 seconds
Started Jul 01 11:24:39 AM PDT 24
Finished Jul 01 11:25:56 AM PDT 24
Peak memory 257016 kb
Host smart-fa6fd3a9-08fa-432b-afb3-1297241b508e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15016
45513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1501645513
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3756568087
Short name T458
Test name
Test status
Simulation time 440888752 ps
CPU time 24.47 seconds
Started Jul 01 11:24:38 AM PDT 24
Finished Jul 01 11:25:04 AM PDT 24
Peak memory 256872 kb
Host smart-1e622fdf-49ad-415d-b365-da3112899efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37565
68087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3756568087
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.428996039
Short name T683
Test name
Test status
Simulation time 3596644432 ps
CPU time 21.24 seconds
Started Jul 01 11:24:37 AM PDT 24
Finished Jul 01 11:24:59 AM PDT 24
Peak memory 249400 kb
Host smart-f712cc99-5095-4e9c-b304-a52f61d09984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42899
6039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.428996039
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2042441829
Short name T194
Test name
Test status
Simulation time 113360349 ps
CPU time 2.72 seconds
Started Jul 01 11:24:48 AM PDT 24
Finished Jul 01 11:24:52 AM PDT 24
Peak memory 249444 kb
Host smart-108924d4-1d59-4480-aead-5bb1743f5d52
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2042441829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2042441829
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3334540065
Short name T87
Test name
Test status
Simulation time 18293125737 ps
CPU time 1200.97 seconds
Started Jul 01 11:24:48 AM PDT 24
Finished Jul 01 11:44:51 AM PDT 24
Peak memory 273800 kb
Host smart-18fc8f69-e268-46fc-a55b-808d2ba3d871
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334540065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3334540065
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1438094691
Short name T16
Test name
Test status
Simulation time 527660358 ps
CPU time 14.48 seconds
Started Jul 01 11:24:54 AM PDT 24
Finished Jul 01 11:25:12 AM PDT 24
Peak memory 249244 kb
Host smart-3ca0f6c2-dc84-4943-a20f-4ecc5a9fb915
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1438094691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1438094691
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.4066965575
Short name T66
Test name
Test status
Simulation time 1938605794 ps
CPU time 41.71 seconds
Started Jul 01 11:24:38 AM PDT 24
Finished Jul 01 11:25:21 AM PDT 24
Peak memory 257360 kb
Host smart-a23e95de-16ec-4b5d-8892-d69074d8924f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40669
65575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.4066965575
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2319125311
Short name T71
Test name
Test status
Simulation time 4373892154 ps
CPU time 51.59 seconds
Started Jul 01 11:24:37 AM PDT 24
Finished Jul 01 11:25:30 AM PDT 24
Peak memory 249392 kb
Host smart-cdbcbc8b-b704-4936-8c13-0a62aef24a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23191
25311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2319125311
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.828283041
Short name T488
Test name
Test status
Simulation time 32729869308 ps
CPU time 2091.2 seconds
Started Jul 01 11:24:48 AM PDT 24
Finished Jul 01 11:59:41 AM PDT 24
Peak memory 290056 kb
Host smart-88acea23-ec5a-48e6-b502-2c515a6feee7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828283041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.828283041
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1018380058
Short name T464
Test name
Test status
Simulation time 37150656040 ps
CPU time 116.44 seconds
Started Jul 01 11:24:40 AM PDT 24
Finished Jul 01 11:26:38 AM PDT 24
Peak memory 248952 kb
Host smart-5f8ef1a3-9c14-40c2-a68f-92bb4ef5332b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018380058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1018380058
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1450979732
Short name T462
Test name
Test status
Simulation time 675546747 ps
CPU time 31.44 seconds
Started Jul 01 11:24:37 AM PDT 24
Finished Jul 01 11:25:10 AM PDT 24
Peak memory 256788 kb
Host smart-3b472b33-9e5f-4989-a273-56240dfe5c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14509
79732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1450979732
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3580858697
Short name T431
Test name
Test status
Simulation time 441512335 ps
CPU time 11.43 seconds
Started Jul 01 11:24:37 AM PDT 24
Finished Jul 01 11:24:51 AM PDT 24
Peak memory 256948 kb
Host smart-72b18a42-ce88-45d9-9bf6-7f3c96fc2927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35808
58697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3580858697
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1197910327
Short name T562
Test name
Test status
Simulation time 516376484 ps
CPU time 38.49 seconds
Started Jul 01 11:24:48 AM PDT 24
Finished Jul 01 11:25:28 AM PDT 24
Peak memory 257288 kb
Host smart-3c7dc8e7-9338-4a0b-bb2f-ccd718c680c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11979
10327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1197910327
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.421004412
Short name T43
Test name
Test status
Simulation time 4387454711 ps
CPU time 172.04 seconds
Started Jul 01 11:24:38 AM PDT 24
Finished Jul 01 11:27:32 AM PDT 24
Peak memory 257520 kb
Host smart-8a8ba15e-9b81-44cb-8baf-3f7a6a871daa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421004412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.421004412
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.302717445
Short name T209
Test name
Test status
Simulation time 181081263 ps
CPU time 4.2 seconds
Started Jul 01 11:24:43 AM PDT 24
Finished Jul 01 11:24:49 AM PDT 24
Peak memory 249536 kb
Host smart-d8ffd26c-7d6f-4a72-8d26-ae2d3a0180ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=302717445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.302717445
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1390067714
Short name T427
Test name
Test status
Simulation time 78983174244 ps
CPU time 2615.86 seconds
Started Jul 01 11:24:53 AM PDT 24
Finished Jul 01 12:08:31 PM PDT 24
Peak memory 290044 kb
Host smart-34b8d19d-83e3-45c7-a86a-6c0f01ddc6a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390067714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1390067714
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1906042162
Short name T669
Test name
Test status
Simulation time 1045564133 ps
CPU time 13.87 seconds
Started Jul 01 11:24:43 AM PDT 24
Finished Jul 01 11:24:59 AM PDT 24
Peak memory 249080 kb
Host smart-04633b2e-f3d0-4b80-a4f7-abc7224f0087
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1906042162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1906042162
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1087431603
Short name T389
Test name
Test status
Simulation time 1119785529 ps
CPU time 17.52 seconds
Started Jul 01 11:24:40 AM PDT 24
Finished Jul 01 11:24:59 AM PDT 24
Peak memory 255456 kb
Host smart-74731c97-2236-4445-8490-0ac15b2092be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10874
31603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1087431603
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.768231907
Short name T3
Test name
Test status
Simulation time 330937867 ps
CPU time 20.78 seconds
Started Jul 01 11:24:40 AM PDT 24
Finished Jul 01 11:25:02 AM PDT 24
Peak memory 249232 kb
Host smart-ee97cfc0-6aad-4b39-baac-d5834a029e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76823
1907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.768231907
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3805210313
Short name T679
Test name
Test status
Simulation time 260348850049 ps
CPU time 1612.08 seconds
Started Jul 01 11:24:53 AM PDT 24
Finished Jul 01 11:51:48 AM PDT 24
Peak memory 273192 kb
Host smart-f0786869-0561-46a3-a76a-fd0ce1e7e644
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805210313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3805210313
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3474636830
Short name T512
Test name
Test status
Simulation time 310179909423 ps
CPU time 2329.4 seconds
Started Jul 01 11:25:00 AM PDT 24
Finished Jul 01 12:03:55 PM PDT 24
Peak memory 289500 kb
Host smart-1c80fa06-855a-405a-a605-93443a4200e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474636830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3474636830
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1095909366
Short name T298
Test name
Test status
Simulation time 6954982070 ps
CPU time 134.79 seconds
Started Jul 01 11:24:42 AM PDT 24
Finished Jul 01 11:26:58 AM PDT 24
Peak memory 249408 kb
Host smart-f51586b5-cef8-4b4a-8e64-9be1cb831703
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095909366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1095909366
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3607259817
Short name T402
Test name
Test status
Simulation time 1713807387 ps
CPU time 21.39 seconds
Started Jul 01 11:24:42 AM PDT 24
Finished Jul 01 11:25:05 AM PDT 24
Peak memory 256752 kb
Host smart-0f4d0109-24db-48a8-b050-ef0ea55af65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36072
59817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3607259817
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3206440797
Short name T393
Test name
Test status
Simulation time 2980517317 ps
CPU time 53.13 seconds
Started Jul 01 11:24:47 AM PDT 24
Finished Jul 01 11:25:42 AM PDT 24
Peak memory 256792 kb
Host smart-e38f84db-2bba-4844-bee5-6d87f8d2172e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32064
40797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3206440797
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2726348390
Short name T663
Test name
Test status
Simulation time 864494692 ps
CPU time 25.65 seconds
Started Jul 01 11:24:38 AM PDT 24
Finished Jul 01 11:25:06 AM PDT 24
Peak memory 248924 kb
Host smart-77506c12-4369-4066-b29c-f6925597e0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27263
48390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2726348390
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3546834428
Short name T2
Test name
Test status
Simulation time 373353373 ps
CPU time 18.76 seconds
Started Jul 01 11:24:38 AM PDT 24
Finished Jul 01 11:24:59 AM PDT 24
Peak memory 257320 kb
Host smart-32b42eff-fe5f-4ffd-bf11-2e4e710e05ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35468
34428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3546834428
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2977614587
Short name T101
Test name
Test status
Simulation time 17295104546 ps
CPU time 1679.58 seconds
Started Jul 01 11:24:54 AM PDT 24
Finished Jul 01 11:52:58 AM PDT 24
Peak memory 290144 kb
Host smart-8abd9306-42b6-48ff-95a2-bd2ad670b33c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977614587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2977614587
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2285769663
Short name T199
Test name
Test status
Simulation time 177017100 ps
CPU time 3.48 seconds
Started Jul 01 11:24:47 AM PDT 24
Finished Jul 01 11:24:52 AM PDT 24
Peak memory 249488 kb
Host smart-99143fd2-06a0-4da3-ba62-410d433967fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2285769663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2285769663
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3974054042
Short name T171
Test name
Test status
Simulation time 22267014781 ps
CPU time 1264.78 seconds
Started Jul 01 11:24:46 AM PDT 24
Finished Jul 01 11:45:52 AM PDT 24
Peak memory 268876 kb
Host smart-bae43cee-9ebc-4ff8-8e6c-421c31e83d00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974054042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3974054042
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2169223314
Short name T403
Test name
Test status
Simulation time 224124272 ps
CPU time 7.96 seconds
Started Jul 01 11:24:44 AM PDT 24
Finished Jul 01 11:24:53 AM PDT 24
Peak memory 249272 kb
Host smart-bafbe86c-6cb9-4f9e-a80c-691167c2b327
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2169223314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2169223314
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1474709167
Short name T409
Test name
Test status
Simulation time 3625392902 ps
CPU time 62.78 seconds
Started Jul 01 11:24:57 AM PDT 24
Finished Jul 01 11:26:04 AM PDT 24
Peak memory 256924 kb
Host smart-d830a45b-fb08-436a-87dc-4c9e1ffa5491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14747
09167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1474709167
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1887858263
Short name T630
Test name
Test status
Simulation time 1728551472 ps
CPU time 24.61 seconds
Started Jul 01 11:24:55 AM PDT 24
Finished Jul 01 11:25:23 AM PDT 24
Peak memory 256972 kb
Host smart-5cc482a5-100a-4f6b-8df2-268e67c72678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18878
58263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1887858263
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1034531735
Short name T40
Test name
Test status
Simulation time 86254895945 ps
CPU time 2655.52 seconds
Started Jul 01 11:24:55 AM PDT 24
Finished Jul 01 12:09:14 PM PDT 24
Peak memory 290256 kb
Host smart-db032562-fa01-43f4-b943-bd4629cc568f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034531735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1034531735
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.4197883864
Short name T93
Test name
Test status
Simulation time 52340227485 ps
CPU time 988.92 seconds
Started Jul 01 11:25:00 AM PDT 24
Finished Jul 01 11:41:34 AM PDT 24
Peak memory 288540 kb
Host smart-6990e06d-a75d-42a0-9c2a-9a4e291020b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197883864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.4197883864
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2612411144
Short name T284
Test name
Test status
Simulation time 12244945735 ps
CPU time 261.78 seconds
Started Jul 01 11:24:48 AM PDT 24
Finished Jul 01 11:29:12 AM PDT 24
Peak memory 249384 kb
Host smart-7d8080b5-483a-4a2f-8412-dd62a8f3e5b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612411144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2612411144
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2474980541
Short name T479
Test name
Test status
Simulation time 687361669 ps
CPU time 15.17 seconds
Started Jul 01 11:24:44 AM PDT 24
Finished Jul 01 11:25:01 AM PDT 24
Peak memory 249312 kb
Host smart-b4e2a649-4f01-4d54-bbf9-5797fc2fee2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24749
80541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2474980541
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.116810819
Short name T473
Test name
Test status
Simulation time 1415537100 ps
CPU time 20.38 seconds
Started Jul 01 11:24:53 AM PDT 24
Finished Jul 01 11:25:17 AM PDT 24
Peak memory 256624 kb
Host smart-c4f088c4-5b3b-470b-98b3-8c1f1c783783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11681
0819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.116810819
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.491568213
Short name T465
Test name
Test status
Simulation time 3114067893 ps
CPU time 32.43 seconds
Started Jul 01 11:24:43 AM PDT 24
Finished Jul 01 11:25:17 AM PDT 24
Peak memory 257140 kb
Host smart-08234441-d473-4c75-9dfa-9449e8a8313b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49156
8213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.491568213
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.41134935
Short name T597
Test name
Test status
Simulation time 1109016222 ps
CPU time 11.23 seconds
Started Jul 01 11:24:55 AM PDT 24
Finished Jul 01 11:25:10 AM PDT 24
Peak memory 249268 kb
Host smart-850e4e50-25f2-4563-b2f6-721dedacae84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41134
935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.41134935
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.378926441
Short name T176
Test name
Test status
Simulation time 2166325014 ps
CPU time 139.05 seconds
Started Jul 01 11:24:46 AM PDT 24
Finished Jul 01 11:27:06 AM PDT 24
Peak memory 257560 kb
Host smart-669eb9dd-263d-4dbb-b042-4e65623bebc9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378926441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.378926441
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1722814984
Short name T568
Test name
Test status
Simulation time 5860278513 ps
CPU time 629.3 seconds
Started Jul 01 11:24:54 AM PDT 24
Finished Jul 01 11:35:27 AM PDT 24
Peak memory 273704 kb
Host smart-5bec86aa-d77d-483e-9650-5d904245749a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722814984 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1722814984
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3533507423
Short name T205
Test name
Test status
Simulation time 383254905 ps
CPU time 3.21 seconds
Started Jul 01 11:24:52 AM PDT 24
Finished Jul 01 11:24:57 AM PDT 24
Peak memory 249564 kb
Host smart-65984a08-2263-416f-9906-c73001b2ec51
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3533507423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3533507423
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3630739117
Short name T594
Test name
Test status
Simulation time 157865599 ps
CPU time 9.65 seconds
Started Jul 01 11:24:49 AM PDT 24
Finished Jul 01 11:25:01 AM PDT 24
Peak memory 249272 kb
Host smart-f06a48b1-8b69-4ec9-adfa-cb665f66aa74
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3630739117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3630739117
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2886548379
Short name T554
Test name
Test status
Simulation time 3951027165 ps
CPU time 107.12 seconds
Started Jul 01 11:24:49 AM PDT 24
Finished Jul 01 11:26:38 AM PDT 24
Peak memory 257072 kb
Host smart-a4c81119-35e2-4719-9274-fb1657b8dbe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28865
48379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2886548379
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.150044753
Short name T21
Test name
Test status
Simulation time 447229431 ps
CPU time 21.39 seconds
Started Jul 01 11:24:51 AM PDT 24
Finished Jul 01 11:25:14 AM PDT 24
Peak memory 256456 kb
Host smart-13f4c75e-44b4-4e27-9491-6970cec8c11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15004
4753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.150044753
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3550424011
Short name T254
Test name
Test status
Simulation time 98045824044 ps
CPU time 2033.49 seconds
Started Jul 01 11:25:01 AM PDT 24
Finished Jul 01 11:58:59 AM PDT 24
Peak memory 282276 kb
Host smart-f15978d2-1a19-4a58-a9e7-160186a82eb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550424011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3550424011
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1328974203
Short name T504
Test name
Test status
Simulation time 92193147421 ps
CPU time 900.23 seconds
Started Jul 01 11:25:00 AM PDT 24
Finished Jul 01 11:40:05 AM PDT 24
Peak memory 273324 kb
Host smart-a5d9bcff-04c2-444a-9a16-0d25fe50aa31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328974203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1328974203
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2372082127
Short name T290
Test name
Test status
Simulation time 41788802844 ps
CPU time 222.06 seconds
Started Jul 01 11:25:00 AM PDT 24
Finished Jul 01 11:28:47 AM PDT 24
Peak memory 249164 kb
Host smart-f330b3bc-364e-4791-9beb-f808a2f22271
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372082127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2372082127
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2536556833
Short name T408
Test name
Test status
Simulation time 124732315 ps
CPU time 4.69 seconds
Started Jul 01 11:24:54 AM PDT 24
Finished Jul 01 11:25:02 AM PDT 24
Peak memory 240940 kb
Host smart-60b4e132-1831-4b99-bd1a-22e9ae5f72f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25365
56833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2536556833
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2959402337
Short name T670
Test name
Test status
Simulation time 964730855 ps
CPU time 16.76 seconds
Started Jul 01 11:24:52 AM PDT 24
Finished Jul 01 11:25:10 AM PDT 24
Peak memory 248828 kb
Host smart-b414896c-00a3-4946-9965-987f12183a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29594
02337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2959402337
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.549321779
Short name T507
Test name
Test status
Simulation time 363819459 ps
CPU time 37.39 seconds
Started Jul 01 11:24:56 AM PDT 24
Finished Jul 01 11:25:37 AM PDT 24
Peak memory 249260 kb
Host smart-b2eb1e9a-f05a-470a-af7b-ad8322496fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54932
1779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.549321779
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1591653995
Short name T219
Test name
Test status
Simulation time 407647126 ps
CPU time 24.91 seconds
Started Jul 01 11:24:49 AM PDT 24
Finished Jul 01 11:25:16 AM PDT 24
Peak memory 257460 kb
Host smart-6e1c6a0a-40e1-441d-bb76-8e3c5a67a8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15916
53995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1591653995
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2023198237
Short name T47
Test name
Test status
Simulation time 113134219268 ps
CPU time 3150.53 seconds
Started Jul 01 11:24:47 AM PDT 24
Finished Jul 01 12:17:19 PM PDT 24
Peak memory 289872 kb
Host smart-248d41f3-dc35-45fc-9241-f603c2c307a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023198237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2023198237
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.4134042248
Short name T200
Test name
Test status
Simulation time 203135500 ps
CPU time 3.7 seconds
Started Jul 01 11:24:07 AM PDT 24
Finished Jul 01 11:24:15 AM PDT 24
Peak memory 249568 kb
Host smart-ace3aaaa-3388-4ec4-b760-5a5a852f2854
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4134042248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.4134042248
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3630229871
Short name T377
Test name
Test status
Simulation time 13652873905 ps
CPU time 759.23 seconds
Started Jul 01 11:24:12 AM PDT 24
Finished Jul 01 11:36:56 AM PDT 24
Peak memory 269784 kb
Host smart-32b5f82b-1dbd-48a7-9769-2c0afb581148
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630229871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3630229871
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3872804177
Short name T611
Test name
Test status
Simulation time 797526899 ps
CPU time 11.24 seconds
Started Jul 01 11:24:18 AM PDT 24
Finished Jul 01 11:24:32 AM PDT 24
Peak memory 249328 kb
Host smart-dc9711e6-d36e-4ead-9558-1b21e2b33144
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3872804177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3872804177
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2154455287
Short name T426
Test name
Test status
Simulation time 13687410600 ps
CPU time 179.92 seconds
Started Jul 01 11:24:11 AM PDT 24
Finished Jul 01 11:27:15 AM PDT 24
Peak memory 257568 kb
Host smart-3c3685df-f535-49c9-834e-d5f846475aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21544
55287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2154455287
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.4093741777
Short name T605
Test name
Test status
Simulation time 955813103 ps
CPU time 31.84 seconds
Started Jul 01 11:24:09 AM PDT 24
Finished Jul 01 11:24:45 AM PDT 24
Peak memory 249216 kb
Host smart-d1d8f878-29bf-4d3e-892f-9c8b532f3809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40937
41777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.4093741777
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3890091005
Short name T327
Test name
Test status
Simulation time 302277997073 ps
CPU time 2649.61 seconds
Started Jul 01 11:24:11 AM PDT 24
Finished Jul 01 12:08:25 PM PDT 24
Peak memory 284856 kb
Host smart-0722e20b-b793-4c5f-988c-c596c991a877
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890091005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3890091005
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2154563550
Short name T589
Test name
Test status
Simulation time 34869825046 ps
CPU time 2363.63 seconds
Started Jul 01 11:24:10 AM PDT 24
Finished Jul 01 12:03:38 PM PDT 24
Peak memory 289488 kb
Host smart-2371ec30-d894-4d6c-94fc-cd64c42f5933
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154563550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2154563550
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.219458137
Short name T286
Test name
Test status
Simulation time 4476745078 ps
CPU time 173.9 seconds
Started Jul 01 11:24:09 AM PDT 24
Finished Jul 01 11:27:07 AM PDT 24
Peak memory 249404 kb
Host smart-d966a7be-06ac-4f38-a162-b4d8157d49ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219458137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.219458137
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3192998079
Short name T676
Test name
Test status
Simulation time 2109728111 ps
CPU time 19.12 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:24:37 AM PDT 24
Peak memory 249344 kb
Host smart-779eee02-3c9e-4424-b35d-2bdd24b1523a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31929
98079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3192998079
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1409091884
Short name T467
Test name
Test status
Simulation time 420783929 ps
CPU time 27.06 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:24:44 AM PDT 24
Peak memory 248600 kb
Host smart-733c5bbc-8187-4bda-963f-099d38230014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14090
91884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1409091884
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.215853045
Short name T382
Test name
Test status
Simulation time 149029225 ps
CPU time 15.82 seconds
Started Jul 01 11:24:12 AM PDT 24
Finished Jul 01 11:24:32 AM PDT 24
Peak memory 249128 kb
Host smart-e231530a-35f2-41a1-92b4-9e0da5136953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21585
3045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.215853045
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1722427969
Short name T367
Test name
Test status
Simulation time 4638772233 ps
CPU time 20.43 seconds
Started Jul 01 11:24:16 AM PDT 24
Finished Jul 01 11:24:41 AM PDT 24
Peak memory 256696 kb
Host smart-8e2818dd-5c7c-4d0d-9ced-676c8e724796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17224
27969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1722427969
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2131052062
Short name T690
Test name
Test status
Simulation time 279192956232 ps
CPU time 3724.43 seconds
Started Jul 01 11:24:15 AM PDT 24
Finished Jul 01 12:26:24 PM PDT 24
Peak memory 299228 kb
Host smart-b803999d-146a-4fc4-97dc-571380b88421
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131052062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2131052062
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.588714087
Short name T454
Test name
Test status
Simulation time 59629136599 ps
CPU time 1609.42 seconds
Started Jul 01 11:24:11 AM PDT 24
Finished Jul 01 11:51:05 AM PDT 24
Peak memory 289480 kb
Host smart-7c8c1ce2-d9f5-4469-97a1-a37608799fb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588714087 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.588714087
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.594776781
Short name T549
Test name
Test status
Simulation time 303206615050 ps
CPU time 2104.61 seconds
Started Jul 01 11:24:54 AM PDT 24
Finished Jul 01 12:00:02 PM PDT 24
Peak memory 285944 kb
Host smart-e76f67de-bd4b-4cc5-b630-e9c6bbe6f087
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594776781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.594776781
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2197675490
Short name T173
Test name
Test status
Simulation time 692752351 ps
CPU time 57.75 seconds
Started Jul 01 11:24:48 AM PDT 24
Finished Jul 01 11:25:48 AM PDT 24
Peak memory 257404 kb
Host smart-f10a77c9-5e29-4a40-9693-b44ab15b533c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21976
75490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2197675490
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2969776776
Short name T456
Test name
Test status
Simulation time 428521182 ps
CPU time 27.13 seconds
Started Jul 01 11:24:52 AM PDT 24
Finished Jul 01 11:25:21 AM PDT 24
Peak memory 256688 kb
Host smart-19d6e131-9c96-443a-8574-13478220f874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29697
76776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2969776776
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3466336422
Short name T665
Test name
Test status
Simulation time 64498162087 ps
CPU time 1408.91 seconds
Started Jul 01 11:24:48 AM PDT 24
Finished Jul 01 11:48:19 AM PDT 24
Peak memory 290160 kb
Host smart-8b6af147-1afd-44bb-b2f4-1cc3bec1908c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466336422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3466336422
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.985255344
Short name T256
Test name
Test status
Simulation time 12827350913 ps
CPU time 527.52 seconds
Started Jul 01 11:24:49 AM PDT 24
Finished Jul 01 11:33:39 AM PDT 24
Peak memory 257132 kb
Host smart-267adf06-3d39-4d88-b2e7-690d75d6fb97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985255344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.985255344
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.788769245
Short name T363
Test name
Test status
Simulation time 141492651 ps
CPU time 5.69 seconds
Started Jul 01 11:25:00 AM PDT 24
Finished Jul 01 11:25:11 AM PDT 24
Peak memory 249256 kb
Host smart-4b8cbe85-f525-45c2-b99c-95b7deee4642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78876
9245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.788769245
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2455298046
Short name T691
Test name
Test status
Simulation time 4604896620 ps
CPU time 55.23 seconds
Started Jul 01 11:25:01 AM PDT 24
Finished Jul 01 11:26:02 AM PDT 24
Peak memory 249144 kb
Host smart-70b71be8-0859-4329-99dd-18162b59659b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24552
98046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2455298046
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1096204028
Short name T44
Test name
Test status
Simulation time 1153127042 ps
CPU time 77.38 seconds
Started Jul 01 11:25:04 AM PDT 24
Finished Jul 01 11:26:27 AM PDT 24
Peak memory 249004 kb
Host smart-81c730f9-2322-4fbe-930c-9d462e1c4289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10962
04028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1096204028
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1182074997
Short name T644
Test name
Test status
Simulation time 857242935 ps
CPU time 50.6 seconds
Started Jul 01 11:24:56 AM PDT 24
Finished Jul 01 11:25:51 AM PDT 24
Peak memory 256988 kb
Host smart-6fe1dc8f-d9ad-4ab4-acfd-7fce29781a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11820
74997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1182074997
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1986027712
Short name T509
Test name
Test status
Simulation time 57379975301 ps
CPU time 1800.09 seconds
Started Jul 01 11:24:54 AM PDT 24
Finished Jul 01 11:54:58 AM PDT 24
Peak memory 285064 kb
Host smart-a40b82b9-b3ea-47ae-943a-5c7d6756cf6b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986027712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1986027712
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.205498387
Short name T211
Test name
Test status
Simulation time 94536675213 ps
CPU time 1823.83 seconds
Started Jul 01 11:24:57 AM PDT 24
Finished Jul 01 11:55:25 AM PDT 24
Peak memory 283956 kb
Host smart-8b1decce-ddf8-42f0-bde5-31f053a84282
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205498387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.205498387
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3073697231
Short name T557
Test name
Test status
Simulation time 1100549491 ps
CPU time 34.19 seconds
Started Jul 01 11:24:48 AM PDT 24
Finished Jul 01 11:25:25 AM PDT 24
Peak memory 256932 kb
Host smart-54cc3a48-6b59-49f2-8972-59407df63cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30736
97231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3073697231
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.706311474
Short name T398
Test name
Test status
Simulation time 277139097 ps
CPU time 16.66 seconds
Started Jul 01 11:25:02 AM PDT 24
Finished Jul 01 11:25:24 AM PDT 24
Peak memory 257044 kb
Host smart-5c438d1f-71eb-44f0-bfcb-219aec3138d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70631
1474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.706311474
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2646798046
Short name T321
Test name
Test status
Simulation time 139563042248 ps
CPU time 1973.54 seconds
Started Jul 01 11:24:58 AM PDT 24
Finished Jul 01 11:57:57 AM PDT 24
Peak memory 286472 kb
Host smart-78a447d7-5918-4985-8be6-faab7307c08f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646798046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2646798046
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3269665304
Short name T565
Test name
Test status
Simulation time 61606960875 ps
CPU time 1595.03 seconds
Started Jul 01 11:24:59 AM PDT 24
Finished Jul 01 11:51:39 AM PDT 24
Peak memory 290384 kb
Host smart-a1c77dbb-490e-43c5-a798-ee4eb0c41b9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269665304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3269665304
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3195687708
Short name T536
Test name
Test status
Simulation time 12882768785 ps
CPU time 491.74 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:33:21 AM PDT 24
Peak memory 249408 kb
Host smart-1d16bff4-ba57-4f62-80a4-eabda263574d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195687708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3195687708
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1651153751
Short name T609
Test name
Test status
Simulation time 718757543 ps
CPU time 40.56 seconds
Started Jul 01 11:24:49 AM PDT 24
Finished Jul 01 11:25:32 AM PDT 24
Peak memory 256844 kb
Host smart-2f0f7e9f-f73d-420b-8b4b-09ed12f6cd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16511
53751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1651153751
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1859231366
Short name T360
Test name
Test status
Simulation time 841023728 ps
CPU time 21.78 seconds
Started Jul 01 11:24:54 AM PDT 24
Finished Jul 01 11:25:19 AM PDT 24
Peak memory 256508 kb
Host smart-624d5c12-4586-4316-8d48-9bb83b3ddf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18592
31366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1859231366
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.480362821
Short name T49
Test name
Test status
Simulation time 1932282718 ps
CPU time 33.99 seconds
Started Jul 01 11:24:57 AM PDT 24
Finished Jul 01 11:25:35 AM PDT 24
Peak memory 257420 kb
Host smart-344b199a-a7de-453b-98dd-b1499e639c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48036
2821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.480362821
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.739703253
Short name T678
Test name
Test status
Simulation time 1037097739 ps
CPU time 12.59 seconds
Started Jul 01 11:24:56 AM PDT 24
Finished Jul 01 11:25:13 AM PDT 24
Peak memory 254072 kb
Host smart-9471703b-ada8-4c9d-b47f-576b5dc259aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73970
3253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.739703253
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.4167176457
Short name T443
Test name
Test status
Simulation time 32879669406 ps
CPU time 2005.64 seconds
Started Jul 01 11:24:56 AM PDT 24
Finished Jul 01 11:58:26 AM PDT 24
Peak memory 288212 kb
Host smart-960ffac3-5c21-44e8-82e1-a66ddc226449
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167176457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.4167176457
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3880056827
Short name T390
Test name
Test status
Simulation time 133669549956 ps
CPU time 3887.94 seconds
Started Jul 01 11:24:54 AM PDT 24
Finished Jul 01 12:29:46 PM PDT 24
Peak memory 315004 kb
Host smart-bb3d36a5-02a9-405f-b4d3-b818eb072cba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880056827 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3880056827
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.792610239
Short name T352
Test name
Test status
Simulation time 14658175972 ps
CPU time 1044.79 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:42:34 AM PDT 24
Peak memory 273368 kb
Host smart-d8a67977-99e1-426e-8313-0383840899a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792610239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.792610239
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1643015736
Short name T457
Test name
Test status
Simulation time 7444003262 ps
CPU time 151.8 seconds
Started Jul 01 11:24:57 AM PDT 24
Finished Jul 01 11:27:33 AM PDT 24
Peak memory 257292 kb
Host smart-f7a9a5f5-76c3-45de-b81b-19be12d129d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16430
15736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1643015736
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3695878771
Short name T242
Test name
Test status
Simulation time 800694096 ps
CPU time 19.18 seconds
Started Jul 01 11:24:55 AM PDT 24
Finished Jul 01 11:25:18 AM PDT 24
Peak memory 256524 kb
Host smart-7c81b3d1-ec4f-4ca0-a5f9-103cdb9ea2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36958
78771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3695878771
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2191589838
Short name T302
Test name
Test status
Simulation time 16537243967 ps
CPU time 1204.37 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:45:13 AM PDT 24
Peak memory 286952 kb
Host smart-c559834d-9734-4729-aff0-1416b7ad9076
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191589838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2191589838
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1715942046
Short name T372
Test name
Test status
Simulation time 77376212387 ps
CPU time 1699.78 seconds
Started Jul 01 11:24:56 AM PDT 24
Finished Jul 01 11:53:20 AM PDT 24
Peak memory 290160 kb
Host smart-2da78369-bd86-4f5a-8b73-f269ec026dde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715942046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1715942046
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3780878062
Short name T291
Test name
Test status
Simulation time 21891205050 ps
CPU time 434.57 seconds
Started Jul 01 11:24:54 AM PDT 24
Finished Jul 01 11:32:13 AM PDT 24
Peak memory 249384 kb
Host smart-f910cad0-b4a1-481c-b1ee-23496b66b40e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780878062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3780878062
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.561295176
Short name T346
Test name
Test status
Simulation time 67632046 ps
CPU time 5.38 seconds
Started Jul 01 11:25:00 AM PDT 24
Finished Jul 01 11:25:11 AM PDT 24
Peak memory 249256 kb
Host smart-b9dac602-5110-4840-bd16-8071c08fc6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56129
5176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.561295176
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1361078678
Short name T339
Test name
Test status
Simulation time 552020404 ps
CPU time 22.84 seconds
Started Jul 01 11:24:56 AM PDT 24
Finished Jul 01 11:25:23 AM PDT 24
Peak memory 249216 kb
Host smart-2330f236-5cc7-43cd-8cab-97d77a09e75f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13610
78678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1361078678
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1158703338
Short name T239
Test name
Test status
Simulation time 675851335 ps
CPU time 50.83 seconds
Started Jul 01 11:25:04 AM PDT 24
Finished Jul 01 11:26:00 AM PDT 24
Peak memory 256816 kb
Host smart-2b81a9c4-b86b-412f-b8be-bc622a50331a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11587
03338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1158703338
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.696076809
Short name T590
Test name
Test status
Simulation time 638963091 ps
CPU time 28.19 seconds
Started Jul 01 11:25:00 AM PDT 24
Finished Jul 01 11:25:33 AM PDT 24
Peak memory 257420 kb
Host smart-8671c35f-a7a4-41f2-be8f-b4a98455ac57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69607
6809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.696076809
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.4096275607
Short name T544
Test name
Test status
Simulation time 26919235799 ps
CPU time 1068.11 seconds
Started Jul 01 11:25:01 AM PDT 24
Finished Jul 01 11:42:54 AM PDT 24
Peak memory 289428 kb
Host smart-64dcf8b6-25fd-45db-99b6-5bb106dd6d86
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096275607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.4096275607
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.4034838344
Short name T227
Test name
Test status
Simulation time 1061760297019 ps
CPU time 9095.56 seconds
Started Jul 01 11:24:55 AM PDT 24
Finished Jul 01 01:56:36 PM PDT 24
Peak memory 371788 kb
Host smart-4573030e-6fea-40fd-9dfc-ea7c6f688346
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034838344 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.4034838344
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1588622999
Short name T407
Test name
Test status
Simulation time 31760560142 ps
CPU time 889.66 seconds
Started Jul 01 11:24:55 AM PDT 24
Finished Jul 01 11:39:48 AM PDT 24
Peak memory 282912 kb
Host smart-7fcc5b96-22ff-4939-9297-5850c4226c5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588622999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1588622999
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.435315935
Short name T662
Test name
Test status
Simulation time 2483271812 ps
CPU time 32.46 seconds
Started Jul 01 11:24:55 AM PDT 24
Finished Jul 01 11:25:31 AM PDT 24
Peak memory 257596 kb
Host smart-7409c6be-4fe7-4e18-b2d9-9c3bee0b5380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43531
5935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.435315935
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.349562194
Short name T175
Test name
Test status
Simulation time 417343570 ps
CPU time 17.35 seconds
Started Jul 01 11:24:54 AM PDT 24
Finished Jul 01 11:25:14 AM PDT 24
Peak memory 256540 kb
Host smart-0ad15b5d-63a8-4ccf-b56b-d94b49e2745b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34956
2194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.349562194
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1004552625
Short name T315
Test name
Test status
Simulation time 145670872922 ps
CPU time 1950.9 seconds
Started Jul 01 11:25:17 AM PDT 24
Finished Jul 01 11:57:51 AM PDT 24
Peak memory 290388 kb
Host smart-068e2382-1f89-496b-ad87-7f464a0cdd76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004552625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1004552625
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2604301864
Short name T517
Test name
Test status
Simulation time 41466854665 ps
CPU time 2589.4 seconds
Started Jul 01 11:24:59 AM PDT 24
Finished Jul 01 12:08:13 PM PDT 24
Peak memory 290160 kb
Host smart-de339603-779c-4ebe-a48c-1c81450c3a02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604301864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2604301864
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3917550138
Short name T278
Test name
Test status
Simulation time 4771143316 ps
CPU time 197.93 seconds
Started Jul 01 11:24:57 AM PDT 24
Finished Jul 01 11:28:19 AM PDT 24
Peak memory 249256 kb
Host smart-2f5dc915-d233-4902-898e-31349c104125
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917550138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3917550138
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1289042941
Short name T645
Test name
Test status
Simulation time 2002126976 ps
CPU time 11.47 seconds
Started Jul 01 11:24:53 AM PDT 24
Finished Jul 01 11:25:08 AM PDT 24
Peak memory 255844 kb
Host smart-f9208317-224e-4164-8607-26734a3bac50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12890
42941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1289042941
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3984973609
Short name T632
Test name
Test status
Simulation time 837002598 ps
CPU time 50.54 seconds
Started Jul 01 11:24:57 AM PDT 24
Finished Jul 01 11:25:51 AM PDT 24
Peak memory 256556 kb
Host smart-e1c64939-dc83-448d-9c6a-8e2963ee1fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39849
73609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3984973609
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2874233762
Short name T48
Test name
Test status
Simulation time 363246736 ps
CPU time 22.57 seconds
Started Jul 01 11:24:56 AM PDT 24
Finished Jul 01 11:25:22 AM PDT 24
Peak memory 248844 kb
Host smart-b2f4ad7e-1094-4e5e-9d5f-de25bbbce8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28742
33762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2874233762
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.4069437784
Short name T682
Test name
Test status
Simulation time 2507367598 ps
CPU time 44.03 seconds
Started Jul 01 11:24:52 AM PDT 24
Finished Jul 01 11:25:38 AM PDT 24
Peak memory 257568 kb
Host smart-0fcb4600-fbe3-458a-8c15-a8d98509ec5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40694
37784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.4069437784
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.396578769
Short name T30
Test name
Test status
Simulation time 66866526779 ps
CPU time 5281.47 seconds
Started Jul 01 11:25:04 AM PDT 24
Finished Jul 01 12:53:11 PM PDT 24
Peak memory 316568 kb
Host smart-af68d78c-741e-4351-804d-599b63464d76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396578769 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.396578769
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1713526582
Short name T406
Test name
Test status
Simulation time 25933048414 ps
CPU time 1436.2 seconds
Started Jul 01 11:25:00 AM PDT 24
Finished Jul 01 11:49:02 AM PDT 24
Peak memory 274024 kb
Host smart-3d14c197-e08e-496f-a58f-e8342fb14f0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713526582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1713526582
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2799772637
Short name T496
Test name
Test status
Simulation time 3237956700 ps
CPU time 46.58 seconds
Started Jul 01 11:25:02 AM PDT 24
Finished Jul 01 11:25:54 AM PDT 24
Peak memory 256968 kb
Host smart-58406785-d8e0-4d56-88d0-14343bd62e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27997
72637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2799772637
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.4025918290
Short name T664
Test name
Test status
Simulation time 866075520 ps
CPU time 50.54 seconds
Started Jul 01 11:25:00 AM PDT 24
Finished Jul 01 11:25:56 AM PDT 24
Peak memory 257428 kb
Host smart-41bcb7e4-2702-42db-ae4a-bc5146f14e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40259
18290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.4025918290
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3857313544
Short name T584
Test name
Test status
Simulation time 67279521755 ps
CPU time 1441.49 seconds
Started Jul 01 11:25:10 AM PDT 24
Finished Jul 01 11:49:14 AM PDT 24
Peak memory 288400 kb
Host smart-09bb3c09-629c-46a0-9f4f-e910fb99b2a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857313544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3857313544
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1384927630
Short name T701
Test name
Test status
Simulation time 845331974 ps
CPU time 54.84 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:26:03 AM PDT 24
Peak memory 249332 kb
Host smart-09f1f3bc-c186-4916-ab7a-d673c745e857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13849
27630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1384927630
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.38025626
Short name T358
Test name
Test status
Simulation time 156120489 ps
CPU time 14.16 seconds
Started Jul 01 11:25:10 AM PDT 24
Finished Jul 01 11:25:26 AM PDT 24
Peak memory 249284 kb
Host smart-ef02c8b1-0fb4-49e8-bef3-fce8cf6efe4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38025
626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.38025626
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2710585065
Short name T210
Test name
Test status
Simulation time 380195027 ps
CPU time 28.77 seconds
Started Jul 01 11:24:58 AM PDT 24
Finished Jul 01 11:25:31 AM PDT 24
Peak memory 256320 kb
Host smart-1cdd504b-f211-4f36-be59-665e4f751673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27105
85065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2710585065
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3307234658
Short name T172
Test name
Test status
Simulation time 4621349416 ps
CPU time 202.04 seconds
Started Jul 01 11:25:10 AM PDT 24
Finished Jul 01 11:28:34 AM PDT 24
Peak memory 257516 kb
Host smart-19e89acd-2476-4420-b851-5e28980f58eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307234658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3307234658
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.4054555443
Short name T548
Test name
Test status
Simulation time 45593546560 ps
CPU time 2609.96 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 12:08:39 PM PDT 24
Peak memory 289688 kb
Host smart-33d9b48a-eb0c-45ce-804a-858aec006b86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054555443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4054555443
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1480622157
Short name T397
Test name
Test status
Simulation time 3109967209 ps
CPU time 101.27 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:26:50 AM PDT 24
Peak memory 250452 kb
Host smart-848822fe-0cb6-420d-945b-1b1ef502f26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14806
22157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1480622157
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.703469196
Short name T581
Test name
Test status
Simulation time 410234801 ps
CPU time 19.28 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:25:28 AM PDT 24
Peak memory 249672 kb
Host smart-34ba3850-af0c-4e22-a0e1-270a11f2ccfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70346
9196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.703469196
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3412466711
Short name T576
Test name
Test status
Simulation time 8047611465 ps
CPU time 678.57 seconds
Started Jul 01 11:25:09 AM PDT 24
Finished Jul 01 11:36:30 AM PDT 24
Peak memory 273492 kb
Host smart-d0a8c42d-ca95-49d3-9697-474d4410b260
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412466711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3412466711
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3126723996
Short name T618
Test name
Test status
Simulation time 51792315234 ps
CPU time 416.7 seconds
Started Jul 01 11:25:17 AM PDT 24
Finished Jul 01 11:32:17 AM PDT 24
Peak memory 249508 kb
Host smart-07c17252-45b7-4586-b6aa-8e4cc44962e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126723996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3126723996
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.4176704094
Short name T628
Test name
Test status
Simulation time 340293400 ps
CPU time 28.8 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:25:37 AM PDT 24
Peak memory 249292 kb
Host smart-cf581c2d-276a-4b5f-be96-50f9d637bd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41767
04094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.4176704094
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2954617586
Short name T466
Test name
Test status
Simulation time 168262741 ps
CPU time 7.44 seconds
Started Jul 01 11:25:04 AM PDT 24
Finished Jul 01 11:25:16 AM PDT 24
Peak memory 248808 kb
Host smart-595e91b2-4d7f-441f-b8f9-8b0e919566b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29546
17586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2954617586
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1538787574
Short name T253
Test name
Test status
Simulation time 1208368395 ps
CPU time 38.3 seconds
Started Jul 01 11:25:01 AM PDT 24
Finished Jul 01 11:25:44 AM PDT 24
Peak memory 256668 kb
Host smart-0a5e00fb-2be6-48d3-bf77-470b27a7e8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15387
87574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1538787574
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.396589788
Short name T379
Test name
Test status
Simulation time 1240990666 ps
CPU time 25.08 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:25:46 AM PDT 24
Peak memory 249352 kb
Host smart-89ccfad9-714c-4ccc-9a2a-54b4b87ce2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39658
9788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.396589788
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2076818297
Short name T64
Test name
Test status
Simulation time 22982530306 ps
CPU time 878.9 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:39:47 AM PDT 24
Peak memory 273224 kb
Host smart-b142cacb-cfe8-4c87-9f42-40af214997f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076818297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2076818297
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1007147816
Short name T224
Test name
Test status
Simulation time 203416715105 ps
CPU time 1638.62 seconds
Started Jul 01 11:25:10 AM PDT 24
Finished Jul 01 11:52:31 AM PDT 24
Peak memory 289352 kb
Host smart-07c8e3dc-c512-41ec-953f-5268c2f93198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007147816 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1007147816
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.435409368
Short name T52
Test name
Test status
Simulation time 36591165433 ps
CPU time 1979.72 seconds
Started Jul 01 11:25:07 AM PDT 24
Finished Jul 01 11:58:10 AM PDT 24
Peak memory 273960 kb
Host smart-1e44a64f-d711-46a1-ba1c-ac417aba7cbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435409368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.435409368
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1568844149
Short name T647
Test name
Test status
Simulation time 3610543077 ps
CPU time 209.29 seconds
Started Jul 01 11:25:04 AM PDT 24
Finished Jul 01 11:28:39 AM PDT 24
Peak memory 257628 kb
Host smart-7de84d61-8fe7-42ce-96af-a155ad2bd6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15688
44149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1568844149
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.969974586
Short name T653
Test name
Test status
Simulation time 6686912313 ps
CPU time 28.26 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:25:37 AM PDT 24
Peak memory 256004 kb
Host smart-af94f072-ddbd-4d0b-b970-0389b3915b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96997
4586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.969974586
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.160207461
Short name T319
Test name
Test status
Simulation time 124558930086 ps
CPU time 1962.39 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:57:51 AM PDT 24
Peak memory 273984 kb
Host smart-24a35d2a-bc23-4e4a-bbf3-fbe586f68d28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160207461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.160207461
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.10798323
Short name T635
Test name
Test status
Simulation time 56690558965 ps
CPU time 1394.96 seconds
Started Jul 01 11:25:04 AM PDT 24
Finished Jul 01 11:48:24 AM PDT 24
Peak memory 289036 kb
Host smart-9fbb1884-df71-42be-8207-5af1f5b0c10e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10798323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.10798323
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3269370470
Short name T280
Test name
Test status
Simulation time 9834486840 ps
CPU time 382.35 seconds
Started Jul 01 11:25:08 AM PDT 24
Finished Jul 01 11:31:34 AM PDT 24
Peak memory 255952 kb
Host smart-5c7a3cfb-ae96-41b8-bafc-96546c8b8fa1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269370470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3269370470
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2509228218
Short name T341
Test name
Test status
Simulation time 1171643976 ps
CPU time 67.19 seconds
Started Jul 01 11:24:58 AM PDT 24
Finished Jul 01 11:26:09 AM PDT 24
Peak memory 256688 kb
Host smart-f1a85fd4-fbcb-448c-8da6-3f7d2d9f6422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25092
28218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2509228218
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.953554223
Short name T476
Test name
Test status
Simulation time 1050020209 ps
CPU time 30.91 seconds
Started Jul 01 11:25:08 AM PDT 24
Finished Jul 01 11:25:42 AM PDT 24
Peak memory 256564 kb
Host smart-b84a52b0-ff4b-4371-bfa9-67b3911982de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95355
4223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.953554223
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1021449610
Short name T627
Test name
Test status
Simulation time 35983022 ps
CPU time 5.04 seconds
Started Jul 01 11:25:04 AM PDT 24
Finished Jul 01 11:25:14 AM PDT 24
Peak memory 251884 kb
Host smart-89c00cd6-fa0d-4d53-9fb2-e9f260f8b6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10214
49610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1021449610
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3224640471
Short name T552
Test name
Test status
Simulation time 2238820913 ps
CPU time 35.97 seconds
Started Jul 01 11:24:59 AM PDT 24
Finished Jul 01 11:25:39 AM PDT 24
Peak memory 257264 kb
Host smart-1a3af51d-67c8-4d48-af10-2ae7cd8849eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32246
40471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3224640471
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2759746234
Short name T77
Test name
Test status
Simulation time 63732893248 ps
CPU time 2739.5 seconds
Started Jul 01 11:25:04 AM PDT 24
Finished Jul 01 12:10:48 PM PDT 24
Peak memory 290384 kb
Host smart-fbef2cb3-4e72-4e2b-8d1e-87086b87619f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759746234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2759746234
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.331131649
Short name T666
Test name
Test status
Simulation time 78179180739 ps
CPU time 8556.03 seconds
Started Jul 01 11:25:09 AM PDT 24
Finished Jul 01 01:47:48 PM PDT 24
Peak memory 404488 kb
Host smart-7db68155-61ce-46a4-aa6e-4ac9d3f36d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331131649 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.331131649
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2797994763
Short name T671
Test name
Test status
Simulation time 16900386141 ps
CPU time 1327.73 seconds
Started Jul 01 11:25:08 AM PDT 24
Finished Jul 01 11:47:19 AM PDT 24
Peak memory 290096 kb
Host smart-c364630b-2499-443b-bf25-7a05146eb42d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797994763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2797994763
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3327074285
Short name T410
Test name
Test status
Simulation time 6171895380 ps
CPU time 162.07 seconds
Started Jul 01 11:25:05 AM PDT 24
Finished Jul 01 11:27:52 AM PDT 24
Peak memory 252840 kb
Host smart-0c694c00-474f-4aa1-a8c1-43cdb7b6777d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33270
74285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3327074285
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1933018544
Short name T79
Test name
Test status
Simulation time 4335826584 ps
CPU time 70.87 seconds
Started Jul 01 11:25:09 AM PDT 24
Finished Jul 01 11:26:23 AM PDT 24
Peak memory 256840 kb
Host smart-dca4321e-0339-4dd1-aa89-5865dc528113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19330
18544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1933018544
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.334857394
Short name T274
Test name
Test status
Simulation time 59550346972 ps
CPU time 804.13 seconds
Started Jul 01 11:25:13 AM PDT 24
Finished Jul 01 11:38:40 AM PDT 24
Peak memory 273992 kb
Host smart-11741cc1-ca87-4761-9c3c-77b9c3b5e2f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334857394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.334857394
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3987794794
Short name T452
Test name
Test status
Simulation time 33006485064 ps
CPU time 1443.09 seconds
Started Jul 01 11:25:13 AM PDT 24
Finished Jul 01 11:49:19 AM PDT 24
Peak memory 289664 kb
Host smart-64f8ae8e-5b37-4014-bbee-200658639088
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987794794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3987794794
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2306123328
Short name T293
Test name
Test status
Simulation time 62996116007 ps
CPU time 146.16 seconds
Started Jul 01 11:25:12 AM PDT 24
Finished Jul 01 11:27:41 AM PDT 24
Peak memory 256216 kb
Host smart-78b3f098-8539-44c9-8661-a367f35b8309
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306123328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2306123328
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.4135843706
Short name T500
Test name
Test status
Simulation time 1350583699 ps
CPU time 27.83 seconds
Started Jul 01 11:25:01 AM PDT 24
Finished Jul 01 11:25:34 AM PDT 24
Peak memory 256820 kb
Host smart-c41547b7-5cd4-4e57-bff2-49e672055f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41358
43706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.4135843706
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1490465245
Short name T84
Test name
Test status
Simulation time 772608362 ps
CPU time 46.61 seconds
Started Jul 01 11:25:04 AM PDT 24
Finished Jul 01 11:25:56 AM PDT 24
Peak memory 256984 kb
Host smart-ef8248d1-53db-482d-b591-c9e237d45081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14904
65245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1490465245
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.128538139
Short name T523
Test name
Test status
Simulation time 259512523 ps
CPU time 9.1 seconds
Started Jul 01 11:25:03 AM PDT 24
Finished Jul 01 11:25:18 AM PDT 24
Peak memory 249256 kb
Host smart-f00908e2-5fa9-48ab-b6db-96aceb83ff7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12853
8139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.128538139
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3712329464
Short name T637
Test name
Test status
Simulation time 897720803 ps
CPU time 29.38 seconds
Started Jul 01 11:25:02 AM PDT 24
Finished Jul 01 11:25:37 AM PDT 24
Peak memory 257488 kb
Host smart-385335ce-7abf-4ddd-a137-a6f88af91bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37123
29464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3712329464
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3297628819
Short name T69
Test name
Test status
Simulation time 7680674326 ps
CPU time 410.23 seconds
Started Jul 01 11:25:12 AM PDT 24
Finished Jul 01 11:32:05 AM PDT 24
Peak memory 257632 kb
Host smart-fbe61386-a13c-4dea-8ba9-5f119b0776b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297628819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3297628819
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3200482159
Short name T31
Test name
Test status
Simulation time 7258756507 ps
CPU time 866.91 seconds
Started Jul 01 11:25:10 AM PDT 24
Finished Jul 01 11:39:39 AM PDT 24
Peak memory 273512 kb
Host smart-8079ea3c-3e41-44cb-8a78-88dcd9533658
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200482159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3200482159
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1519309980
Short name T439
Test name
Test status
Simulation time 21925203700 ps
CPU time 299.49 seconds
Started Jul 01 11:25:13 AM PDT 24
Finished Jul 01 11:30:15 AM PDT 24
Peak memory 257488 kb
Host smart-75b87388-9039-41b1-acc1-da96d38f76ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15193
09980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1519309980
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3818909629
Short name T399
Test name
Test status
Simulation time 46904487 ps
CPU time 6.08 seconds
Started Jul 01 11:25:15 AM PDT 24
Finished Jul 01 11:25:23 AM PDT 24
Peak memory 249264 kb
Host smart-0b815e8d-8719-4e18-9171-54569437db78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38189
09629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3818909629
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1162181912
Short name T272
Test name
Test status
Simulation time 201701441204 ps
CPU time 1091.72 seconds
Started Jul 01 11:25:10 AM PDT 24
Finished Jul 01 11:43:25 AM PDT 24
Peak memory 273828 kb
Host smart-b1bb1e93-32f0-4b97-87e6-0e0cfb0f8016
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162181912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1162181912
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2515467437
Short name T447
Test name
Test status
Simulation time 428362547 ps
CPU time 33.8 seconds
Started Jul 01 11:25:10 AM PDT 24
Finished Jul 01 11:25:46 AM PDT 24
Peak memory 256684 kb
Host smart-73a3487d-09bb-4510-b579-5830d0b62ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25154
67437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2515467437
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2904012504
Short name T709
Test name
Test status
Simulation time 884093062 ps
CPU time 61.29 seconds
Started Jul 01 11:25:12 AM PDT 24
Finished Jul 01 11:26:16 AM PDT 24
Peak memory 257012 kb
Host smart-926b02a3-37ec-43ba-9070-72cd105b2308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29040
12504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2904012504
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.419136058
Short name T50
Test name
Test status
Simulation time 2217210396 ps
CPU time 27.68 seconds
Started Jul 01 11:25:11 AM PDT 24
Finished Jul 01 11:25:41 AM PDT 24
Peak memory 257208 kb
Host smart-6ce1f5ab-bbb5-4dba-815c-f5a265f4e0c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41913
6058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.419136058
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3720605381
Short name T424
Test name
Test status
Simulation time 1467893419 ps
CPU time 25.52 seconds
Started Jul 01 11:25:14 AM PDT 24
Finished Jul 01 11:25:42 AM PDT 24
Peak memory 256664 kb
Host smart-ec10617f-aa2a-4eb4-91a8-7b212feca8e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37206
05381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3720605381
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.4277836779
Short name T27
Test name
Test status
Simulation time 21939961851 ps
CPU time 1434.59 seconds
Started Jul 01 11:25:09 AM PDT 24
Finished Jul 01 11:49:06 AM PDT 24
Peak memory 285908 kb
Host smart-320cd88c-ebc5-45ad-b28d-9c0f54fea3df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277836779 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.4277836779
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2261006696
Short name T264
Test name
Test status
Simulation time 80495738478 ps
CPU time 2663.52 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 12:09:46 PM PDT 24
Peak memory 288576 kb
Host smart-06b46a3e-00c1-4157-99b0-046a600d82c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261006696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2261006696
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2806464000
Short name T345
Test name
Test status
Simulation time 4816683796 ps
CPU time 149.08 seconds
Started Jul 01 11:25:20 AM PDT 24
Finished Jul 01 11:27:53 AM PDT 24
Peak memory 257496 kb
Host smart-5e47206e-8d46-4c35-a403-daaf3227cfdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28064
64000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2806464000
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.250190836
Short name T373
Test name
Test status
Simulation time 3290419689 ps
CPU time 50.95 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:26:12 AM PDT 24
Peak memory 249296 kb
Host smart-d7bcfba2-5c56-408f-96ff-f9075615ccd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25019
0836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.250190836
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.4107497109
Short name T704
Test name
Test status
Simulation time 13300218777 ps
CPU time 1327.47 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:47:29 AM PDT 24
Peak memory 289728 kb
Host smart-fda6e1c1-c85c-4523-879c-6b2e29f3467d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107497109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.4107497109
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3686748907
Short name T525
Test name
Test status
Simulation time 24331812674 ps
CPU time 1357.82 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:47:59 AM PDT 24
Peak memory 273308 kb
Host smart-709576d1-85f8-4f25-86ed-5426b4fa22f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686748907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3686748907
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2987560621
Short name T306
Test name
Test status
Simulation time 153290682746 ps
CPU time 366.55 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:31:28 AM PDT 24
Peak memory 248304 kb
Host smart-6330d9c6-bcc4-4807-ae73-80d86a1d8415
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987560621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2987560621
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3493109977
Short name T656
Test name
Test status
Simulation time 1252439234 ps
CPU time 29.18 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:25:50 AM PDT 24
Peak memory 256712 kb
Host smart-7cb5065e-f08a-45e8-9689-11e1e474dc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34931
09977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3493109977
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3071375049
Short name T257
Test name
Test status
Simulation time 607717624 ps
CPU time 36.74 seconds
Started Jul 01 11:25:17 AM PDT 24
Finished Jul 01 11:25:56 AM PDT 24
Peak memory 257344 kb
Host smart-8ff2aac8-b927-432d-ab1b-341b98312562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30713
75049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3071375049
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3520494595
Short name T109
Test name
Test status
Simulation time 179286461 ps
CPU time 15.56 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:25:37 AM PDT 24
Peak memory 253392 kb
Host smart-cc29a55a-5cce-4ce7-a805-fae6015fdc95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35204
94595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3520494595
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2099292732
Short name T633
Test name
Test status
Simulation time 952091529 ps
CPU time 30.02 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:25:52 AM PDT 24
Peak memory 256596 kb
Host smart-0cd0dfd1-5b0a-4d89-8028-58cab804ab7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20992
92732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2099292732
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2934039342
Short name T405
Test name
Test status
Simulation time 63791116450 ps
CPU time 1437.86 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:49:19 AM PDT 24
Peak memory 288724 kb
Host smart-52f618df-bc76-43af-a06f-52ad44d7c675
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934039342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2934039342
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1820807662
Short name T178
Test name
Test status
Simulation time 69882238542 ps
CPU time 3172.81 seconds
Started Jul 01 11:25:29 AM PDT 24
Finished Jul 01 12:18:24 PM PDT 24
Peak memory 298668 kb
Host smart-e2d1f12f-d2c5-4ab4-a1bc-506da2487898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820807662 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1820807662
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3457985358
Short name T198
Test name
Test status
Simulation time 69304157 ps
CPU time 2.66 seconds
Started Jul 01 11:24:16 AM PDT 24
Finished Jul 01 11:24:23 AM PDT 24
Peak memory 249584 kb
Host smart-3f8846f9-48f6-4a94-b6e3-27d23784ef8c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3457985358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3457985358
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1591347808
Short name T498
Test name
Test status
Simulation time 489719355717 ps
CPU time 2408.3 seconds
Started Jul 01 11:24:15 AM PDT 24
Finished Jul 01 12:04:28 PM PDT 24
Peak memory 290188 kb
Host smart-23ad77bb-0529-4171-9e76-9dd3a304c1bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591347808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1591347808
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.294988000
Short name T432
Test name
Test status
Simulation time 1496451398 ps
CPU time 18.18 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:24:36 AM PDT 24
Peak memory 249280 kb
Host smart-8c538d10-538c-40f4-b4ea-d7d4dbb5fc30
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=294988000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.294988000
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3916963464
Short name T598
Test name
Test status
Simulation time 977983679 ps
CPU time 7.51 seconds
Started Jul 01 11:24:08 AM PDT 24
Finished Jul 01 11:24:20 AM PDT 24
Peak memory 254840 kb
Host smart-db10732a-a2f2-4f29-8145-bede3bc4bb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39169
63464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3916963464
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.880711297
Short name T503
Test name
Test status
Simulation time 187617713 ps
CPU time 16.17 seconds
Started Jul 01 11:24:19 AM PDT 24
Finished Jul 01 11:24:38 AM PDT 24
Peak memory 248848 kb
Host smart-87bcc9e2-ba39-4364-b315-903adb99406b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88071
1297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.880711297
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2947766395
Short name T526
Test name
Test status
Simulation time 31235204639 ps
CPU time 1945.3 seconds
Started Jul 01 11:24:09 AM PDT 24
Finished Jul 01 11:56:39 AM PDT 24
Peak memory 290136 kb
Host smart-91051750-f5f5-4058-8bdb-1661da49e528
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947766395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2947766395
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1235216922
Short name T708
Test name
Test status
Simulation time 114179018289 ps
CPU time 1949.24 seconds
Started Jul 01 11:24:09 AM PDT 24
Finished Jul 01 11:56:43 AM PDT 24
Peak memory 286396 kb
Host smart-48679a06-9091-40d9-b398-f6f58c6b6f79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235216922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1235216922
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.481006866
Short name T283
Test name
Test status
Simulation time 11874029993 ps
CPU time 506.38 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:32:44 AM PDT 24
Peak memory 248264 kb
Host smart-fba12aed-cd9d-497b-b3ac-9b0a83100803
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481006866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.481006866
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.4100796825
Short name T384
Test name
Test status
Simulation time 932971419 ps
CPU time 13.91 seconds
Started Jul 01 11:24:16 AM PDT 24
Finished Jul 01 11:24:34 AM PDT 24
Peak memory 249172 kb
Host smart-cb54ae13-55e3-4343-9a0b-754832d6e68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41007
96825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.4100796825
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2154137481
Short name T374
Test name
Test status
Simulation time 849622342 ps
CPU time 14.3 seconds
Started Jul 01 11:24:12 AM PDT 24
Finished Jul 01 11:24:31 AM PDT 24
Peak memory 249108 kb
Host smart-19251158-787e-43f8-b890-a7bf158fc32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21541
37481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2154137481
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1636524675
Short name T35
Test name
Test status
Simulation time 1699761355 ps
CPU time 22.55 seconds
Started Jul 01 11:24:16 AM PDT 24
Finished Jul 01 11:24:43 AM PDT 24
Peak memory 274648 kb
Host smart-23d1b881-85a9-4aba-9a4f-f20084fcfe75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1636524675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1636524675
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3361980928
Short name T246
Test name
Test status
Simulation time 2987609680 ps
CPU time 24.48 seconds
Started Jul 01 11:24:11 AM PDT 24
Finished Jul 01 11:24:40 AM PDT 24
Peak memory 257484 kb
Host smart-ac5dfa86-8f4d-4091-975a-1a42db414263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33619
80928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3361980928
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3580482605
Short name T561
Test name
Test status
Simulation time 418612611 ps
CPU time 27.18 seconds
Started Jul 01 11:24:25 AM PDT 24
Finished Jul 01 11:24:55 AM PDT 24
Peak memory 257408 kb
Host smart-b5dcf336-4618-47a3-a27f-446c9f221ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35804
82605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3580482605
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1955986351
Short name T106
Test name
Test status
Simulation time 16141011758 ps
CPU time 1337.88 seconds
Started Jul 01 11:24:10 AM PDT 24
Finished Jul 01 11:46:33 AM PDT 24
Peak memory 289288 kb
Host smart-993e93d9-451c-4069-9ac9-3f7c44071175
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955986351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1955986351
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2558872026
Short name T491
Test name
Test status
Simulation time 4154689193 ps
CPU time 90.66 seconds
Started Jul 01 11:25:19 AM PDT 24
Finished Jul 01 11:26:53 AM PDT 24
Peak memory 257180 kb
Host smart-f9814821-adca-4b6d-8930-bb8c027d8cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25588
72026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2558872026
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.157315465
Short name T356
Test name
Test status
Simulation time 296192330 ps
CPU time 11.13 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:25:33 AM PDT 24
Peak memory 249256 kb
Host smart-2bd9ba55-8d35-4600-9472-af430607e354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15731
5465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.157315465
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.601420307
Short name T63
Test name
Test status
Simulation time 66545158594 ps
CPU time 1425.15 seconds
Started Jul 01 11:25:21 AM PDT 24
Finished Jul 01 11:49:10 AM PDT 24
Peak memory 289452 kb
Host smart-36dce74b-9c30-4804-9425-cd3929fe3b64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601420307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.601420307
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2525637954
Short name T218
Test name
Test status
Simulation time 30156421016 ps
CPU time 1310.46 seconds
Started Jul 01 11:25:20 AM PDT 24
Finished Jul 01 11:47:15 AM PDT 24
Peak memory 286420 kb
Host smart-2c2c0dc8-3a51-440c-b97a-128177122a3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525637954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2525637954
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3157600008
Short name T303
Test name
Test status
Simulation time 1863864858 ps
CPU time 83.83 seconds
Started Jul 01 11:25:19 AM PDT 24
Finished Jul 01 11:26:47 AM PDT 24
Peak memory 249212 kb
Host smart-6369db98-da45-490e-b7b0-3251291ef710
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157600008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3157600008
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4194381775
Short name T612
Test name
Test status
Simulation time 526857750 ps
CPU time 21.19 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:25:42 AM PDT 24
Peak memory 249336 kb
Host smart-08aafcca-e4c7-4f53-b374-9705981411e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41943
81775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4194381775
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3035119137
Short name T510
Test name
Test status
Simulation time 2443741504 ps
CPU time 12.76 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:25:34 AM PDT 24
Peak memory 254812 kb
Host smart-52079416-96da-42c0-b1cf-f20cda7a81ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30351
19137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3035119137
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.4043884685
Short name T234
Test name
Test status
Simulation time 674228545 ps
CPU time 47.01 seconds
Started Jul 01 11:25:17 AM PDT 24
Finished Jul 01 11:26:07 AM PDT 24
Peak memory 248944 kb
Host smart-b8242c24-d9e9-4827-b272-eece57cbbec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40438
84685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.4043884685
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1696602785
Short name T705
Test name
Test status
Simulation time 1341287256 ps
CPU time 14.03 seconds
Started Jul 01 11:25:19 AM PDT 24
Finished Jul 01 11:25:38 AM PDT 24
Peak memory 255180 kb
Host smart-dcb15b87-0370-4758-b4ed-70b238782c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16966
02785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1696602785
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2026455756
Short name T615
Test name
Test status
Simulation time 18198946400 ps
CPU time 563.87 seconds
Started Jul 01 11:25:18 AM PDT 24
Finished Jul 01 11:34:46 AM PDT 24
Peak memory 265828 kb
Host smart-8edf3bfe-07cd-4f7e-9d71-95d13afcfdd0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026455756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2026455756
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2021005340
Short name T687
Test name
Test status
Simulation time 52973429192 ps
CPU time 3190.61 seconds
Started Jul 01 11:25:19 AM PDT 24
Finished Jul 01 12:18:34 PM PDT 24
Peak memory 290152 kb
Host smart-f137a3c5-6b8a-4a0c-b696-236115a0c738
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021005340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2021005340
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2110606969
Short name T459
Test name
Test status
Simulation time 25178771425 ps
CPU time 312.28 seconds
Started Jul 01 11:25:19 AM PDT 24
Finished Jul 01 11:30:35 AM PDT 24
Peak memory 257596 kb
Host smart-0f58591a-e9e6-45f4-a31a-d39897c2f0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21106
06969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2110606969
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.83792576
Short name T61
Test name
Test status
Simulation time 759018028 ps
CPU time 41.66 seconds
Started Jul 01 11:25:27 AM PDT 24
Finished Jul 01 11:26:11 AM PDT 24
Peak memory 249096 kb
Host smart-9efe102c-70e0-4aba-aa68-a50a468c8102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83792
576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.83792576
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1803065380
Short name T317
Test name
Test status
Simulation time 32063462717 ps
CPU time 1867.95 seconds
Started Jul 01 11:25:20 AM PDT 24
Finished Jul 01 11:56:32 AM PDT 24
Peak memory 285444 kb
Host smart-4d3935c2-3f36-495d-a84e-c7a3f18a2f3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803065380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1803065380
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1338787530
Short name T102
Test name
Test status
Simulation time 16048907112 ps
CPU time 1398.26 seconds
Started Jul 01 11:25:22 AM PDT 24
Finished Jul 01 11:48:43 AM PDT 24
Peak memory 289432 kb
Host smart-8fe9cd17-ae66-4a33-ac7b-441490090ebe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338787530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1338787530
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2745181348
Short name T289
Test name
Test status
Simulation time 27671789066 ps
CPU time 320.66 seconds
Started Jul 01 11:25:20 AM PDT 24
Finished Jul 01 11:30:45 AM PDT 24
Peak memory 249384 kb
Host smart-0db1c2be-4b2b-40cb-9a12-cf2d52aa03e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745181348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2745181348
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1433661341
Short name T574
Test name
Test status
Simulation time 662226852 ps
CPU time 47.97 seconds
Started Jul 01 11:25:22 AM PDT 24
Finished Jul 01 11:26:13 AM PDT 24
Peak memory 257088 kb
Host smart-7833c53f-f8f4-47f0-afbe-b8110124824e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14336
61341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1433661341
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.849661735
Short name T46
Test name
Test status
Simulation time 4504050634 ps
CPU time 69.48 seconds
Started Jul 01 11:25:22 AM PDT 24
Finished Jul 01 11:26:35 AM PDT 24
Peak memory 249452 kb
Host smart-b86be31d-864e-4a76-8038-540a7759eaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84966
1735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.849661735
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2538709451
Short name T241
Test name
Test status
Simulation time 1269462885 ps
CPU time 23.55 seconds
Started Jul 01 11:25:21 AM PDT 24
Finished Jul 01 11:25:48 AM PDT 24
Peak memory 249348 kb
Host smart-925479f6-c387-465f-ad62-3321795f5e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25387
09451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2538709451
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.139369385
Short name T660
Test name
Test status
Simulation time 833193251 ps
CPU time 25 seconds
Started Jul 01 11:25:19 AM PDT 24
Finished Jul 01 11:25:47 AM PDT 24
Peak memory 257116 kb
Host smart-e2dbdb85-b159-4763-939e-ec008d8b6bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13936
9385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.139369385
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1922126250
Short name T237
Test name
Test status
Simulation time 76235048269 ps
CPU time 4703.42 seconds
Started Jul 01 11:25:22 AM PDT 24
Finished Jul 01 12:43:50 PM PDT 24
Peak memory 304584 kb
Host smart-df4ac040-36e8-40be-ac7a-bf20ea848d3d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922126250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1922126250
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3936502019
Short name T39
Test name
Test status
Simulation time 96014175992 ps
CPU time 1721.99 seconds
Started Jul 01 11:25:36 AM PDT 24
Finished Jul 01 11:54:21 AM PDT 24
Peak memory 273536 kb
Host smart-df7a4733-7168-4638-86d2-069f8e44fd04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936502019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3936502019
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1543583618
Short name T681
Test name
Test status
Simulation time 7917336777 ps
CPU time 65.88 seconds
Started Jul 01 11:25:26 AM PDT 24
Finished Jul 01 11:26:33 AM PDT 24
Peak memory 257572 kb
Host smart-3a8fb80c-86ae-4c66-963b-a187126f1848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15435
83618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1543583618
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.486901039
Short name T472
Test name
Test status
Simulation time 330015650 ps
CPU time 32.21 seconds
Started Jul 01 11:25:22 AM PDT 24
Finished Jul 01 11:25:57 AM PDT 24
Peak memory 249132 kb
Host smart-9e2bee22-3f0c-42c5-a56d-7132a20f9124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48690
1039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.486901039
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3124279502
Short name T7
Test name
Test status
Simulation time 40589004917 ps
CPU time 2479.8 seconds
Started Jul 01 11:25:24 AM PDT 24
Finished Jul 01 12:06:46 PM PDT 24
Peak memory 289356 kb
Host smart-7f5360dc-e8d1-4e5f-b918-5602b1d53a36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124279502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3124279502
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3585524639
Short name T621
Test name
Test status
Simulation time 69367308133 ps
CPU time 1432.58 seconds
Started Jul 01 11:25:41 AM PDT 24
Finished Jul 01 11:49:36 AM PDT 24
Peak memory 289704 kb
Host smart-4511baa7-db32-40fd-b69c-f6407cdbd58d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585524639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3585524639
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3877264958
Short name T282
Test name
Test status
Simulation time 29070689289 ps
CPU time 313.63 seconds
Started Jul 01 11:25:26 AM PDT 24
Finished Jul 01 11:30:41 AM PDT 24
Peak memory 249132 kb
Host smart-8a347f07-c0b8-49ac-809c-0389de40d055
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877264958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3877264958
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2881332957
Short name T41
Test name
Test status
Simulation time 3771651485 ps
CPU time 49.74 seconds
Started Jul 01 11:25:22 AM PDT 24
Finished Jul 01 11:26:15 AM PDT 24
Peak memory 256960 kb
Host smart-20ccd1fa-47e2-4e9b-b309-c7bd000adb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28813
32957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2881332957
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2981638632
Short name T572
Test name
Test status
Simulation time 12875233362 ps
CPU time 59.44 seconds
Started Jul 01 11:25:19 AM PDT 24
Finished Jul 01 11:26:23 AM PDT 24
Peak memory 257316 kb
Host smart-7b4077f1-9970-496b-b665-9aff4cd29695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29816
38632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2981638632
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4253015208
Short name T684
Test name
Test status
Simulation time 4702894190 ps
CPU time 27.13 seconds
Started Jul 01 11:25:32 AM PDT 24
Finished Jul 01 11:26:00 AM PDT 24
Peak memory 249020 kb
Host smart-9f9f07d3-ec58-44a3-9314-2c244e148028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42530
15208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4253015208
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.547623022
Short name T20
Test name
Test status
Simulation time 1095701348 ps
CPU time 18.33 seconds
Started Jul 01 11:25:22 AM PDT 24
Finished Jul 01 11:25:44 AM PDT 24
Peak memory 256388 kb
Host smart-d858fd9e-6cb8-446e-bcc5-015202432ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54762
3022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.547623022
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3513958331
Short name T564
Test name
Test status
Simulation time 272872578033 ps
CPU time 5630.17 seconds
Started Jul 01 11:25:35 AM PDT 24
Finished Jul 01 12:59:27 PM PDT 24
Peak memory 355760 kb
Host smart-3ceabf95-de28-4c79-af81-dcf10a2417cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513958331 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3513958331
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.739040313
Short name T104
Test name
Test status
Simulation time 104821172117 ps
CPU time 3032.28 seconds
Started Jul 01 11:25:27 AM PDT 24
Finished Jul 01 12:16:03 PM PDT 24
Peak memory 290320 kb
Host smart-66d0ed75-e927-4b3f-9112-15712674e5e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739040313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.739040313
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.701099887
Short name T600
Test name
Test status
Simulation time 7005915286 ps
CPU time 134.68 seconds
Started Jul 01 11:25:24 AM PDT 24
Finished Jul 01 11:27:41 AM PDT 24
Peak memory 257616 kb
Host smart-2077519a-4baa-43b3-bc08-cc9a450790a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70109
9887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.701099887
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1531033478
Short name T232
Test name
Test status
Simulation time 3471191742 ps
CPU time 24.11 seconds
Started Jul 01 11:25:26 AM PDT 24
Finished Jul 01 11:25:52 AM PDT 24
Peak memory 249228 kb
Host smart-9508672f-d6ca-43b0-bedb-2c096f187240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15310
33478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1531033478
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3935033920
Short name T323
Test name
Test status
Simulation time 8578551524 ps
CPU time 831.18 seconds
Started Jul 01 11:25:41 AM PDT 24
Finished Jul 01 11:39:34 AM PDT 24
Peak memory 274004 kb
Host smart-354073b3-47fc-4429-b771-91a0855a044a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935033920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3935033920
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2789456695
Short name T267
Test name
Test status
Simulation time 56276610279 ps
CPU time 3064.77 seconds
Started Jul 01 11:25:36 AM PDT 24
Finished Jul 01 12:16:43 PM PDT 24
Peak memory 290128 kb
Host smart-9406d8f7-4ee8-4ed1-aa96-7ae87b1b027b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789456695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2789456695
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2772836371
Short name T471
Test name
Test status
Simulation time 15299842737 ps
CPU time 164.03 seconds
Started Jul 01 11:25:30 AM PDT 24
Finished Jul 01 11:28:15 AM PDT 24
Peak memory 249404 kb
Host smart-0df83e54-3a6e-4817-8b97-17e4fea6a6a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772836371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2772836371
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2632363150
Short name T391
Test name
Test status
Simulation time 830507683 ps
CPU time 16.48 seconds
Started Jul 01 11:25:26 AM PDT 24
Finished Jul 01 11:25:44 AM PDT 24
Peak memory 254872 kb
Host smart-c36f46fd-08d6-4a91-b9d5-6dc1cb2e9b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26323
63150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2632363150
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.725791393
Short name T177
Test name
Test status
Simulation time 1142443934 ps
CPU time 31.81 seconds
Started Jul 01 11:25:40 AM PDT 24
Finished Jul 01 11:26:14 AM PDT 24
Peak memory 256964 kb
Host smart-22248e21-62ca-4232-8619-c24a60f2db08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72579
1393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.725791393
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2481944311
Short name T535
Test name
Test status
Simulation time 780292331 ps
CPU time 28.42 seconds
Started Jul 01 11:25:25 AM PDT 24
Finished Jul 01 11:25:55 AM PDT 24
Peak memory 248924 kb
Host smart-383b0087-c44a-47c0-8841-dbb0ebb8b6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24819
44311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2481944311
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1774536341
Short name T404
Test name
Test status
Simulation time 821175700 ps
CPU time 41.84 seconds
Started Jul 01 11:25:38 AM PDT 24
Finished Jul 01 11:26:22 AM PDT 24
Peak memory 257348 kb
Host smart-ca272622-ec1d-4630-8712-32f8c42c22c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17745
36341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1774536341
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4165361501
Short name T522
Test name
Test status
Simulation time 244495164782 ps
CPU time 3822.76 seconds
Started Jul 01 11:25:37 AM PDT 24
Finished Jul 01 12:29:23 PM PDT 24
Peak memory 290132 kb
Host smart-ec029aea-38ab-4de5-8575-1841839c0b39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165361501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4165361501
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3496176504
Short name T411
Test name
Test status
Simulation time 20773710481 ps
CPU time 622.41 seconds
Started Jul 01 11:25:37 AM PDT 24
Finished Jul 01 11:36:02 AM PDT 24
Peak memory 273972 kb
Host smart-c3602afe-0f85-41b4-9287-38d2745642c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496176504 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3496176504
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3670271836
Short name T680
Test name
Test status
Simulation time 73312815997 ps
CPU time 2327.62 seconds
Started Jul 01 11:25:42 AM PDT 24
Finished Jul 01 12:04:32 PM PDT 24
Peak memory 289688 kb
Host smart-af7da70d-5841-41d9-81c9-7065e4099bb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670271836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3670271836
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1947089572
Short name T515
Test name
Test status
Simulation time 6499817979 ps
CPU time 281.55 seconds
Started Jul 01 11:25:44 AM PDT 24
Finished Jul 01 11:30:28 AM PDT 24
Peak memory 256896 kb
Host smart-da380dca-dee2-4a36-a586-2fd6df6da713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19470
89572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1947089572
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1358765770
Short name T505
Test name
Test status
Simulation time 319777540 ps
CPU time 22.76 seconds
Started Jul 01 11:25:35 AM PDT 24
Finished Jul 01 11:26:00 AM PDT 24
Peak memory 249020 kb
Host smart-bc78980b-2996-4f2c-91ec-6d64425aa87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13587
65770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1358765770
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3849337546
Short name T371
Test name
Test status
Simulation time 47293053064 ps
CPU time 2653.7 seconds
Started Jul 01 11:25:37 AM PDT 24
Finished Jul 01 12:09:53 PM PDT 24
Peak memory 282064 kb
Host smart-fbde4f79-c881-46ef-9b41-f99a53c3c647
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849337546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3849337546
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2267788748
Short name T307
Test name
Test status
Simulation time 4879779025 ps
CPU time 207.04 seconds
Started Jul 01 11:25:39 AM PDT 24
Finished Jul 01 11:29:08 AM PDT 24
Peak memory 249424 kb
Host smart-d4c8c539-68ef-488a-827d-aacb2f7c2bca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267788748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2267788748
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2734971318
Short name T547
Test name
Test status
Simulation time 386723932 ps
CPU time 22.56 seconds
Started Jul 01 11:25:43 AM PDT 24
Finished Jul 01 11:26:07 AM PDT 24
Peak memory 256500 kb
Host smart-b20127ac-f7fa-470a-abf9-4d279ba3fafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27349
71318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2734971318
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1623430357
Short name T650
Test name
Test status
Simulation time 164799094 ps
CPU time 11.46 seconds
Started Jul 01 11:25:39 AM PDT 24
Finished Jul 01 11:25:52 AM PDT 24
Peak memory 254280 kb
Host smart-17180020-ba42-4fe7-8c12-20813740a671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16234
30357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1623430357
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3933223368
Short name T617
Test name
Test status
Simulation time 464188825 ps
CPU time 8.19 seconds
Started Jul 01 11:25:31 AM PDT 24
Finished Jul 01 11:25:40 AM PDT 24
Peak memory 252092 kb
Host smart-7a385a1b-9b19-47b9-8caf-41c1eaecf52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39332
23368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3933223368
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3152210811
Short name T343
Test name
Test status
Simulation time 1941601220 ps
CPU time 27.76 seconds
Started Jul 01 11:25:33 AM PDT 24
Finished Jul 01 11:26:02 AM PDT 24
Peak memory 256828 kb
Host smart-2cec7942-761a-4371-873a-ba7d14068ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31522
10811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3152210811
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.155750625
Short name T73
Test name
Test status
Simulation time 274936338694 ps
CPU time 3451.11 seconds
Started Jul 01 11:25:31 AM PDT 24
Finished Jul 01 12:23:03 PM PDT 24
Peak memory 305024 kb
Host smart-e3dc34f1-16f9-44e0-8d1d-100669a589a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155750625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.155750625
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2594138041
Short name T659
Test name
Test status
Simulation time 66434984106 ps
CPU time 2179.45 seconds
Started Jul 01 11:25:45 AM PDT 24
Finished Jul 01 12:02:07 PM PDT 24
Peak memory 289460 kb
Host smart-0e7860b4-70e5-4755-8287-da4defcc6fb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594138041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2594138041
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.299120462
Short name T217
Test name
Test status
Simulation time 2676982552 ps
CPU time 131.81 seconds
Started Jul 01 11:25:37 AM PDT 24
Finished Jul 01 11:27:51 AM PDT 24
Peak memory 251612 kb
Host smart-aca088f3-a567-4754-a73d-65478c5429d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29912
0462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.299120462
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2546559061
Short name T468
Test name
Test status
Simulation time 172808739 ps
CPU time 8.72 seconds
Started Jul 01 11:25:43 AM PDT 24
Finished Jul 01 11:25:53 AM PDT 24
Peak memory 249216 kb
Host smart-e1553722-eee5-4697-b851-559f36a36da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25465
59061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2546559061
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.181796836
Short name T707
Test name
Test status
Simulation time 45256559861 ps
CPU time 1023.25 seconds
Started Jul 01 11:25:36 AM PDT 24
Finished Jul 01 11:42:42 AM PDT 24
Peak memory 283252 kb
Host smart-28194cd3-5a57-493e-b70e-c003e0a75ff3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181796836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.181796836
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3764464371
Short name T445
Test name
Test status
Simulation time 77265451922 ps
CPU time 2255.61 seconds
Started Jul 01 11:25:36 AM PDT 24
Finished Jul 01 12:03:15 PM PDT 24
Peak memory 289616 kb
Host smart-3ee9a6d5-6ae1-483a-8f9d-de7f8272766f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764464371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3764464371
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3900427137
Short name T570
Test name
Test status
Simulation time 19538435270 ps
CPU time 398.46 seconds
Started Jul 01 11:25:48 AM PDT 24
Finished Jul 01 11:32:28 AM PDT 24
Peak memory 249412 kb
Host smart-5b3193f0-c4a4-4485-9448-c1b8fdaf25a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900427137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3900427137
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.982520851
Short name T56
Test name
Test status
Simulation time 1218160097 ps
CPU time 29.47 seconds
Started Jul 01 11:25:30 AM PDT 24
Finished Jul 01 11:26:00 AM PDT 24
Peak memory 257428 kb
Host smart-d1afd71e-73a9-4dee-af3c-10b47e3ac5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98252
0851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.982520851
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1042350242
Short name T559
Test name
Test status
Simulation time 138934471 ps
CPU time 9.53 seconds
Started Jul 01 11:25:36 AM PDT 24
Finished Jul 01 11:25:48 AM PDT 24
Peak memory 248820 kb
Host smart-7d76c338-b8ca-4a39-ab4d-c1a6570fddc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10423
50242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1042350242
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3437726412
Short name T271
Test name
Test status
Simulation time 437342346 ps
CPU time 34.06 seconds
Started Jul 01 11:25:41 AM PDT 24
Finished Jul 01 11:26:17 AM PDT 24
Peak memory 249328 kb
Host smart-3cfc9549-5a90-4d75-9c21-8e2f724e7c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34377
26412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3437726412
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2045343253
Short name T369
Test name
Test status
Simulation time 4615407974 ps
CPU time 23.56 seconds
Started Jul 01 11:25:31 AM PDT 24
Finished Jul 01 11:25:55 AM PDT 24
Peak memory 256540 kb
Host smart-38676638-4ac5-40a6-9767-9632f58807d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20453
43253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2045343253
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3866137545
Short name T387
Test name
Test status
Simulation time 53539964425 ps
CPU time 1739.71 seconds
Started Jul 01 11:25:47 AM PDT 24
Finished Jul 01 11:54:49 AM PDT 24
Peak memory 282220 kb
Host smart-a8030902-42ba-4a36-a707-50fa6cbe97ae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866137545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3866137545
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1042226505
Short name T378
Test name
Test status
Simulation time 36330188608 ps
CPU time 1874.29 seconds
Started Jul 01 11:25:41 AM PDT 24
Finished Jul 01 11:56:57 AM PDT 24
Peak memory 282144 kb
Host smart-70451cb9-bab3-4c65-bc7b-718395f37602
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042226505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1042226505
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.4153739008
Short name T577
Test name
Test status
Simulation time 3147317991 ps
CPU time 137.77 seconds
Started Jul 01 11:25:45 AM PDT 24
Finished Jul 01 11:28:05 AM PDT 24
Peak memory 257596 kb
Host smart-803e8ad3-79f0-4725-a6c3-4b37fae56cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41537
39008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4153739008
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.4231183737
Short name T433
Test name
Test status
Simulation time 103931882 ps
CPU time 10.13 seconds
Started Jul 01 11:25:37 AM PDT 24
Finished Jul 01 11:25:50 AM PDT 24
Peak memory 249684 kb
Host smart-b14137d8-5155-4502-bdcd-dd6c66a655ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42311
83737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.4231183737
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1432239170
Short name T643
Test name
Test status
Simulation time 40208600194 ps
CPU time 1190.21 seconds
Started Jul 01 11:25:46 AM PDT 24
Finished Jul 01 11:45:39 AM PDT 24
Peak memory 285272 kb
Host smart-6da11382-d94d-416e-9f19-4f37ea6b6831
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432239170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1432239170
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1204001603
Short name T301
Test name
Test status
Simulation time 9337959057 ps
CPU time 382.59 seconds
Started Jul 01 11:25:36 AM PDT 24
Finished Jul 01 11:32:02 AM PDT 24
Peak memory 249132 kb
Host smart-0dd8df3f-78c7-48ef-a1de-9d3c9183e374
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204001603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1204001603
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.490614066
Short name T532
Test name
Test status
Simulation time 29064390 ps
CPU time 3.89 seconds
Started Jul 01 11:25:45 AM PDT 24
Finished Jul 01 11:25:51 AM PDT 24
Peak memory 251432 kb
Host smart-230bae1a-fe72-443a-b796-70b6a048c66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49061
4066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.490614066
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3784135897
Short name T624
Test name
Test status
Simulation time 7302106084 ps
CPU time 42.93 seconds
Started Jul 01 11:25:35 AM PDT 24
Finished Jul 01 11:26:19 AM PDT 24
Peak memory 248644 kb
Host smart-cb7f6ccd-1f74-410c-a1af-4e8a5a365532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37841
35897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3784135897
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1903861963
Short name T359
Test name
Test status
Simulation time 240097113 ps
CPU time 10.18 seconds
Started Jul 01 11:25:38 AM PDT 24
Finished Jul 01 11:25:50 AM PDT 24
Peak memory 248820 kb
Host smart-5044b6cb-a20d-4b99-80fb-1cbba35f962f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19038
61963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1903861963
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.281558881
Short name T422
Test name
Test status
Simulation time 818754954 ps
CPU time 16.21 seconds
Started Jul 01 11:25:44 AM PDT 24
Finished Jul 01 11:26:02 AM PDT 24
Peak memory 256340 kb
Host smart-0ece0982-0528-41cf-8dee-e460bef4331e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28155
8881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.281558881
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1610861426
Short name T235
Test name
Test status
Simulation time 132492117081 ps
CPU time 6041.25 seconds
Started Jul 01 11:25:36 AM PDT 24
Finished Jul 01 01:06:20 PM PDT 24
Peak memory 331404 kb
Host smart-a06a6ca2-ddf0-45d1-bd94-9635f8c6291c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610861426 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1610861426
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3100316156
Short name T626
Test name
Test status
Simulation time 180306638030 ps
CPU time 2705.78 seconds
Started Jul 01 11:25:45 AM PDT 24
Finished Jul 01 12:10:53 PM PDT 24
Peak memory 282044 kb
Host smart-c602e72f-efd7-4e43-8463-db789f8c359e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100316156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3100316156
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1964440057
Short name T494
Test name
Test status
Simulation time 4083833943 ps
CPU time 57.41 seconds
Started Jul 01 11:25:40 AM PDT 24
Finished Jul 01 11:26:39 AM PDT 24
Peak memory 257568 kb
Host smart-fdd75436-2164-4877-a3a1-22ddcee476ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19644
40057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1964440057
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3410675755
Short name T599
Test name
Test status
Simulation time 476058259 ps
CPU time 21.24 seconds
Started Jul 01 11:25:36 AM PDT 24
Finished Jul 01 11:26:00 AM PDT 24
Peak memory 249244 kb
Host smart-8f567328-0b24-47b8-a881-bb02f00c9c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34106
75755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3410675755
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.4256595169
Short name T326
Test name
Test status
Simulation time 8104326941 ps
CPU time 711.48 seconds
Started Jul 01 11:25:38 AM PDT 24
Finished Jul 01 11:37:32 AM PDT 24
Peak memory 273320 kb
Host smart-1d2a23f2-d40f-46ce-9f15-1e6b1b6684b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256595169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.4256595169
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3003986985
Short name T344
Test name
Test status
Simulation time 12729759946 ps
CPU time 818.23 seconds
Started Jul 01 11:25:39 AM PDT 24
Finished Jul 01 11:39:19 AM PDT 24
Peak memory 271948 kb
Host smart-19cbe070-14e0-48c1-8565-ae11eed74cd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003986985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3003986985
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1009186681
Short name T310
Test name
Test status
Simulation time 26016758739 ps
CPU time 298 seconds
Started Jul 01 11:25:44 AM PDT 24
Finished Jul 01 11:30:43 AM PDT 24
Peak memory 249296 kb
Host smart-7ac0c7d2-561a-45de-b055-35ad70fac1b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009186681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1009186681
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3970747437
Short name T262
Test name
Test status
Simulation time 624997091 ps
CPU time 16.76 seconds
Started Jul 01 11:25:41 AM PDT 24
Finished Jul 01 11:26:00 AM PDT 24
Peak memory 249244 kb
Host smart-d908daf3-4549-4e50-9a80-d22547402c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39707
47437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3970747437
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3629981045
Short name T388
Test name
Test status
Simulation time 118602044 ps
CPU time 8.86 seconds
Started Jul 01 11:25:45 AM PDT 24
Finished Jul 01 11:25:55 AM PDT 24
Peak memory 248584 kb
Host smart-a622b7fa-ebd6-495d-83f6-e5ac4cbd4ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36299
81045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3629981045
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1870250867
Short name T449
Test name
Test status
Simulation time 111390142 ps
CPU time 8.62 seconds
Started Jul 01 11:25:53 AM PDT 24
Finished Jul 01 11:26:02 AM PDT 24
Peak memory 248600 kb
Host smart-2c0e43bc-0625-4a7a-9147-3f8b4f1c3fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18702
50867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1870250867
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.4087796505
Short name T38
Test name
Test status
Simulation time 219185191 ps
CPU time 11.22 seconds
Started Jul 01 11:25:35 AM PDT 24
Finished Jul 01 11:25:48 AM PDT 24
Peak memory 249284 kb
Host smart-8cd3856f-cc48-4cfe-8284-24607f24f9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40877
96505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.4087796505
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1887667661
Short name T249
Test name
Test status
Simulation time 75565547505 ps
CPU time 1687.17 seconds
Started Jul 01 11:25:38 AM PDT 24
Finished Jul 01 11:53:48 AM PDT 24
Peak memory 305160 kb
Host smart-7547afb2-a7cf-4377-a288-0256eb67410d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887667661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1887667661
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.546199262
Short name T511
Test name
Test status
Simulation time 80216643669 ps
CPU time 2426.9 seconds
Started Jul 01 11:25:47 AM PDT 24
Finished Jul 01 12:06:17 PM PDT 24
Peak memory 284416 kb
Host smart-45391078-7793-4ab2-a0e8-83de3bbdba52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546199262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.546199262
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1961078149
Short name T361
Test name
Test status
Simulation time 707826296 ps
CPU time 14.1 seconds
Started Jul 01 11:25:45 AM PDT 24
Finished Jul 01 11:26:01 AM PDT 24
Peak memory 255632 kb
Host smart-1ccec95d-1022-4c01-9a75-a13f4ac77c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19610
78149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1961078149
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.440271016
Short name T423
Test name
Test status
Simulation time 4309579874 ps
CPU time 55.54 seconds
Started Jul 01 11:25:40 AM PDT 24
Finished Jul 01 11:26:37 AM PDT 24
Peak memory 256780 kb
Host smart-f70ab02c-444f-45e3-a7dc-8125b9266e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44027
1016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.440271016
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2130666597
Short name T305
Test name
Test status
Simulation time 33307713250 ps
CPU time 1618.11 seconds
Started Jul 01 11:25:55 AM PDT 24
Finished Jul 01 11:52:55 AM PDT 24
Peak memory 273064 kb
Host smart-cad1c82d-9072-49b8-8835-2859257e2841
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130666597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2130666597
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2255573714
Short name T33
Test name
Test status
Simulation time 124765798684 ps
CPU time 2282.31 seconds
Started Jul 01 11:25:48 AM PDT 24
Finished Jul 01 12:03:53 PM PDT 24
Peak memory 285584 kb
Host smart-2aa0d6e7-42f9-47c3-ae89-9e0145df1269
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255573714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2255573714
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.774293560
Short name T527
Test name
Test status
Simulation time 44830313672 ps
CPU time 456.19 seconds
Started Jul 01 11:25:46 AM PDT 24
Finished Jul 01 11:33:25 AM PDT 24
Peak memory 248128 kb
Host smart-3f6f1570-250d-44d7-b96f-3362df30636c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774293560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.774293560
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2997216893
Short name T437
Test name
Test status
Simulation time 445298700 ps
CPU time 14.62 seconds
Started Jul 01 11:25:50 AM PDT 24
Finished Jul 01 11:26:06 AM PDT 24
Peak memory 249316 kb
Host smart-4ea500a0-5309-4a37-89eb-75beb3307e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29972
16893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2997216893
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.508099268
Short name T540
Test name
Test status
Simulation time 271065936 ps
CPU time 12.88 seconds
Started Jul 01 11:25:38 AM PDT 24
Finished Jul 01 11:25:53 AM PDT 24
Peak memory 248720 kb
Host smart-2acfefd3-5c00-4a27-9a97-8caf46281213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50809
9268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.508099268
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2046540725
Short name T442
Test name
Test status
Simulation time 320767123 ps
CPU time 37.84 seconds
Started Jul 01 11:25:45 AM PDT 24
Finished Jul 01 11:26:25 AM PDT 24
Peak memory 256996 kb
Host smart-bf088a4a-cd8b-4628-bdc7-fb4e975d1510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20465
40725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2046540725
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3024519267
Short name T75
Test name
Test status
Simulation time 911149248 ps
CPU time 55.65 seconds
Started Jul 01 11:25:44 AM PDT 24
Finished Jul 01 11:26:42 AM PDT 24
Peak memory 257468 kb
Host smart-3fcd483e-0b5b-479d-a071-18b3b519c9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30245
19267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3024519267
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.541442928
Short name T76
Test name
Test status
Simulation time 531794866213 ps
CPU time 2956.79 seconds
Started Jul 01 11:25:53 AM PDT 24
Finished Jul 01 12:15:11 PM PDT 24
Peak memory 290080 kb
Host smart-0db9e12d-5ece-4d58-ae65-85b87523fb8c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541442928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.541442928
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3717179125
Short name T90
Test name
Test status
Simulation time 30659399082 ps
CPU time 3295.71 seconds
Started Jul 01 11:25:45 AM PDT 24
Finished Jul 01 12:20:44 PM PDT 24
Peak memory 321672 kb
Host smart-07d512ce-ef05-4a68-a786-bda86f379a42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717179125 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3717179125
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2918283532
Short name T580
Test name
Test status
Simulation time 18568487024 ps
CPU time 1126.96 seconds
Started Jul 01 11:25:53 AM PDT 24
Finished Jul 01 11:44:41 AM PDT 24
Peak memory 273068 kb
Host smart-46999580-79a7-42b0-97e6-12a71d6c37d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918283532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2918283532
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1872170361
Short name T394
Test name
Test status
Simulation time 2532302769 ps
CPU time 158.4 seconds
Started Jul 01 11:25:53 AM PDT 24
Finished Jul 01 11:28:33 AM PDT 24
Peak memory 257560 kb
Host smart-f205733b-cb8c-4494-8801-172de0fb3aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18721
70361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1872170361
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1213445854
Short name T623
Test name
Test status
Simulation time 2224871958 ps
CPU time 38.45 seconds
Started Jul 01 11:25:49 AM PDT 24
Finished Jul 01 11:26:30 AM PDT 24
Peak memory 249372 kb
Host smart-87844925-470f-48d1-b71c-7bed43e793ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12134
45854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1213445854
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.624458762
Short name T221
Test name
Test status
Simulation time 43268625059 ps
CPU time 1646.94 seconds
Started Jul 01 11:25:49 AM PDT 24
Finished Jul 01 11:53:19 AM PDT 24
Peak memory 290256 kb
Host smart-243b19bd-bdf6-466e-a739-f930686e71dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624458762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.624458762
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1750914773
Short name T216
Test name
Test status
Simulation time 41893452752 ps
CPU time 2613.56 seconds
Started Jul 01 11:25:49 AM PDT 24
Finished Jul 01 12:09:25 PM PDT 24
Peak memory 285272 kb
Host smart-dc865891-4a32-49a9-860b-caefa8f29437
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750914773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1750914773
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3633192164
Short name T281
Test name
Test status
Simulation time 55127071497 ps
CPU time 554.35 seconds
Started Jul 01 11:25:48 AM PDT 24
Finished Jul 01 11:35:05 AM PDT 24
Peak memory 248508 kb
Host smart-7fb33fe5-ac86-46b3-a0c3-612f11ca3ded
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633192164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3633192164
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2496204188
Short name T450
Test name
Test status
Simulation time 837001481 ps
CPU time 48.12 seconds
Started Jul 01 11:25:46 AM PDT 24
Finished Jul 01 11:26:36 AM PDT 24
Peak memory 256568 kb
Host smart-b9a99679-1d8b-42a0-85df-91761b41f0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24962
04188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2496204188
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1050455899
Short name T668
Test name
Test status
Simulation time 368054044 ps
CPU time 35.58 seconds
Started Jul 01 11:25:52 AM PDT 24
Finished Jul 01 11:26:29 AM PDT 24
Peak memory 257264 kb
Host smart-9edd105e-f8bf-4361-9380-61403d6fd639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10504
55899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1050455899
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3006809066
Short name T252
Test name
Test status
Simulation time 515856792 ps
CPU time 30.7 seconds
Started Jul 01 11:25:55 AM PDT 24
Finished Jul 01 11:26:27 AM PDT 24
Peak memory 249012 kb
Host smart-d5b4d608-1488-4956-adb5-cce33c859f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30068
09066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3006809066
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.725587584
Short name T269
Test name
Test status
Simulation time 842465059 ps
CPU time 47.35 seconds
Started Jul 01 11:25:46 AM PDT 24
Finished Jul 01 11:26:35 AM PDT 24
Peak memory 257420 kb
Host smart-a84a2ad6-c37b-4e06-8b09-c271c4f08e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72558
7584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.725587584
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.544565935
Short name T613
Test name
Test status
Simulation time 78463936700 ps
CPU time 1605.08 seconds
Started Jul 01 11:25:53 AM PDT 24
Finished Jul 01 11:52:39 AM PDT 24
Peak memory 298592 kb
Host smart-440572d8-e8d1-4af4-9a9a-dde120fd67f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544565935 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.544565935
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2086664294
Short name T203
Test name
Test status
Simulation time 235287901 ps
CPU time 3.1 seconds
Started Jul 01 11:24:11 AM PDT 24
Finished Jul 01 11:24:19 AM PDT 24
Peak memory 249528 kb
Host smart-76158b9a-2124-450d-af03-196c560daf5c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2086664294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2086664294
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2500812668
Short name T268
Test name
Test status
Simulation time 43475142976 ps
CPU time 1389.64 seconds
Started Jul 01 11:24:09 AM PDT 24
Finished Jul 01 11:47:24 AM PDT 24
Peak memory 273200 kb
Host smart-c5f42797-12ce-423d-8dbe-1ae2a9878c97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500812668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2500812668
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2874049090
Short name T434
Test name
Test status
Simulation time 3383014500 ps
CPU time 69.5 seconds
Started Jul 01 11:24:09 AM PDT 24
Finished Jul 01 11:25:23 AM PDT 24
Peak memory 249460 kb
Host smart-b4ee72a1-5732-4452-9071-f7cae1c221c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2874049090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2874049090
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2903411344
Short name T592
Test name
Test status
Simulation time 4095235172 ps
CPU time 229.1 seconds
Started Jul 01 11:24:24 AM PDT 24
Finished Jul 01 11:28:16 AM PDT 24
Peak memory 256868 kb
Host smart-60944bad-aa8c-4717-8f91-0395dd06b603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29034
11344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2903411344
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.863927143
Short name T586
Test name
Test status
Simulation time 866252990 ps
CPU time 54.91 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:25:13 AM PDT 24
Peak memory 249312 kb
Host smart-60de39fd-a941-4599-8ccb-59a0c8f2bf58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86392
7143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.863927143
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2852179140
Short name T541
Test name
Test status
Simulation time 191896472164 ps
CPU time 1378.89 seconds
Started Jul 01 11:24:15 AM PDT 24
Finished Jul 01 11:47:18 AM PDT 24
Peak memory 289344 kb
Host smart-13289082-57db-42ab-b116-62ca15e9eac8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852179140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2852179140
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.249367397
Short name T539
Test name
Test status
Simulation time 21815915105 ps
CPU time 1369.03 seconds
Started Jul 01 11:24:21 AM PDT 24
Finished Jul 01 11:47:12 AM PDT 24
Peak memory 273908 kb
Host smart-bd41c192-cece-477c-a62e-e16680cd5150
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249367397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.249367397
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1226021699
Short name T311
Test name
Test status
Simulation time 14623224705 ps
CPU time 577.8 seconds
Started Jul 01 11:24:12 AM PDT 24
Finished Jul 01 11:33:54 AM PDT 24
Peak memory 249384 kb
Host smart-4f03f3a8-de7d-4a44-98e0-13f7f96ea9e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226021699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1226021699
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1057548072
Short name T545
Test name
Test status
Simulation time 324652682 ps
CPU time 11.44 seconds
Started Jul 01 11:24:32 AM PDT 24
Finished Jul 01 11:24:46 AM PDT 24
Peak memory 249316 kb
Host smart-2585cf73-a5e1-455e-bf96-f94055558b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10575
48072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1057548072
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.398748067
Short name T661
Test name
Test status
Simulation time 1146874495 ps
CPU time 28.83 seconds
Started Jul 01 11:24:07 AM PDT 24
Finished Jul 01 11:24:40 AM PDT 24
Peak memory 257264 kb
Host smart-e1f006e8-4591-42cc-a056-42bd933f789d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39874
8067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.398748067
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1995150768
Short name T13
Test name
Test status
Simulation time 1281814488 ps
CPU time 13.12 seconds
Started Jul 01 11:24:18 AM PDT 24
Finished Jul 01 11:24:34 AM PDT 24
Peak memory 271736 kb
Host smart-676d0964-540f-4731-bce5-855bfd1ba852
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1995150768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1995150768
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.745262542
Short name T655
Test name
Test status
Simulation time 194981512 ps
CPU time 21.32 seconds
Started Jul 01 11:24:19 AM PDT 24
Finished Jul 01 11:24:43 AM PDT 24
Peak memory 248756 kb
Host smart-925b001d-04b4-4499-a6d5-14bc78c2e4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74526
2542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.745262542
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1902677542
Short name T365
Test name
Test status
Simulation time 285812596 ps
CPU time 5.64 seconds
Started Jul 01 11:24:09 AM PDT 24
Finished Jul 01 11:24:19 AM PDT 24
Peak memory 251544 kb
Host smart-07757c07-2a16-4108-9f4c-de533ecb0a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19026
77542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1902677542
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3327672529
Short name T192
Test name
Test status
Simulation time 94383850349 ps
CPU time 3487.04 seconds
Started Jul 01 11:24:39 AM PDT 24
Finished Jul 01 12:22:48 PM PDT 24
Peak memory 306732 kb
Host smart-5fb02060-0d43-490c-8764-f22a15eabb34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327672529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3327672529
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3040188479
Short name T710
Test name
Test status
Simulation time 35757420200 ps
CPU time 3933.67 seconds
Started Jul 01 11:24:19 AM PDT 24
Finished Jul 01 12:29:56 PM PDT 24
Peak memory 338460 kb
Host smart-9e37bb2c-5d14-4a8a-b752-292aa368bb75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040188479 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3040188479
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2342500623
Short name T17
Test name
Test status
Simulation time 29719816462 ps
CPU time 1418.48 seconds
Started Jul 01 11:25:55 AM PDT 24
Finished Jul 01 11:49:35 AM PDT 24
Peak memory 289320 kb
Host smart-f40c3556-407d-4de5-a37d-ceb8eedbc8c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342500623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2342500623
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3498803284
Short name T493
Test name
Test status
Simulation time 1990492227 ps
CPU time 168.34 seconds
Started Jul 01 11:25:50 AM PDT 24
Finished Jul 01 11:28:40 AM PDT 24
Peak memory 252360 kb
Host smart-375df492-2448-4a3a-ac22-88e50c03453a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34988
03284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3498803284
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.4015980487
Short name T421
Test name
Test status
Simulation time 68938813 ps
CPU time 4.98 seconds
Started Jul 01 11:25:55 AM PDT 24
Finished Jul 01 11:26:02 AM PDT 24
Peak memory 241044 kb
Host smart-6d4682ea-33cd-4c39-92fa-8b3157f931f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40159
80487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.4015980487
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2792793957
Short name T699
Test name
Test status
Simulation time 32266475605 ps
CPU time 2093.09 seconds
Started Jul 01 11:25:54 AM PDT 24
Finished Jul 01 12:00:49 PM PDT 24
Peak memory 287712 kb
Host smart-01d82629-e207-44ca-be4f-0f4daa398bb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792793957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2792793957
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3537450294
Short name T591
Test name
Test status
Simulation time 37259804242 ps
CPU time 2315.86 seconds
Started Jul 01 11:25:54 AM PDT 24
Finished Jul 01 12:04:32 PM PDT 24
Peak memory 282204 kb
Host smart-6cc59f76-52bb-436b-b4ac-8c4fa963ff34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537450294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3537450294
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3305208005
Short name T673
Test name
Test status
Simulation time 3215354302 ps
CPU time 128.38 seconds
Started Jul 01 11:25:51 AM PDT 24
Finished Jul 01 11:28:01 AM PDT 24
Peak memory 255668 kb
Host smart-fe3f1f8c-41db-455c-812f-ae2e5c5d5e78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305208005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3305208005
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1882066724
Short name T400
Test name
Test status
Simulation time 480164197 ps
CPU time 26.87 seconds
Started Jul 01 11:25:48 AM PDT 24
Finished Jul 01 11:26:18 AM PDT 24
Peak memory 256708 kb
Host smart-859ff8af-9199-45e4-ab54-d741c4e2e194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18820
66724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1882066724
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3971910980
Short name T571
Test name
Test status
Simulation time 996302223 ps
CPU time 60.13 seconds
Started Jul 01 11:25:56 AM PDT 24
Finished Jul 01 11:26:57 AM PDT 24
Peak memory 257384 kb
Host smart-48c8c367-77ec-4876-96d5-33210b482f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39719
10980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3971910980
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2067509446
Short name T606
Test name
Test status
Simulation time 2908729917 ps
CPU time 47.99 seconds
Started Jul 01 11:25:51 AM PDT 24
Finished Jul 01 11:26:41 AM PDT 24
Peak memory 248576 kb
Host smart-c154c4f1-1630-4043-9323-56927b688d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20675
09446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2067509446
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.816616160
Short name T490
Test name
Test status
Simulation time 6321573036 ps
CPU time 60.15 seconds
Started Jul 01 11:25:54 AM PDT 24
Finished Jul 01 11:26:56 AM PDT 24
Peak memory 257588 kb
Host smart-7dd726c3-a2c1-4588-bd57-240b1ac15eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81661
6160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.816616160
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2756021857
Short name T42
Test name
Test status
Simulation time 7772068931 ps
CPU time 923.74 seconds
Started Jul 01 11:25:55 AM PDT 24
Finished Jul 01 11:41:20 AM PDT 24
Peak memory 273664 kb
Host smart-ae7e4251-00ca-4f66-8037-b8f1742480e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756021857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2756021857
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1222122877
Short name T6
Test name
Test status
Simulation time 33792349945 ps
CPU time 1598.06 seconds
Started Jul 01 11:25:56 AM PDT 24
Finished Jul 01 11:52:35 AM PDT 24
Peak memory 289396 kb
Host smart-d250b827-064a-487d-8a1f-5e69e19979e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222122877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1222122877
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3036460813
Short name T677
Test name
Test status
Simulation time 504466743 ps
CPU time 25.4 seconds
Started Jul 01 11:25:56 AM PDT 24
Finished Jul 01 11:26:22 AM PDT 24
Peak memory 256680 kb
Host smart-ba3b1b34-0a80-4dee-9343-99c027c6d3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30364
60813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3036460813
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.293439935
Short name T1
Test name
Test status
Simulation time 302558366 ps
CPU time 23.79 seconds
Started Jul 01 11:25:54 AM PDT 24
Finished Jul 01 11:26:20 AM PDT 24
Peak memory 257224 kb
Host smart-f66a5aa6-a5ae-4688-b8c5-7a8a5ec63c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29343
9935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.293439935
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.389150092
Short name T270
Test name
Test status
Simulation time 9949404944 ps
CPU time 919.23 seconds
Started Jul 01 11:25:56 AM PDT 24
Finished Jul 01 11:41:17 AM PDT 24
Peak memory 273668 kb
Host smart-58028edc-0901-4adf-a499-e492e95cf9f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389150092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.389150092
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3269993758
Short name T10
Test name
Test status
Simulation time 5782087184 ps
CPU time 89.27 seconds
Started Jul 01 11:25:54 AM PDT 24
Finished Jul 01 11:27:25 AM PDT 24
Peak memory 248304 kb
Host smart-e75b614f-0953-4971-bd77-d3ea6d770433
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269993758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3269993758
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3940923274
Short name T364
Test name
Test status
Simulation time 476361666 ps
CPU time 44.13 seconds
Started Jul 01 11:26:00 AM PDT 24
Finished Jul 01 11:26:45 AM PDT 24
Peak memory 256772 kb
Host smart-72a5fad5-b14c-42e9-90fa-b6138cce6215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39409
23274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3940923274
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2768097345
Short name T32
Test name
Test status
Simulation time 422069945 ps
CPU time 26.88 seconds
Started Jul 01 11:25:54 AM PDT 24
Finished Jul 01 11:26:23 AM PDT 24
Peak memory 256884 kb
Host smart-3f993c7b-6293-4f79-9ba4-de09fd298518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27680
97345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2768097345
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1523590868
Short name T108
Test name
Test status
Simulation time 2316663425 ps
CPU time 16.42 seconds
Started Jul 01 11:25:56 AM PDT 24
Finished Jul 01 11:26:13 AM PDT 24
Peak memory 249420 kb
Host smart-cb397e9b-2f53-4eb0-8227-308c4a5577ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15235
90868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1523590868
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2452344466
Short name T441
Test name
Test status
Simulation time 1469299464 ps
CPU time 37.26 seconds
Started Jul 01 11:25:54 AM PDT 24
Finished Jul 01 11:26:33 AM PDT 24
Peak memory 249336 kb
Host smart-3dd5c2f9-515e-4c6f-9638-731047d8ec10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24523
44466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2452344466
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3991822870
Short name T233
Test name
Test status
Simulation time 74524713335 ps
CPU time 1599.1 seconds
Started Jul 01 11:25:54 AM PDT 24
Finished Jul 01 11:52:35 AM PDT 24
Peak memory 289616 kb
Host smart-5522908b-a6f3-4960-a63a-16d27fe95cde
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991822870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3991822870
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3783484261
Short name T642
Test name
Test status
Simulation time 196238638084 ps
CPU time 2338.47 seconds
Started Jul 01 11:26:01 AM PDT 24
Finished Jul 01 12:05:01 PM PDT 24
Peak memory 286092 kb
Host smart-3414929a-d055-49cf-a85b-e50fddba1486
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783484261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3783484261
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.824011765
Short name T375
Test name
Test status
Simulation time 3629636988 ps
CPU time 166.38 seconds
Started Jul 01 11:26:01 AM PDT 24
Finished Jul 01 11:28:49 AM PDT 24
Peak memory 257160 kb
Host smart-d0579e53-5782-4804-b394-c8d1dde493df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82401
1765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.824011765
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3965327490
Short name T689
Test name
Test status
Simulation time 16618310 ps
CPU time 2.89 seconds
Started Jul 01 11:26:01 AM PDT 24
Finished Jul 01 11:26:05 AM PDT 24
Peak memory 240564 kb
Host smart-7faf5a8c-635c-4cde-ad49-86ad966036b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39653
27490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3965327490
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.192994480
Short name T667
Test name
Test status
Simulation time 27231238779 ps
CPU time 1110.01 seconds
Started Jul 01 11:26:02 AM PDT 24
Finished Jul 01 11:44:34 AM PDT 24
Peak memory 290136 kb
Host smart-f8bb8acc-2692-4c00-a3cd-aa81b03a3644
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192994480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.192994480
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2439256651
Short name T67
Test name
Test status
Simulation time 8232818689 ps
CPU time 662.23 seconds
Started Jul 01 11:26:01 AM PDT 24
Finished Jul 01 11:37:04 AM PDT 24
Peak memory 273356 kb
Host smart-fd3c5944-cfbe-43bb-a8af-3529b6a3fa7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439256651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2439256651
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.4192008092
Short name T648
Test name
Test status
Simulation time 36411439677 ps
CPU time 439.31 seconds
Started Jul 01 11:26:04 AM PDT 24
Finished Jul 01 11:33:24 AM PDT 24
Peak memory 249096 kb
Host smart-00633633-ab88-4480-8cbd-05ca00a8178b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192008092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.4192008092
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1229573053
Short name T486
Test name
Test status
Simulation time 286020458 ps
CPU time 28.04 seconds
Started Jul 01 11:25:57 AM PDT 24
Finished Jul 01 11:26:26 AM PDT 24
Peak memory 256576 kb
Host smart-0a799b1c-1a86-4aea-9950-7ae376b7570c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12295
73053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1229573053
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.4200228988
Short name T383
Test name
Test status
Simulation time 1867541140 ps
CPU time 32.13 seconds
Started Jul 01 11:26:00 AM PDT 24
Finished Jul 01 11:26:33 AM PDT 24
Peak memory 256848 kb
Host smart-394c18b7-193f-4229-ae2b-3a90eb8a011d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42002
28988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.4200228988
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.691695429
Short name T245
Test name
Test status
Simulation time 558979383 ps
CPU time 36.74 seconds
Started Jul 01 11:25:59 AM PDT 24
Finished Jul 01 11:26:36 AM PDT 24
Peak memory 249232 kb
Host smart-980cb937-90bc-443c-9eba-2fabb0880598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69169
5429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.691695429
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1720632631
Short name T703
Test name
Test status
Simulation time 148130823 ps
CPU time 4.27 seconds
Started Jul 01 11:25:57 AM PDT 24
Finished Jul 01 11:26:02 AM PDT 24
Peak memory 250644 kb
Host smart-4f5c9785-fe2f-4c8a-b276-df5225bb5b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17206
32631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1720632631
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2008930000
Short name T82
Test name
Test status
Simulation time 26988872779 ps
CPU time 370.06 seconds
Started Jul 01 11:26:01 AM PDT 24
Finished Jul 01 11:32:12 AM PDT 24
Peak memory 257652 kb
Host smart-ad9233b5-144d-4604-80c8-20f3e0375af9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008930000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2008930000
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2433930845
Short name T258
Test name
Test status
Simulation time 144534754635 ps
CPU time 2533.01 seconds
Started Jul 01 11:26:03 AM PDT 24
Finished Jul 01 12:08:17 PM PDT 24
Peak memory 289524 kb
Host smart-05d6a478-f13f-45d3-86e4-945684f5a134
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433930845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2433930845
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1571990451
Short name T455
Test name
Test status
Simulation time 2113918336 ps
CPU time 152.74 seconds
Started Jul 01 11:26:03 AM PDT 24
Finished Jul 01 11:28:37 AM PDT 24
Peak memory 257444 kb
Host smart-7040909b-574e-4247-ac9b-cbf3f66422b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15719
90451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1571990451
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2704774553
Short name T582
Test name
Test status
Simulation time 5182056188 ps
CPU time 76.3 seconds
Started Jul 01 11:26:01 AM PDT 24
Finished Jul 01 11:27:19 AM PDT 24
Peak memory 249048 kb
Host smart-1c0e3fcf-6069-4688-94aa-85e83e6851ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27047
74553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2704774553
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2546912267
Short name T324
Test name
Test status
Simulation time 135260749082 ps
CPU time 1970.18 seconds
Started Jul 01 11:26:06 AM PDT 24
Finished Jul 01 11:58:58 AM PDT 24
Peak memory 273980 kb
Host smart-63f5aff0-5bd8-4bd3-ab6b-7770de329d7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546912267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2546912267
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2006143571
Short name T29
Test name
Test status
Simulation time 144465351949 ps
CPU time 1409.2 seconds
Started Jul 01 11:26:07 AM PDT 24
Finished Jul 01 11:49:37 AM PDT 24
Peak memory 273540 kb
Host smart-7bee32b1-6c16-447b-a964-7715b93625c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006143571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2006143571
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1526761317
Short name T461
Test name
Test status
Simulation time 271085700 ps
CPU time 18.47 seconds
Started Jul 01 11:26:00 AM PDT 24
Finished Jul 01 11:26:19 AM PDT 24
Peak memory 249312 kb
Host smart-1d389347-92e5-4400-a058-94b9f3e82f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15267
61317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1526761317
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1369827021
Short name T636
Test name
Test status
Simulation time 262850679 ps
CPU time 12.82 seconds
Started Jul 01 11:26:01 AM PDT 24
Finished Jul 01 11:26:15 AM PDT 24
Peak memory 257036 kb
Host smart-55d750cd-e89d-402d-8e17-26491ff49449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13698
27021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1369827021
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2182452544
Short name T428
Test name
Test status
Simulation time 245083577 ps
CPU time 30.82 seconds
Started Jul 01 11:26:00 AM PDT 24
Finished Jul 01 11:26:32 AM PDT 24
Peak memory 249252 kb
Host smart-925ceca5-20f5-48e3-893d-06fe667f7372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21824
52544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2182452544
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3079872321
Short name T674
Test name
Test status
Simulation time 642239456 ps
CPU time 36.93 seconds
Started Jul 01 11:26:04 AM PDT 24
Finished Jul 01 11:26:41 AM PDT 24
Peak memory 256944 kb
Host smart-5e98dc56-dbae-4507-94b6-349d74bfdc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30798
72321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3079872321
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3512136236
Short name T481
Test name
Test status
Simulation time 13409641006 ps
CPU time 1203.94 seconds
Started Jul 01 11:26:05 AM PDT 24
Finished Jul 01 11:46:10 AM PDT 24
Peak memory 286668 kb
Host smart-8615506b-3699-4c7f-ae2c-9c72d40ce97c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512136236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3512136236
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1418675814
Short name T68
Test name
Test status
Simulation time 19784289214 ps
CPU time 1092.33 seconds
Started Jul 01 11:26:14 AM PDT 24
Finished Jul 01 11:44:27 AM PDT 24
Peak memory 272252 kb
Host smart-50a3ff42-ef7d-431b-9d80-aeef137638a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418675814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1418675814
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2852146772
Short name T593
Test name
Test status
Simulation time 2678509304 ps
CPU time 76.21 seconds
Started Jul 01 11:26:08 AM PDT 24
Finished Jul 01 11:27:25 AM PDT 24
Peak memory 257576 kb
Host smart-7226ee7d-884e-4abd-907c-c00b2f9e4584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28521
46772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2852146772
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3871641630
Short name T460
Test name
Test status
Simulation time 22802922145 ps
CPU time 63.9 seconds
Started Jul 01 11:26:10 AM PDT 24
Finished Jul 01 11:27:15 AM PDT 24
Peak memory 256768 kb
Host smart-3ffb99b8-841d-4f6a-aec1-9e3f3a8c399e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38716
41630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3871641630
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1529843577
Short name T295
Test name
Test status
Simulation time 45618065323 ps
CPU time 831.3 seconds
Started Jul 01 11:26:13 AM PDT 24
Finished Jul 01 11:40:05 AM PDT 24
Peak memory 270880 kb
Host smart-eacc4fca-0980-48a1-9ea4-ad1f126648e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529843577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1529843577
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3993387612
Short name T413
Test name
Test status
Simulation time 304892229095 ps
CPU time 2486.05 seconds
Started Jul 01 11:26:12 AM PDT 24
Finished Jul 01 12:07:39 PM PDT 24
Peak memory 273952 kb
Host smart-46a3bbd0-b9ad-41ef-a975-f5ceb6834628
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993387612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3993387612
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1925832137
Short name T631
Test name
Test status
Simulation time 14294127965 ps
CPU time 569.29 seconds
Started Jul 01 11:26:12 AM PDT 24
Finished Jul 01 11:35:43 AM PDT 24
Peak memory 249332 kb
Host smart-c2566ec0-fda0-4aa0-bbda-cefd9dd34dd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925832137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1925832137
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.119199390
Short name T638
Test name
Test status
Simulation time 1213448017 ps
CPU time 70.17 seconds
Started Jul 01 11:26:06 AM PDT 24
Finished Jul 01 11:27:17 AM PDT 24
Peak memory 256800 kb
Host smart-c41e9278-6730-45fd-8743-01985f93a227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11919
9390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.119199390
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3108969562
Short name T607
Test name
Test status
Simulation time 444504666 ps
CPU time 8.73 seconds
Started Jul 01 11:26:07 AM PDT 24
Finished Jul 01 11:26:16 AM PDT 24
Peak memory 252420 kb
Host smart-9148f377-9e94-4bce-84c9-b4e789e1738c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31089
69562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3108969562
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.932296447
Short name T229
Test name
Test status
Simulation time 2176428227 ps
CPU time 69.55 seconds
Started Jul 01 11:26:12 AM PDT 24
Finished Jul 01 11:27:22 AM PDT 24
Peak memory 256792 kb
Host smart-e8c1c5e2-5cbf-4cfa-8c3c-c4aa306642c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93229
6447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.932296447
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1760611423
Short name T354
Test name
Test status
Simulation time 8174083120 ps
CPU time 50.04 seconds
Started Jul 01 11:26:06 AM PDT 24
Finished Jul 01 11:26:57 AM PDT 24
Peak memory 249356 kb
Host smart-3752f0a7-86ff-4e11-9f66-17c31130cb8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17606
11423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1760611423
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3935405629
Short name T625
Test name
Test status
Simulation time 2729461880 ps
CPU time 65.43 seconds
Started Jul 01 11:26:10 AM PDT 24
Finished Jul 01 11:27:17 AM PDT 24
Peak memory 257628 kb
Host smart-5bec884a-6f60-4013-a228-fd8ce9595af9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935405629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3935405629
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1361872589
Short name T187
Test name
Test status
Simulation time 281106153706 ps
CPU time 2180.15 seconds
Started Jul 01 11:26:11 AM PDT 24
Finished Jul 01 12:02:33 PM PDT 24
Peak memory 306624 kb
Host smart-53d8c40a-9aa8-45ac-aba5-6872bce83b42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361872589 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1361872589
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3450091022
Short name T14
Test name
Test status
Simulation time 26646191247 ps
CPU time 1765.49 seconds
Started Jul 01 11:26:09 AM PDT 24
Finished Jul 01 11:55:36 AM PDT 24
Peak memory 290372 kb
Host smart-8a5f3b6a-ee87-4169-bce1-fb721057de56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450091022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3450091022
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2788086608
Short name T573
Test name
Test status
Simulation time 460170276 ps
CPU time 38.84 seconds
Started Jul 01 11:26:09 AM PDT 24
Finished Jul 01 11:26:49 AM PDT 24
Peak memory 257476 kb
Host smart-2f9f8fd3-0ab6-4709-9c59-06a37f23a2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27880
86608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2788086608
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1357059690
Short name T72
Test name
Test status
Simulation time 438320228 ps
CPU time 23.63 seconds
Started Jul 01 11:26:10 AM PDT 24
Finished Jul 01 11:26:34 AM PDT 24
Peak memory 249156 kb
Host smart-da61040a-974c-40ea-883c-d5cd011763c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13570
59690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1357059690
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.282209228
Short name T700
Test name
Test status
Simulation time 73305433321 ps
CPU time 2332.22 seconds
Started Jul 01 11:26:12 AM PDT 24
Finished Jul 01 12:05:06 PM PDT 24
Peak memory 290024 kb
Host smart-ecd03621-1f21-49da-b722-86643db86d72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282209228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.282209228
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.844311092
Short name T99
Test name
Test status
Simulation time 17152367737 ps
CPU time 1347.73 seconds
Started Jul 01 11:26:11 AM PDT 24
Finished Jul 01 11:48:40 AM PDT 24
Peak memory 273720 kb
Host smart-088b11f2-7f11-461a-9e22-054aee08d378
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844311092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.844311092
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1158131474
Short name T308
Test name
Test status
Simulation time 14480696258 ps
CPU time 566.98 seconds
Started Jul 01 11:26:10 AM PDT 24
Finished Jul 01 11:35:39 AM PDT 24
Peak memory 249112 kb
Host smart-76812514-91c5-45c6-a490-c85bfbc5c0bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158131474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1158131474
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.4116623709
Short name T401
Test name
Test status
Simulation time 182639183 ps
CPU time 12.76 seconds
Started Jul 01 11:26:09 AM PDT 24
Finished Jul 01 11:26:23 AM PDT 24
Peak memory 255060 kb
Host smart-35de040c-3607-42a8-9f8d-12007a9dba0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41166
23709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.4116623709
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2034238782
Short name T654
Test name
Test status
Simulation time 2778946685 ps
CPU time 30.59 seconds
Started Jul 01 11:26:11 AM PDT 24
Finished Jul 01 11:26:43 AM PDT 24
Peak memory 257116 kb
Host smart-12d46119-87ca-43f5-989c-be177f1bd4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20342
38782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2034238782
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1436812563
Short name T675
Test name
Test status
Simulation time 774828170 ps
CPU time 56.55 seconds
Started Jul 01 11:26:11 AM PDT 24
Finished Jul 01 11:27:09 AM PDT 24
Peak memory 256612 kb
Host smart-1bd1dbba-15df-4cdd-9c9e-7aaf81f5a9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14368
12563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1436812563
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2822468161
Short name T534
Test name
Test status
Simulation time 69500547 ps
CPU time 8.38 seconds
Started Jul 01 11:26:10 AM PDT 24
Finished Jul 01 11:26:20 AM PDT 24
Peak memory 249152 kb
Host smart-efb78d57-903d-44f6-af35-515c6ad34bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28224
68161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2822468161
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2254598954
Short name T276
Test name
Test status
Simulation time 535973465 ps
CPU time 47.62 seconds
Started Jul 01 11:26:15 AM PDT 24
Finished Jul 01 11:27:05 AM PDT 24
Peak memory 257532 kb
Host smart-7d373fdb-0e45-490d-acf3-b12366dbee2c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254598954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2254598954
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1787249399
Short name T226
Test name
Test status
Simulation time 23025533857 ps
CPU time 746.54 seconds
Started Jul 01 11:26:15 AM PDT 24
Finished Jul 01 11:38:44 AM PDT 24
Peak memory 268700 kb
Host smart-698b0abf-3816-452b-928c-5e4a6ee84b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787249399 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1787249399
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3298984766
Short name T506
Test name
Test status
Simulation time 8137508985 ps
CPU time 956.26 seconds
Started Jul 01 11:26:15 AM PDT 24
Finished Jul 01 11:42:14 AM PDT 24
Peak memory 285704 kb
Host smart-6763f159-6ea4-4b20-a2f7-8abcbd58e776
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298984766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3298984766
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3794627074
Short name T524
Test name
Test status
Simulation time 7050175596 ps
CPU time 158.94 seconds
Started Jul 01 11:26:15 AM PDT 24
Finished Jul 01 11:28:56 AM PDT 24
Peak memory 257716 kb
Host smart-1b146c0a-992f-4aa5-a99f-5c0d42e292fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37946
27074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3794627074
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1749564842
Short name T353
Test name
Test status
Simulation time 134878702 ps
CPU time 9.93 seconds
Started Jul 01 11:26:15 AM PDT 24
Finished Jul 01 11:26:27 AM PDT 24
Peak memory 248784 kb
Host smart-c79d6cc7-eeac-41a5-ad14-adfeb3a29ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17495
64842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1749564842
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3298757615
Short name T94
Test name
Test status
Simulation time 12085175995 ps
CPU time 923.3 seconds
Started Jul 01 11:26:23 AM PDT 24
Finished Jul 01 11:41:48 AM PDT 24
Peak memory 273232 kb
Host smart-10a1a0d9-30ee-4e29-a2d9-3285385d7820
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298757615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3298757615
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.729109812
Short name T629
Test name
Test status
Simulation time 124389609281 ps
CPU time 2040.45 seconds
Started Jul 01 11:26:20 AM PDT 24
Finished Jul 01 12:00:22 PM PDT 24
Peak memory 288204 kb
Host smart-ce281c06-3a5c-4b63-9c4c-6d8b2d3e8462
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729109812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.729109812
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2214147236
Short name T294
Test name
Test status
Simulation time 14506332048 ps
CPU time 430.45 seconds
Started Jul 01 11:26:15 AM PDT 24
Finished Jul 01 11:33:27 AM PDT 24
Peak memory 249472 kb
Host smart-d4f10985-5eae-432f-86c3-b8567b02675a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214147236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2214147236
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2697270719
Short name T19
Test name
Test status
Simulation time 3687290874 ps
CPU time 54.44 seconds
Started Jul 01 11:26:13 AM PDT 24
Finished Jul 01 11:27:08 AM PDT 24
Peak memory 257644 kb
Host smart-2997dd7a-d624-499c-b64b-3caa8d70843e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26972
70719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2697270719
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3957429696
Short name T558
Test name
Test status
Simulation time 1171038792 ps
CPU time 41.2 seconds
Started Jul 01 11:26:15 AM PDT 24
Finished Jul 01 11:26:57 AM PDT 24
Peak memory 248928 kb
Host smart-8664a4c4-84b5-4a1c-a291-ad003ad417fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39574
29696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3957429696
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.544620413
Short name T469
Test name
Test status
Simulation time 813345874 ps
CPU time 12.57 seconds
Started Jul 01 11:26:14 AM PDT 24
Finished Jul 01 11:26:27 AM PDT 24
Peak memory 253892 kb
Host smart-97428b77-3404-4e88-a48a-28fb2f8b6683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54462
0413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.544620413
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1611127458
Short name T542
Test name
Test status
Simulation time 428820447 ps
CPU time 15.63 seconds
Started Jul 01 11:26:15 AM PDT 24
Finished Jul 01 11:26:33 AM PDT 24
Peak memory 256796 kb
Host smart-07b3227f-8892-4134-95e0-122d572b1da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16111
27458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1611127458
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3298802580
Short name T247
Test name
Test status
Simulation time 19035588092 ps
CPU time 555.73 seconds
Started Jul 01 11:26:20 AM PDT 24
Finished Jul 01 11:35:37 AM PDT 24
Peak memory 265792 kb
Host smart-c0511427-5b0d-4148-9ba5-6a1b22b25b14
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298802580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3298802580
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3966547073
Short name T215
Test name
Test status
Simulation time 15892516548 ps
CPU time 1168.3 seconds
Started Jul 01 11:26:22 AM PDT 24
Finished Jul 01 11:45:51 AM PDT 24
Peak memory 273476 kb
Host smart-420042b8-3f64-4a90-b9b1-ee2ac9eb23c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966547073 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3966547073
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3508906901
Short name T538
Test name
Test status
Simulation time 153449683518 ps
CPU time 2128 seconds
Started Jul 01 11:26:22 AM PDT 24
Finished Jul 01 12:01:51 PM PDT 24
Peak memory 282128 kb
Host smart-d32ca806-c4a3-4359-b594-df581a4c7608
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508906901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3508906901
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.137715100
Short name T220
Test name
Test status
Simulation time 209988072 ps
CPU time 24.83 seconds
Started Jul 01 11:26:25 AM PDT 24
Finished Jul 01 11:26:51 AM PDT 24
Peak memory 257088 kb
Host smart-1768c0c9-ac89-4a50-9d13-6b74d11207b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13771
5100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.137715100
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1981649645
Short name T436
Test name
Test status
Simulation time 788077677 ps
CPU time 48.13 seconds
Started Jul 01 11:26:21 AM PDT 24
Finished Jul 01 11:27:10 AM PDT 24
Peak memory 249100 kb
Host smart-83e5d38d-658b-4613-9b13-36b9aaccab2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19816
49645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1981649645
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1524500438
Short name T266
Test name
Test status
Simulation time 19362133956 ps
CPU time 752.54 seconds
Started Jul 01 11:26:33 AM PDT 24
Finished Jul 01 11:39:07 AM PDT 24
Peak memory 273388 kb
Host smart-a8c2ad6f-6668-4b33-afa8-1370fc2d361a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524500438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1524500438
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1803404686
Short name T686
Test name
Test status
Simulation time 8169247909 ps
CPU time 371.58 seconds
Started Jul 01 11:26:30 AM PDT 24
Finished Jul 01 11:32:43 AM PDT 24
Peak memory 249356 kb
Host smart-da5e464a-1621-46b6-b291-bb4aecd4f750
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803404686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1803404686
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3198788528
Short name T453
Test name
Test status
Simulation time 695508038 ps
CPU time 34.35 seconds
Started Jul 01 11:26:31 AM PDT 24
Finished Jul 01 11:27:06 AM PDT 24
Peak memory 256992 kb
Host smart-6196b0dc-79d2-4bf6-9200-93c1790c586f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31987
88528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3198788528
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2858274954
Short name T579
Test name
Test status
Simulation time 326949637 ps
CPU time 4.7 seconds
Started Jul 01 11:26:20 AM PDT 24
Finished Jul 01 11:26:26 AM PDT 24
Peak memory 249384 kb
Host smart-c40331d1-10de-4a59-a3f0-fb516de2f2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28582
74954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2858274954
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3570112540
Short name T53
Test name
Test status
Simulation time 698142115 ps
CPU time 47 seconds
Started Jul 01 11:26:20 AM PDT 24
Finished Jul 01 11:27:08 AM PDT 24
Peak memory 248644 kb
Host smart-e4f06fc6-4878-4465-9984-b3120550dc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35701
12540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3570112540
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2786345011
Short name T501
Test name
Test status
Simulation time 206378608 ps
CPU time 19.27 seconds
Started Jul 01 11:26:21 AM PDT 24
Finished Jul 01 11:26:41 AM PDT 24
Peak memory 256532 kb
Host smart-07a552c1-8151-43c7-ac1d-e89e513bc9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27863
45011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2786345011
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2556697226
Short name T492
Test name
Test status
Simulation time 44825980434 ps
CPU time 339.76 seconds
Started Jul 01 11:26:27 AM PDT 24
Finished Jul 01 11:32:08 AM PDT 24
Peak memory 254728 kb
Host smart-1abd8a34-be98-4005-972b-885797cf5605
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556697226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2556697226
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2532673637
Short name T78
Test name
Test status
Simulation time 50600105847 ps
CPU time 922.68 seconds
Started Jul 01 11:26:34 AM PDT 24
Finished Jul 01 11:41:58 AM PDT 24
Peak memory 282804 kb
Host smart-7316b0b9-99c1-4b8e-bdea-dee3dab145f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532673637 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2532673637
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1347575302
Short name T448
Test name
Test status
Simulation time 8883604423 ps
CPU time 988.7 seconds
Started Jul 01 11:26:26 AM PDT 24
Finished Jul 01 11:42:56 AM PDT 24
Peak memory 289708 kb
Host smart-61d3bbef-9f77-4ca3-b532-495e51316401
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347575302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1347575302
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3280775964
Short name T530
Test name
Test status
Simulation time 3110410783 ps
CPU time 153.52 seconds
Started Jul 01 11:26:27 AM PDT 24
Finished Jul 01 11:29:01 AM PDT 24
Peak memory 257604 kb
Host smart-76dbb95a-ffa1-46a1-af98-48b43e553ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32807
75964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3280775964
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2361242674
Short name T622
Test name
Test status
Simulation time 110148918 ps
CPU time 5.37 seconds
Started Jul 01 11:26:34 AM PDT 24
Finished Jul 01 11:26:40 AM PDT 24
Peak memory 240656 kb
Host smart-7c7ca1e3-e8bb-4a1c-af37-a28230a22c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23612
42674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2361242674
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3645204349
Short name T273
Test name
Test status
Simulation time 30301114108 ps
CPU time 1831.65 seconds
Started Jul 01 11:26:25 AM PDT 24
Finished Jul 01 11:56:58 AM PDT 24
Peak memory 282040 kb
Host smart-eff3875e-b804-4cfc-84ab-5947bd9bfeaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645204349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3645204349
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2548068364
Short name T446
Test name
Test status
Simulation time 13996139444 ps
CPU time 1435.91 seconds
Started Jul 01 11:26:35 AM PDT 24
Finished Jul 01 11:50:32 AM PDT 24
Peak memory 290148 kb
Host smart-166c3ad8-ed90-4404-bba3-bcde1b051817
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548068364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2548068364
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3931731924
Short name T634
Test name
Test status
Simulation time 206423076350 ps
CPU time 412.31 seconds
Started Jul 01 11:26:24 AM PDT 24
Finished Jul 01 11:33:18 AM PDT 24
Peak memory 249324 kb
Host smart-d4b89def-dba7-4505-8b8f-5edac680fd58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931731924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3931731924
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2601001882
Short name T429
Test name
Test status
Simulation time 5127076838 ps
CPU time 26.2 seconds
Started Jul 01 11:26:35 AM PDT 24
Finished Jul 01 11:27:02 AM PDT 24
Peak memory 256824 kb
Host smart-3def11c8-7b8f-4972-bebf-580b60e1f50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26010
01882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2601001882
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.467950591
Short name T569
Test name
Test status
Simulation time 129095596 ps
CPU time 16.91 seconds
Started Jul 01 11:26:25 AM PDT 24
Finished Jul 01 11:26:44 AM PDT 24
Peak memory 248696 kb
Host smart-00033ce2-83eb-40d1-95ea-924b3142d39c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46795
0591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.467950591
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.383556090
Short name T70
Test name
Test status
Simulation time 2315208655 ps
CPU time 20.33 seconds
Started Jul 01 11:26:24 AM PDT 24
Finished Jul 01 11:26:46 AM PDT 24
Peak memory 249360 kb
Host smart-4310f936-a8bd-4115-9fee-d05b55e9fdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38355
6090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.383556090
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1901447018
Short name T485
Test name
Test status
Simulation time 133175199 ps
CPU time 5.47 seconds
Started Jul 01 11:26:24 AM PDT 24
Finished Jul 01 11:26:31 AM PDT 24
Peak memory 249516 kb
Host smart-e35bd58a-022d-4ab2-86c1-9e0b8b12e654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19014
47018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1901447018
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3814372009
Short name T259
Test name
Test status
Simulation time 8723555305 ps
CPU time 550.71 seconds
Started Jul 01 11:26:24 AM PDT 24
Finished Jul 01 11:35:37 AM PDT 24
Peak memory 257424 kb
Host smart-6316d92f-cae5-4887-a5c9-235c0d57d18b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814372009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3814372009
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1893587394
Short name T55
Test name
Test status
Simulation time 17609214866 ps
CPU time 1816.34 seconds
Started Jul 01 11:26:25 AM PDT 24
Finished Jul 01 11:56:43 AM PDT 24
Peak memory 306076 kb
Host smart-98a5f3ad-3fe2-4aea-adcb-7847a0f1e38b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893587394 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1893587394
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3143104638
Short name T89
Test name
Test status
Simulation time 201658256978 ps
CPU time 3182.35 seconds
Started Jul 01 11:26:31 AM PDT 24
Finished Jul 01 12:19:35 PM PDT 24
Peak memory 289532 kb
Host smart-8fdd7cee-61df-457d-b38b-974a272260b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143104638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3143104638
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3911982811
Short name T355
Test name
Test status
Simulation time 148214664 ps
CPU time 10.8 seconds
Started Jul 01 11:26:32 AM PDT 24
Finished Jul 01 11:26:44 AM PDT 24
Peak memory 254564 kb
Host smart-d1901564-bd5d-4683-af6d-391c0b04883d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39119
82811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3911982811
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2213265061
Short name T588
Test name
Test status
Simulation time 70834082 ps
CPU time 6.51 seconds
Started Jul 01 11:26:32 AM PDT 24
Finished Jul 01 11:26:40 AM PDT 24
Peak memory 248696 kb
Host smart-e796169d-feba-418f-9236-9a1fa63eb3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22132
65061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2213265061
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2975475199
Short name T316
Test name
Test status
Simulation time 51368943085 ps
CPU time 1716.34 seconds
Started Jul 01 11:26:33 AM PDT 24
Finished Jul 01 11:55:11 AM PDT 24
Peak memory 273312 kb
Host smart-f477c998-35ba-4eff-ad04-7fd5f81bde4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975475199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2975475199
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.209968243
Short name T514
Test name
Test status
Simulation time 51380597015 ps
CPU time 1649.19 seconds
Started Jul 01 11:26:31 AM PDT 24
Finished Jul 01 11:54:02 AM PDT 24
Peak memory 284252 kb
Host smart-83c75dcb-f108-4e55-ac78-d73b6a9795b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209968243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.209968243
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1405727783
Short name T489
Test name
Test status
Simulation time 7856234858 ps
CPU time 75.58 seconds
Started Jul 01 11:26:32 AM PDT 24
Finished Jul 01 11:27:49 AM PDT 24
Peak memory 254532 kb
Host smart-85822df1-0866-4035-867b-2bd57e193a92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405727783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1405727783
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.120818464
Short name T214
Test name
Test status
Simulation time 317686371 ps
CPU time 38.67 seconds
Started Jul 01 11:26:34 AM PDT 24
Finished Jul 01 11:27:14 AM PDT 24
Peak memory 249316 kb
Host smart-6188cec1-d013-4be1-a77e-9c35703c2b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12081
8464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.120818464
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.779621733
Short name T595
Test name
Test status
Simulation time 9121487371 ps
CPU time 72.23 seconds
Started Jul 01 11:26:34 AM PDT 24
Finished Jul 01 11:27:48 AM PDT 24
Peak memory 249064 kb
Host smart-d603b74b-3e31-4faf-b2f5-1149ce537e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77962
1733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.779621733
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.594037786
Short name T236
Test name
Test status
Simulation time 258351110 ps
CPU time 17.03 seconds
Started Jul 01 11:26:31 AM PDT 24
Finished Jul 01 11:26:50 AM PDT 24
Peak memory 249252 kb
Host smart-7b0c604e-0673-4b34-8b8c-57ef877076bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59403
7786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.594037786
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.4233555993
Short name T519
Test name
Test status
Simulation time 3226430617 ps
CPU time 40.11 seconds
Started Jul 01 11:26:24 AM PDT 24
Finished Jul 01 11:27:06 AM PDT 24
Peak memory 257492 kb
Host smart-dec62d6c-6970-4f43-bbb9-850e2a67dee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42335
55993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.4233555993
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1202113202
Short name T190
Test name
Test status
Simulation time 886215207784 ps
CPU time 4188.02 seconds
Started Jul 01 11:26:31 AM PDT 24
Finished Jul 01 12:36:21 PM PDT 24
Peak memory 306584 kb
Host smart-402880f2-ef16-4eac-a50d-e106992da4c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202113202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1202113202
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.572867726
Short name T395
Test name
Test status
Simulation time 135511528167 ps
CPU time 2788.06 seconds
Started Jul 01 11:24:15 AM PDT 24
Finished Jul 01 12:10:48 PM PDT 24
Peak memory 290100 kb
Host smart-638d0af1-1364-4896-8e3c-781b31c7f3bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572867726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.572867726
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3631316416
Short name T575
Test name
Test status
Simulation time 1224098440 ps
CPU time 16.09 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:24:34 AM PDT 24
Peak memory 249096 kb
Host smart-d3c8ab5b-466c-49ba-b09c-9ffeeb22a0a1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3631316416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3631316416
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.179084035
Short name T649
Test name
Test status
Simulation time 5005403043 ps
CPU time 121.72 seconds
Started Jul 01 11:24:15 AM PDT 24
Finished Jul 01 11:26:21 AM PDT 24
Peak memory 256932 kb
Host smart-c568b40f-e8b7-4f0f-bcab-10b7bde9af03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17908
4035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.179084035
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.399102934
Short name T444
Test name
Test status
Simulation time 184025609 ps
CPU time 7.56 seconds
Started Jul 01 11:24:14 AM PDT 24
Finished Jul 01 11:24:26 AM PDT 24
Peak memory 248824 kb
Host smart-6d7fa390-d043-4fc0-99dd-66974be4a563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39910
2934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.399102934
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1732000352
Short name T304
Test name
Test status
Simulation time 330323548246 ps
CPU time 2446.04 seconds
Started Jul 01 11:24:15 AM PDT 24
Finished Jul 01 12:05:06 PM PDT 24
Peak memory 273992 kb
Host smart-8d246711-6972-44e9-97c7-5e9871edce46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732000352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1732000352
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1909888624
Short name T255
Test name
Test status
Simulation time 95303230420 ps
CPU time 1445.4 seconds
Started Jul 01 11:24:18 AM PDT 24
Finished Jul 01 11:48:27 AM PDT 24
Peak memory 272832 kb
Host smart-9edc1bef-8b10-44ef-8bec-d8a70d27ddf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909888624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1909888624
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3079602490
Short name T657
Test name
Test status
Simulation time 55352203203 ps
CPU time 558.62 seconds
Started Jul 01 11:24:26 AM PDT 24
Finished Jul 01 11:33:46 AM PDT 24
Peak memory 249260 kb
Host smart-c24dd71a-c604-4d98-aaea-bb82c58d97f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079602490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3079602490
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.4184834394
Short name T692
Test name
Test status
Simulation time 9481606317 ps
CPU time 48.23 seconds
Started Jul 01 11:24:09 AM PDT 24
Finished Jul 01 11:25:02 AM PDT 24
Peak memory 256752 kb
Host smart-58be34b0-9f29-4ef0-8441-d990711a7191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41848
34394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.4184834394
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3877678103
Short name T362
Test name
Test status
Simulation time 5929968565 ps
CPU time 47.66 seconds
Started Jul 01 11:24:25 AM PDT 24
Finished Jul 01 11:25:15 AM PDT 24
Peak memory 257596 kb
Host smart-f9fa18ac-ab96-4696-9039-d991f737c578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38776
78103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3877678103
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3755504615
Short name T368
Test name
Test status
Simulation time 35248151 ps
CPU time 2.82 seconds
Started Jul 01 11:24:14 AM PDT 24
Finished Jul 01 11:24:21 AM PDT 24
Peak memory 240224 kb
Host smart-074d94ab-98b8-4eda-a58e-489aeeaa7eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37555
04615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3755504615
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.4078584908
Short name T529
Test name
Test status
Simulation time 661958972 ps
CPU time 44.11 seconds
Started Jul 01 11:24:08 AM PDT 24
Finished Jul 01 11:24:57 AM PDT 24
Peak memory 257124 kb
Host smart-3bd07a40-4275-42a4-852f-98c638fa9530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40785
84908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.4078584908
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2798996217
Short name T619
Test name
Test status
Simulation time 108854389866 ps
CPU time 1451.41 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:48:30 AM PDT 24
Peak memory 305768 kb
Host smart-cc4b901d-f130-41b1-9cff-365b9b190b9a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798996217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2798996217
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1394925630
Short name T100
Test name
Test status
Simulation time 1041398747227 ps
CPU time 6809.63 seconds
Started Jul 01 11:24:14 AM PDT 24
Finished Jul 01 01:17:49 PM PDT 24
Peak memory 355444 kb
Host smart-9f448810-49ec-4570-98da-c7911c6f6548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394925630 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1394925630
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2027363797
Short name T196
Test name
Test status
Simulation time 80650452 ps
CPU time 3.13 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:24:21 AM PDT 24
Peak memory 249576 kb
Host smart-e8dbe0ea-f3d3-4c32-bef8-aa0564a296d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2027363797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2027363797
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2182252240
Short name T419
Test name
Test status
Simulation time 77099636215 ps
CPU time 2622.75 seconds
Started Jul 01 11:24:15 AM PDT 24
Finished Jul 01 12:08:03 PM PDT 24
Peak memory 272988 kb
Host smart-0bca9e10-20e7-482d-91a1-4919791e8440
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182252240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2182252240
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2755057515
Short name T583
Test name
Test status
Simulation time 1457804908 ps
CPU time 17.17 seconds
Started Jul 01 11:24:15 AM PDT 24
Finished Jul 01 11:24:37 AM PDT 24
Peak memory 249324 kb
Host smart-edc65523-6c48-4ecc-b000-17a71601f9bb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2755057515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2755057515
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3795448166
Short name T711
Test name
Test status
Simulation time 14315721835 ps
CPU time 223.96 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:28:02 AM PDT 24
Peak memory 257612 kb
Host smart-3155d74a-c932-47d9-8e2c-4b80e43b251d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37954
48166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3795448166
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3121055318
Short name T608
Test name
Test status
Simulation time 427689503 ps
CPU time 17.16 seconds
Started Jul 01 11:24:17 AM PDT 24
Finished Jul 01 11:24:38 AM PDT 24
Peak memory 248680 kb
Host smart-36c0fc83-0819-41fb-8266-6e64efa4d4f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31210
55318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3121055318
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.74082637
Short name T265
Test name
Test status
Simulation time 139336097562 ps
CPU time 1323.89 seconds
Started Jul 01 11:24:14 AM PDT 24
Finished Jul 01 11:46:23 AM PDT 24
Peak memory 290048 kb
Host smart-4476ac21-f26e-4794-9c67-a7f1b9d33732
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74082637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.74082637
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.390400188
Short name T451
Test name
Test status
Simulation time 25532780677 ps
CPU time 1170.39 seconds
Started Jul 01 11:24:17 AM PDT 24
Finished Jul 01 11:43:51 AM PDT 24
Peak memory 289872 kb
Host smart-fe6431ba-709c-47c2-a3e1-b358877af76f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390400188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.390400188
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1778174920
Short name T658
Test name
Test status
Simulation time 38914309929 ps
CPU time 399.17 seconds
Started Jul 01 11:24:12 AM PDT 24
Finished Jul 01 11:30:56 AM PDT 24
Peak memory 249136 kb
Host smart-d027a0c9-ab30-4bf6-8449-260bf330888e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778174920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1778174920
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2418829610
Short name T380
Test name
Test status
Simulation time 87927393 ps
CPU time 8.48 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:24:27 AM PDT 24
Peak memory 249284 kb
Host smart-b2272724-b94d-4a77-9cd1-0fc6799680bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24188
29610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2418829610
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1900411752
Short name T95
Test name
Test status
Simulation time 760873385 ps
CPU time 47.21 seconds
Started Jul 01 11:24:15 AM PDT 24
Finished Jul 01 11:25:06 AM PDT 24
Peak memory 248692 kb
Host smart-3f8fc6dc-3d04-4365-90aa-b560830c40be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19004
11752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1900411752
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2247103246
Short name T651
Test name
Test status
Simulation time 838565474 ps
CPU time 24.86 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:24:43 AM PDT 24
Peak memory 256504 kb
Host smart-0b3dd369-c39b-4f24-8cf2-3ae8a7b69162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22471
03246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2247103246
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1779188427
Short name T83
Test name
Test status
Simulation time 5150177399 ps
CPU time 37.87 seconds
Started Jul 01 11:24:16 AM PDT 24
Finished Jul 01 11:24:58 AM PDT 24
Peak memory 257564 kb
Host smart-6458bafc-ab01-4fcc-bd41-bdc8da6595dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17791
88427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1779188427
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.4033903331
Short name T238
Test name
Test status
Simulation time 19076173399 ps
CPU time 749.66 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:36:48 AM PDT 24
Peak memory 271304 kb
Host smart-d6b96a00-daa3-4b97-b17c-6bb9c0944cd0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033903331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.4033903331
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1062508177
Short name T54
Test name
Test status
Simulation time 15776268948 ps
CPU time 1015.57 seconds
Started Jul 01 11:24:18 AM PDT 24
Finished Jul 01 11:41:17 AM PDT 24
Peak memory 283192 kb
Host smart-871f2db9-bcff-4f27-b0c7-58ec1cffcd47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062508177 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1062508177
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1068832705
Short name T195
Test name
Test status
Simulation time 197284269 ps
CPU time 4.37 seconds
Started Jul 01 11:24:20 AM PDT 24
Finished Jul 01 11:24:27 AM PDT 24
Peak memory 249588 kb
Host smart-5406e32a-6525-45b1-bfa2-9fcc8d2e0124
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1068832705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1068832705
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.758134473
Short name T392
Test name
Test status
Simulation time 56815025283 ps
CPU time 1507.71 seconds
Started Jul 01 11:24:23 AM PDT 24
Finished Jul 01 11:49:34 AM PDT 24
Peak memory 273484 kb
Host smart-ccc675b0-ec4a-46c3-a485-865fe9d40e82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758134473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.758134473
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.376135896
Short name T706
Test name
Test status
Simulation time 434072266 ps
CPU time 11.32 seconds
Started Jul 01 11:24:25 AM PDT 24
Finished Jul 01 11:24:39 AM PDT 24
Peak memory 249276 kb
Host smart-54addc80-2f4f-490b-ab8f-33bd11e24e9a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=376135896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.376135896
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1836106494
Short name T596
Test name
Test status
Simulation time 3773600974 ps
CPU time 132.81 seconds
Started Jul 01 11:24:30 AM PDT 24
Finished Jul 01 11:26:44 AM PDT 24
Peak memory 257156 kb
Host smart-2f2a18d8-cf81-4e1c-ab0f-b7075ba34e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18361
06494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1836106494
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3919810899
Short name T614
Test name
Test status
Simulation time 413487317 ps
CPU time 26.29 seconds
Started Jul 01 11:24:20 AM PDT 24
Finished Jul 01 11:24:49 AM PDT 24
Peak memory 249236 kb
Host smart-31cbc7aa-3b74-4e04-949a-0cd1aa285f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39198
10899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3919810899
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1777918500
Short name T312
Test name
Test status
Simulation time 123292588316 ps
CPU time 2118.07 seconds
Started Jul 01 11:24:21 AM PDT 24
Finished Jul 01 11:59:42 AM PDT 24
Peak memory 289388 kb
Host smart-7ac6c1ab-01e0-4a89-ae49-9cb99d7d724d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777918500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1777918500
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1440744733
Short name T470
Test name
Test status
Simulation time 80463351547 ps
CPU time 2431.93 seconds
Started Jul 01 11:24:32 AM PDT 24
Finished Jul 01 12:05:06 PM PDT 24
Peak memory 282208 kb
Host smart-886fe1d0-6de1-43c1-ad42-e3f4cc69b860
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440744733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1440744733
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1871269664
Short name T9
Test name
Test status
Simulation time 5719424579 ps
CPU time 235.98 seconds
Started Jul 01 11:24:30 AM PDT 24
Finished Jul 01 11:28:27 AM PDT 24
Peak memory 256264 kb
Host smart-9aab8c4c-82dc-43a4-804d-24926506aa0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871269664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1871269664
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1127729511
Short name T502
Test name
Test status
Simulation time 1639170280 ps
CPU time 19.16 seconds
Started Jul 01 11:24:13 AM PDT 24
Finished Jul 01 11:24:37 AM PDT 24
Peak memory 256676 kb
Host smart-17e5d698-25fe-42e5-a16b-ccc1b042d7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11277
29511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1127729511
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3320067675
Short name T483
Test name
Test status
Simulation time 1640335174 ps
CPU time 32.1 seconds
Started Jul 01 11:24:20 AM PDT 24
Finished Jul 01 11:24:55 AM PDT 24
Peak memory 249136 kb
Host smart-8ae85235-70bb-4c27-b8e7-2b901428e7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33200
67675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3320067675
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3222298160
Short name T357
Test name
Test status
Simulation time 158321876 ps
CPU time 16.22 seconds
Started Jul 01 11:24:39 AM PDT 24
Finished Jul 01 11:24:57 AM PDT 24
Peak memory 248832 kb
Host smart-c23abe68-08f1-479c-8aae-f35783c9692d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32222
98160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3222298160
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1741395697
Short name T60
Test name
Test status
Simulation time 2073389796 ps
CPU time 36.3 seconds
Started Jul 01 11:24:34 AM PDT 24
Finished Jul 01 11:25:12 AM PDT 24
Peak memory 257452 kb
Host smart-7d4ebf4a-e42b-4bdb-a20e-fc4e16b47af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17413
95697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1741395697
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3661393825
Short name T520
Test name
Test status
Simulation time 32926607458 ps
CPU time 1234.44 seconds
Started Jul 01 11:24:21 AM PDT 24
Finished Jul 01 11:44:58 AM PDT 24
Peak memory 273764 kb
Host smart-fc610164-db78-4b91-88ba-3868cbf08810
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661393825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3661393825
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.394861369
Short name T652
Test name
Test status
Simulation time 121342968256 ps
CPU time 3110.76 seconds
Started Jul 01 11:24:25 AM PDT 24
Finished Jul 01 12:16:24 PM PDT 24
Peak memory 322604 kb
Host smart-e9460ba7-2477-4ad0-b61c-9ad3b795cc31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394861369 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.394861369
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.149336143
Short name T204
Test name
Test status
Simulation time 157709043 ps
CPU time 3.67 seconds
Started Jul 01 11:24:24 AM PDT 24
Finished Jul 01 11:24:31 AM PDT 24
Peak memory 249568 kb
Host smart-870999a1-aad8-405c-ae7a-a768058b4fc3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=149336143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.149336143
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2608213234
Short name T366
Test name
Test status
Simulation time 113452676928 ps
CPU time 1722.78 seconds
Started Jul 01 11:24:24 AM PDT 24
Finished Jul 01 11:53:09 AM PDT 24
Peak memory 273800 kb
Host smart-f73c9c83-9e79-4363-ab08-3f02079906aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608213234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2608213234
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1278514054
Short name T351
Test name
Test status
Simulation time 1426533978 ps
CPU time 18.01 seconds
Started Jul 01 11:24:41 AM PDT 24
Finished Jul 01 11:25:00 AM PDT 24
Peak memory 249308 kb
Host smart-21340e12-122b-402c-95b2-eec7e239cf2d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1278514054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1278514054
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1934847152
Short name T487
Test name
Test status
Simulation time 5485709984 ps
CPU time 310.3 seconds
Started Jul 01 11:24:23 AM PDT 24
Finished Jul 01 11:29:36 AM PDT 24
Peak memory 257136 kb
Host smart-98a66c21-1cc9-4bcd-849f-9a89233ed544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19348
47152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1934847152
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2025687613
Short name T602
Test name
Test status
Simulation time 290239063 ps
CPU time 17.72 seconds
Started Jul 01 11:24:21 AM PDT 24
Finished Jul 01 11:24:41 AM PDT 24
Peak memory 249688 kb
Host smart-2c358759-4130-41ca-8321-e064fe996b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20256
87613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2025687613
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2675078371
Short name T314
Test name
Test status
Simulation time 163235043288 ps
CPU time 1513.27 seconds
Started Jul 01 11:24:18 AM PDT 24
Finished Jul 01 11:49:35 AM PDT 24
Peak memory 273916 kb
Host smart-216d4ae2-e19a-411b-8e77-52d06588fbe9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675078371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2675078371
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1635750434
Short name T516
Test name
Test status
Simulation time 8831508835 ps
CPU time 720.47 seconds
Started Jul 01 11:24:23 AM PDT 24
Finished Jul 01 11:36:26 AM PDT 24
Peak memory 265824 kb
Host smart-5f8821c5-a1ea-42ef-bafe-502de879dfef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635750434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1635750434
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2958403916
Short name T51
Test name
Test status
Simulation time 697848359 ps
CPU time 46.11 seconds
Started Jul 01 11:24:33 AM PDT 24
Finished Jul 01 11:25:21 AM PDT 24
Peak memory 257356 kb
Host smart-4aa98f92-96ad-4d6c-b289-631fc02e2575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29584
03916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2958403916
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1489525245
Short name T533
Test name
Test status
Simulation time 3518300577 ps
CPU time 52.43 seconds
Started Jul 01 11:24:24 AM PDT 24
Finished Jul 01 11:25:20 AM PDT 24
Peak memory 257132 kb
Host smart-fe9ec7ce-a014-48da-8901-b7db95e312c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14895
25245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1489525245
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2629932351
Short name T228
Test name
Test status
Simulation time 2674394457 ps
CPU time 32.58 seconds
Started Jul 01 11:24:19 AM PDT 24
Finished Jul 01 11:24:55 AM PDT 24
Peak memory 249056 kb
Host smart-8ae05d5e-1b9e-4cd3-b344-10c81fcd0458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26299
32351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2629932351
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.297309315
Short name T695
Test name
Test status
Simulation time 485375809 ps
CPU time 27.34 seconds
Started Jul 01 11:24:21 AM PDT 24
Finished Jul 01 11:24:51 AM PDT 24
Peak memory 249268 kb
Host smart-e7db97d5-ee4c-4006-a581-04082677b5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29730
9315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.297309315
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1373972856
Short name T601
Test name
Test status
Simulation time 3229938356 ps
CPU time 193.5 seconds
Started Jul 01 11:24:22 AM PDT 24
Finished Jul 01 11:27:37 AM PDT 24
Peak memory 257492 kb
Host smart-a782203a-51d9-4595-997d-d9a34b18970c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373972856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1373972856
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.737115600
Short name T243
Test name
Test status
Simulation time 211286640930 ps
CPU time 5416.26 seconds
Started Jul 01 11:24:32 AM PDT 24
Finished Jul 01 12:54:51 PM PDT 24
Peak memory 368592 kb
Host smart-3f3b2b3f-0929-4ada-8345-21061a60ecaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737115600 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.737115600
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3099798565
Short name T193
Test name
Test status
Simulation time 146752219 ps
CPU time 3.27 seconds
Started Jul 01 11:24:23 AM PDT 24
Finished Jul 01 11:24:28 AM PDT 24
Peak memory 249584 kb
Host smart-252b7c6b-b19a-4632-b997-dcb6d0c2f4ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3099798565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3099798565
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1291821732
Short name T531
Test name
Test status
Simulation time 96018166952 ps
CPU time 1865.09 seconds
Started Jul 01 11:24:24 AM PDT 24
Finished Jul 01 11:55:31 AM PDT 24
Peak memory 273732 kb
Host smart-867d0d94-c122-42d8-8bb4-06956e63a042
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291821732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1291821732
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3012950462
Short name T440
Test name
Test status
Simulation time 479330902 ps
CPU time 12.59 seconds
Started Jul 01 11:24:40 AM PDT 24
Finished Jul 01 11:24:54 AM PDT 24
Peak memory 249168 kb
Host smart-df61b5cc-e253-499e-bbe2-8b50e2b0235a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3012950462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3012950462
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4102985911
Short name T463
Test name
Test status
Simulation time 2572897427 ps
CPU time 51.2 seconds
Started Jul 01 11:24:43 AM PDT 24
Finished Jul 01 11:25:36 AM PDT 24
Peak memory 257568 kb
Host smart-df29f38c-9535-4373-b577-63682894e479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41029
85911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4102985911
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1249278869
Short name T37
Test name
Test status
Simulation time 854566711 ps
CPU time 22.75 seconds
Started Jul 01 11:24:24 AM PDT 24
Finished Jul 01 11:24:50 AM PDT 24
Peak memory 257440 kb
Host smart-8a560a36-2ee9-4fc7-baf5-8787ff93ab26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12492
78869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1249278869
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1749420552
Short name T418
Test name
Test status
Simulation time 29853388418 ps
CPU time 1738.07 seconds
Started Jul 01 11:24:33 AM PDT 24
Finished Jul 01 11:53:34 AM PDT 24
Peak memory 273896 kb
Host smart-362fdf6a-8af1-4d0b-8d26-13ff6f4242e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749420552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1749420552
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1236443736
Short name T277
Test name
Test status
Simulation time 5009619079 ps
CPU time 107.72 seconds
Started Jul 01 11:24:35 AM PDT 24
Finished Jul 01 11:26:25 AM PDT 24
Peak memory 249344 kb
Host smart-a1072198-dd5f-4039-b22b-bf1add949c06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236443736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1236443736
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1527499637
Short name T338
Test name
Test status
Simulation time 422815102 ps
CPU time 26.41 seconds
Started Jul 01 11:24:30 AM PDT 24
Finished Jul 01 11:24:57 AM PDT 24
Peak memory 249280 kb
Host smart-7588ad69-d531-4423-bd7f-9739007a56d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15274
99637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1527499637
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1638423493
Short name T103
Test name
Test status
Simulation time 1150583100 ps
CPU time 32.72 seconds
Started Jul 01 11:24:25 AM PDT 24
Finished Jul 01 11:25:00 AM PDT 24
Peak memory 256408 kb
Host smart-a731f650-f61d-47fc-a193-f5c54542c036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16384
23493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1638423493
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2223227708
Short name T513
Test name
Test status
Simulation time 801033742 ps
CPU time 45.26 seconds
Started Jul 01 11:24:31 AM PDT 24
Finished Jul 01 11:25:19 AM PDT 24
Peak memory 256848 kb
Host smart-8250f3dd-5b5d-4580-932d-07bca337e222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22232
27708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2223227708
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1303817127
Short name T347
Test name
Test status
Simulation time 584402111 ps
CPU time 31.89 seconds
Started Jul 01 11:24:42 AM PDT 24
Finished Jul 01 11:25:16 AM PDT 24
Peak memory 255956 kb
Host smart-4144cca1-b7d2-4551-8d87-6f85309838d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13038
17127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1303817127
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1664946720
Short name T97
Test name
Test status
Simulation time 1569699531 ps
CPU time 104.74 seconds
Started Jul 01 11:24:33 AM PDT 24
Finished Jul 01 11:26:20 AM PDT 24
Peak memory 250468 kb
Host smart-2c305a6f-789a-4842-93b4-dd442def86ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664946720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1664946720
Directory /workspace/9.alert_handler_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%