Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	74860	1			T1	1606		T3	260		T17	2
class_i[0x1]	51793	1			T1	6		T3	6		T17	4520
class_i[0x2]	67869	1			T1	2034		T3	261		T17	8
class_i[0x3]	70331	1			T1	546		T3	10		T17	25

---

Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	66120	1			T1	937		T3	131		T17	1261
alert[0x1]	68068	1			T1	816		T3	73		T17	1142
alert[0x2]	64272	1			T1	971		T3	158		T17	1036
alert[0x3]	66393	1			T1	1468		T3	175		T17	1116

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

264579

1

T1

4192

T3

537

T17

4555

esc_ping_fail

274

1

T6

9

T10

6

T11

8

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	66045	1			T1	937		T3	131		T17	1261
esc_integrity_fail	alert[0x1]	67993	1			T1	816		T3	73		T17	1142
esc_integrity_fail	alert[0x2]	64195	1			T1	971		T3	158		T17	1036
esc_integrity_fail	alert[0x3]	66346	1			T1	1468		T3	175		T17	1116
esc_ping_fail	alert[0x0]	75	1			T6	2		T10	2		T11	1
esc_ping_fail	alert[0x1]	75	1			T6	2		T11	3		T15	1
esc_ping_fail	alert[0x2]	77	1			T6	2		T10	3		T11	3
esc_ping_fail	alert[0x3]	47	1			T6	3		T10	1		T11	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	74796	1			T1	1606		T3	260		T17	2
esc_integrity_fail	class_i[0x1]	51728	1			T1	6		T3	6		T17	4520
esc_integrity_fail	class_i[0x2]	67803	1			T1	2034		T3	261		T17	8
esc_integrity_fail	class_i[0x3]	70252	1			T1	546		T3	10		T17	25
esc_ping_fail	class_i[0x0]	64	1			T6	9		T188	2		T291	7
esc_ping_fail	class_i[0x1]	65	1			T66	7		T225	4		T212	1
esc_ping_fail	class_i[0x2]	66	1			T10	6		T11	8		T15	4
esc_ping_fail	class_i[0x3]	79	1			T188	2		T218	10		T299	3