Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	158	1			T1	2		T17	1		T9	1
index[0x1]	202	1			T1	6		T3	3		T17	2
index[0x2]	179	1			T1	2		T3	2		T31	1
index[0x3]	183	1			T3	3		T31	1		T9	7

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	250	1			T1	1		T3	5		T17	1
lens_less_than_1000[1]	134	1			T1	4		T3	2		T17	1
lens_less_than_1000[2]	108	1			T3	1		T18	1		T9	1
lens_less_than_1000[3]	85	1			T1	2		T65	1		T70	1
lens_less_than_1000[4]	38	1			T1	2		T17	1		T75	2
lens_less_than_1000[5]	42	1			T9	1		T75	1		T188	1
lens_less_than_1000[6]	18	1			T225	1		T190	1		T51	1
lens_less_than_1000[7]	21	1			T29	1		T88	2		T171	1
lens_less_than_1000[8]	13	1			T105	3		T55	1		T234	2
lens_less_than_1000[9]	3	1			T235	1		T236	1		T237	1
len_2	10	1			T1	1		T100	1		T238	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[8]]	0	1	1
[index[0x2] , index[0x3]]	[lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	62	1			T17	1		T26	6		T75	1
index[0x0]	lens_less_than_1000[1]	24	1			T239	1		T240	1		T221	1
index[0x0]	lens_less_than_1000[2]	14	1			T241	1		T106	1		T242	1
index[0x0]	lens_less_than_1000[3]	26	1			T70	1		T238	1		T53	1
index[0x0]	lens_less_than_1000[4]	10	1			T1	2		T75	1		T243	1
index[0x0]	lens_less_than_1000[5]	7	1			T9	1		T188	1		T85	1
index[0x0]	lens_less_than_1000[6]	4	1			T56	1		T244	1		T245	1
index[0x0]	lens_less_than_1000[7]	7	1			T88	2		T246	1		T247	1
index[0x0]	lens_less_than_1000[9]	2	1			T235	1		T237	1		-	-
index[0x0]	len_2	2	1			T248	1		T249	1		-	-
index[0x1]	lens_less_than_1000[0]	66	1			T1	1		T3	1		T32	1
index[0x1]	lens_less_than_1000[1]	45	1			T1	2		T3	2		T17	1
index[0x1]	lens_less_than_1000[2]	30	1			T18	1		T26	1		T45	1
index[0x1]	lens_less_than_1000[3]	19	1			T1	2		T75	1		T250	1
index[0x1]	lens_less_than_1000[4]	13	1			T17	1		T75	1		T251	1
index[0x1]	lens_less_than_1000[5]	15	1			T75	1		T252	1		T97	1
index[0x1]	lens_less_than_1000[6]	4	1			T51	1		T60	1		T253	1
index[0x1]	lens_less_than_1000[7]	1	1			T254	1		-	-		-	-
index[0x1]	lens_less_than_1000[8]	6	1			T55	1		T255	1		T248	1
index[0x1]	lens_less_than_1000[9]	1	1			T236	1		-	-		-	-
index[0x1]	len_2	2	1			T1	1		T249	1		-	-
index[0x2]	lens_less_than_1000[0]	62	1			T3	2		T26	1		T32	1
index[0x2]	lens_less_than_1000[1]	36	1			T1	2		T31	1		T77	1
index[0x2]	lens_less_than_1000[2]	35	1			T43	1		T75	1		T29	1
index[0x2]	lens_less_than_1000[3]	20	1			T65	1		T240	1		T79	1
index[0x2]	lens_less_than_1000[4]	5	1			T256	1		T178	1		T257	1
index[0x2]	lens_less_than_1000[5]	6	1			T258	3		T257	1		T259	1
index[0x2]	lens_less_than_1000[6]	3	1			T62	1		T260	1		T259	1
index[0x2]	lens_less_than_1000[7]	5	1			T29	1		T171	1		T261	1
index[0x2]	lens_less_than_1000[8]	3	1			T234	2		T262	1		-	-
index[0x2]	len_2	4	1			T100	1		T263	2		T249	1
index[0x3]	lens_less_than_1000[0]	60	1			T3	2		T31	1		T9	4
index[0x3]	lens_less_than_1000[1]	29	1			T9	2		T75	1		T29	1
index[0x3]	lens_less_than_1000[2]	29	1			T3	1		T9	1		T77	1
index[0x3]	lens_less_than_1000[3]	20	1			T240	1		T77	1		T47	1
index[0x3]	lens_less_than_1000[4]	10	1			T29	1		T54	1		T264	1
index[0x3]	lens_less_than_1000[5]	14	1			T250	1		T47	1		T51	1
index[0x3]	lens_less_than_1000[6]	7	1			T225	1		T190	1		T265	2
index[0x3]	lens_less_than_1000[7]	8	1			T254	1		T245	1		T261	1
index[0x3]	lens_less_than_1000[8]	4	1			T105	3		T230	1		-	-
index[0x3]	len_2	2	1			T238	1		T266	1		-	-