Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	87	1			T3	2		T17	1		T9	1
class_index[0x1]	62	1			T3	1		T63	1		T26	1
class_index[0x2]	55	1			T17	1		T9	1		T44	1
class_index[0x3]	74	1			T1	2		T17	1		T63	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	116	1			T1	1		T3	2		T17	2
intr_timeout_cnt[1]	56	1			T1	1		T17	1		T9	1
intr_timeout_cnt[2]	20	1			T63	1		T44	1		T26	1
intr_timeout_cnt[3]	17	1			T29	1		T47	1		T83	3
intr_timeout_cnt[4]	13	1			T44	1		T29	1		T53	2
intr_timeout_cnt[5]	11	1			T47	2		T267	1		T55	1
intr_timeout_cnt[6]	13	1			T77	1		T80	1		T171	1
intr_timeout_cnt[7]	10	1			T50	1		T51	1		T245	2
intr_timeout_cnt[8]	15	1			T43	1		T75	1		T268	1
intr_timeout_cnt[9]	7	1			T3	1		T77	1		T47	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	47	1			T3	1		T9	1		T27	1
class_index[0x0]	intr_timeout_cnt[1]	17	1			T17	1		T77	1		T269	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T26	1		T29	1		T83	1
class_index[0x0]	intr_timeout_cnt[3]	1	1			T254	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[4]	2	1			T44	1		T270	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	3	1			T80	1		T171	1		T226	1
class_index[0x0]	intr_timeout_cnt[7]	4	1			T271	1		T272	1		T273	2
class_index[0x0]	intr_timeout_cnt[8]	6	1			T43	1		T268	1		T274	1
class_index[0x0]	intr_timeout_cnt[9]	2	1			T3	1		T47	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	23	1			T3	1		T46	2		T55	1
class_index[0x1]	intr_timeout_cnt[1]	10	1			T63	1		T26	1		T75	2
class_index[0x1]	intr_timeout_cnt[2]	6	1			T53	1		T60	1		T171	2
class_index[0x1]	intr_timeout_cnt[3]	5	1			T29	1		T83	3		T237	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T29	1		T275	1		T276	1
class_index[0x1]	intr_timeout_cnt[5]	6	1			T47	2		T267	1		T94	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T254	1		T277	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T51	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T50	1		T25	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	4	1			T77	1		T278	1		T279	1
class_index[0x2]	intr_timeout_cnt[0]	20	1			T17	1		T26	2		T78	1
class_index[0x2]	intr_timeout_cnt[1]	12	1			T9	1		T69	1		T80	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T44	1		T280	1		T237	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T278	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	2	1			T55	1		T98	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T90	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	5	1			T245	1		T236	1		T271	1
class_index[0x2]	intr_timeout_cnt[7]	4	1			T50	1		T245	2		T226	1
class_index[0x2]	intr_timeout_cnt[8]	5	1			T75	1		T245	1		T226	1
class_index[0x3]	intr_timeout_cnt[0]	26	1			T1	1		T17	1		T74	1
class_index[0x3]	intr_timeout_cnt[1]	17	1			T1	1		T8	1		T46	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T63	1		T61	1		T281	1
class_index[0x3]	intr_timeout_cnt[3]	10	1			T47	1		T282	1		T94	4
class_index[0x3]	intr_timeout_cnt[4]	6	1			T53	2		T283	1		T61	1
class_index[0x3]	intr_timeout_cnt[5]	4	1			T55	1		T284	1		T285	2
class_index[0x3]	intr_timeout_cnt[6]	3	1			T77	1		T248	1		T230	1
class_index[0x3]	intr_timeout_cnt[7]	1	1			T259	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T271	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T60	1		-	-		-	-