Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	355267	1			T1	2920		T2	53		T3	2773
all_values[1]	355267	1			T1	2920		T2	53		T3	2773
all_values[2]	355267	1			T1	2920		T2	53		T3	2773
all_values[3]	355267	1			T1	2920		T2	53		T3	2773

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

706891

1

T1

5724

T2

106

T3

5486

auto[1]

714177

1

T1

5956

T2

106

T3

5606

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

839442

1

T1

6390

T2

109

T3

5845

auto[1]

581626

1

T1

5290

T2

103

T3

5247

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99485	1			T1	862		T2	17		T3	707
all_values[0]	auto[0]	auto[1]	77083	1			T1	614		T2	16		T3	692
all_values[0]	auto[1]	auto[0]	101015	1			T1	821		T2	10		T3	695
all_values[0]	auto[1]	auto[1]	77684	1			T1	623		T2	10		T3	679
all_values[1]	auto[0]	auto[0]	105390	1			T1	767		T2	11		T3	782
all_values[1]	auto[0]	auto[1]	71750	1			T1	651		T2	11		T3	601
all_values[1]	auto[1]	auto[0]	106248	1			T1	821		T2	17		T3	791
all_values[1]	auto[1]	auto[1]	71879	1			T1	681		T2	14		T3	599
all_values[2]	auto[0]	auto[0]	106292	1			T1	754		T2	13		T3	715
all_values[2]	auto[0]	auto[1]	70580	1			T1	652		T2	12		T3	657
all_values[2]	auto[1]	auto[0]	107506	1			T1	814		T2	14		T3	732
all_values[2]	auto[1]	auto[1]	70889	1			T1	700		T2	14		T3	669
all_values[3]	auto[0]	auto[0]	105846	1			T1	766		T2	13		T3	683
all_values[3]	auto[0]	auto[1]	70465	1			T1	658		T2	13		T3	649
all_values[3]	auto[1]	auto[0]	107660	1			T1	785		T2	14		T3	740
all_values[3]	auto[1]	auto[1]	71296	1			T1	711		T2	13		T3	701