Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	355267	1			T1	2920		T2	53		T3	2773
all_pins[1]	355267	1			T1	2920		T2	53		T3	2773
all_pins[2]	355267	1			T1	2920		T2	53		T3	2773
all_pins[3]	355267	1			T1	2920		T2	53		T3	2773

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1129320	1			T1	8965		T2	161		T3	8444
values[0x1]	291748	1			T1	2715		T2	51		T3	2648
transitions[0x0=>0x1]	193357	1			T1	1699		T2	30		T3	1734
transitions[0x1=>0x0]	193609	1			T1	1699		T2	30		T3	1734

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	277583	1			T1	2297		T2	43		T3	2094
all_pins[0]	values[0x1]	77684	1			T1	623		T2	10		T3	679
all_pins[0]	transitions[0x0=>0x1]	77007	1			T1	610		T2	10		T3	671
all_pins[0]	transitions[0x1=>0x0]	70871	1			T1	698		T2	13		T3	693
all_pins[1]	values[0x0]	283388	1			T1	2239		T2	39		T3	2174
all_pins[1]	values[0x1]	71879	1			T1	681		T2	14		T3	599
all_pins[1]	transitions[0x0=>0x1]	38846	1			T1	376		T2	8		T3	302
all_pins[1]	transitions[0x1=>0x0]	44651	1			T1	318		T2	4		T3	382
all_pins[2]	values[0x0]	284378	1			T1	2220		T2	39		T3	2104
all_pins[2]	values[0x1]	70889	1			T1	700		T2	14		T3	669
all_pins[2]	transitions[0x0=>0x1]	38542	1			T1	349		T2	6		T3	381
all_pins[2]	transitions[0x1=>0x0]	39532	1			T1	330		T2	6		T3	311
all_pins[3]	values[0x0]	283971	1			T1	2209		T2	40		T3	2072
all_pins[3]	values[0x1]	71296	1			T1	711		T2	13		T3	701
all_pins[3]	transitions[0x0=>0x1]	38962	1			T1	364		T2	6		T3	380
all_pins[3]	transitions[0x1=>0x0]	38555	1			T1	353		T2	7		T3	348