Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	95701	1			T1	156		T17	690		T9	558
accum_cnt_1000	223840	1			T1	2883		T3	2079		T17	1077
accum_cnt_100	25450	1			T1	591		T3	196		T17	155
accum_cnt_50	64341	1			T1	456		T3	973		T17	174
accum_cnt_10	173243	1			T1	279		T2	52		T3	2805
accum_cnt_0	420752	1			T1	3898		T2	52		T3	1419

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	263026	1			T1	2094		T2	26		T3	1868
class_index[0x1]	263026	1			T1	2094		T2	26		T3	1868
class_index[0x2]	263026	1			T1	2094		T2	26		T3	1868
class_index[0x3]	263026	1			T1	2094		T2	26		T3	1868

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	29274	1			T17	56		T9	279		T8	130
class_index[0x0]	accum_cnt_1000	71346	1			T1	763		T3	290		T17	67
class_index[0x0]	accum_cnt_100	8619	1			T1	139		T3	22		T17	83
class_index[0x0]	accum_cnt_50	18447	1			T1	111		T3	161		T17	98
class_index[0x0]	accum_cnt_10	42186	1			T1	140		T2	26		T3	797
class_index[0x0]	accum_cnt_0	81631	1			T1	941		T3	598		T16	15
class_index[0x1]	accum_cnt_2000	21182	1			T17	218		T8	130		T71	192
class_index[0x1]	accum_cnt_1000	50980	1			T1	698		T3	270		T17	175
class_index[0x1]	accum_cnt_100	5248	1			T1	178		T3	39		T17	15
class_index[0x1]	accum_cnt_50	17750	1			T1	146		T3	707		T17	10
class_index[0x1]	accum_cnt_10	38866	1			T1	39		T2	26		T3	502
class_index[0x1]	accum_cnt_0	117438	1			T1	1033		T3	350		T16	15
class_index[0x2]	accum_cnt_2000	21309	1			T17	416		T32	166		T45	295
class_index[0x2]	accum_cnt_1000	50833	1			T1	359		T3	938		T17	835
class_index[0x2]	accum_cnt_100	5184	1			T1	107		T3	58		T17	57
class_index[0x2]	accum_cnt_50	16970	1			T1	79		T3	50		T17	66
class_index[0x2]	accum_cnt_10	42194	1			T1	31		T3	385		T17	9
class_index[0x2]	accum_cnt_0	114333	1			T1	1518		T2	26		T3	437
class_index[0x3]	accum_cnt_2000	23936	1			T1	156		T9	279		T45	411
class_index[0x3]	accum_cnt_1000	50681	1			T1	1063		T3	581		T9	526
class_index[0x3]	accum_cnt_100	6399	1			T1	167		T3	77		T9	104
class_index[0x3]	accum_cnt_50	11174	1			T1	120		T3	55		T23	4
class_index[0x3]	accum_cnt_10	49997	1			T1	69		T3	1121		T17	1
class_index[0x3]	accum_cnt_0	107350	1			T1	406		T2	26		T3	34