Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	14199	1			T3	42		T17	5393		T15	1
alert[0x1]	12413	1			T1	2633		T26	1		T66	1
alert[0x2]	8889	1			T6	1		T15	1		T75	259
alert[0x3]	2769	1			T1	25		T3	10		T17	46
alert[0x4]	5636	1			T1	331		T6	1		T10	1
alert[0x5]	3185	1			T32	213		T290	1		T291	1
alert[0x6]	2837	1			T3	5		T17	54		T26	1
alert[0x7]	13423	1			T17	195		T75	20		T72	211
alert[0x8]	4719	1			T3	63		T6	1		T32	12
alert[0x9]	5537	1			T1	17		T3	7		T43	27
alert[0xa]	4192	1			T3	2		T17	29		T43	11
alert[0xb]	8209	1			T30	1378		T218	2		T292	329
alert[0xc]	4697	1			T1	7		T3	6		T26	783
alert[0xd]	5321	1			T1	38		T3	19		T17	59
alert[0xe]	5069	1			T1	12		T17	220		T66	1
alert[0xf]	8335	1			T3	16		T17	249		T26	43
alert[0x10]	4505	1			T6	1		T30	14		T77	3
alert[0x11]	10036	1			T1	5		T3	8		T17	108
alert[0x12]	9036	1			T3	2		T17	409		T26	347
alert[0x13]	12951	1			T17	37		T10	1		T26	12
alert[0x14]	14570	1			T3	10		T17	78		T67	1
alert[0x15]	7827	1			T17	1961		T6	1		T75	465
alert[0x16]	12664	1			T17	138		T26	438		T66	1
alert[0x17]	4636	1			T17	73		T6	1		T26	20
alert[0x18]	5879	1			T1	242		T15	1		T66	1
alert[0x19]	7008	1			T17	40		T6	1		T43	2
alert[0x1a]	1791	1			T1	40		T11	1		T32	15
alert[0x1b]	5527	1			T3	7		T17	75		T11	1
alert[0x1c]	1999	1			T17	371		T43	1		T11	2
alert[0x1d]	8827	1			T10	1		T26	2306		T11	2
alert[0x1e]	3622	1			T3	1		T17	281		T10	1
alert[0x1f]	17534	1			T1	190		T17	3479		T44	3
alert[0x20]	4751	1			T17	577		T72	21		T30	26
alert[0x21]	4260	1			T1	23		T3	69		T6	2
alert[0x22]	10254	1			T3	143		T6	1		T26	5
alert[0x23]	3554	1			T3	5		T6	1		T26	229
alert[0x24]	10317	1			T17	36		T43	5		T15	1
alert[0x25]	5393	1			T1	11		T6	1		T11	1
alert[0x26]	3952	1			T3	29		T17	1		T43	4
alert[0x27]	11841	1			T3	2		T26	112		T32	342
alert[0x28]	12634	1			T10	1		T15	1		T32	28
alert[0x29]	3364	1			T1	21		T17	269		T43	2
alert[0x2a]	4510	1			T3	1		T17	1269		T6	1
alert[0x2b]	2544	1			T17	28		T11	1		T15	1
alert[0x2c]	8247	1			T17	87		T6	1		T10	1
alert[0x2d]	3972	1			T1	1		T3	7		T17	54
alert[0x2e]	4973	1			T26	2		T15	1		T225	1
alert[0x2f]	7822	1			T1	30		T3	21		T17	62
alert[0x30]	6939	1			T211	1		T72	13		T29	20
alert[0x31]	9576	1			T43	40		T26	233		T75	2458
alert[0x32]	8844	1			T3	2		T6	1		T32	90
alert[0x33]	1736	1			T43	1		T32	142		T212	1
alert[0x34]	5229	1			T10	1		T43	1		T66	1
alert[0x35]	9732	1			T1	586		T6	2		T10	1
alert[0x36]	7789	1			T1	11		T3	1		T17	132
alert[0x37]	5858	1			T10	1		T26	234		T75	17
alert[0x38]	10892	1			T1	115		T17	6		T32	15
alert[0x39]	7431	1			T1	23		T3	29		T66	1
alert[0x3a]	3680	1			T3	2		T17	208		T32	154
alert[0x3b]	9884	1			T43	1		T66	1		T211	1
alert[0x3c]	2526	1			T3	4		T43	2		T26	303
alert[0x3d]	5438	1			T1	22		T10	2		T32	832
alert[0x3e]	13309	1			T1	297		T17	5088		T75	130
alert[0x3f]	3998	1			T3	1		T17	40		T75	76
alert[0x40]	3070	1			T1	227		T17	2		T26	17

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	85559	1			T1	66		T17	21045		T6	1
class_i[0x1]	126434	1			T1	2380		T10	1		T26	15
class_i[0x2]	100542	1			T3	36		T17	18		T43	97
class_i[0x3]	143626	1			T1	2461		T3	478		T17	91

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

455509

1

T1

4907

T3

514

T17

21154

alert_ping_fail

652

1

T6

21

T10

13

T11

11

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	14190	1			T3	42		T17	5393		T77	4
alert_integrity_fail	alert[0x1]	12398	1			T1	2633		T26	1		T72	31
alert_integrity_fail	alert[0x2]	8878	1			T75	259		T72	201		T30	7
alert_integrity_fail	alert[0x3]	2764	1			T1	25		T3	10		T17	46
alert_integrity_fail	alert[0x4]	5627	1			T1	331		T44	1		T29	310
alert_integrity_fail	alert[0x5]	3171	1			T32	213		T290	1		T293	57
alert_integrity_fail	alert[0x6]	2825	1			T3	5		T17	54		T26	1
alert_integrity_fail	alert[0x7]	13415	1			T17	195		T75	20		T72	211
alert_integrity_fail	alert[0x8]	4707	1			T3	63		T32	12		T72	81
alert_integrity_fail	alert[0x9]	5530	1			T1	17		T3	7		T43	27
alert_integrity_fail	alert[0xa]	4183	1			T3	2		T17	29		T43	11
alert_integrity_fail	alert[0xb]	8200	1			T30	1378		T292	329		T53	1209
alert_integrity_fail	alert[0xc]	4687	1			T1	7		T3	6		T26	783
alert_integrity_fail	alert[0xd]	5311	1			T1	38		T3	19		T17	59
alert_integrity_fail	alert[0xe]	5062	1			T1	12		T17	220		T75	319
alert_integrity_fail	alert[0xf]	8331	1			T3	16		T17	249		T26	43
alert_integrity_fail	alert[0x10]	4495	1			T30	14		T77	3		T47	66
alert_integrity_fail	alert[0x11]	10029	1			T1	5		T3	8		T17	108
alert_integrity_fail	alert[0x12]	9030	1			T3	2		T17	409		T26	347
alert_integrity_fail	alert[0x13]	12933	1			T17	37		T26	12		T32	77
alert_integrity_fail	alert[0x14]	14558	1			T3	10		T17	78		T75	53
alert_integrity_fail	alert[0x15]	7814	1			T17	1961		T75	465		T72	53
alert_integrity_fail	alert[0x16]	12645	1			T17	138		T26	438		T72	3935
alert_integrity_fail	alert[0x17]	4623	1			T17	73		T26	20		T72	76
alert_integrity_fail	alert[0x18]	5865	1			T1	242		T72	515		T29	7
alert_integrity_fail	alert[0x19]	7001	1			T17	40		T43	2		T29	4
alert_integrity_fail	alert[0x1a]	1787	1			T1	40		T32	15		T77	12
alert_integrity_fail	alert[0x1b]	5510	1			T3	7		T17	75		T75	18
alert_integrity_fail	alert[0x1c]	1995	1			T17	371		T43	1		T77	65
alert_integrity_fail	alert[0x1d]	8817	1			T26	2306		T72	559		T30	472
alert_integrity_fail	alert[0x1e]	3616	1			T3	1		T17	281		T72	156
alert_integrity_fail	alert[0x1f]	17516	1			T1	190		T17	3479		T44	3
alert_integrity_fail	alert[0x20]	4745	1			T17	577		T72	21		T30	26
alert_integrity_fail	alert[0x21]	4251	1			T1	23		T3	69		T26	61
alert_integrity_fail	alert[0x22]	10239	1			T3	143		T26	5		T96	2
alert_integrity_fail	alert[0x23]	3546	1			T3	5		T26	229		T72	184
alert_integrity_fail	alert[0x24]	10307	1			T17	36		T43	5		T32	2
alert_integrity_fail	alert[0x25]	5384	1			T1	11		T29	29		T30	450
alert_integrity_fail	alert[0x26]	3947	1			T3	29		T17	1		T43	4
alert_integrity_fail	alert[0x27]	11833	1			T3	2		T26	112		T32	342
alert_integrity_fail	alert[0x28]	12620	1			T32	28		T72	22		T77	4
alert_integrity_fail	alert[0x29]	3356	1			T1	21		T17	269		T43	2
alert_integrity_fail	alert[0x2a]	4499	1			T3	1		T17	1269		T30	97
alert_integrity_fail	alert[0x2b]	2526	1			T17	28		T75	244		T72	132
alert_integrity_fail	alert[0x2c]	8234	1			T17	87		T32	54		T29	107
alert_integrity_fail	alert[0x2d]	3958	1			T1	1		T3	7		T17	54
alert_integrity_fail	alert[0x2e]	4961	1			T26	2		T77	2		T47	44
alert_integrity_fail	alert[0x2f]	7813	1			T1	30		T3	21		T17	62
alert_integrity_fail	alert[0x30]	6932	1			T211	1		T72	13		T29	20
alert_integrity_fail	alert[0x31]	9566	1			T43	40		T26	233		T75	2458
alert_integrity_fail	alert[0x32]	8835	1			T3	2		T32	90		T77	12
alert_integrity_fail	alert[0x33]	1728	1			T43	1		T32	142		T72	55
alert_integrity_fail	alert[0x34]	5223	1			T43	1		T77	2		T51	17
alert_integrity_fail	alert[0x35]	9714	1			T1	586		T75	25		T211	3
alert_integrity_fail	alert[0x36]	7778	1			T1	11		T3	1		T17	132
alert_integrity_fail	alert[0x37]	5847	1			T26	234		T75	17		T77	7
alert_integrity_fail	alert[0x38]	10885	1			T1	115		T17	6		T32	15
alert_integrity_fail	alert[0x39]	7421	1			T1	23		T3	29		T30	200
alert_integrity_fail	alert[0x3a]	3668	1			T3	2		T17	208		T32	154
alert_integrity_fail	alert[0x3b]	9878	1			T43	1		T211	1		T29	16
alert_integrity_fail	alert[0x3c]	2512	1			T3	4		T43	2		T26	303
alert_integrity_fail	alert[0x3d]	5422	1			T1	22		T32	832		T75	314
alert_integrity_fail	alert[0x3e]	13304	1			T1	297		T17	5088		T75	130
alert_integrity_fail	alert[0x3f]	3995	1			T3	1		T17	40		T75	76
alert_integrity_fail	alert[0x40]	3069	1			T1	227		T17	2		T26	17
alert_ping_fail	alert[0x0]	9	1			T15	1		T294	1		T295	1
alert_ping_fail	alert[0x1]	15	1			T66	1		T218	1		T296	1
alert_ping_fail	alert[0x2]	11	1			T6	1		T15	1		T297	1
alert_ping_fail	alert[0x3]	5	1			T225	1		T218	1		T298	1
alert_ping_fail	alert[0x4]	9	1			T6	1		T10	1		T299	1
alert_ping_fail	alert[0x5]	14	1			T291	1		T300	1		T301	1
alert_ping_fail	alert[0x6]	12	1			T66	1		T218	1		T294	1
alert_ping_fail	alert[0x7]	8	1			T291	1		T302	1		T244	1
alert_ping_fail	alert[0x8]	12	1			T6	1		T294	1		T106	1
alert_ping_fail	alert[0x9]	7	1			T291	1		T297	1		T303	1
alert_ping_fail	alert[0xa]	9	1			T225	1		T218	1		T304	1
alert_ping_fail	alert[0xb]	9	1			T218	2		T106	1		T297	1
alert_ping_fail	alert[0xc]	10	1			T188	1		T218	1		T296	1
alert_ping_fail	alert[0xd]	10	1			T10	1		T66	1		T225	1
alert_ping_fail	alert[0xe]	7	1			T66	1		T304	1		T305	1
alert_ping_fail	alert[0xf]	4	1			T291	1		T306	1		T307	1
alert_ping_fail	alert[0x10]	10	1			T6	1		T106	1		T308	1
alert_ping_fail	alert[0x11]	7	1			T6	1		T10	1		T225	1
alert_ping_fail	alert[0x12]	6	1			T66	1		T304	2		T309	1
alert_ping_fail	alert[0x13]	18	1			T10	1		T66	1		T67	1
alert_ping_fail	alert[0x14]	12	1			T67	1		T240	1		T218	1
alert_ping_fail	alert[0x15]	13	1			T6	1		T212	1		T289	1
alert_ping_fail	alert[0x16]	19	1			T66	1		T67	2		T212	2
alert_ping_fail	alert[0x17]	13	1			T6	1		T225	1		T212	1
alert_ping_fail	alert[0x18]	14	1			T15	1		T66	1		T212	1
alert_ping_fail	alert[0x19]	7	1			T6	1		T15	1		T299	1
alert_ping_fail	alert[0x1a]	4	1			T11	1		T296	1		T299	1
alert_ping_fail	alert[0x1b]	17	1			T11	1		T66	1		T225	1
alert_ping_fail	alert[0x1c]	4	1			T11	2		T295	1		T310	1
alert_ping_fail	alert[0x1d]	10	1			T10	1		T11	2		T289	1
alert_ping_fail	alert[0x1e]	6	1			T10	1		T225	1		T212	2
alert_ping_fail	alert[0x1f]	18	1			T212	1		T218	1		T220	1
alert_ping_fail	alert[0x20]	6	1			T188	1		T218	1		T291	1
alert_ping_fail	alert[0x21]	9	1			T6	2		T291	2		T301	1
alert_ping_fail	alert[0x22]	15	1			T6	1		T218	1		T232	1
alert_ping_fail	alert[0x23]	8	1			T6	1		T225	1		T212	1
alert_ping_fail	alert[0x24]	10	1			T15	1		T66	1		T225	2
alert_ping_fail	alert[0x25]	9	1			T6	1		T11	1		T218	1
alert_ping_fail	alert[0x26]	5	1			T11	1		T106	1		T306	1
alert_ping_fail	alert[0x27]	8	1			T188	1		T299	1		T301	1
alert_ping_fail	alert[0x28]	14	1			T10	1		T15	1		T66	1
alert_ping_fail	alert[0x29]	8	1			T299	1		T300	1		T308	1
alert_ping_fail	alert[0x2a]	11	1			T6	1		T188	1		T291	1
alert_ping_fail	alert[0x2b]	18	1			T11	1		T15	1		T304	1
alert_ping_fail	alert[0x2c]	13	1			T6	1		T10	1		T212	1
alert_ping_fail	alert[0x2d]	14	1			T286	1		T294	1		T299	1
alert_ping_fail	alert[0x2e]	12	1			T15	1		T225	1		T232	1
alert_ping_fail	alert[0x2f]	9	1			T6	1		T218	3		T289	1
alert_ping_fail	alert[0x30]	7	1			T301	1		T308	1		T311	2
alert_ping_fail	alert[0x31]	10	1			T188	1		T304	1		T296	1
alert_ping_fail	alert[0x32]	9	1			T6	1		T188	1		T296	1
alert_ping_fail	alert[0x33]	8	1			T212	1		T312	1		T301	1
alert_ping_fail	alert[0x34]	6	1			T10	1		T66	1		T218	1
alert_ping_fail	alert[0x35]	18	1			T6	2		T10	1		T15	1
alert_ping_fail	alert[0x36]	11	1			T6	2		T11	1		T225	1
alert_ping_fail	alert[0x37]	11	1			T10	1		T188	1		T299	1
alert_ping_fail	alert[0x38]	7	1			T300	1		T298	1		T306	1
alert_ping_fail	alert[0x39]	10	1			T66	1		T225	1		T106	1
alert_ping_fail	alert[0x3a]	12	1			T66	1		T218	2		T313	1
alert_ping_fail	alert[0x3b]	6	1			T66	1		T218	1		T313	1
alert_ping_fail	alert[0x3c]	14	1			T11	1		T304	1		T296	1
alert_ping_fail	alert[0x3d]	16	1			T10	2		T296	1		T300	1
alert_ping_fail	alert[0x3e]	5	1			T304	2		T313	1		T312	1
alert_ping_fail	alert[0x3f]	3	1			T304	1		T299	1		T309	1
alert_ping_fail	alert[0x40]	1	1			T314	1		-	-		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	85429	1			T1	66		T17	21045		T26	5269
alert_integrity_fail	class_i[0x1]	126247	1			T1	2380		T26	15		T32	2574
alert_integrity_fail	class_i[0x2]	100354	1			T3	36		T17	18		T43	97
alert_integrity_fail	class_i[0x3]	143479	1			T1	2461		T3	478		T17	91
alert_ping_fail	class_i[0x0]	130	1			T6	1		T10	12		T67	4
alert_ping_fail	class_i[0x1]	187	1			T10	1		T15	1		T223	1
alert_ping_fail	class_i[0x2]	188	1			T15	8		T66	13		T212	6
alert_ping_fail	class_i[0x3]	147	1			T6	20		T11	11		T66	2