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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.72 100.00 100.00 100.00 99.38 99.60


Total test records in report: 833
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T115 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3825612592 Jul 05 04:30:33 PM PDT 24 Jul 05 04:35:08 PM PDT 24 4452010484 ps
T773 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3690084962 Jul 05 04:30:21 PM PDT 24 Jul 05 04:30:27 PM PDT 24 99044691 ps
T774 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.921682315 Jul 05 04:30:48 PM PDT 24 Jul 05 04:30:50 PM PDT 24 13580531 ps
T775 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2750176882 Jul 05 04:30:45 PM PDT 24 Jul 05 04:30:47 PM PDT 24 9643065 ps
T776 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2007731654 Jul 05 04:30:39 PM PDT 24 Jul 05 04:30:44 PM PDT 24 17550661 ps
T130 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1173461511 Jul 05 04:30:19 PM PDT 24 Jul 05 04:31:57 PM PDT 24 1726614511 ps
T777 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2947051293 Jul 05 04:30:10 PM PDT 24 Jul 05 04:30:17 PM PDT 24 21879532 ps
T778 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4245190659 Jul 05 04:30:31 PM PDT 24 Jul 05 04:30:43 PM PDT 24 48094003 ps
T117 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4285186409 Jul 05 04:30:37 PM PDT 24 Jul 05 04:35:39 PM PDT 24 2334151908 ps
T779 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1315819780 Jul 05 04:30:36 PM PDT 24 Jul 05 04:30:42 PM PDT 24 10635693 ps
T141 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2846693295 Jul 05 04:30:19 PM PDT 24 Jul 05 04:34:58 PM PDT 24 8854679854 ps
T780 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3219901254 Jul 05 04:30:16 PM PDT 24 Jul 05 04:30:21 PM PDT 24 12505109 ps
T136 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.458807035 Jul 05 04:30:29 PM PDT 24 Jul 05 04:39:05 PM PDT 24 11507094891 ps
T781 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2943132200 Jul 05 04:30:22 PM PDT 24 Jul 05 04:30:31 PM PDT 24 68644450 ps
T166 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.201753814 Jul 05 04:30:16 PM PDT 24 Jul 05 04:30:24 PM PDT 24 89103387 ps
T131 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2751949264 Jul 05 04:30:21 PM PDT 24 Jul 05 04:33:39 PM PDT 24 6151523066 ps
T782 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3528709857 Jul 05 04:30:28 PM PDT 24 Jul 05 04:37:06 PM PDT 24 8925375657 ps
T783 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2357806785 Jul 05 04:30:28 PM PDT 24 Jul 05 04:30:49 PM PDT 24 942850201 ps
T784 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3125073281 Jul 05 04:30:33 PM PDT 24 Jul 05 04:30:41 PM PDT 24 36330184 ps
T785 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.844605193 Jul 05 04:30:36 PM PDT 24 Jul 05 04:31:18 PM PDT 24 614857952 ps
T786 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2099363237 Jul 05 04:30:26 PM PDT 24 Jul 05 04:30:44 PM PDT 24 208407148 ps
T787 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.4012738925 Jul 05 04:30:15 PM PDT 24 Jul 05 04:30:39 PM PDT 24 336708977 ps
T139 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.394879962 Jul 05 04:30:30 PM PDT 24 Jul 05 04:45:42 PM PDT 24 26242160511 ps
T140 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.534533053 Jul 05 04:30:10 PM PDT 24 Jul 05 04:46:32 PM PDT 24 12923204473 ps
T788 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.984644893 Jul 05 04:30:43 PM PDT 24 Jul 05 04:31:05 PM PDT 24 177742148 ps
T789 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3699002797 Jul 05 04:30:18 PM PDT 24 Jul 05 04:30:25 PM PDT 24 57466093 ps
T790 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.480373219 Jul 05 04:30:20 PM PDT 24 Jul 05 04:30:25 PM PDT 24 60603448 ps
T791 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.398653218 Jul 05 04:30:24 PM PDT 24 Jul 05 04:30:53 PM PDT 24 172351926 ps
T792 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3651093651 Jul 05 04:30:08 PM PDT 24 Jul 05 04:30:32 PM PDT 24 1172441338 ps
T793 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1973405555 Jul 05 04:30:18 PM PDT 24 Jul 05 04:30:25 PM PDT 24 1196678297 ps
T163 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2941557018 Jul 05 04:30:31 PM PDT 24 Jul 05 04:30:44 PM PDT 24 41249750 ps
T127 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1502431422 Jul 05 04:30:34 PM PDT 24 Jul 05 04:35:53 PM PDT 24 9980471009 ps
T145 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.821311734 Jul 05 04:30:21 PM PDT 24 Jul 05 04:32:51 PM PDT 24 10867393531 ps
T794 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1923035177 Jul 05 04:30:32 PM PDT 24 Jul 05 04:30:38 PM PDT 24 9356286 ps
T795 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2484202705 Jul 05 04:30:40 PM PDT 24 Jul 05 04:30:45 PM PDT 24 15063106 ps
T796 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.80955999 Jul 05 04:30:31 PM PDT 24 Jul 05 04:30:37 PM PDT 24 6470673 ps
T137 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1845475422 Jul 05 04:30:22 PM PDT 24 Jul 05 04:40:40 PM PDT 24 4832642872 ps
T128 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3816275520 Jul 05 04:30:31 PM PDT 24 Jul 05 04:40:13 PM PDT 24 59848579135 ps
T146 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.577980290 Jul 05 04:30:17 PM PDT 24 Jul 05 04:31:40 PM PDT 24 906338547 ps
T160 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.4021144147 Jul 05 04:30:13 PM PDT 24 Jul 05 04:30:19 PM PDT 24 105917020 ps
T797 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3199495044 Jul 05 04:30:22 PM PDT 24 Jul 05 04:30:26 PM PDT 24 18854402 ps
T798 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1668621380 Jul 05 04:30:11 PM PDT 24 Jul 05 04:30:20 PM PDT 24 1697022416 ps
T799 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4048385587 Jul 05 04:30:27 PM PDT 24 Jul 05 04:31:08 PM PDT 24 1898971782 ps
T800 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.190677630 Jul 05 04:30:15 PM PDT 24 Jul 05 04:30:25 PM PDT 24 448536559 ps
T801 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1182449006 Jul 05 04:30:39 PM PDT 24 Jul 05 04:30:47 PM PDT 24 33729061 ps
T802 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2020248915 Jul 05 04:30:09 PM PDT 24 Jul 05 04:30:23 PM PDT 24 587264921 ps
T803 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3272919292 Jul 05 04:30:42 PM PDT 24 Jul 05 04:30:56 PM PDT 24 2439080158 ps
T804 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1149296652 Jul 05 04:30:24 PM PDT 24 Jul 05 04:30:31 PM PDT 24 10663742 ps
T805 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.20878093 Jul 05 04:30:39 PM PDT 24 Jul 05 04:30:44 PM PDT 24 13723052 ps
T806 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.514263217 Jul 05 04:30:24 PM PDT 24 Jul 05 04:30:38 PM PDT 24 491024945 ps
T807 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3319563191 Jul 05 04:30:33 PM PDT 24 Jul 05 04:30:48 PM PDT 24 1231205706 ps
T808 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1461799231 Jul 05 04:30:33 PM PDT 24 Jul 05 04:30:39 PM PDT 24 19918157 ps
T809 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2055566410 Jul 05 04:30:37 PM PDT 24 Jul 05 04:30:54 PM PDT 24 143032551 ps
T810 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1527294836 Jul 05 04:30:20 PM PDT 24 Jul 05 04:30:46 PM PDT 24 250872826 ps
T811 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2324815854 Jul 05 04:31:19 PM PDT 24 Jul 05 04:31:24 PM PDT 24 32840519 ps
T812 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2903076094 Jul 05 04:30:30 PM PDT 24 Jul 05 04:33:14 PM PDT 24 3268766755 ps
T813 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1378546538 Jul 05 04:30:29 PM PDT 24 Jul 05 04:30:36 PM PDT 24 8743808 ps
T121 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1482829334 Jul 05 04:30:41 PM PDT 24 Jul 05 04:34:27 PM PDT 24 7512778233 ps
T147 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4041230483 Jul 05 04:30:17 PM PDT 24 Jul 05 04:34:05 PM PDT 24 2699128245 ps
T814 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.101476096 Jul 05 04:30:14 PM PDT 24 Jul 05 04:33:58 PM PDT 24 3458487265 ps
T142 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1589578309 Jul 05 04:30:04 PM PDT 24 Jul 05 04:32:53 PM PDT 24 16771989097 ps
T815 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2487878332 Jul 05 04:30:23 PM PDT 24 Jul 05 04:32:16 PM PDT 24 1664032978 ps
T816 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.4167906271 Jul 05 04:30:22 PM PDT 24 Jul 05 04:30:30 PM PDT 24 23314156 ps
T817 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2832269458 Jul 05 04:30:19 PM PDT 24 Jul 05 04:30:27 PM PDT 24 44839299 ps
T818 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1813992274 Jul 05 04:30:32 PM PDT 24 Jul 05 04:30:59 PM PDT 24 1316754226 ps
T819 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.4139147535 Jul 05 04:30:43 PM PDT 24 Jul 05 04:30:53 PM PDT 24 617010004 ps
T820 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3578923328 Jul 05 04:30:29 PM PDT 24 Jul 05 04:30:36 PM PDT 24 23503057 ps
T821 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2645560780 Jul 05 04:30:39 PM PDT 24 Jul 05 04:30:54 PM PDT 24 118966302 ps
T822 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3248531059 Jul 05 04:30:31 PM PDT 24 Jul 05 04:30:42 PM PDT 24 50380122 ps
T823 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.428824025 Jul 05 04:30:34 PM PDT 24 Jul 05 04:30:52 PM PDT 24 693743352 ps
T824 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3249926724 Jul 05 04:30:31 PM PDT 24 Jul 05 04:30:57 PM PDT 24 1371901178 ps
T825 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1532651720 Jul 05 04:30:31 PM PDT 24 Jul 05 04:30:37 PM PDT 24 11754726 ps
T826 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2021443168 Jul 05 04:30:16 PM PDT 24 Jul 05 04:30:24 PM PDT 24 184711212 ps
T827 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2621830653 Jul 05 04:30:31 PM PDT 24 Jul 05 04:30:49 PM PDT 24 335305013 ps
T144 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2615137886 Jul 05 04:30:07 PM PDT 24 Jul 05 04:31:40 PM PDT 24 1563462303 ps
T828 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3286358399 Jul 05 04:30:12 PM PDT 24 Jul 05 04:30:25 PM PDT 24 77457440 ps
T143 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3460409282 Jul 05 04:30:25 PM PDT 24 Jul 05 04:32:19 PM PDT 24 6574750169 ps
T829 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1203490586 Jul 05 04:30:26 PM PDT 24 Jul 05 04:30:37 PM PDT 24 76635819 ps
T170 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1669543270 Jul 05 04:30:25 PM PDT 24 Jul 05 04:30:36 PM PDT 24 98205239 ps
T830 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.92363017 Jul 05 04:30:39 PM PDT 24 Jul 05 04:30:44 PM PDT 24 10240154 ps
T831 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3441191573 Jul 05 04:30:18 PM PDT 24 Jul 05 04:30:29 PM PDT 24 71991054 ps
T832 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1337767326 Jul 05 04:30:11 PM PDT 24 Jul 05 04:33:26 PM PDT 24 6802295540 ps
T833 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1418834979 Jul 05 04:30:24 PM PDT 24 Jul 05 04:30:38 PM PDT 24 375332116 ps

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.162655384
Short name T3
Test name
Test status
Simulation time 191936791222 ps
CPU time 6577.21 seconds
Started Jul 05 04:44:24 PM PDT 24
Finished Jul 05 06:34:03 PM PDT 24
Peak memory 339024 kb
Host smart-eddb3b77-a96c-4a58-a009-0b465a4200b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162655384 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.162655384
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3247573444
Short name T4
Test name
Test status
Simulation time 1437207282 ps
CPU time 54.16 seconds
Started Jul 05 04:42:46 PM PDT 24
Finished Jul 05 04:43:42 PM PDT 24
Peak memory 271152 kb
Host smart-14475db0-213b-4d59-879b-e16794313585
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3247573444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3247573444
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1499107300
Short name T77
Test name
Test status
Simulation time 78706833065 ps
CPU time 3254.7 seconds
Started Jul 05 04:43:27 PM PDT 24
Finished Jul 05 05:37:44 PM PDT 24
Peak memory 282136 kb
Host smart-136fabdb-e7a0-475f-a250-d8248aa5ba0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499107300 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1499107300
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1373453970
Short name T148
Test name
Test status
Simulation time 623982382 ps
CPU time 19.42 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:31:01 PM PDT 24
Peak memory 240372 kb
Host smart-a34770e9-d783-4683-9653-b80ee55148b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1373453970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1373453970
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2965885318
Short name T14
Test name
Test status
Simulation time 418671139 ps
CPU time 19.92 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:43:43 PM PDT 24
Peak memory 249152 kb
Host smart-9a4b3f40-1064-4994-8082-f12eec7ae94e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2965885318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2965885318
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3209322486
Short name T112
Test name
Test status
Simulation time 1753467489 ps
CPU time 205.11 seconds
Started Jul 05 04:30:08 PM PDT 24
Finished Jul 05 04:33:36 PM PDT 24
Peak memory 265232 kb
Host smart-a694bfe2-dfea-423d-838a-52e83bcf3c1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3209322486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3209322486
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1975277348
Short name T666
Test name
Test status
Simulation time 204719666725 ps
CPU time 3433.36 seconds
Started Jul 05 04:43:19 PM PDT 24
Finished Jul 05 05:40:36 PM PDT 24
Peak memory 298720 kb
Host smart-0eaf1e32-1f58-4839-9716-ca5ab929a570
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975277348 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1975277348
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2922175548
Short name T514
Test name
Test status
Simulation time 13191976055 ps
CPU time 1089.57 seconds
Started Jul 05 04:43:31 PM PDT 24
Finished Jul 05 05:01:43 PM PDT 24
Peak memory 284160 kb
Host smart-90aa10e2-737a-4c70-a99c-6282c0622033
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922175548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2922175548
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3199517657
Short name T67
Test name
Test status
Simulation time 172684179288 ps
CPU time 1945.26 seconds
Started Jul 05 04:43:23 PM PDT 24
Finished Jul 05 05:15:50 PM PDT 24
Peak memory 282100 kb
Host smart-7a8dcbd8-b46f-462c-b404-8081ab1f523a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199517657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3199517657
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.4200918883
Short name T34
Test name
Test status
Simulation time 17590153117 ps
CPU time 1159.32 seconds
Started Jul 05 04:43:19 PM PDT 24
Finished Jul 05 05:02:40 PM PDT 24
Peak memory 273432 kb
Host smart-c8557da7-29f0-4d6e-b85a-e3a45ffd0b72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200918883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.4200918883
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.732996392
Short name T114
Test name
Test status
Simulation time 6128529702 ps
CPU time 678.62 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:41:56 PM PDT 24
Peak memory 265292 kb
Host smart-921dbe88-1d5c-4e80-b304-f4f79b106872
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732996392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.732996392
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.4031569490
Short name T85
Test name
Test status
Simulation time 52061339255 ps
CPU time 2245.76 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 05:20:31 PM PDT 24
Peak memory 322488 kb
Host smart-9248f8db-81ff-45ff-9982-8ec769c266ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031569490 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.4031569490
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2104433677
Short name T122
Test name
Test status
Simulation time 68390278991 ps
CPU time 234.23 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:34:35 PM PDT 24
Peak memory 270784 kb
Host smart-6e24d902-188d-470d-be6f-0ffddfd3ae90
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2104433677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2104433677
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1808467150
Short name T29
Test name
Test status
Simulation time 135673158838 ps
CPU time 4273.18 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 05:54:18 PM PDT 24
Peak memory 349812 kb
Host smart-b618020d-affc-422f-9d93-28e9733f7dc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808467150 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1808467150
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.4215251703
Short name T289
Test name
Test status
Simulation time 48684026463 ps
CPU time 2727.43 seconds
Started Jul 05 04:43:10 PM PDT 24
Finished Jul 05 05:28:40 PM PDT 24
Peak memory 288248 kb
Host smart-09c38500-5550-4e8f-9d1a-9e33dba2edf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215251703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4215251703
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3816275520
Short name T128
Test name
Test status
Simulation time 59848579135 ps
CPU time 576.64 seconds
Started Jul 05 04:30:31 PM PDT 24
Finished Jul 05 04:40:13 PM PDT 24
Peak memory 265416 kb
Host smart-e231f18a-4bcc-4c85-9d17-174259f8ce93
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816275520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3816275520
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1225749238
Short name T152
Test name
Test status
Simulation time 47147430 ps
CPU time 1.26 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:30:27 PM PDT 24
Peak memory 237412 kb
Host smart-903e4526-5826-4395-9132-0692b9f207bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1225749238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1225749238
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1230919193
Short name T218
Test name
Test status
Simulation time 22888004081 ps
CPU time 508.72 seconds
Started Jul 05 04:43:27 PM PDT 24
Finished Jul 05 04:51:58 PM PDT 24
Peak memory 256244 kb
Host smart-0f830ec1-a3bf-4ad5-ad61-9d5097ef5961
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230919193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1230919193
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.856806014
Short name T109
Test name
Test status
Simulation time 4479126533 ps
CPU time 301.34 seconds
Started Jul 05 04:30:34 PM PDT 24
Finished Jul 05 04:35:44 PM PDT 24
Peak memory 272624 kb
Host smart-360e84ec-5478-4e16-b424-51f4f488f087
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=856806014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.856806014
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2778170874
Short name T302
Test name
Test status
Simulation time 240170944878 ps
CPU time 2472.21 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 05:24:17 PM PDT 24
Peak memory 287100 kb
Host smart-ff078943-37ee-4959-ade8-e166d650a304
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778170874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2778170874
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3458550799
Short name T1
Test name
Test status
Simulation time 238374523068 ps
CPU time 3653.6 seconds
Started Jul 05 04:43:08 PM PDT 24
Finished Jul 05 05:44:04 PM PDT 24
Peak memory 338520 kb
Host smart-57ba965f-e807-4fdb-9fc8-019b21eb715d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458550799 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3458550799
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3511418517
Short name T119
Test name
Test status
Simulation time 4545666658 ps
CPU time 618.56 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:40:41 PM PDT 24
Peak memory 265212 kb
Host smart-484cb3a9-967f-4e03-aa56-11073e5d72b9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511418517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3511418517
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1757587378
Short name T6
Test name
Test status
Simulation time 46694327788 ps
CPU time 505.67 seconds
Started Jul 05 04:42:47 PM PDT 24
Finished Jul 05 04:51:15 PM PDT 24
Peak memory 249384 kb
Host smart-fb8ece15-962a-40b1-9ec4-e87e07313c55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757587378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1757587378
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1205994080
Short name T150
Test name
Test status
Simulation time 2135582920 ps
CPU time 31.82 seconds
Started Jul 05 04:30:19 PM PDT 24
Finished Jul 05 04:30:53 PM PDT 24
Peak memory 240376 kb
Host smart-1f4916a4-0295-4cf7-83f1-b6a361a18867
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1205994080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1205994080
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2420004096
Short name T47
Test name
Test status
Simulation time 586535067512 ps
CPU time 8152.82 seconds
Started Jul 05 04:44:00 PM PDT 24
Finished Jul 05 06:59:54 PM PDT 24
Peak memory 371624 kb
Host smart-cdc14a0b-2823-429b-abb2-cf26427b44e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420004096 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2420004096
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3089284670
Short name T299
Test name
Test status
Simulation time 26501260959 ps
CPU time 563.69 seconds
Started Jul 05 04:43:05 PM PDT 24
Finished Jul 05 04:52:30 PM PDT 24
Peak memory 249384 kb
Host smart-2a766665-3e89-4065-8ad5-53b1adcd60ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089284670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3089284670
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3856540758
Short name T129
Test name
Test status
Simulation time 20804540194 ps
CPU time 924.65 seconds
Started Jul 05 04:30:33 PM PDT 24
Finished Jul 05 04:46:02 PM PDT 24
Peak memory 265364 kb
Host smart-847b2885-9e0d-4fb6-ba25-2afd6a8c68e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856540758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3856540758
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2193584235
Short name T60
Test name
Test status
Simulation time 97829290991 ps
CPU time 2755.79 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 05:29:22 PM PDT 24
Peak memory 289672 kb
Host smart-207e932e-1833-4309-9468-d6f59e32746c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193584235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2193584235
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1860724685
Short name T315
Test name
Test status
Simulation time 50749268767 ps
CPU time 2737.26 seconds
Started Jul 05 04:43:27 PM PDT 24
Finished Jul 05 05:29:06 PM PDT 24
Peak memory 289452 kb
Host smart-82f04d4f-dd66-4576-8054-220ffc96f5f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860724685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1860724685
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1791441565
Short name T17
Test name
Test status
Simulation time 63936281355 ps
CPU time 3379.28 seconds
Started Jul 05 04:44:32 PM PDT 24
Finished Jul 05 05:40:52 PM PDT 24
Peak memory 305656 kb
Host smart-3fcf8f89-caa2-47dd-9480-ccfe585e4273
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791441565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1791441565
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.577980290
Short name T146
Test name
Test status
Simulation time 906338547 ps
CPU time 80.94 seconds
Started Jul 05 04:30:17 PM PDT 24
Finished Jul 05 04:31:40 PM PDT 24
Peak memory 257036 kb
Host smart-a8fbd0cb-29b2-4c6a-8578-3a792b5b1b8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=577980290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.577980290
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2846693295
Short name T141
Test name
Test status
Simulation time 8854679854 ps
CPU time 276.53 seconds
Started Jul 05 04:30:19 PM PDT 24
Finished Jul 05 04:34:58 PM PDT 24
Peak memory 265232 kb
Host smart-0dca3aab-1bfc-4490-a63f-1720e3a65c7a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846693295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2846693295
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.209062816
Short name T232
Test name
Test status
Simulation time 144906639694 ps
CPU time 2286.01 seconds
Started Jul 05 04:43:41 PM PDT 24
Finished Jul 05 05:21:49 PM PDT 24
Peak memory 288400 kb
Host smart-039aa0bf-952d-4664-a5bb-2ea206faac23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209062816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.209062816
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.361960329
Short name T106
Test name
Test status
Simulation time 13414087188 ps
CPU time 531.16 seconds
Started Jul 05 04:43:15 PM PDT 24
Finished Jul 05 04:52:07 PM PDT 24
Peak memory 249412 kb
Host smart-5a900fcc-6f87-4820-8612-f73b9598f9f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361960329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.361960329
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1716874681
Short name T245
Test name
Test status
Simulation time 30459444857 ps
CPU time 2103.02 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 05:17:53 PM PDT 24
Peak memory 287004 kb
Host smart-4efa65c9-0494-4dd1-8faf-59f2f2cc9b52
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716874681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1716874681
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2135980029
Short name T316
Test name
Test status
Simulation time 76838396064 ps
CPU time 1239.52 seconds
Started Jul 05 04:43:31 PM PDT 24
Finished Jul 05 05:04:12 PM PDT 24
Peak memory 273868 kb
Host smart-bbf57d61-55de-4269-88d1-8a93ae05d3f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135980029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2135980029
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1004114408
Short name T55
Test name
Test status
Simulation time 328215226535 ps
CPU time 1982.08 seconds
Started Jul 05 04:43:21 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 289828 kb
Host smart-d89b6842-c923-48de-ac57-4f6eb5d80c1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004114408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1004114408
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1482829334
Short name T121
Test name
Test status
Simulation time 7512778233 ps
CPU time 223.32 seconds
Started Jul 05 04:30:41 PM PDT 24
Finished Jul 05 04:34:27 PM PDT 24
Peak memory 265296 kb
Host smart-4221c66a-6896-42a2-ac7d-fd2c53cf3b5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1482829334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1482829334
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2321897775
Short name T151
Test name
Test status
Simulation time 14892498 ps
CPU time 1.48 seconds
Started Jul 05 04:30:29 PM PDT 24
Finished Jul 05 04:30:36 PM PDT 24
Peak memory 237452 kb
Host smart-5b38fc37-2778-4f77-b475-29e520609b59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2321897775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2321897775
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3923425247
Short name T688
Test name
Test status
Simulation time 14184511980 ps
CPU time 393.56 seconds
Started Jul 05 04:43:30 PM PDT 24
Finished Jul 05 04:50:06 PM PDT 24
Peak memory 249228 kb
Host smart-eb19d8d8-6a58-4fac-9e09-0906ad787493
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923425247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3923425247
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3417179178
Short name T311
Test name
Test status
Simulation time 649256062590 ps
CPU time 3116.42 seconds
Started Jul 05 04:44:28 PM PDT 24
Finished Jul 05 05:36:25 PM PDT 24
Peak memory 290328 kb
Host smart-d98cca15-1e85-46d9-90bb-418152283246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417179178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3417179178
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2868305773
Short name T108
Test name
Test status
Simulation time 9091381997 ps
CPU time 303.31 seconds
Started Jul 05 04:30:23 PM PDT 24
Finished Jul 05 04:35:32 PM PDT 24
Peak memory 269216 kb
Host smart-79b91903-3a2e-4f07-a51a-51aaf577881a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868305773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2868305773
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3644926548
Short name T254
Test name
Test status
Simulation time 133431933744 ps
CPU time 4998.69 seconds
Started Jul 05 04:44:39 PM PDT 24
Finished Jul 05 06:07:59 PM PDT 24
Peak memory 306080 kb
Host smart-dfc38b60-0654-4096-8e2d-3122aa15a2cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644926548 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3644926548
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.365872834
Short name T237
Test name
Test status
Simulation time 26147914483 ps
CPU time 1564.1 seconds
Started Jul 05 04:44:45 PM PDT 24
Finished Jul 05 05:10:50 PM PDT 24
Peak memory 286144 kb
Host smart-036600e9-020c-4e0a-b078-80bd74bf42b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365872834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.365872834
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1529933946
Short name T120
Test name
Test status
Simulation time 855400110 ps
CPU time 102.28 seconds
Started Jul 05 04:30:43 PM PDT 24
Finished Jul 05 04:32:27 PM PDT 24
Peak memory 265224 kb
Host smart-235bf3fd-3f3a-4eee-9913-081a77048cce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1529933946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1529933946
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.226511796
Short name T79
Test name
Test status
Simulation time 25008767552 ps
CPU time 1272.87 seconds
Started Jul 05 04:43:15 PM PDT 24
Finished Jul 05 05:04:30 PM PDT 24
Peak memory 290332 kb
Host smart-45222b39-d87e-4d63-b630-c75d90ec85dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226511796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.226511796
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.4011083761
Short name T212
Test name
Test status
Simulation time 7621909704 ps
CPU time 315.93 seconds
Started Jul 05 04:42:47 PM PDT 24
Finished Jul 05 04:48:05 PM PDT 24
Peak memory 249384 kb
Host smart-da9721f2-bd4c-4eac-bbca-15a4c20d256e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011083761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4011083761
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.18146
Short name T259
Test name
Test status
Simulation time 68707843440 ps
CPU time 2279.49 seconds
Started Jul 05 04:43:26 PM PDT 24
Finished Jul 05 05:21:28 PM PDT 24
Peak memory 290312 kb
Host smart-1f14ccdc-6e46-49f7-8a37-d48794e1ef6e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler
_stress_all.18146
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.836658540
Short name T295
Test name
Test status
Simulation time 5567581607 ps
CPU time 246.32 seconds
Started Jul 05 04:42:54 PM PDT 24
Finished Jul 05 04:47:01 PM PDT 24
Peak memory 256336 kb
Host smart-5a0d619c-4748-48f4-8985-cd955e578e2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836658540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.836658540
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1840893679
Short name T180
Test name
Test status
Simulation time 54009439 ps
CPU time 4.52 seconds
Started Jul 05 04:30:27 PM PDT 24
Finished Jul 05 04:30:38 PM PDT 24
Peak memory 237436 kb
Host smart-7c2443fa-0a32-4515-a54c-ca93b28ca7bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1840893679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1840893679
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2615137886
Short name T144
Test name
Test status
Simulation time 1563462303 ps
CPU time 89.17 seconds
Started Jul 05 04:30:07 PM PDT 24
Finished Jul 05 04:31:40 PM PDT 24
Peak memory 257128 kb
Host smart-57765a2d-4ad1-44ad-bf01-64e0efbe104c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2615137886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2615137886
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2222587146
Short name T162
Test name
Test status
Simulation time 605642064 ps
CPU time 3.45 seconds
Started Jul 05 04:30:35 PM PDT 24
Finished Jul 05 04:30:43 PM PDT 24
Peak memory 236344 kb
Host smart-aa676ea3-6915-4b95-8e11-8ec0a8c50b1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2222587146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2222587146
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.394879962
Short name T139
Test name
Test status
Simulation time 26242160511 ps
CPU time 906.87 seconds
Started Jul 05 04:30:30 PM PDT 24
Finished Jul 05 04:45:42 PM PDT 24
Peak memory 265296 kb
Host smart-c3c9ff05-778d-4d29-8dd8-2bd62629caea
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394879962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.394879962
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.929799940
Short name T207
Test name
Test status
Simulation time 64662200 ps
CPU time 3.73 seconds
Started Jul 05 04:42:42 PM PDT 24
Finished Jul 05 04:42:48 PM PDT 24
Peak memory 249524 kb
Host smart-6b07d433-94e4-4093-9104-a4892c03ce16
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=929799940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.929799940
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2063976621
Short name T195
Test name
Test status
Simulation time 124698980 ps
CPU time 2.15 seconds
Started Jul 05 04:42:47 PM PDT 24
Finished Jul 05 04:42:52 PM PDT 24
Peak memory 249400 kb
Host smart-6f9d39a4-9f32-4a91-b0da-39f1f42c3151
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2063976621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2063976621
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2122756194
Short name T196
Test name
Test status
Simulation time 42543546 ps
CPU time 3.86 seconds
Started Jul 05 04:42:58 PM PDT 24
Finished Jul 05 04:43:03 PM PDT 24
Peak memory 249536 kb
Host smart-fb3edb9a-8101-485f-86c4-13ea20c0b79e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2122756194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2122756194
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.4291659567
Short name T205
Test name
Test status
Simulation time 32961262 ps
CPU time 3.3 seconds
Started Jul 05 04:43:10 PM PDT 24
Finished Jul 05 04:43:16 PM PDT 24
Peak memory 249580 kb
Host smart-03dce1cb-1d51-4744-9512-0ceb1042b74d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4291659567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.4291659567
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2767785524
Short name T708
Test name
Test status
Simulation time 475168394530 ps
CPU time 1936.31 seconds
Started Jul 05 04:43:08 PM PDT 24
Finished Jul 05 05:15:26 PM PDT 24
Peak memory 273152 kb
Host smart-246c1a57-c1f8-4457-b707-5193dc6d7d59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767785524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2767785524
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1998448053
Short name T249
Test name
Test status
Simulation time 4475868233 ps
CPU time 53 seconds
Started Jul 05 04:42:40 PM PDT 24
Finished Jul 05 04:43:36 PM PDT 24
Peak memory 249208 kb
Host smart-1d88c719-32be-4f96-bea0-4e099acd00ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19984
48053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1998448053
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1638327614
Short name T265
Test name
Test status
Simulation time 281616382255 ps
CPU time 1292.22 seconds
Started Jul 05 04:43:29 PM PDT 24
Finished Jul 05 05:05:03 PM PDT 24
Peak memory 273740 kb
Host smart-6037295e-fb43-4aa1-b5f7-99171177e241
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638327614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1638327614
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.824453059
Short name T278
Test name
Test status
Simulation time 21946969865 ps
CPU time 1067.71 seconds
Started Jul 05 04:43:26 PM PDT 24
Finished Jul 05 05:01:16 PM PDT 24
Peak memory 290180 kb
Host smart-049269b4-31d7-42e9-a012-74b70e08295a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824453059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.824453059
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3504748269
Short name T589
Test name
Test status
Simulation time 171527382 ps
CPU time 15 seconds
Started Jul 05 04:42:42 PM PDT 24
Finished Jul 05 04:42:59 PM PDT 24
Peak memory 257368 kb
Host smart-59e6cc36-cd5f-4f5d-a429-285ecd37ef8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35047
48269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3504748269
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2792001862
Short name T271
Test name
Test status
Simulation time 44383025051 ps
CPU time 2994.29 seconds
Started Jul 05 04:43:37 PM PDT 24
Finished Jul 05 05:33:32 PM PDT 24
Peak memory 290040 kb
Host smart-3b2b7ceb-e29f-4d36-b7e4-c76897e1e088
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792001862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2792001862
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2663843596
Short name T25
Test name
Test status
Simulation time 103775696896 ps
CPU time 3509.86 seconds
Started Jul 05 04:42:47 PM PDT 24
Finished Jul 05 05:41:20 PM PDT 24
Peak memory 283228 kb
Host smart-885d00af-9c34-4adc-b540-d707bd785a1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663843596 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2663843596
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3124176302
Short name T740
Test name
Test status
Simulation time 20156151 ps
CPU time 1.24 seconds
Started Jul 05 04:30:28 PM PDT 24
Finished Jul 05 04:30:35 PM PDT 24
Peak memory 237404 kb
Host smart-37d09368-6a80-41da-a6b0-bd0fec1a426b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3124176302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3124176302
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.446301470
Short name T662
Test name
Test status
Simulation time 31292653071 ps
CPU time 886.5 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 04:57:48 PM PDT 24
Peak memory 265808 kb
Host smart-a86ddae1-ead5-4147-83ef-8d1761fd937b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446301470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.446301470
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.179121647
Short name T247
Test name
Test status
Simulation time 151173111305 ps
CPU time 2226.59 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 05:20:10 PM PDT 24
Peak memory 288148 kb
Host smart-5d56b504-7c2d-4bca-a65a-fb7e70d8c969
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179121647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.179121647
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2148633242
Short name T51
Test name
Test status
Simulation time 122925369670 ps
CPU time 1645.8 seconds
Started Jul 05 04:43:19 PM PDT 24
Finished Jul 05 05:10:48 PM PDT 24
Peak memory 298312 kb
Host smart-b9fd1913-50cd-43f5-9534-67d02f9573f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148633242 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2148633242
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.359797404
Short name T300
Test name
Test status
Simulation time 11154843080 ps
CPU time 441.81 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:50:45 PM PDT 24
Peak memory 249120 kb
Host smart-b1e550c5-0467-47e5-8806-6fb7dc9a4706
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359797404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.359797404
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2139100968
Short name T266
Test name
Test status
Simulation time 4118445823 ps
CPU time 58.24 seconds
Started Jul 05 04:43:26 PM PDT 24
Finished Jul 05 04:44:26 PM PDT 24
Peak memory 257044 kb
Host smart-3d55f043-ad8e-435e-9a97-b2e441a2e212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21391
00968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2139100968
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2778168444
Short name T236
Test name
Test status
Simulation time 687009279 ps
CPU time 25.64 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:43:49 PM PDT 24
Peak memory 248720 kb
Host smart-afdd6f65-742c-4859-bf92-ac718f07b665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27781
68444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2778168444
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3080684022
Short name T226
Test name
Test status
Simulation time 435793069719 ps
CPU time 5687.35 seconds
Started Jul 05 04:43:38 PM PDT 24
Finished Jul 05 06:18:27 PM PDT 24
Peak memory 319964 kb
Host smart-1c696102-2bed-4d46-b6b3-de25009d9bea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080684022 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3080684022
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2486291638
Short name T314
Test name
Test status
Simulation time 13199958494 ps
CPU time 521.82 seconds
Started Jul 05 04:44:01 PM PDT 24
Finished Jul 05 04:52:44 PM PDT 24
Peak memory 249140 kb
Host smart-47eaffe7-a0f2-4d93-8eac-7f32af216e21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486291638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2486291638
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2352545222
Short name T262
Test name
Test status
Simulation time 203545682952 ps
CPU time 2845.97 seconds
Started Jul 05 04:44:18 PM PDT 24
Finished Jul 05 05:31:47 PM PDT 24
Peak memory 289544 kb
Host smart-58416709-68c7-4dd2-988e-c0ac785b053c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352545222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2352545222
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.531025038
Short name T270
Test name
Test status
Simulation time 6264241624 ps
CPU time 56.36 seconds
Started Jul 05 04:44:24 PM PDT 24
Finished Jul 05 04:45:22 PM PDT 24
Peak memory 256136 kb
Host smart-a84e0ab2-2db8-4daa-8adc-c4aec5a00208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53102
5038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.531025038
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.916600750
Short name T105
Test name
Test status
Simulation time 450490726 ps
CPU time 51.91 seconds
Started Jul 05 04:44:39 PM PDT 24
Finished Jul 05 04:45:32 PM PDT 24
Peak memory 249720 kb
Host smart-1aa98b5e-9c21-46e3-ac91-0448ee5112e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91660
0750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.916600750
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3265959566
Short name T90
Test name
Test status
Simulation time 80678779365 ps
CPU time 1269.65 seconds
Started Jul 05 04:44:54 PM PDT 24
Finished Jul 05 05:06:05 PM PDT 24
Peak memory 282192 kb
Host smart-bc443995-5c9e-4bb5-8af5-889a1a71ae5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265959566 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3265959566
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2252949790
Short name T81
Test name
Test status
Simulation time 7360351264 ps
CPU time 870.79 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:57:54 PM PDT 24
Peak memory 273796 kb
Host smart-5f839e73-d8c8-4cf5-ac41-e3140248e8ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252949790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2252949790
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2751949264
Short name T131
Test name
Test status
Simulation time 6151523066 ps
CPU time 195.26 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:33:39 PM PDT 24
Peak memory 270900 kb
Host smart-900e1337-d79b-4451-bade-f5d5f4829ec9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2751949264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2751949264
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.166561625
Short name T158
Test name
Test status
Simulation time 1618610449 ps
CPU time 35.13 seconds
Started Jul 05 04:30:41 PM PDT 24
Finished Jul 05 04:31:19 PM PDT 24
Peak memory 248652 kb
Host smart-80882385-193a-4c09-b662-254e4c335ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=166561625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.166561625
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2647117567
Short name T164
Test name
Test status
Simulation time 1850917167 ps
CPU time 64.55 seconds
Started Jul 05 04:30:25 PM PDT 24
Finished Jul 05 04:31:36 PM PDT 24
Peak memory 240328 kb
Host smart-2a9b8043-399a-49c2-ab97-28b47bfac896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2647117567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2647117567
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3825612592
Short name T115
Test name
Test status
Simulation time 4452010484 ps
CPU time 269.96 seconds
Started Jul 05 04:30:33 PM PDT 24
Finished Jul 05 04:35:08 PM PDT 24
Peak memory 265228 kb
Host smart-0bd050fa-b3f7-4452-a020-ae191e80fc11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3825612592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3825612592
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1989244012
Short name T165
Test name
Test status
Simulation time 223522974 ps
CPU time 3.99 seconds
Started Jul 05 04:30:06 PM PDT 24
Finished Jul 05 04:30:14 PM PDT 24
Peak memory 238036 kb
Host smart-da85aa4a-7533-4f37-be07-52a4355be7e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1989244012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1989244012
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2934964950
Short name T154
Test name
Test status
Simulation time 1515838437 ps
CPU time 36.5 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:31:04 PM PDT 24
Peak memory 240360 kb
Host smart-3f76e29c-f407-4429-88a9-a94e869e12c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2934964950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2934964950
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1446416856
Short name T149
Test name
Test status
Simulation time 64315181 ps
CPU time 2.97 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 04:30:32 PM PDT 24
Peak memory 237500 kb
Host smart-721f79ca-73b8-4e2c-a66b-9d2bcfb93184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1446416856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1446416856
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3285308181
Short name T159
Test name
Test status
Simulation time 629928483 ps
CPU time 23.24 seconds
Started Jul 05 04:30:45 PM PDT 24
Finished Jul 05 04:31:09 PM PDT 24
Peak memory 240460 kb
Host smart-f5fe3e1b-b4a9-4594-bec0-2bc073bfeb22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3285308181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3285308181
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2750012904
Short name T156
Test name
Test status
Simulation time 155544085 ps
CPU time 2.62 seconds
Started Jul 05 04:30:15 PM PDT 24
Finished Jul 05 04:30:21 PM PDT 24
Peak memory 237416 kb
Host smart-3bdc1a05-be19-45b5-a607-e4c57f4ea89b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2750012904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2750012904
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1669543270
Short name T170
Test name
Test status
Simulation time 98205239 ps
CPU time 5.36 seconds
Started Jul 05 04:30:25 PM PDT 24
Finished Jul 05 04:30:36 PM PDT 24
Peak memory 238476 kb
Host smart-24be1c0d-b4f7-4ae0-8a2e-e130cd4c17d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1669543270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1669543270
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.201753814
Short name T166
Test name
Test status
Simulation time 89103387 ps
CPU time 4.65 seconds
Started Jul 05 04:30:16 PM PDT 24
Finished Jul 05 04:30:24 PM PDT 24
Peak memory 237696 kb
Host smart-abe78c19-98e2-4856-9e2c-64a58c5e8ece
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=201753814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.201753814
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3236917428
Short name T157
Test name
Test status
Simulation time 59403520 ps
CPU time 2.59 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:30:26 PM PDT 24
Peak memory 237660 kb
Host smart-73ee8f69-4365-456c-b9ae-8841fec82844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3236917428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3236917428
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2414340061
Short name T161
Test name
Test status
Simulation time 310014036 ps
CPU time 22.22 seconds
Started Jul 05 04:30:28 PM PDT 24
Finished Jul 05 04:30:56 PM PDT 24
Peak memory 245996 kb
Host smart-23bc352e-07b3-4996-bb89-921e1cd6b0e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2414340061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2414340061
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2941557018
Short name T163
Test name
Test status
Simulation time 41249750 ps
CPU time 3.38 seconds
Started Jul 05 04:30:31 PM PDT 24
Finished Jul 05 04:30:44 PM PDT 24
Peak memory 237800 kb
Host smart-d3917485-e518-4c99-8834-f47adf45096b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2941557018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2941557018
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2840141451
Short name T155
Test name
Test status
Simulation time 854529683 ps
CPU time 20.59 seconds
Started Jul 05 04:30:40 PM PDT 24
Finished Jul 05 04:31:04 PM PDT 24
Peak memory 237468 kb
Host smart-bf41b0e6-0f72-431c-9897-c1aea109cd32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2840141451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2840141451
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2175711222
Short name T28
Test name
Test status
Simulation time 2305814384 ps
CPU time 35.24 seconds
Started Jul 05 04:44:17 PM PDT 24
Finished Jul 05 04:44:55 PM PDT 24
Peak memory 249080 kb
Host smart-abe97922-59a1-4d1e-b8a5-0a8ff9fe7421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21757
11222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2175711222
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1267724732
Short name T181
Test name
Test status
Simulation time 1340568844 ps
CPU time 70.55 seconds
Started Jul 05 04:30:20 PM PDT 24
Finished Jul 05 04:31:33 PM PDT 24
Peak memory 237344 kb
Host smart-941d1291-7d49-453b-b49a-a5be70f6efbf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1267724732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1267724732
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2903076094
Short name T812
Test name
Test status
Simulation time 3268766755 ps
CPU time 158.38 seconds
Started Jul 05 04:30:30 PM PDT 24
Finished Jul 05 04:33:14 PM PDT 24
Peak memory 236592 kb
Host smart-530a5633-f33e-4117-b0ef-fe482fba08da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2903076094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2903076094
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2832269458
Short name T817
Test name
Test status
Simulation time 44839299 ps
CPU time 6.17 seconds
Started Jul 05 04:30:19 PM PDT 24
Finished Jul 05 04:30:27 PM PDT 24
Peak memory 248636 kb
Host smart-46eef78e-7d64-448d-9a3f-c0b2b8b63457
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2832269458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2832269458
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2413013433
Short name T341
Test name
Test status
Simulation time 92854681 ps
CPU time 8.43 seconds
Started Jul 05 04:30:14 PM PDT 24
Finished Jul 05 04:30:26 PM PDT 24
Peak memory 251876 kb
Host smart-dc87c12a-9546-4b79-8778-558b38774a10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413013433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2413013433
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3699002797
Short name T789
Test name
Test status
Simulation time 57466093 ps
CPU time 4.49 seconds
Started Jul 05 04:30:18 PM PDT 24
Finished Jul 05 04:30:25 PM PDT 24
Peak memory 240392 kb
Host smart-e67c859c-9566-4dbf-9e50-821c80499a64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3699002797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3699002797
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1185027806
Short name T752
Test name
Test status
Simulation time 15832402 ps
CPU time 1.48 seconds
Started Jul 05 04:30:15 PM PDT 24
Finished Jul 05 04:30:19 PM PDT 24
Peak memory 237520 kb
Host smart-9b4a4c6d-253b-49df-9006-2427506bef83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1185027806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1185027806
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3286323092
Short name T732
Test name
Test status
Simulation time 991984903 ps
CPU time 38.56 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:31:19 PM PDT 24
Peak memory 245592 kb
Host smart-48ab6d86-5f18-40e3-a1d2-4ddbfba70560
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3286323092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3286323092
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.687411798
Short name T132
Test name
Test status
Simulation time 25734255409 ps
CPU time 473.35 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:38:16 PM PDT 24
Peak memory 265440 kb
Host smart-a0a4b3e7-7e8b-43e6-99a5-a3ae5f97cf76
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687411798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.687411798
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2020248915
Short name T802
Test name
Test status
Simulation time 587264921 ps
CPU time 10.41 seconds
Started Jul 05 04:30:09 PM PDT 24
Finished Jul 05 04:30:23 PM PDT 24
Peak memory 247972 kb
Host smart-c728e7c2-965b-49aa-849f-d87bf50da445
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2020248915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2020248915
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.997000351
Short name T168
Test name
Test status
Simulation time 4145664877 ps
CPU time 274.86 seconds
Started Jul 05 04:30:45 PM PDT 24
Finished Jul 05 04:35:21 PM PDT 24
Peak memory 240456 kb
Host smart-259db586-19e5-4048-947e-bf5b65418412
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=997000351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.997000351
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.398502209
Short name T749
Test name
Test status
Simulation time 5717681723 ps
CPU time 353.74 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:36:34 PM PDT 24
Peak memory 237512 kb
Host smart-2732cb2e-1fc1-43f0-a16d-c67a49d718fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=398502209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.398502209
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4245190659
Short name T778
Test name
Test status
Simulation time 48094003 ps
CPU time 6.15 seconds
Started Jul 05 04:30:31 PM PDT 24
Finished Jul 05 04:30:43 PM PDT 24
Peak memory 248900 kb
Host smart-ba4f24a5-dc80-4e43-9590-3ac2e1a8c8a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4245190659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.4245190659
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.816582963
Short name T735
Test name
Test status
Simulation time 130702526 ps
CPU time 9.1 seconds
Started Jul 05 04:30:23 PM PDT 24
Finished Jul 05 04:30:37 PM PDT 24
Peak memory 237684 kb
Host smart-9e5449cb-9830-4797-917f-53c84bc89349
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816582963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.816582963
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.155459628
Short name T183
Test name
Test status
Simulation time 99690978 ps
CPU time 7.32 seconds
Started Jul 05 04:30:30 PM PDT 24
Finished Jul 05 04:30:43 PM PDT 24
Peak memory 240360 kb
Host smart-c53be402-998b-4c04-949a-ad54c826a751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=155459628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.155459628
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.80955999
Short name T796
Test name
Test status
Simulation time 6470673 ps
CPU time 1.36 seconds
Started Jul 05 04:30:31 PM PDT 24
Finished Jul 05 04:30:37 PM PDT 24
Peak memory 237416 kb
Host smart-ec605b3d-75fa-4358-988a-1ba0fb2f9b72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=80955999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.80955999
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1527294836
Short name T810
Test name
Test status
Simulation time 250872826 ps
CPU time 16.62 seconds
Started Jul 05 04:30:20 PM PDT 24
Finished Jul 05 04:30:46 PM PDT 24
Peak memory 245608 kb
Host smart-853e1b78-cb03-4879-8fb1-fb5b78c24fa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1527294836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1527294836
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2274149012
Short name T125
Test name
Test status
Simulation time 5243877567 ps
CPU time 148.37 seconds
Started Jul 05 04:30:11 PM PDT 24
Finished Jul 05 04:32:42 PM PDT 24
Peak memory 265392 kb
Host smart-c87ea3b6-ab13-4322-9a79-e9b836460150
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2274149012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2274149012
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.534533053
Short name T140
Test name
Test status
Simulation time 12923204473 ps
CPU time 978.59 seconds
Started Jul 05 04:30:10 PM PDT 24
Finished Jul 05 04:46:32 PM PDT 24
Peak memory 265244 kb
Host smart-04ef8aa2-1756-4f40-b547-351e4d1851e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534533053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.534533053
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1716044889
Short name T724
Test name
Test status
Simulation time 230591842 ps
CPU time 14.41 seconds
Started Jul 05 04:30:19 PM PDT 24
Finished Jul 05 04:30:35 PM PDT 24
Peak memory 256552 kb
Host smart-d36c65cb-3586-4bc7-8d7b-ed8f6ad174ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1716044889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1716044889
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2324815854
Short name T811
Test name
Test status
Simulation time 32840519 ps
CPU time 4.53 seconds
Started Jul 05 04:31:19 PM PDT 24
Finished Jul 05 04:31:24 PM PDT 24
Peak memory 241704 kb
Host smart-9cb8176c-ac61-43e4-a152-6c6963ae5703
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324815854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2324815854
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2808683903
Short name T756
Test name
Test status
Simulation time 51672399 ps
CPU time 4.24 seconds
Started Jul 05 04:30:48 PM PDT 24
Finished Jul 05 04:30:53 PM PDT 24
Peak memory 236468 kb
Host smart-31222b3f-d878-43a8-ab4f-228c5110ea12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2808683903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2808683903
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3199495044
Short name T797
Test name
Test status
Simulation time 18854402 ps
CPU time 1.35 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:30:26 PM PDT 24
Peak memory 236464 kb
Host smart-b142e9d7-ce97-4ed3-9dd7-841a7f3e4a8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3199495044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3199495044
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.844605193
Short name T785
Test name
Test status
Simulation time 614857952 ps
CPU time 37.6 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:31:18 PM PDT 24
Peak memory 244692 kb
Host smart-abf4bc73-2009-4b48-abe5-5665f7479b6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=844605193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.844605193
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3460409282
Short name T143
Test name
Test status
Simulation time 6574750169 ps
CPU time 108.21 seconds
Started Jul 05 04:30:25 PM PDT 24
Finished Jul 05 04:32:19 PM PDT 24
Peak memory 266312 kb
Host smart-df298017-68b0-4238-902b-76eada3ec4bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3460409282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3460409282
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.458807035
Short name T136
Test name
Test status
Simulation time 11507094891 ps
CPU time 510.65 seconds
Started Jul 05 04:30:29 PM PDT 24
Finished Jul 05 04:39:05 PM PDT 24
Peak memory 265352 kb
Host smart-d4c0106f-87af-4059-a52e-4874632d657a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458807035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.458807035
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3248531059
Short name T822
Test name
Test status
Simulation time 50380122 ps
CPU time 6.26 seconds
Started Jul 05 04:30:31 PM PDT 24
Finished Jul 05 04:30:42 PM PDT 24
Peak memory 248888 kb
Host smart-0bfb9e96-70c4-49b6-897e-76968d8cc998
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3248531059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3248531059
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3737763930
Short name T739
Test name
Test status
Simulation time 148948118 ps
CPU time 11.95 seconds
Started Jul 05 04:30:05 PM PDT 24
Finished Jul 05 04:30:22 PM PDT 24
Peak memory 243588 kb
Host smart-d802f578-1fe4-487c-a9c2-3fc0607ed9a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737763930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3737763930
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.4209491076
Short name T192
Test name
Test status
Simulation time 356482967 ps
CPU time 8.18 seconds
Started Jul 05 04:30:18 PM PDT 24
Finished Jul 05 04:30:28 PM PDT 24
Peak memory 240460 kb
Host smart-89165d93-43f0-45ba-876e-204ad79f5161
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4209491076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.4209491076
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1321753883
Short name T336
Test name
Test status
Simulation time 7797508 ps
CPU time 1.26 seconds
Started Jul 05 04:30:23 PM PDT 24
Finished Jul 05 04:30:30 PM PDT 24
Peak memory 235568 kb
Host smart-74f13d07-9436-4975-85f8-652ae3d2640b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1321753883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1321753883
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4048385587
Short name T799
Test name
Test status
Simulation time 1898971782 ps
CPU time 35.35 seconds
Started Jul 05 04:30:27 PM PDT 24
Finished Jul 05 04:31:08 PM PDT 24
Peak memory 245680 kb
Host smart-19bd413c-a36f-4db3-ba07-7e60f430800d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4048385587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4048385587
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1589578309
Short name T142
Test name
Test status
Simulation time 16771989097 ps
CPU time 163.88 seconds
Started Jul 05 04:30:04 PM PDT 24
Finished Jul 05 04:32:53 PM PDT 24
Peak memory 266532 kb
Host smart-7465baf6-31ca-4d6f-865b-e7453ca746b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1589578309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1589578309
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1502431422
Short name T127
Test name
Test status
Simulation time 9980471009 ps
CPU time 314.58 seconds
Started Jul 05 04:30:34 PM PDT 24
Finished Jul 05 04:35:53 PM PDT 24
Peak memory 268840 kb
Host smart-9818ff4a-7021-41d2-9293-935376111f7c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502431422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1502431422
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.4139147535
Short name T819
Test name
Test status
Simulation time 617010004 ps
CPU time 8.59 seconds
Started Jul 05 04:30:43 PM PDT 24
Finished Jul 05 04:30:53 PM PDT 24
Peak memory 248756 kb
Host smart-3d64fd3a-6c0b-43be-a086-bd056c5e809e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4139147535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.4139147535
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.815698098
Short name T764
Test name
Test status
Simulation time 65371341 ps
CPU time 5.5 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:30:43 PM PDT 24
Peak memory 239988 kb
Host smart-e91fd83d-b0e6-4b11-adf4-d938eeb5d140
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815698098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.815698098
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.132839858
Short name T747
Test name
Test status
Simulation time 6411400 ps
CPU time 1.35 seconds
Started Jul 05 04:30:47 PM PDT 24
Finished Jul 05 04:30:49 PM PDT 24
Peak memory 237428 kb
Host smart-fdbc715e-e0eb-4905-afa7-c8db873b8f0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=132839858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.132839858
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1172756788
Short name T167
Test name
Test status
Simulation time 90773544 ps
CPU time 11.52 seconds
Started Jul 05 04:30:40 PM PDT 24
Finished Jul 05 04:30:55 PM PDT 24
Peak memory 245628 kb
Host smart-44a62aa5-b6bf-4180-99dc-f2d3572996e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1172756788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1172756788
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4041230483
Short name T147
Test name
Test status
Simulation time 2699128245 ps
CPU time 225.52 seconds
Started Jul 05 04:30:17 PM PDT 24
Finished Jul 05 04:34:05 PM PDT 24
Peak memory 265248 kb
Host smart-c8e6a219-d572-4024-b5e2-1d84f65b17eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4041230483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.4041230483
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3251401204
Short name T712
Test name
Test status
Simulation time 95736315 ps
CPU time 12.02 seconds
Started Jul 05 04:30:31 PM PDT 24
Finished Jul 05 04:30:48 PM PDT 24
Peak memory 248632 kb
Host smart-8b03bd17-4507-4905-b748-57a424ccb3c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3251401204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3251401204
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1941242772
Short name T746
Test name
Test status
Simulation time 270228424 ps
CPU time 8.95 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:30:46 PM PDT 24
Peak memory 240464 kb
Host smart-37d02ce8-db9e-44a3-a74c-bb819c720ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941242772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1941242772
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1418834979
Short name T833
Test name
Test status
Simulation time 375332116 ps
CPU time 7.71 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 04:30:38 PM PDT 24
Peak memory 237444 kb
Host smart-c7ec6673-a6db-489f-a963-f5ff2f60c33a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1418834979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1418834979
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1577102368
Short name T768
Test name
Test status
Simulation time 713751644 ps
CPU time 46.91 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:31:24 PM PDT 24
Peak memory 248576 kb
Host smart-635e5906-2492-4d15-bd72-9db49ab00784
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1577102368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1577102368
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2357806785
Short name T783
Test name
Test status
Simulation time 942850201 ps
CPU time 14.94 seconds
Started Jul 05 04:30:28 PM PDT 24
Finished Jul 05 04:30:49 PM PDT 24
Peak memory 253740 kb
Host smart-00b32da7-cc4e-4bf6-a75c-1a793440c523
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2357806785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2357806785
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.825752348
Short name T723
Test name
Test status
Simulation time 29567074 ps
CPU time 4.1 seconds
Started Jul 05 04:30:26 PM PDT 24
Finished Jul 05 04:30:35 PM PDT 24
Peak memory 248664 kb
Host smart-2f8d84d7-8902-4c2b-b2f3-f3dcefa894e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825752348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.825752348
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1110614909
Short name T741
Test name
Test status
Simulation time 63334996 ps
CPU time 5 seconds
Started Jul 05 04:30:29 PM PDT 24
Finished Jul 05 04:30:39 PM PDT 24
Peak memory 237396 kb
Host smart-c7f1dd81-932a-4f8b-a1c2-54c054973ebe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1110614909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1110614909
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2559505388
Short name T750
Test name
Test status
Simulation time 12787720 ps
CPU time 1.3 seconds
Started Jul 05 04:30:35 PM PDT 24
Finished Jul 05 04:30:41 PM PDT 24
Peak memory 237456 kb
Host smart-02a5edfe-2186-4c97-9293-969553dee049
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2559505388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2559505388
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2622095073
Short name T762
Test name
Test status
Simulation time 512153427 ps
CPU time 38.46 seconds
Started Jul 05 04:30:33 PM PDT 24
Finished Jul 05 04:31:16 PM PDT 24
Peak memory 248532 kb
Host smart-b3a82a4d-1364-4f0e-a0c5-66f35700d800
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2622095073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2622095073
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3391422992
Short name T769
Test name
Test status
Simulation time 66268758 ps
CPU time 7.46 seconds
Started Jul 05 04:30:35 PM PDT 24
Finished Jul 05 04:30:47 PM PDT 24
Peak memory 248512 kb
Host smart-878f1712-abbe-4846-9926-d03bbe676595
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3391422992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3391422992
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.4021144147
Short name T160
Test name
Test status
Simulation time 105917020 ps
CPU time 3.56 seconds
Started Jul 05 04:30:13 PM PDT 24
Finished Jul 05 04:30:19 PM PDT 24
Peak memory 237488 kb
Host smart-0f7511a8-ec57-48ea-b2ba-287fc747ac9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4021144147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.4021144147
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3319563191
Short name T807
Test name
Test status
Simulation time 1231205706 ps
CPU time 10.11 seconds
Started Jul 05 04:30:33 PM PDT 24
Finished Jul 05 04:30:48 PM PDT 24
Peak memory 240272 kb
Host smart-7385693d-07b4-4fed-b442-3654b1399574
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319563191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3319563191
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.4133926986
Short name T751
Test name
Test status
Simulation time 498607354 ps
CPU time 8.21 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:30:49 PM PDT 24
Peak memory 237444 kb
Host smart-cad3f6e4-946e-469a-97ad-8e9a0432a15c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4133926986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.4133926986
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2358071750
Short name T759
Test name
Test status
Simulation time 23740790 ps
CPU time 1.22 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 04:30:30 PM PDT 24
Peak memory 236512 kb
Host smart-64a89ae8-3746-43e2-8d76-d92b707846be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2358071750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2358071750
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1071800354
Short name T184
Test name
Test status
Simulation time 683764940 ps
CPU time 22.78 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 04:30:53 PM PDT 24
Peak memory 245628 kb
Host smart-a2833b8f-a551-4975-868f-7bb93a04d69f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1071800354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1071800354
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.501481898
Short name T135
Test name
Test status
Simulation time 4791080280 ps
CPU time 289.89 seconds
Started Jul 05 04:30:26 PM PDT 24
Finished Jul 05 04:35:21 PM PDT 24
Peak memory 269424 kb
Host smart-7136e4fa-5f1c-4bd8-a349-2b63d3c4dc72
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501481898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.501481898
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.949410930
Short name T718
Test name
Test status
Simulation time 272866719 ps
CPU time 19.07 seconds
Started Jul 05 04:30:33 PM PDT 24
Finished Jul 05 04:30:58 PM PDT 24
Peak memory 255348 kb
Host smart-5b28175d-5fb6-49d9-929c-f768d46c119f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=949410930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.949410930
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2355229544
Short name T342
Test name
Test status
Simulation time 54829806 ps
CPU time 4.05 seconds
Started Jul 05 04:30:26 PM PDT 24
Finished Jul 05 04:30:35 PM PDT 24
Peak memory 240712 kb
Host smart-1d2a363b-5483-465d-97d4-fa5940c00a6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355229544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2355229544
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2021443168
Short name T826
Test name
Test status
Simulation time 184711212 ps
CPU time 4.92 seconds
Started Jul 05 04:30:16 PM PDT 24
Finished Jul 05 04:30:24 PM PDT 24
Peak memory 237444 kb
Host smart-96281632-2de6-454a-a41d-da6cc45d8a2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2021443168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2021443168
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3219901254
Short name T780
Test name
Test status
Simulation time 12505109 ps
CPU time 1.62 seconds
Started Jul 05 04:30:16 PM PDT 24
Finished Jul 05 04:30:21 PM PDT 24
Peak memory 236496 kb
Host smart-5997497d-4769-4310-b845-f770cdeb7d41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3219901254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3219901254
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3917317914
Short name T733
Test name
Test status
Simulation time 613210578 ps
CPU time 22.36 seconds
Started Jul 05 04:30:45 PM PDT 24
Finished Jul 05 04:31:08 PM PDT 24
Peak memory 245620 kb
Host smart-26e11397-77b7-4775-ae83-2942f7ce0d85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3917317914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3917317914
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.92760110
Short name T133
Test name
Test status
Simulation time 3178422015 ps
CPU time 343.07 seconds
Started Jul 05 04:30:35 PM PDT 24
Finished Jul 05 04:36:22 PM PDT 24
Peak memory 265480 kb
Host smart-7b59f74c-a673-4936-a426-74570c94cda0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92760110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.92760110
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3632944995
Short name T758
Test name
Test status
Simulation time 295584073 ps
CPU time 9.95 seconds
Started Jul 05 04:30:34 PM PDT 24
Finished Jul 05 04:30:49 PM PDT 24
Peak memory 248636 kb
Host smart-e31c366a-6666-401d-a44c-604c2be61952
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3632944995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3632944995
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2360248961
Short name T763
Test name
Test status
Simulation time 2086908756 ps
CPU time 33.33 seconds
Started Jul 05 04:30:38 PM PDT 24
Finished Jul 05 04:31:15 PM PDT 24
Peak memory 237556 kb
Host smart-7f67f411-a874-4913-98ef-5e39ee69c0d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2360248961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2360248961
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1901988559
Short name T720
Test name
Test status
Simulation time 1539259223 ps
CPU time 12.5 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:30:49 PM PDT 24
Peak memory 251828 kb
Host smart-607346ab-ff61-4d11-b678-36d39c6bb75d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901988559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1901988559
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.692177515
Short name T761
Test name
Test status
Simulation time 327492715 ps
CPU time 5.56 seconds
Started Jul 05 04:30:34 PM PDT 24
Finished Jul 05 04:30:44 PM PDT 24
Peak memory 237404 kb
Host smart-7c42456e-ceed-4689-8c54-9682e342ff07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=692177515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.692177515
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1532651720
Short name T825
Test name
Test status
Simulation time 11754726 ps
CPU time 1.57 seconds
Started Jul 05 04:30:31 PM PDT 24
Finished Jul 05 04:30:37 PM PDT 24
Peak memory 236452 kb
Host smart-e7684ad9-a3b1-487a-909d-ea5c93160a53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1532651720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1532651720
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2055566410
Short name T809
Test name
Test status
Simulation time 143032551 ps
CPU time 12.36 seconds
Started Jul 05 04:30:37 PM PDT 24
Finished Jul 05 04:30:54 PM PDT 24
Peak memory 240264 kb
Host smart-be7e1c3a-81eb-49d7-a981-f36a5d2e67aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2055566410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2055566410
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1064852992
Short name T123
Test name
Test status
Simulation time 1431291233 ps
CPU time 81.49 seconds
Started Jul 05 04:30:41 PM PDT 24
Finished Jul 05 04:32:05 PM PDT 24
Peak memory 265320 kb
Host smart-4cf8c62a-aa9d-4ae0-8dd8-a49526f29544
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1064852992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1064852992
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.514263217
Short name T806
Test name
Test status
Simulation time 491024945 ps
CPU time 8.48 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 04:30:38 PM PDT 24
Peak memory 249668 kb
Host smart-f1201fc3-9f52-4cd9-8a77-639dd8dd8cd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=514263217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.514263217
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2094769121
Short name T737
Test name
Test status
Simulation time 105298065 ps
CPU time 7.31 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:30:31 PM PDT 24
Peak memory 240464 kb
Host smart-8ace5940-2d07-49ff-9605-dbff1d46159b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094769121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2094769121
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1182449006
Short name T801
Test name
Test status
Simulation time 33729061 ps
CPU time 5.23 seconds
Started Jul 05 04:30:39 PM PDT 24
Finished Jul 05 04:30:47 PM PDT 24
Peak memory 237392 kb
Host smart-6744e709-226a-4f6e-a164-ae0ba61d4b17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1182449006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1182449006
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2557662770
Short name T767
Test name
Test status
Simulation time 13872417 ps
CPU time 1.43 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:30:39 PM PDT 24
Peak memory 236732 kb
Host smart-e6f08b7a-0b9e-4c50-b28f-60d47548977f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2557662770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2557662770
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3249926724
Short name T824
Test name
Test status
Simulation time 1371901178 ps
CPU time 21.42 seconds
Started Jul 05 04:30:31 PM PDT 24
Finished Jul 05 04:30:57 PM PDT 24
Peak memory 245544 kb
Host smart-531765af-5b7c-4848-b1fd-39c461000f0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3249926724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3249926724
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4285186409
Short name T117
Test name
Test status
Simulation time 2334151908 ps
CPU time 297.8 seconds
Started Jul 05 04:30:37 PM PDT 24
Finished Jul 05 04:35:39 PM PDT 24
Peak memory 265232 kb
Host smart-a9c393e4-2706-46ac-b719-6a0a4530741b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285186409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4285186409
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2621830653
Short name T827
Test name
Test status
Simulation time 335305013 ps
CPU time 13.02 seconds
Started Jul 05 04:30:31 PM PDT 24
Finished Jul 05 04:30:49 PM PDT 24
Peak memory 248032 kb
Host smart-e40a34f2-3092-4110-9abe-0303c663b727
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2621830653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2621830653
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3272919292
Short name T803
Test name
Test status
Simulation time 2439080158 ps
CPU time 11.67 seconds
Started Jul 05 04:30:42 PM PDT 24
Finished Jul 05 04:30:56 PM PDT 24
Peak memory 256404 kb
Host smart-64fc830f-1b3e-4845-937f-d430c52755e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272919292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3272919292
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3715257524
Short name T765
Test name
Test status
Simulation time 444739689 ps
CPU time 4.13 seconds
Started Jul 05 04:30:42 PM PDT 24
Finished Jul 05 04:30:48 PM PDT 24
Peak memory 237444 kb
Host smart-b653ceb0-ecf7-4636-a54a-55cfdbbd152d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3715257524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3715257524
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1149296652
Short name T804
Test name
Test status
Simulation time 10663742 ps
CPU time 1.26 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 04:30:31 PM PDT 24
Peak memory 237456 kb
Host smart-e8322014-3378-4cf8-9864-4f9a8dec095d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1149296652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1149296652
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2645560780
Short name T821
Test name
Test status
Simulation time 118966302 ps
CPU time 11.86 seconds
Started Jul 05 04:30:39 PM PDT 24
Finished Jul 05 04:30:54 PM PDT 24
Peak memory 240356 kb
Host smart-f003aef7-c21a-4aa3-a203-86f5c5483a45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2645560780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2645560780
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2912881131
Short name T134
Test name
Test status
Simulation time 51193078227 ps
CPU time 496.55 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:38:58 PM PDT 24
Peak memory 265396 kb
Host smart-e1ae3fcc-21a3-46dc-b56a-975254c1fe74
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912881131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2912881131
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.428824025
Short name T823
Test name
Test status
Simulation time 693743352 ps
CPU time 12.91 seconds
Started Jul 05 04:30:34 PM PDT 24
Finished Jul 05 04:30:52 PM PDT 24
Peak memory 252580 kb
Host smart-e9e7cf4f-061b-4e7b-83b8-eab2b41a5543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=428824025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.428824025
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.101476096
Short name T814
Test name
Test status
Simulation time 3458487265 ps
CPU time 220.28 seconds
Started Jul 05 04:30:14 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 241436 kb
Host smart-7092d701-9d46-4a85-bbd1-1de4b865c054
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=101476096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.101476096
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3528709857
Short name T782
Test name
Test status
Simulation time 8925375657 ps
CPU time 392.54 seconds
Started Jul 05 04:30:28 PM PDT 24
Finished Jul 05 04:37:06 PM PDT 24
Peak memory 236500 kb
Host smart-b716ffaf-3bf2-4579-a658-3c9491b78e8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3528709857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3528709857
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2749782384
Short name T730
Test name
Test status
Simulation time 71384814 ps
CPU time 5.62 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:30:30 PM PDT 24
Peak memory 240328 kb
Host smart-2ff83132-2080-413b-a9c6-f1bcddb2c871
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2749782384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2749782384
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3504371245
Short name T736
Test name
Test status
Simulation time 469945456 ps
CPU time 8.89 seconds
Started Jul 05 04:30:28 PM PDT 24
Finished Jul 05 04:30:42 PM PDT 24
Peak memory 256936 kb
Host smart-cbfcba1f-41da-4a34-b718-fdd29b12e2a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504371245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3504371245
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2947051293
Short name T777
Test name
Test status
Simulation time 21879532 ps
CPU time 3.35 seconds
Started Jul 05 04:30:10 PM PDT 24
Finished Jul 05 04:30:17 PM PDT 24
Peak memory 240368 kb
Host smart-2ed9fa0e-ee57-4763-907e-abec66becbab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2947051293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2947051293
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.262260698
Short name T771
Test name
Test status
Simulation time 1226257213 ps
CPU time 38.3 seconds
Started Jul 05 04:30:23 PM PDT 24
Finished Jul 05 04:31:12 PM PDT 24
Peak memory 244648 kb
Host smart-fa7dd3bb-8171-4fc0-b9f9-dcfbe45172a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=262260698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.262260698
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2136633392
Short name T118
Test name
Test status
Simulation time 12804017227 ps
CPU time 158.57 seconds
Started Jul 05 04:30:44 PM PDT 24
Finished Jul 05 04:33:23 PM PDT 24
Peak memory 265300 kb
Host smart-55f873c4-ffbd-43f6-a2bd-32330cd837ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2136633392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2136633392
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3286358399
Short name T828
Test name
Test status
Simulation time 77457440 ps
CPU time 10.31 seconds
Started Jul 05 04:30:12 PM PDT 24
Finished Jul 05 04:30:25 PM PDT 24
Peak memory 248532 kb
Host smart-2b67887d-60cf-4a08-bf9a-02485b4a97ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3286358399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3286358399
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.20878093
Short name T805
Test name
Test status
Simulation time 13723052 ps
CPU time 1.47 seconds
Started Jul 05 04:30:39 PM PDT 24
Finished Jul 05 04:30:44 PM PDT 24
Peak memory 236500 kb
Host smart-3d1c3a09-5922-4b40-880b-c8b52e08097d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=20878093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.20878093
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3138918745
Short name T334
Test name
Test status
Simulation time 25612240 ps
CPU time 1.37 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 04:30:32 PM PDT 24
Peak memory 236512 kb
Host smart-b0088452-e101-4b51-a4ad-3682c94decc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3138918745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3138918745
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1896519005
Short name T722
Test name
Test status
Simulation time 10958403 ps
CPU time 1.27 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:30:42 PM PDT 24
Peak memory 236520 kb
Host smart-febfddc5-c0f4-4f62-98ed-129db2d8610f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1896519005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1896519005
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1841488672
Short name T754
Test name
Test status
Simulation time 32128225 ps
CPU time 1.32 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:30:42 PM PDT 24
Peak memory 237220 kb
Host smart-5aa6c47f-8589-41e5-91cb-867daeffed13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1841488672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1841488672
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1461799231
Short name T808
Test name
Test status
Simulation time 19918157 ps
CPU time 1.39 seconds
Started Jul 05 04:30:33 PM PDT 24
Finished Jul 05 04:30:39 PM PDT 24
Peak memory 236480 kb
Host smart-fc58e140-39e0-42ad-80bc-1f1076a8e42e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1461799231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1461799231
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.92363017
Short name T830
Test name
Test status
Simulation time 10240154 ps
CPU time 1.32 seconds
Started Jul 05 04:30:39 PM PDT 24
Finished Jul 05 04:30:44 PM PDT 24
Peak memory 237408 kb
Host smart-5cc83c68-3148-4aff-96de-5c2e5243c9ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=92363017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.92363017
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2754179233
Short name T335
Test name
Test status
Simulation time 7638192 ps
CPU time 1.42 seconds
Started Jul 05 04:30:57 PM PDT 24
Finished Jul 05 04:31:00 PM PDT 24
Peak memory 237460 kb
Host smart-8d95182b-5460-4461-8ece-4da27d7a4f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2754179233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2754179233
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2007731654
Short name T776
Test name
Test status
Simulation time 17550661 ps
CPU time 1.35 seconds
Started Jul 05 04:30:39 PM PDT 24
Finished Jul 05 04:30:44 PM PDT 24
Peak memory 235484 kb
Host smart-c0c2ba06-aab6-40c4-a240-fcaabe1561cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2007731654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2007731654
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.979737824
Short name T717
Test name
Test status
Simulation time 29789226 ps
CPU time 1.41 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:30:39 PM PDT 24
Peak memory 236504 kb
Host smart-09426472-ccbf-47d2-bf1b-00734b96cd6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=979737824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.979737824
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.928017397
Short name T725
Test name
Test status
Simulation time 24636297 ps
CPU time 1.29 seconds
Started Jul 05 04:30:34 PM PDT 24
Finished Jul 05 04:30:40 PM PDT 24
Peak memory 237284 kb
Host smart-5b73aa54-021a-40c7-9076-29ee57e96db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=928017397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.928017397
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1441964555
Short name T185
Test name
Test status
Simulation time 9729713508 ps
CPU time 144.89 seconds
Started Jul 05 04:30:15 PM PDT 24
Finished Jul 05 04:32:43 PM PDT 24
Peak memory 240276 kb
Host smart-c79ee962-45d6-453b-98f0-acb007abe5f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1441964555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1441964555
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3677790498
Short name T772
Test name
Test status
Simulation time 15260074488 ps
CPU time 249.47 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:34:33 PM PDT 24
Peak memory 240452 kb
Host smart-e1ea2cc3-7dc6-4129-8989-3fd45d9a0ada
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3677790498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3677790498
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1874850094
Short name T734
Test name
Test status
Simulation time 101860252 ps
CPU time 4.73 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 04:30:34 PM PDT 24
Peak memory 240392 kb
Host smart-719c4728-d9dc-4088-b0fe-e55a638f52ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1874850094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1874850094
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.190677630
Short name T800
Test name
Test status
Simulation time 448536559 ps
CPU time 6.63 seconds
Started Jul 05 04:30:15 PM PDT 24
Finished Jul 05 04:30:25 PM PDT 24
Peak memory 240424 kb
Host smart-9ecf644f-a345-453b-9f83-837eb45af298
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190677630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.190677630
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1668621380
Short name T798
Test name
Test status
Simulation time 1697022416 ps
CPU time 6.66 seconds
Started Jul 05 04:30:11 PM PDT 24
Finished Jul 05 04:30:20 PM PDT 24
Peak memory 240384 kb
Host smart-e0358f3e-ddea-4a96-a89a-19cd51a04bde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1668621380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1668621380
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3047318164
Short name T745
Test name
Test status
Simulation time 16150638 ps
CPU time 1.3 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:30:28 PM PDT 24
Peak memory 236468 kb
Host smart-e9638503-c87e-49bc-86c3-0dc585e33bd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3047318164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3047318164
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.398653218
Short name T791
Test name
Test status
Simulation time 172351926 ps
CPU time 22.99 seconds
Started Jul 05 04:30:24 PM PDT 24
Finished Jul 05 04:30:53 PM PDT 24
Peak memory 245632 kb
Host smart-14d98f68-a669-4b4f-a19e-1fdbf6ca95e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=398653218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.398653218
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3657646405
Short name T116
Test name
Test status
Simulation time 3613259577 ps
CPU time 118.17 seconds
Started Jul 05 04:30:25 PM PDT 24
Finished Jul 05 04:32:29 PM PDT 24
Peak memory 257024 kb
Host smart-bb295f36-0bf7-4875-a8dd-f383c31eb767
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3657646405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3657646405
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1845475422
Short name T137
Test name
Test status
Simulation time 4832642872 ps
CPU time 615.59 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:40:40 PM PDT 24
Peak memory 265268 kb
Host smart-212fa484-3c4f-4041-8444-be9174d68a18
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845475422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1845475422
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3441191573
Short name T831
Test name
Test status
Simulation time 71991054 ps
CPU time 9.05 seconds
Started Jul 05 04:30:18 PM PDT 24
Finished Jul 05 04:30:29 PM PDT 24
Peak memory 246800 kb
Host smart-e3c57731-017b-457a-892e-420fc5a3320d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3441191573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3441191573
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2471033387
Short name T744
Test name
Test status
Simulation time 17802951 ps
CPU time 1.33 seconds
Started Jul 05 04:30:45 PM PDT 24
Finished Jul 05 04:30:47 PM PDT 24
Peak memory 235540 kb
Host smart-7175ae24-3121-45c1-bfa0-8d3e741ee94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2471033387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2471033387
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3097354385
Short name T719
Test name
Test status
Simulation time 12813981 ps
CPU time 1.65 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:30:39 PM PDT 24
Peak memory 237372 kb
Host smart-b478030c-2c9e-463b-8955-0cf27c8aa173
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3097354385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3097354385
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3012331088
Short name T222
Test name
Test status
Simulation time 8544726 ps
CPU time 1.63 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:30:43 PM PDT 24
Peak memory 237460 kb
Host smart-bf68d6ea-d223-46fa-af22-5a7e34e671a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3012331088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3012331088
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3714071188
Short name T742
Test name
Test status
Simulation time 8053760 ps
CPU time 1.33 seconds
Started Jul 05 04:30:27 PM PDT 24
Finished Jul 05 04:30:34 PM PDT 24
Peak memory 237452 kb
Host smart-e2fda59d-83fb-449c-972a-2434427f7541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3714071188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3714071188
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3363641106
Short name T715
Test name
Test status
Simulation time 8447762 ps
CPU time 1.36 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:30:24 PM PDT 24
Peak memory 236628 kb
Host smart-3de55cf0-1f3c-43b2-bd83-cce531fc86a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3363641106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3363641106
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1378546538
Short name T813
Test name
Test status
Simulation time 8743808 ps
CPU time 1.44 seconds
Started Jul 05 04:30:29 PM PDT 24
Finished Jul 05 04:30:36 PM PDT 24
Peak memory 237460 kb
Host smart-4794dcdd-b959-4952-b788-937918f8c709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1378546538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1378546538
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2529755637
Short name T726
Test name
Test status
Simulation time 7912985 ps
CPU time 1.33 seconds
Started Jul 05 04:30:45 PM PDT 24
Finished Jul 05 04:30:47 PM PDT 24
Peak memory 235452 kb
Host smart-f414234b-d444-4eb1-b858-6dcdabd7c3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2529755637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2529755637
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3760141191
Short name T153
Test name
Test status
Simulation time 22357994 ps
CPU time 1.19 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:30:39 PM PDT 24
Peak memory 237412 kb
Host smart-af2d953f-9e1e-4851-a449-c36ea967f576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3760141191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3760141191
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1315819780
Short name T779
Test name
Test status
Simulation time 10635693 ps
CPU time 1.36 seconds
Started Jul 05 04:30:36 PM PDT 24
Finished Jul 05 04:30:42 PM PDT 24
Peak memory 235652 kb
Host smart-22ddb7f3-3729-4902-8933-29bc939bf687
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1315819780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1315819780
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3912853483
Short name T340
Test name
Test status
Simulation time 9663855 ps
CPU time 1.31 seconds
Started Jul 05 04:30:29 PM PDT 24
Finished Jul 05 04:30:40 PM PDT 24
Peak memory 235464 kb
Host smart-7c01f9bd-7a1a-480d-bdc0-389bf855bf14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3912853483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3912853483
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2487878332
Short name T815
Test name
Test status
Simulation time 1664032978 ps
CPU time 107.33 seconds
Started Jul 05 04:30:23 PM PDT 24
Finished Jul 05 04:32:16 PM PDT 24
Peak memory 237436 kb
Host smart-c6dd61ed-3425-4d06-8320-20389986572e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2487878332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2487878332
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1337767326
Short name T832
Test name
Test status
Simulation time 6802295540 ps
CPU time 191.97 seconds
Started Jul 05 04:30:11 PM PDT 24
Finished Jul 05 04:33:26 PM PDT 24
Peak memory 237596 kb
Host smart-16777d6d-ecc8-462f-8d83-dc7cc4020d76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1337767326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1337767326
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.4167906271
Short name T816
Test name
Test status
Simulation time 23314156 ps
CPU time 3.67 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:30:30 PM PDT 24
Peak memory 240352 kb
Host smart-01f0b87a-1aeb-449d-8374-c9d61dd995cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4167906271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.4167906271
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3993740974
Short name T728
Test name
Test status
Simulation time 33489039 ps
CPU time 4.96 seconds
Started Jul 05 04:30:25 PM PDT 24
Finished Jul 05 04:30:35 PM PDT 24
Peak memory 242092 kb
Host smart-99eb954e-e607-4381-8748-61c72d38be77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993740974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3993740974
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1065396791
Short name T182
Test name
Test status
Simulation time 197905426 ps
CPU time 4.99 seconds
Started Jul 05 04:30:12 PM PDT 24
Finished Jul 05 04:30:20 PM PDT 24
Peak memory 240376 kb
Host smart-e7014d11-20ae-4960-8d5c-5ad55f8c2315
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1065396791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1065396791
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3217927879
Short name T339
Test name
Test status
Simulation time 10579053 ps
CPU time 1.28 seconds
Started Jul 05 04:30:20 PM PDT 24
Finished Jul 05 04:30:24 PM PDT 24
Peak memory 236576 kb
Host smart-59dfad33-e69a-44f2-a2dd-b52e963e1c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3217927879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3217927879
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2468880054
Short name T169
Test name
Test status
Simulation time 2804590715 ps
CPU time 47.09 seconds
Started Jul 05 04:30:13 PM PDT 24
Finished Jul 05 04:31:03 PM PDT 24
Peak memory 245668 kb
Host smart-3b8cc9a3-67a1-4e86-b912-0a49e7d0354e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2468880054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2468880054
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1837434222
Short name T113
Test name
Test status
Simulation time 17734788384 ps
CPU time 302.25 seconds
Started Jul 05 04:30:18 PM PDT 24
Finished Jul 05 04:35:22 PM PDT 24
Peak memory 272848 kb
Host smart-9b3a7c8f-2a87-4bc8-88f9-0571ccf010cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1837434222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1837434222
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2421438383
Short name T126
Test name
Test status
Simulation time 8550097091 ps
CPU time 591.53 seconds
Started Jul 05 04:30:05 PM PDT 24
Finished Jul 05 04:40:05 PM PDT 24
Peak memory 270656 kb
Host smart-f2dcd0b5-4d7b-4ae8-8a06-d666fc083e78
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421438383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2421438383
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.563884596
Short name T713
Test name
Test status
Simulation time 363135182 ps
CPU time 11.09 seconds
Started Jul 05 04:30:27 PM PDT 24
Finished Jul 05 04:30:43 PM PDT 24
Peak memory 253444 kb
Host smart-2b8c15ea-3743-473e-9676-40d67baed3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=563884596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.563884596
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3578923328
Short name T820
Test name
Test status
Simulation time 23503057 ps
CPU time 1.33 seconds
Started Jul 05 04:30:29 PM PDT 24
Finished Jul 05 04:30:36 PM PDT 24
Peak memory 236492 kb
Host smart-dedb827b-f357-43cb-b830-48250a1d1ecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3578923328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3578923328
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.767556785
Short name T760
Test name
Test status
Simulation time 18030150 ps
CPU time 1.33 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:30:39 PM PDT 24
Peak memory 237524 kb
Host smart-d9531343-f107-4d09-981d-235a7c84113b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=767556785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.767556785
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2963104401
Short name T770
Test name
Test status
Simulation time 26749432 ps
CPU time 1.24 seconds
Started Jul 05 04:30:26 PM PDT 24
Finished Jul 05 04:30:33 PM PDT 24
Peak memory 237456 kb
Host smart-65a2907c-8141-4d30-b1c5-f2945c66590b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2963104401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2963104401
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2484202705
Short name T795
Test name
Test status
Simulation time 15063106 ps
CPU time 1.25 seconds
Started Jul 05 04:30:40 PM PDT 24
Finished Jul 05 04:30:45 PM PDT 24
Peak memory 237452 kb
Host smart-7d8ae693-ef0b-4789-90a3-179d51fccd8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2484202705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2484202705
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2278648119
Short name T721
Test name
Test status
Simulation time 8707552 ps
CPU time 1.5 seconds
Started Jul 05 04:30:39 PM PDT 24
Finished Jul 05 04:30:44 PM PDT 24
Peak memory 237408 kb
Host smart-07d8e81d-c9a2-4a84-b26e-c443eafeae92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2278648119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2278648119
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3430151233
Short name T727
Test name
Test status
Simulation time 10282289 ps
CPU time 1.63 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:30:29 PM PDT 24
Peak memory 236464 kb
Host smart-e92d7b37-7490-4aaf-9eb7-0c505b968901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3430151233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3430151233
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2808138806
Short name T338
Test name
Test status
Simulation time 17881725 ps
CPU time 1.35 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:30:39 PM PDT 24
Peak memory 237380 kb
Host smart-9e3e937e-41ca-4984-b0cf-37bbe2a0d1f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2808138806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2808138806
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.921682315
Short name T774
Test name
Test status
Simulation time 13580531 ps
CPU time 1.33 seconds
Started Jul 05 04:30:48 PM PDT 24
Finished Jul 05 04:30:50 PM PDT 24
Peak memory 237456 kb
Host smart-fc1663d1-2d75-4b66-bf04-2b522be41cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=921682315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.921682315
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2750176882
Short name T775
Test name
Test status
Simulation time 9643065 ps
CPU time 1.27 seconds
Started Jul 05 04:30:45 PM PDT 24
Finished Jul 05 04:30:47 PM PDT 24
Peak memory 235556 kb
Host smart-48c0d40e-e505-47a0-b4ef-14686b18c547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2750176882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2750176882
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1945880306
Short name T337
Test name
Test status
Simulation time 62390552 ps
CPU time 1.42 seconds
Started Jul 05 04:30:35 PM PDT 24
Finished Jul 05 04:30:41 PM PDT 24
Peak memory 236508 kb
Host smart-c6afc0c5-2c1d-4d30-9bfb-c1a045940bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1945880306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1945880306
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2943132200
Short name T781
Test name
Test status
Simulation time 68644450 ps
CPU time 5.29 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:30:31 PM PDT 24
Peak memory 256712 kb
Host smart-c08f9795-e98b-4b6c-aaae-1527f1fa3a48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943132200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2943132200
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1973405555
Short name T793
Test name
Test status
Simulation time 1196678297 ps
CPU time 5.37 seconds
Started Jul 05 04:30:18 PM PDT 24
Finished Jul 05 04:30:25 PM PDT 24
Peak memory 240696 kb
Host smart-63bb3ad0-f613-4d38-84fd-5e6106f8742e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1973405555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1973405555
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1480024513
Short name T743
Test name
Test status
Simulation time 10736990 ps
CPU time 1.33 seconds
Started Jul 05 04:30:14 PM PDT 24
Finished Jul 05 04:30:18 PM PDT 24
Peak memory 237452 kb
Host smart-68ad705e-017d-4394-ab5b-426043e458be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1480024513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1480024513
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1813992274
Short name T818
Test name
Test status
Simulation time 1316754226 ps
CPU time 21.11 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:30:59 PM PDT 24
Peak memory 245600 kb
Host smart-55dcc05f-a3c0-47db-bc71-cf905f17279d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1813992274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1813992274
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.4012738925
Short name T787
Test name
Test status
Simulation time 336708977 ps
CPU time 20.6 seconds
Started Jul 05 04:30:15 PM PDT 24
Finished Jul 05 04:30:39 PM PDT 24
Peak memory 253348 kb
Host smart-3b81fc8c-3b11-4307-9a83-8fbcf76e0195
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4012738925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.4012738925
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1203490586
Short name T829
Test name
Test status
Simulation time 76635819 ps
CPU time 5.47 seconds
Started Jul 05 04:30:26 PM PDT 24
Finished Jul 05 04:30:37 PM PDT 24
Peak memory 240396 kb
Host smart-01683831-2601-4d03-ba49-b369820e2f6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203490586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1203490586
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3584656405
Short name T766
Test name
Test status
Simulation time 33180843 ps
CPU time 5.09 seconds
Started Jul 05 04:30:47 PM PDT 24
Finished Jul 05 04:30:53 PM PDT 24
Peak memory 236416 kb
Host smart-b9e8e96f-24dc-4b3e-a8d2-48467318f7d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3584656405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3584656405
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1372951579
Short name T755
Test name
Test status
Simulation time 15821883 ps
CPU time 1.29 seconds
Started Jul 05 04:30:30 PM PDT 24
Finished Jul 05 04:30:36 PM PDT 24
Peak memory 237768 kb
Host smart-b99c893e-cd03-46eb-89c5-cd983cf2b62f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1372951579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1372951579
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3651093651
Short name T792
Test name
Test status
Simulation time 1172441338 ps
CPU time 20.36 seconds
Started Jul 05 04:30:08 PM PDT 24
Finished Jul 05 04:30:32 PM PDT 24
Peak memory 244688 kb
Host smart-33e3bac1-47bb-4cbb-a9c7-06ac8f960e12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3651093651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3651093651
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1173461511
Short name T130
Test name
Test status
Simulation time 1726614511 ps
CPU time 96.16 seconds
Started Jul 05 04:30:19 PM PDT 24
Finished Jul 05 04:31:57 PM PDT 24
Peak memory 267576 kb
Host smart-2c43e711-fb79-4d12-a2fa-ec07add0363f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1173461511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1173461511
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3997000479
Short name T124
Test name
Test status
Simulation time 11544968767 ps
CPU time 315.44 seconds
Started Jul 05 04:30:13 PM PDT 24
Finished Jul 05 04:35:32 PM PDT 24
Peak memory 270408 kb
Host smart-c223f8e7-5499-45c0-8713-3998b336d7ab
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997000479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3997000479
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.647185275
Short name T716
Test name
Test status
Simulation time 121882141 ps
CPU time 9.41 seconds
Started Jul 05 04:30:33 PM PDT 24
Finished Jul 05 04:30:47 PM PDT 24
Peak memory 248616 kb
Host smart-96aef51d-35b1-46dd-b155-788537181510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=647185275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.647185275
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2371614755
Short name T191
Test name
Test status
Simulation time 80025222 ps
CPU time 6.76 seconds
Started Jul 05 04:30:13 PM PDT 24
Finished Jul 05 04:30:23 PM PDT 24
Peak memory 240904 kb
Host smart-c1eb2678-d335-4c12-a995-bb279e4d5eb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371614755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2371614755
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3871756850
Short name T343
Test name
Test status
Simulation time 175092446 ps
CPU time 7.64 seconds
Started Jul 05 04:30:41 PM PDT 24
Finished Jul 05 04:30:51 PM PDT 24
Peak memory 237528 kb
Host smart-47e6234f-1f47-479e-ac3d-114c191747de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3871756850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3871756850
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3294670232
Short name T731
Test name
Test status
Simulation time 16272888 ps
CPU time 1.46 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:30:24 PM PDT 24
Peak memory 237448 kb
Host smart-43a62286-e922-4fd4-9117-765cb2f975bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3294670232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3294670232
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.984644893
Short name T788
Test name
Test status
Simulation time 177742148 ps
CPU time 20.31 seconds
Started Jul 05 04:30:43 PM PDT 24
Finished Jul 05 04:31:05 PM PDT 24
Peak memory 244660 kb
Host smart-94467e7d-adc5-4ea3-8b56-89333796930e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=984644893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.984644893
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2099363237
Short name T786
Test name
Test status
Simulation time 208407148 ps
CPU time 11.99 seconds
Started Jul 05 04:30:26 PM PDT 24
Finished Jul 05 04:30:44 PM PDT 24
Peak memory 254372 kb
Host smart-3ac06416-082a-4cd9-a3f2-ccae96a0fa24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2099363237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2099363237
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1712628899
Short name T231
Test name
Test status
Simulation time 446912408 ps
CPU time 10 seconds
Started Jul 05 04:30:30 PM PDT 24
Finished Jul 05 04:30:45 PM PDT 24
Peak memory 250900 kb
Host smart-10132799-02c3-414a-8264-bef82514e9d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712628899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1712628899
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1477305731
Short name T729
Test name
Test status
Simulation time 192720253 ps
CPU time 4.45 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:30:42 PM PDT 24
Peak memory 237444 kb
Host smart-997e147c-de74-482d-9fb3-33241c6a71fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1477305731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1477305731
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1923035177
Short name T794
Test name
Test status
Simulation time 9356286 ps
CPU time 1.56 seconds
Started Jul 05 04:30:32 PM PDT 24
Finished Jul 05 04:30:38 PM PDT 24
Peak memory 236516 kb
Host smart-0b5745e3-4954-4cd7-a712-15991388d464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1923035177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1923035177
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2452943829
Short name T738
Test name
Test status
Simulation time 688375481 ps
CPU time 43.82 seconds
Started Jul 05 04:30:17 PM PDT 24
Finished Jul 05 04:31:03 PM PDT 24
Peak memory 245600 kb
Host smart-cb69b364-4202-47b8-9ab4-feef83eebf42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2452943829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2452943829
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2099086867
Short name T110
Test name
Test status
Simulation time 16743529455 ps
CPU time 288.05 seconds
Started Jul 05 04:30:35 PM PDT 24
Finished Jul 05 04:35:28 PM PDT 24
Peak memory 265332 kb
Host smart-68989ffb-5a83-4819-af08-a980a8493119
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2099086867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2099086867
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2133575545
Short name T111
Test name
Test status
Simulation time 2194109620 ps
CPU time 292.66 seconds
Started Jul 05 04:30:13 PM PDT 24
Finished Jul 05 04:35:08 PM PDT 24
Peak memory 265280 kb
Host smart-db55ebb2-ae61-4f2c-a539-d6ea239245fe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133575545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2133575545
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2442699917
Short name T748
Test name
Test status
Simulation time 958713111 ps
CPU time 16.03 seconds
Started Jul 05 04:30:22 PM PDT 24
Finished Jul 05 04:30:41 PM PDT 24
Peak memory 255340 kb
Host smart-00217e3f-5b0e-4a44-85e3-da3b13af37cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2442699917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2442699917
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3125073281
Short name T784
Test name
Test status
Simulation time 36330184 ps
CPU time 2.96 seconds
Started Jul 05 04:30:33 PM PDT 24
Finished Jul 05 04:30:41 PM PDT 24
Peak memory 238560 kb
Host smart-1353893c-f63e-49ac-a9b8-555087acf522
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3125073281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3125073281
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3690084962
Short name T773
Test name
Test status
Simulation time 99044691 ps
CPU time 4.5 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:30:27 PM PDT 24
Peak memory 238536 kb
Host smart-1715b599-4c61-4ca2-b656-9b0915e5bd32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690084962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3690084962
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.4042350124
Short name T757
Test name
Test status
Simulation time 351937433 ps
CPU time 7.63 seconds
Started Jul 05 04:30:49 PM PDT 24
Finished Jul 05 04:30:57 PM PDT 24
Peak memory 237416 kb
Host smart-b27d17ba-d805-4b27-a06b-2c0435a15110
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4042350124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.4042350124
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3027700562
Short name T753
Test name
Test status
Simulation time 261678391 ps
CPU time 16.06 seconds
Started Jul 05 04:30:23 PM PDT 24
Finished Jul 05 04:30:44 PM PDT 24
Peak memory 244708 kb
Host smart-e07280de-1219-462a-9185-72d790000c33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3027700562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3027700562
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.821311734
Short name T145
Test name
Test status
Simulation time 10867393531 ps
CPU time 147.32 seconds
Started Jul 05 04:30:21 PM PDT 24
Finished Jul 05 04:32:51 PM PDT 24
Peak memory 265264 kb
Host smart-28f840cd-76d4-4846-8e92-0af1c14a0f2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=821311734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.821311734
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2564095735
Short name T138
Test name
Test status
Simulation time 16335915748 ps
CPU time 566.9 seconds
Started Jul 05 04:30:27 PM PDT 24
Finished Jul 05 04:40:00 PM PDT 24
Peak memory 269356 kb
Host smart-93b114ba-9ffa-45e6-86c7-0d56f18c847c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564095735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2564095735
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1073071487
Short name T714
Test name
Test status
Simulation time 159592666 ps
CPU time 6.23 seconds
Started Jul 05 04:30:29 PM PDT 24
Finished Jul 05 04:30:41 PM PDT 24
Peak memory 248256 kb
Host smart-a844ac4a-71a9-4f4e-888c-036842e9f7ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1073071487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1073071487
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.480373219
Short name T790
Test name
Test status
Simulation time 60603448 ps
CPU time 3.41 seconds
Started Jul 05 04:30:20 PM PDT 24
Finished Jul 05 04:30:25 PM PDT 24
Peak memory 237440 kb
Host smart-a8106d75-bcb7-487d-bf2d-2aca35c517af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=480373219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.480373219
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2476466968
Short name T446
Test name
Test status
Simulation time 28282983069 ps
CPU time 1578.31 seconds
Started Jul 05 04:42:45 PM PDT 24
Finished Jul 05 05:09:05 PM PDT 24
Peak memory 274012 kb
Host smart-a9f608ae-0b1e-4eec-ac68-cb1b2ce492bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476466968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2476466968
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1327315943
Short name T420
Test name
Test status
Simulation time 2431373515 ps
CPU time 28.43 seconds
Started Jul 05 04:42:40 PM PDT 24
Finished Jul 05 04:43:11 PM PDT 24
Peak memory 249328 kb
Host smart-aea1bb1a-1ba3-46ec-a86f-fe75af064618
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1327315943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1327315943
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3677424403
Short name T18
Test name
Test status
Simulation time 1271846586 ps
CPU time 121.58 seconds
Started Jul 05 04:42:41 PM PDT 24
Finished Jul 05 04:44:45 PM PDT 24
Peak memory 257004 kb
Host smart-8ffec491-1717-4c1e-9524-c383de8bac2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36774
24403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3677424403
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2853172343
Short name T102
Test name
Test status
Simulation time 806743508 ps
CPU time 47.05 seconds
Started Jul 05 04:42:46 PM PDT 24
Finished Jul 05 04:43:35 PM PDT 24
Peak memory 256688 kb
Host smart-84ce82f1-a684-4efd-8576-78ab0d57d492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28531
72343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2853172343
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1172666876
Short name T310
Test name
Test status
Simulation time 75640593452 ps
CPU time 2367.98 seconds
Started Jul 05 04:42:41 PM PDT 24
Finished Jul 05 05:22:12 PM PDT 24
Peak memory 290320 kb
Host smart-67dba0b6-9464-4328-8c3e-fcfe79ee8013
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172666876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1172666876
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.117292721
Short name T84
Test name
Test status
Simulation time 22567334527 ps
CPU time 1266.61 seconds
Started Jul 05 04:42:40 PM PDT 24
Finished Jul 05 05:03:50 PM PDT 24
Peak memory 287516 kb
Host smart-06a1b264-ed41-490e-a6bf-3532873e4b52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117292721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.117292721
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3974177717
Short name T303
Test name
Test status
Simulation time 13663868015 ps
CPU time 121.71 seconds
Started Jul 05 04:42:40 PM PDT 24
Finished Jul 05 04:44:45 PM PDT 24
Peak memory 256152 kb
Host smart-da653a83-a603-4149-839f-37681191d12a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974177717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3974177717
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2439874552
Short name T433
Test name
Test status
Simulation time 2586684146 ps
CPU time 36.81 seconds
Started Jul 05 04:42:38 PM PDT 24
Finished Jul 05 04:43:18 PM PDT 24
Peak memory 256928 kb
Host smart-9c99a11e-363d-4747-9327-6193f029f0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24398
74552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2439874552
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.293478685
Short name T439
Test name
Test status
Simulation time 13636214683 ps
CPU time 56.24 seconds
Started Jul 05 04:42:34 PM PDT 24
Finished Jul 05 04:43:34 PM PDT 24
Peak memory 256636 kb
Host smart-9d15b3bd-a660-4713-9c76-1ed16fd4903f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29347
8685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.293478685
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.434558875
Short name T35
Test name
Test status
Simulation time 1286564597 ps
CPU time 20.06 seconds
Started Jul 05 04:42:41 PM PDT 24
Finished Jul 05 04:43:04 PM PDT 24
Peak memory 279012 kb
Host smart-11cfcceb-e19d-4a81-a0b0-7d89f52a8fc6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=434558875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.434558875
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2136483381
Short name T357
Test name
Test status
Simulation time 331392257 ps
CPU time 25.51 seconds
Started Jul 05 04:42:39 PM PDT 24
Finished Jul 05 04:43:08 PM PDT 24
Peak memory 248908 kb
Host smart-8e675b4f-d01e-426d-a7b4-c4cde4664d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21364
83381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2136483381
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1020435286
Short name T419
Test name
Test status
Simulation time 1911698928 ps
CPU time 13.97 seconds
Started Jul 05 04:42:34 PM PDT 24
Finished Jul 05 04:42:51 PM PDT 24
Peak memory 257264 kb
Host smart-0f7fee1e-da1c-4fa2-88a6-474b365593c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10204
35286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1020435286
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1459598967
Short name T62
Test name
Test status
Simulation time 28620459049 ps
CPU time 1453.85 seconds
Started Jul 05 04:42:39 PM PDT 24
Finished Jul 05 05:06:56 PM PDT 24
Peak memory 290360 kb
Host smart-505b971f-2939-43f2-af11-dcffca52a224
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459598967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1459598967
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1911193636
Short name T86
Test name
Test status
Simulation time 21938115845 ps
CPU time 695.8 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 04:54:27 PM PDT 24
Peak memory 265696 kb
Host smart-bfe744c0-b8a2-4b3f-aa20-1ecd056dac8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911193636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1911193636
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1758900341
Short name T603
Test name
Test status
Simulation time 138621947 ps
CPU time 8.55 seconds
Started Jul 05 04:42:40 PM PDT 24
Finished Jul 05 04:42:52 PM PDT 24
Peak memory 249140 kb
Host smart-37b1db51-30e8-4efb-8070-aeb2f83ebbf8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1758900341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1758900341
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2637291020
Short name T346
Test name
Test status
Simulation time 3520223140 ps
CPU time 145.32 seconds
Started Jul 05 04:42:49 PM PDT 24
Finished Jul 05 04:45:17 PM PDT 24
Peak memory 257532 kb
Host smart-ed0716ea-23d7-4643-9012-90c1cd7da6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26372
91020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2637291020
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2996628371
Short name T468
Test name
Test status
Simulation time 3564850213 ps
CPU time 50.9 seconds
Started Jul 05 04:42:43 PM PDT 24
Finished Jul 05 04:43:36 PM PDT 24
Peak memory 249420 kb
Host smart-dc510921-a1f1-47d9-b40d-9781b132d8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29966
28371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2996628371
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.948182258
Short name T319
Test name
Test status
Simulation time 51480985550 ps
CPU time 3041.3 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 05:33:33 PM PDT 24
Peak memory 289496 kb
Host smart-0d72e252-aacb-42f1-9ae1-e4e1ea138dce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948182258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.948182258
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1602296709
Short name T681
Test name
Test status
Simulation time 89437201527 ps
CPU time 2715.94 seconds
Started Jul 05 04:42:45 PM PDT 24
Finished Jul 05 05:28:03 PM PDT 24
Peak memory 290084 kb
Host smart-4d6e0c39-917d-4536-94ab-b01838f9bcf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602296709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1602296709
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3576210154
Short name T654
Test name
Test status
Simulation time 116044600341 ps
CPU time 475.69 seconds
Started Jul 05 04:42:47 PM PDT 24
Finished Jul 05 04:50:45 PM PDT 24
Peak memory 249384 kb
Host smart-7da1748b-1169-4727-a81d-d41fccf1d139
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576210154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3576210154
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.4229909914
Short name T606
Test name
Test status
Simulation time 161082507 ps
CPU time 11.92 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 04:43:03 PM PDT 24
Peak memory 255176 kb
Host smart-b1ad2016-73b9-48d2-9595-68b5e22c6355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42299
09914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.4229909914
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2808544307
Short name T362
Test name
Test status
Simulation time 1678108293 ps
CPU time 17.79 seconds
Started Jul 05 04:42:41 PM PDT 24
Finished Jul 05 04:43:01 PM PDT 24
Peak memory 249308 kb
Host smart-3d9ba358-f7ef-44da-a6f1-6699d7dcdbed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28085
44307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2808544307
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3294113164
Short name T36
Test name
Test status
Simulation time 223199004 ps
CPU time 12.82 seconds
Started Jul 05 04:42:41 PM PDT 24
Finished Jul 05 04:42:56 PM PDT 24
Peak memory 278212 kb
Host smart-5e4e7cbb-d24b-4e9c-847a-f5ca968ae339
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3294113164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3294113164
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2788657006
Short name T87
Test name
Test status
Simulation time 168093860 ps
CPU time 19.76 seconds
Started Jul 05 04:42:42 PM PDT 24
Finished Jul 05 04:43:04 PM PDT 24
Peak memory 256744 kb
Host smart-5944a854-24c9-44ee-9800-11d03c16a963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27886
57006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2788657006
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3900139903
Short name T487
Test name
Test status
Simulation time 312191192 ps
CPU time 3.84 seconds
Started Jul 05 04:42:45 PM PDT 24
Finished Jul 05 04:42:50 PM PDT 24
Peak memory 249256 kb
Host smart-63928ff4-2a6f-4dd3-87a5-0fbe8a589c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39001
39903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3900139903
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.961806616
Short name T98
Test name
Test status
Simulation time 207913427139 ps
CPU time 1148.47 seconds
Started Jul 05 04:42:45 PM PDT 24
Finished Jul 05 05:01:55 PM PDT 24
Peak memory 289940 kb
Host smart-51e06743-a34e-4a76-b7d7-3ef638251995
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961806616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.961806616
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3068468017
Short name T201
Test name
Test status
Simulation time 75194731 ps
CPU time 3.92 seconds
Started Jul 05 04:42:57 PM PDT 24
Finished Jul 05 04:43:01 PM PDT 24
Peak memory 249560 kb
Host smart-2c2d1cb6-ca56-483f-aba6-a44393de6981
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3068468017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3068468017
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2818307716
Short name T587
Test name
Test status
Simulation time 99655721453 ps
CPU time 3039.49 seconds
Started Jul 05 04:43:11 PM PDT 24
Finished Jul 05 05:33:53 PM PDT 24
Peak memory 289412 kb
Host smart-f979dc17-cbea-45d3-8a81-9c8402de828b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818307716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2818307716
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.215921814
Short name T607
Test name
Test status
Simulation time 787752984 ps
CPU time 33.41 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 04:43:35 PM PDT 24
Peak memory 249232 kb
Host smart-0f737e9c-f82f-4f7d-827f-2f8f18c6d478
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=215921814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.215921814
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1849831305
Short name T574
Test name
Test status
Simulation time 3087065332 ps
CPU time 93.77 seconds
Started Jul 05 04:43:05 PM PDT 24
Finished Jul 05 04:44:41 PM PDT 24
Peak memory 256936 kb
Host smart-10750a87-4268-4717-b323-b85c89f2037c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18498
31305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1849831305
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3023929676
Short name T683
Test name
Test status
Simulation time 149537366 ps
CPU time 9.7 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 04:43:14 PM PDT 24
Peak memory 253424 kb
Host smart-571441b8-29fe-4178-9b26-5bea4857157a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30239
29676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3023929676
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3990179730
Short name T240
Test name
Test status
Simulation time 13337247844 ps
CPU time 1161.39 seconds
Started Jul 05 04:43:15 PM PDT 24
Finished Jul 05 05:02:38 PM PDT 24
Peak memory 290280 kb
Host smart-a3ab2039-a515-4444-8dd6-7e4bf4ff678d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990179730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3990179730
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2858844904
Short name T700
Test name
Test status
Simulation time 24348965939 ps
CPU time 1563.19 seconds
Started Jul 05 04:43:06 PM PDT 24
Finished Jul 05 05:09:12 PM PDT 24
Peak memory 273956 kb
Host smart-29d321d0-9bc4-47a4-845f-8c2769b3607b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858844904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2858844904
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1035787225
Short name T225
Test name
Test status
Simulation time 8781551074 ps
CPU time 341.87 seconds
Started Jul 05 04:43:04 PM PDT 24
Finished Jul 05 04:48:48 PM PDT 24
Peak memory 249388 kb
Host smart-48c04247-2b1d-45f8-9669-30cf1ed7bd65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035787225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1035787225
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.928762695
Short name T616
Test name
Test status
Simulation time 2029379189 ps
CPU time 53.41 seconds
Started Jul 05 04:42:59 PM PDT 24
Finished Jul 05 04:43:53 PM PDT 24
Peak memory 256576 kb
Host smart-340e6ba1-2d7d-4b27-9c0a-67bbbee24baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92876
2695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.928762695
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4142285882
Short name T99
Test name
Test status
Simulation time 2532225492 ps
CPU time 37.73 seconds
Started Jul 05 04:43:15 PM PDT 24
Finished Jul 05 04:43:55 PM PDT 24
Peak memory 249356 kb
Host smart-67727ee3-d293-4f94-9811-6ee81cdd998b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41422
85882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4142285882
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.637926439
Short name T277
Test name
Test status
Simulation time 278166801 ps
CPU time 29.77 seconds
Started Jul 05 04:43:11 PM PDT 24
Finished Jul 05 04:43:43 PM PDT 24
Peak memory 249300 kb
Host smart-1c384de0-f971-40f7-b978-907120d407f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63792
6439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.637926439
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.329514231
Short name T535
Test name
Test status
Simulation time 509702379 ps
CPU time 13.37 seconds
Started Jul 05 04:43:05 PM PDT 24
Finished Jul 05 04:43:20 PM PDT 24
Peak memory 249280 kb
Host smart-5da07b60-d573-40b1-888f-5a6141dd8504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32951
4231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.329514231
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2099567829
Short name T644
Test name
Test status
Simulation time 58748621655 ps
CPU time 6023.5 seconds
Started Jul 05 04:43:05 PM PDT 24
Finished Jul 05 06:23:31 PM PDT 24
Peak memory 372320 kb
Host smart-1dffe241-d932-440c-81b1-31759c668a87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099567829 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2099567829
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2447018244
Short name T193
Test name
Test status
Simulation time 345181528 ps
CPU time 3.46 seconds
Started Jul 05 04:43:03 PM PDT 24
Finished Jul 05 04:43:09 PM PDT 24
Peak memory 249480 kb
Host smart-783e8797-e6f6-49a1-af02-0a7a53e0ce0d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2447018244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2447018244
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1992390320
Short name T327
Test name
Test status
Simulation time 30189585790 ps
CPU time 2176.13 seconds
Started Jul 05 04:43:14 PM PDT 24
Finished Jul 05 05:19:32 PM PDT 24
Peak memory 285984 kb
Host smart-ec56e753-75d5-40bc-a28e-b1b1c2f729af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992390320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1992390320
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1961168226
Short name T481
Test name
Test status
Simulation time 4951498154 ps
CPU time 45.68 seconds
Started Jul 05 04:43:16 PM PDT 24
Finished Jul 05 04:44:04 PM PDT 24
Peak memory 249308 kb
Host smart-d7434483-8415-4ae4-a9a8-61d2645fcb6c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1961168226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1961168226
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1667846466
Short name T406
Test name
Test status
Simulation time 2054109283 ps
CPU time 168.68 seconds
Started Jul 05 04:42:59 PM PDT 24
Finished Jul 05 04:45:49 PM PDT 24
Peak memory 256944 kb
Host smart-562a541f-2de1-4512-bde6-13e05464cfd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16678
46466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1667846466
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2896877304
Short name T361
Test name
Test status
Simulation time 495173907 ps
CPU time 18.12 seconds
Started Jul 05 04:43:04 PM PDT 24
Finished Jul 05 04:43:25 PM PDT 24
Peak memory 255548 kb
Host smart-e3dac9ff-147f-46e4-a1ef-8edfac125b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28968
77304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2896877304
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1315331560
Short name T615
Test name
Test status
Simulation time 61942603736 ps
CPU time 1099.37 seconds
Started Jul 05 04:42:59 PM PDT 24
Finished Jul 05 05:01:20 PM PDT 24
Peak memory 273900 kb
Host smart-fb4bad09-2adc-4f30-b7ec-860feba0db4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315331560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1315331560
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.4149737393
Short name T524
Test name
Test status
Simulation time 24165545217 ps
CPU time 1335.5 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 05:05:39 PM PDT 24
Peak memory 272268 kb
Host smart-0b6250a3-3f4f-4b8b-a365-19b41137f358
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149737393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.4149737393
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.323538074
Short name T244
Test name
Test status
Simulation time 9471691398 ps
CPU time 190.72 seconds
Started Jul 05 04:42:58 PM PDT 24
Finished Jul 05 04:46:10 PM PDT 24
Peak memory 249396 kb
Host smart-a1ab89da-1c71-48d6-8071-758b0df495b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323538074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.323538074
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3795005483
Short name T436
Test name
Test status
Simulation time 2999547579 ps
CPU time 48.64 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 04:43:53 PM PDT 24
Peak memory 256908 kb
Host smart-3da5c8ce-f71f-4e08-9256-71ddd9f86212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37950
05483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3795005483
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2875012637
Short name T684
Test name
Test status
Simulation time 1776337537 ps
CPU time 41.67 seconds
Started Jul 05 04:42:59 PM PDT 24
Finished Jul 05 04:43:41 PM PDT 24
Peak memory 248740 kb
Host smart-8328b32a-0736-4b5f-9b47-8ec058ebc1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28750
12637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2875012637
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3083843130
Short name T383
Test name
Test status
Simulation time 110799301 ps
CPU time 7.96 seconds
Started Jul 05 04:43:05 PM PDT 24
Finished Jul 05 04:43:15 PM PDT 24
Peak memory 253064 kb
Host smart-b6230f72-8174-4038-8ecd-b7bccb6ca8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30838
43130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3083843130
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1099702444
Short name T550
Test name
Test status
Simulation time 382494583 ps
CPU time 24.48 seconds
Started Jul 05 04:43:08 PM PDT 24
Finished Jul 05 04:43:34 PM PDT 24
Peak memory 257076 kb
Host smart-09ea8e8a-0bb1-4604-b318-0639cb9686ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10997
02444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1099702444
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.4033738707
Short name T292
Test name
Test status
Simulation time 193060952403 ps
CPU time 2398.95 seconds
Started Jul 05 04:43:10 PM PDT 24
Finished Jul 05 05:23:11 PM PDT 24
Peak memory 290212 kb
Host smart-04b903ae-69e9-44d8-8c32-ec830ea80e04
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033738707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.4033738707
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.294773727
Short name T227
Test name
Test status
Simulation time 10570489590 ps
CPU time 660.43 seconds
Started Jul 05 04:43:11 PM PDT 24
Finished Jul 05 04:54:13 PM PDT 24
Peak memory 267060 kb
Host smart-b4765e8b-9366-4346-bdd3-038220e71b84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294773727 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.294773727
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1765745429
Short name T54
Test name
Test status
Simulation time 83672296567 ps
CPU time 2426.29 seconds
Started Jul 05 04:43:04 PM PDT 24
Finished Jul 05 05:23:33 PM PDT 24
Peak memory 286088 kb
Host smart-f8d0d1dc-8d5a-46aa-af80-8d1a0d701f61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765745429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1765745429
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3488846256
Short name T569
Test name
Test status
Simulation time 787730650 ps
CPU time 11.65 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 04:43:15 PM PDT 24
Peak memory 249080 kb
Host smart-13c6c9a4-d02f-49be-b299-c09bbd0b5ab8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3488846256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3488846256
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2848910949
Short name T547
Test name
Test status
Simulation time 5277385535 ps
CPU time 130.36 seconds
Started Jul 05 04:43:17 PM PDT 24
Finished Jul 05 04:45:30 PM PDT 24
Peak memory 256896 kb
Host smart-16312a00-ae16-4e2f-a9cd-8a579400ec8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28489
10949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2848910949
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3059540758
Short name T371
Test name
Test status
Simulation time 458526059 ps
CPU time 8.2 seconds
Started Jul 05 04:43:07 PM PDT 24
Finished Jul 05 04:43:17 PM PDT 24
Peak memory 248752 kb
Host smart-e01beecd-4cb8-4b47-8747-f6bd6a96d669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30595
40758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3059540758
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.261011580
Short name T595
Test name
Test status
Simulation time 135900817931 ps
CPU time 2252.93 seconds
Started Jul 05 04:43:15 PM PDT 24
Finished Jul 05 05:20:49 PM PDT 24
Peak memory 282112 kb
Host smart-e0ac68f6-fbb1-4a98-b4ca-6e6699c7109c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261011580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.261011580
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3635532669
Short name T71
Test name
Test status
Simulation time 131696836165 ps
CPU time 1902.81 seconds
Started Jul 05 04:43:00 PM PDT 24
Finished Jul 05 05:14:44 PM PDT 24
Peak memory 273908 kb
Host smart-a72072dc-cb06-47b7-9c18-99b937abff82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635532669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3635532669
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3589742293
Short name T638
Test name
Test status
Simulation time 10634202207 ps
CPU time 71.04 seconds
Started Jul 05 04:43:08 PM PDT 24
Finished Jul 05 04:44:21 PM PDT 24
Peak memory 248180 kb
Host smart-5673f4ba-5c4b-4d6f-ad5c-fb63bea02442
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589742293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3589742293
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.4273260353
Short name T675
Test name
Test status
Simulation time 658470613 ps
CPU time 41.59 seconds
Started Jul 05 04:43:08 PM PDT 24
Finished Jul 05 04:43:52 PM PDT 24
Peak memory 256708 kb
Host smart-2604a5a9-21c4-4754-a16d-82b0f7d37e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42732
60353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.4273260353
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1853333571
Short name T483
Test name
Test status
Simulation time 3085434911 ps
CPU time 49.72 seconds
Started Jul 05 04:42:58 PM PDT 24
Finished Jul 05 04:43:48 PM PDT 24
Peak memory 249376 kb
Host smart-1a3c1e87-5670-4a13-9e5e-16f1f997fdda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18533
33571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1853333571
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.4265511033
Short name T458
Test name
Test status
Simulation time 10531927707 ps
CPU time 56.34 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 04:44:00 PM PDT 24
Peak memory 248584 kb
Host smart-02567451-768e-449c-9632-84d4d4137377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42655
11033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.4265511033
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2994746457
Short name T22
Test name
Test status
Simulation time 899034883 ps
CPU time 30.71 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 04:43:35 PM PDT 24
Peak memory 256400 kb
Host smart-f6e638bc-3039-45ad-a8f7-697ed96e6c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29947
46457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2994746457
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.4153804891
Short name T463
Test name
Test status
Simulation time 33324439835 ps
CPU time 1225.05 seconds
Started Jul 05 04:43:09 PM PDT 24
Finished Jul 05 05:03:36 PM PDT 24
Peak memory 289856 kb
Host smart-73f98056-20ed-4c01-a734-899118cb868c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153804891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.4153804891
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1210895858
Short name T508
Test name
Test status
Simulation time 1085325059 ps
CPU time 46.25 seconds
Started Jul 05 04:43:15 PM PDT 24
Finished Jul 05 04:44:02 PM PDT 24
Peak memory 249204 kb
Host smart-5bc77e5e-4af0-4b68-ae4f-8b836d831105
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1210895858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1210895858
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3057116956
Short name T359
Test name
Test status
Simulation time 1226420242 ps
CPU time 34.89 seconds
Started Jul 05 04:42:59 PM PDT 24
Finished Jul 05 04:43:35 PM PDT 24
Peak memory 256984 kb
Host smart-65d1764c-7488-4125-b835-75dae7c10c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30571
16956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3057116956
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1106646013
Short name T422
Test name
Test status
Simulation time 147963560 ps
CPU time 5 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 04:43:08 PM PDT 24
Peak memory 248832 kb
Host smart-ed492543-ef5b-45c2-9466-4edbd0e0f930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11066
46013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1106646013
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.434991818
Short name T286
Test name
Test status
Simulation time 60296138442 ps
CPU time 1967.73 seconds
Started Jul 05 04:43:10 PM PDT 24
Finished Jul 05 05:15:59 PM PDT 24
Peak memory 282476 kb
Host smart-d9245d55-588d-4869-9ba2-581fc1582f56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434991818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.434991818
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1232591327
Short name T650
Test name
Test status
Simulation time 95475905306 ps
CPU time 2735.42 seconds
Started Jul 05 04:43:00 PM PDT 24
Finished Jul 05 05:28:36 PM PDT 24
Peak memory 282092 kb
Host smart-91e17fcd-8d3a-44b1-b62f-16d6064d32af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232591327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1232591327
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.26037698
Short name T507
Test name
Test status
Simulation time 20704559882 ps
CPU time 208.26 seconds
Started Jul 05 04:43:10 PM PDT 24
Finished Jul 05 04:46:40 PM PDT 24
Peak memory 249120 kb
Host smart-d22bcdbb-ba0e-4273-b001-e4f9d5e4f7e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26037698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.26037698
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3180438278
Short name T391
Test name
Test status
Simulation time 273577123 ps
CPU time 15.01 seconds
Started Jul 05 04:43:17 PM PDT 24
Finished Jul 05 04:43:33 PM PDT 24
Peak memory 256596 kb
Host smart-e0633cd2-fa4b-47db-aa7c-5e6da7098429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31804
38278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3180438278
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1136513555
Short name T592
Test name
Test status
Simulation time 427904483 ps
CPU time 26.37 seconds
Started Jul 05 04:43:11 PM PDT 24
Finished Jul 05 04:43:40 PM PDT 24
Peak memory 256500 kb
Host smart-aa180f92-6742-4b9c-af41-ca7e7be87800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11365
13555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1136513555
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1069490673
Short name T516
Test name
Test status
Simulation time 62784001 ps
CPU time 2.66 seconds
Started Jul 05 04:42:58 PM PDT 24
Finished Jul 05 04:43:01 PM PDT 24
Peak memory 241000 kb
Host smart-af8ae395-3f4c-443e-b32f-84a6cba2ec6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10694
90673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1069490673
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2881130452
Short name T504
Test name
Test status
Simulation time 660799750 ps
CPU time 14.44 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 04:43:17 PM PDT 24
Peak memory 256024 kb
Host smart-69f9c86a-2ced-4c6e-8d08-583d6f74a378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28811
30452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2881130452
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3864034843
Short name T486
Test name
Test status
Simulation time 222232949995 ps
CPU time 3270.41 seconds
Started Jul 05 04:43:12 PM PDT 24
Finished Jul 05 05:37:45 PM PDT 24
Peak memory 289580 kb
Host smart-4de1480f-17bd-4ad0-9295-3a6ee9b23b99
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864034843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3864034843
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3083679353
Short name T209
Test name
Test status
Simulation time 161779032 ps
CPU time 3.43 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 04:43:08 PM PDT 24
Peak memory 249536 kb
Host smart-8e8a5110-c655-45a2-96ce-912c07f62a65
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3083679353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3083679353
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1940167143
Short name T224
Test name
Test status
Simulation time 332771631 ps
CPU time 17.87 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 04:43:22 PM PDT 24
Peak memory 249236 kb
Host smart-2ae87337-749d-4c67-a3d8-f77995552440
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1940167143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1940167143
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1330918452
Short name T351
Test name
Test status
Simulation time 13091019540 ps
CPU time 45.45 seconds
Started Jul 05 04:43:15 PM PDT 24
Finished Jul 05 04:44:02 PM PDT 24
Peak memory 257504 kb
Host smart-f981c9eb-3a6b-48d2-9c79-c4dc38bb8046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13309
18452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1330918452
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.797109674
Short name T525
Test name
Test status
Simulation time 1472668064 ps
CPU time 33.26 seconds
Started Jul 05 04:43:12 PM PDT 24
Finished Jul 05 04:43:47 PM PDT 24
Peak memory 249172 kb
Host smart-0b506324-725b-4ef7-893f-ef06f78551fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79710
9674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.797109674
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.965669350
Short name T325
Test name
Test status
Simulation time 10467582469 ps
CPU time 992.63 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 04:59:35 PM PDT 24
Peak memory 286732 kb
Host smart-5905feef-c645-4770-a8d1-0299a612e06b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965669350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.965669350
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2431162765
Short name T400
Test name
Test status
Simulation time 251295416312 ps
CPU time 2662.5 seconds
Started Jul 05 04:43:08 PM PDT 24
Finished Jul 05 05:27:33 PM PDT 24
Peak memory 284488 kb
Host smart-1d5c8f33-4b13-4da3-9c04-b5e724e0f4a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431162765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2431162765
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.623262008
Short name T294
Test name
Test status
Simulation time 46701608085 ps
CPU time 480.85 seconds
Started Jul 05 04:43:11 PM PDT 24
Finished Jul 05 04:51:14 PM PDT 24
Peak memory 249384 kb
Host smart-ee12eecd-630f-45e6-8ba4-d17c6534a8c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623262008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.623262008
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1231068383
Short name T20
Test name
Test status
Simulation time 183808731 ps
CPU time 4.91 seconds
Started Jul 05 04:43:15 PM PDT 24
Finished Jul 05 04:43:21 PM PDT 24
Peak memory 249264 kb
Host smart-0bd0527f-d89f-4b79-b8af-262d8115d8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12310
68383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1231068383
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2888371667
Short name T70
Test name
Test status
Simulation time 2870564114 ps
CPU time 42.89 seconds
Started Jul 05 04:42:59 PM PDT 24
Finished Jul 05 04:43:42 PM PDT 24
Peak memory 256540 kb
Host smart-d09d863a-a852-47a4-b81d-ecf38c6b57c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28883
71667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2888371667
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1814981029
Short name T274
Test name
Test status
Simulation time 130847930 ps
CPU time 6.35 seconds
Started Jul 05 04:43:07 PM PDT 24
Finished Jul 05 04:43:15 PM PDT 24
Peak memory 249280 kb
Host smart-936dcaea-78c6-427e-ae21-2e9eeafd8079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18149
81029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1814981029
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.915804065
Short name T425
Test name
Test status
Simulation time 272524787 ps
CPU time 16.13 seconds
Started Jul 05 04:43:03 PM PDT 24
Finished Jul 05 04:43:22 PM PDT 24
Peak memory 256856 kb
Host smart-535c3d0e-684a-48e9-95d3-435a56041193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91580
4065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.915804065
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.562240920
Short name T9
Test name
Test status
Simulation time 17419727827 ps
CPU time 1283.92 seconds
Started Jul 05 04:42:59 PM PDT 24
Finished Jul 05 05:04:23 PM PDT 24
Peak memory 288960 kb
Host smart-3d76fedd-725b-41b6-a962-2d9ded291f24
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562240920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.562240920
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1570546679
Short name T197
Test name
Test status
Simulation time 33275223 ps
CPU time 3.54 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:43:26 PM PDT 24
Peak memory 249532 kb
Host smart-9c1f8c07-8da4-4b19-9ba4-7f8c0841cb15
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1570546679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1570546679
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2782575523
Short name T649
Test name
Test status
Simulation time 10559031652 ps
CPU time 880.67 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:58:04 PM PDT 24
Peak memory 273768 kb
Host smart-c4d18956-791c-421f-a64f-8d9047451054
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782575523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2782575523
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2492919261
Short name T565
Test name
Test status
Simulation time 228279105 ps
CPU time 11.4 seconds
Started Jul 05 04:43:17 PM PDT 24
Finished Jul 05 04:43:31 PM PDT 24
Peak memory 249280 kb
Host smart-65745c24-8e27-49b5-8fc2-470fb6918e78
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2492919261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2492919261
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.448868470
Short name T613
Test name
Test status
Simulation time 6340831688 ps
CPU time 134.99 seconds
Started Jul 05 04:43:04 PM PDT 24
Finished Jul 05 04:45:21 PM PDT 24
Peak memory 257104 kb
Host smart-21ee78b0-1953-44a2-9229-d9253209bf7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44886
8470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.448868470
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3810649219
Short name T617
Test name
Test status
Simulation time 511073633 ps
CPU time 30.92 seconds
Started Jul 05 04:43:21 PM PDT 24
Finished Jul 05 04:43:55 PM PDT 24
Peak memory 249696 kb
Host smart-f8b84246-f565-4ef8-86ba-609c32063c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38106
49219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3810649219
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3492939747
Short name T699
Test name
Test status
Simulation time 75608469890 ps
CPU time 1752.05 seconds
Started Jul 05 04:43:08 PM PDT 24
Finished Jul 05 05:12:22 PM PDT 24
Peak memory 290020 kb
Host smart-698cfe68-cf70-4e79-ae9d-79ce049908de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492939747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3492939747
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.698082205
Short name T573
Test name
Test status
Simulation time 17416589248 ps
CPU time 364.38 seconds
Started Jul 05 04:43:21 PM PDT 24
Finished Jul 05 04:49:28 PM PDT 24
Peak memory 248252 kb
Host smart-0f990172-3866-45b7-abf2-c878a1708378
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698082205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.698082205
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3178546368
Short name T656
Test name
Test status
Simulation time 476126234 ps
CPU time 4.34 seconds
Started Jul 05 04:43:18 PM PDT 24
Finished Jul 05 04:43:24 PM PDT 24
Peak memory 249264 kb
Host smart-d00fcaae-8c67-4954-a194-17fa745cabd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31785
46368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3178546368
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1760877883
Short name T38
Test name
Test status
Simulation time 518146897 ps
CPU time 33.61 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 04:43:39 PM PDT 24
Peak memory 249228 kb
Host smart-7813f70d-cc12-42b9-b0c6-e5e1a7963e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17608
77883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1760877883
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2544854062
Short name T83
Test name
Test status
Simulation time 1083747116 ps
CPU time 28.39 seconds
Started Jul 05 04:43:04 PM PDT 24
Finished Jul 05 04:43:35 PM PDT 24
Peak memory 257032 kb
Host smart-29616bca-2d2d-4a6e-ab6c-c86fd8e3021a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25448
54062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2544854062
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.738039141
Short name T31
Test name
Test status
Simulation time 6257239176 ps
CPU time 51.76 seconds
Started Jul 05 04:43:04 PM PDT 24
Finished Jul 05 04:43:58 PM PDT 24
Peak memory 257560 kb
Host smart-04bc0a5f-7abc-4bae-aa40-5c75d5939691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73803
9141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.738039141
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1049818399
Short name T279
Test name
Test status
Simulation time 19302022218 ps
CPU time 1040.82 seconds
Started Jul 05 04:43:21 PM PDT 24
Finished Jul 05 05:00:45 PM PDT 24
Peak memory 285008 kb
Host smart-8992c25b-0e54-40db-b0c4-54f1cdd939bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049818399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1049818399
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2684883545
Short name T73
Test name
Test status
Simulation time 99251631 ps
CPU time 2.73 seconds
Started Jul 05 04:43:21 PM PDT 24
Finished Jul 05 04:43:27 PM PDT 24
Peak memory 249544 kb
Host smart-8968e90b-04c3-4104-9f5d-92afef2aec20
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2684883545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2684883545
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2599192732
Short name T702
Test name
Test status
Simulation time 75580056368 ps
CPU time 2115.65 seconds
Started Jul 05 04:43:22 PM PDT 24
Finished Jul 05 05:18:40 PM PDT 24
Peak memory 282132 kb
Host smart-3152bfb3-3a32-4b81-a571-7f5884ecde17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599192732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2599192732
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3031101083
Short name T540
Test name
Test status
Simulation time 1426085914 ps
CPU time 11.19 seconds
Started Jul 05 04:43:17 PM PDT 24
Finished Jul 05 04:43:31 PM PDT 24
Peak memory 249128 kb
Host smart-31be711f-37f5-423e-955b-6a71662a41fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3031101083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3031101083
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.905651848
Short name T696
Test name
Test status
Simulation time 1621548949 ps
CPU time 147.98 seconds
Started Jul 05 04:43:03 PM PDT 24
Finished Jul 05 04:45:33 PM PDT 24
Peak memory 252380 kb
Host smart-2541cb15-08ac-4d22-bc38-6ff261d83b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90565
1848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.905651848
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2245087033
Short name T586
Test name
Test status
Simulation time 75294619 ps
CPU time 7.51 seconds
Started Jul 05 04:43:08 PM PDT 24
Finished Jul 05 04:43:17 PM PDT 24
Peak memory 249200 kb
Host smart-7657dd67-dd9a-4a51-9157-8ccfaa939ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22450
87033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2245087033
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2787207381
Short name T461
Test name
Test status
Simulation time 45072253045 ps
CPU time 939.01 seconds
Started Jul 05 04:43:07 PM PDT 24
Finished Jul 05 04:58:48 PM PDT 24
Peak memory 272856 kb
Host smart-99e13641-2d88-4602-ad7b-d986f8086e28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787207381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2787207381
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3871757602
Short name T24
Test name
Test status
Simulation time 560651576 ps
CPU time 25.04 seconds
Started Jul 05 04:43:09 PM PDT 24
Finished Jul 05 04:43:36 PM PDT 24
Peak memory 249296 kb
Host smart-900467ba-6c05-4dd3-a33a-e454426c9f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38717
57602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3871757602
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1955734043
Short name T448
Test name
Test status
Simulation time 3485905659 ps
CPU time 60.13 seconds
Started Jul 05 04:43:13 PM PDT 24
Finished Jul 05 04:44:15 PM PDT 24
Peak memory 249348 kb
Host smart-c1f0cf41-08b2-4af4-b296-302dce5996d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19557
34043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1955734043
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3934112884
Short name T469
Test name
Test status
Simulation time 102614575 ps
CPU time 12.3 seconds
Started Jul 05 04:43:03 PM PDT 24
Finished Jul 05 04:43:18 PM PDT 24
Peak memory 248852 kb
Host smart-cb781339-566f-462f-850f-aa1647cd124c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39341
12884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3934112884
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.209455449
Short name T445
Test name
Test status
Simulation time 854510694 ps
CPU time 31.58 seconds
Started Jul 05 04:43:03 PM PDT 24
Finished Jul 05 04:43:37 PM PDT 24
Peak memory 257368 kb
Host smart-a5dc79ad-b762-45ca-b7f7-0cf40dfaacd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20945
5449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.209455449
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.4045264469
Short name T667
Test name
Test status
Simulation time 3200684575 ps
CPU time 59.25 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 04:44:25 PM PDT 24
Peak memory 257524 kb
Host smart-47a788ec-fa63-4903-b949-8c2b9db18a87
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045264469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.4045264469
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.801708280
Short name T199
Test name
Test status
Simulation time 25204174 ps
CPU time 2.36 seconds
Started Jul 05 04:43:04 PM PDT 24
Finished Jul 05 04:43:08 PM PDT 24
Peak memory 249596 kb
Host smart-a8de70d4-235a-4ace-a2da-aeb66b4b7057
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=801708280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.801708280
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.197712320
Short name T562
Test name
Test status
Simulation time 64928906800 ps
CPU time 1405.38 seconds
Started Jul 05 04:43:23 PM PDT 24
Finished Jul 05 05:06:50 PM PDT 24
Peak memory 289976 kb
Host smart-7c140482-1616-4ae7-985f-a9c5398b164d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197712320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.197712320
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1153829914
Short name T689
Test name
Test status
Simulation time 470910729 ps
CPU time 12.87 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:43:36 PM PDT 24
Peak memory 249124 kb
Host smart-4f022670-f5bf-484a-b18b-28229414d716
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1153829914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1153829914
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1856165897
Short name T557
Test name
Test status
Simulation time 17560140425 ps
CPU time 273.14 seconds
Started Jul 05 04:43:05 PM PDT 24
Finished Jul 05 04:47:40 PM PDT 24
Peak memory 257532 kb
Host smart-e0d956a3-f20f-4534-98ab-72c427924049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18561
65897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1856165897
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1518945
Short name T352
Test name
Test status
Simulation time 268636794 ps
CPU time 29.82 seconds
Started Jul 05 04:43:03 PM PDT 24
Finished Jul 05 04:43:36 PM PDT 24
Peak memory 256052 kb
Host smart-8f5e4969-3840-4674-8ea6-5b314ffe370a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15189
45 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1518945
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1830580167
Short name T255
Test name
Test status
Simulation time 10818187054 ps
CPU time 980.52 seconds
Started Jul 05 04:43:03 PM PDT 24
Finished Jul 05 04:59:26 PM PDT 24
Peak memory 273288 kb
Host smart-e5e3685b-9ee7-40c5-a2b5-f44ed7f37bc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830580167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1830580167
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2685795015
Short name T709
Test name
Test status
Simulation time 34247695988 ps
CPU time 2065.62 seconds
Started Jul 05 04:43:18 PM PDT 24
Finished Jul 05 05:17:45 PM PDT 24
Peak memory 273976 kb
Host smart-1e7dd443-c24c-4418-befb-eede8e4d2cd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685795015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2685795015
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1757094035
Short name T188
Test name
Test status
Simulation time 6097619810 ps
CPU time 245.86 seconds
Started Jul 05 04:43:05 PM PDT 24
Finished Jul 05 04:47:13 PM PDT 24
Peak memory 249372 kb
Host smart-08e22523-f217-47c1-9162-b7e584c69267
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757094035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1757094035
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.988488595
Short name T413
Test name
Test status
Simulation time 239663475 ps
CPU time 10.41 seconds
Started Jul 05 04:43:10 PM PDT 24
Finished Jul 05 04:43:23 PM PDT 24
Peak memory 249268 kb
Host smart-7f06ea7e-f4ec-4da9-a3a3-49a098470b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98848
8595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.988488595
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2098562275
Short name T101
Test name
Test status
Simulation time 2334702502 ps
CPU time 33.22 seconds
Started Jul 05 04:43:18 PM PDT 24
Finished Jul 05 04:43:53 PM PDT 24
Peak memory 256884 kb
Host smart-66265c09-d76c-4e85-bbdc-18de0589045e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20985
62275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2098562275
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3531741137
Short name T575
Test name
Test status
Simulation time 220515455 ps
CPU time 21.77 seconds
Started Jul 05 04:43:10 PM PDT 24
Finished Jul 05 04:43:34 PM PDT 24
Peak memory 248628 kb
Host smart-1757ddd0-3ef9-4605-9de5-d23eebf874dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35317
41137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3531741137
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3894373212
Short name T491
Test name
Test status
Simulation time 4730532755 ps
CPU time 36.25 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:43:59 PM PDT 24
Peak memory 257540 kb
Host smart-8d6ca0bf-8b4f-4b23-81de-8dfbb9ed9b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38943
73212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3894373212
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.822219066
Short name T257
Test name
Test status
Simulation time 53752311691 ps
CPU time 3158.08 seconds
Started Jul 05 04:43:08 PM PDT 24
Finished Jul 05 05:35:49 PM PDT 24
Peak memory 290124 kb
Host smart-171e17ff-1b93-460c-b727-37613037634c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822219066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.822219066
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.698640997
Short name T21
Test name
Test status
Simulation time 14093883 ps
CPU time 2.32 seconds
Started Jul 05 04:43:08 PM PDT 24
Finished Jul 05 04:43:12 PM PDT 24
Peak memory 249580 kb
Host smart-6b5eecb8-1178-4280-9b4c-70ab21bd3bba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=698640997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.698640997
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1874433149
Short name T393
Test name
Test status
Simulation time 78714498309 ps
CPU time 2858.23 seconds
Started Jul 05 04:43:17 PM PDT 24
Finished Jul 05 05:30:58 PM PDT 24
Peak memory 289944 kb
Host smart-def48199-1569-4e13-9cba-ad4cef7f3073
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874433149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1874433149
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2482968476
Short name T375
Test name
Test status
Simulation time 208478114 ps
CPU time 12.25 seconds
Started Jul 05 04:43:05 PM PDT 24
Finished Jul 05 04:43:20 PM PDT 24
Peak memory 249276 kb
Host smart-6b1f83e5-3cca-447f-be3b-a4aec821ab83
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2482968476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2482968476
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2370851936
Short name T537
Test name
Test status
Simulation time 2663669453 ps
CPU time 147.83 seconds
Started Jul 05 04:43:13 PM PDT 24
Finished Jul 05 04:45:42 PM PDT 24
Peak memory 257492 kb
Host smart-5b5d9969-d416-4f0b-a098-3a6a4a1cfa99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23708
51936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2370851936
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2025968665
Short name T40
Test name
Test status
Simulation time 272026003 ps
CPU time 21.48 seconds
Started Jul 05 04:43:10 PM PDT 24
Finished Jul 05 04:43:33 PM PDT 24
Peak memory 256452 kb
Host smart-52089791-2d75-4d43-9c19-928f9882608c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20259
68665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2025968665
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2887177866
Short name T465
Test name
Test status
Simulation time 40655565662 ps
CPU time 2297.23 seconds
Started Jul 05 04:43:22 PM PDT 24
Finished Jul 05 05:21:42 PM PDT 24
Peak memory 289300 kb
Host smart-5da28f95-ba59-4814-8968-1e09108d9597
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887177866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2887177866
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.438514850
Short name T15
Test name
Test status
Simulation time 20016565352 ps
CPU time 220.76 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:47:04 PM PDT 24
Peak memory 255912 kb
Host smart-b31458dd-636a-41f7-ad2a-ca83c35a8529
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438514850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.438514850
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1374495270
Short name T519
Test name
Test status
Simulation time 295177075 ps
CPU time 17.37 seconds
Started Jul 05 04:43:07 PM PDT 24
Finished Jul 05 04:43:26 PM PDT 24
Peak memory 249292 kb
Host smart-c5164b6a-726c-4883-b9e2-c6a0fcee53a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13744
95270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1374495270
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2969322476
Short name T594
Test name
Test status
Simulation time 66082517 ps
CPU time 7.78 seconds
Started Jul 05 04:43:05 PM PDT 24
Finished Jul 05 04:43:15 PM PDT 24
Peak memory 255260 kb
Host smart-9d44ec80-562c-4fb2-b121-be9feb16609f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29693
22476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2969322476
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.227749114
Short name T454
Test name
Test status
Simulation time 267269019 ps
CPU time 26.27 seconds
Started Jul 05 04:43:15 PM PDT 24
Finished Jul 05 04:43:43 PM PDT 24
Peak memory 257128 kb
Host smart-b8d3f3be-ba49-4707-ad6b-5c11d12d2a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22774
9114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.227749114
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2301506302
Short name T517
Test name
Test status
Simulation time 1152870531 ps
CPU time 14.5 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:43:37 PM PDT 24
Peak memory 249300 kb
Host smart-3da1665e-bcba-47a5-93d7-725319a5ce61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23015
06302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2301506302
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2506413441
Short name T678
Test name
Test status
Simulation time 2995273239 ps
CPU time 90.83 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 04:44:33 PM PDT 24
Peak memory 257520 kb
Host smart-57fb9ed8-0f12-488c-8b7e-a8ae765dd00a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506413441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2506413441
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3077936341
Short name T103
Test name
Test status
Simulation time 32279744135 ps
CPU time 997.51 seconds
Started Jul 05 04:43:12 PM PDT 24
Finished Jul 05 04:59:52 PM PDT 24
Peak memory 273544 kb
Host smart-0dda374f-8fb2-497c-b4ab-b41fabcb905d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077936341 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3077936341
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3493686449
Short name T200
Test name
Test status
Simulation time 66276996 ps
CPU time 3.66 seconds
Started Jul 05 04:43:23 PM PDT 24
Finished Jul 05 04:43:29 PM PDT 24
Peak memory 249484 kb
Host smart-8fef6ea2-df93-43b5-a800-57b90c23b588
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3493686449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3493686449
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3417556049
Short name T543
Test name
Test status
Simulation time 31497774739 ps
CPU time 1248.68 seconds
Started Jul 05 04:43:30 PM PDT 24
Finished Jul 05 05:04:20 PM PDT 24
Peak memory 273656 kb
Host smart-544b05b9-ae32-4754-b515-9cbd53817e89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417556049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3417556049
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1544078582
Short name T408
Test name
Test status
Simulation time 1463469803 ps
CPU time 62.58 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:44:26 PM PDT 24
Peak memory 257484 kb
Host smart-85bdb6ee-2d1f-4a27-8289-7c442c4fd752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15440
78582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1544078582
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3820817554
Short name T590
Test name
Test status
Simulation time 921281678 ps
CPU time 62.08 seconds
Started Jul 05 04:43:19 PM PDT 24
Finished Jul 05 04:44:24 PM PDT 24
Peak memory 249204 kb
Host smart-1d3f2b68-6703-4189-9ca0-4d6a6db03132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38208
17554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3820817554
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1782966857
Short name T326
Test name
Test status
Simulation time 22881795985 ps
CPU time 1128.22 seconds
Started Jul 05 04:43:18 PM PDT 24
Finished Jul 05 05:02:08 PM PDT 24
Peak memory 273932 kb
Host smart-444d10d5-549c-428d-856b-073202ade1b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782966857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1782966857
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1328699593
Short name T509
Test name
Test status
Simulation time 65821790613 ps
CPU time 1440.98 seconds
Started Jul 05 04:43:17 PM PDT 24
Finished Jul 05 05:07:21 PM PDT 24
Peak memory 288016 kb
Host smart-604a49a3-f08d-4c4a-bd31-166c6f1f149d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328699593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1328699593
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1762522794
Short name T609
Test name
Test status
Simulation time 815857280 ps
CPU time 48.22 seconds
Started Jul 05 04:43:18 PM PDT 24
Finished Jul 05 04:44:09 PM PDT 24
Peak memory 256612 kb
Host smart-c12c364d-8913-4a44-afb6-5e11bc7ba4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17625
22794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1762522794
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.891851721
Short name T559
Test name
Test status
Simulation time 1741498367 ps
CPU time 26.32 seconds
Started Jul 05 04:43:19 PM PDT 24
Finished Jul 05 04:43:49 PM PDT 24
Peak memory 249296 kb
Host smart-49f5ce9f-8b78-43b4-a40f-8d73eb7277a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89185
1721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.891851721
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3736291275
Short name T39
Test name
Test status
Simulation time 146270868 ps
CPU time 11.16 seconds
Started Jul 05 04:43:27 PM PDT 24
Finished Jul 05 04:43:40 PM PDT 24
Peak memory 254424 kb
Host smart-2f2cc232-d37b-4c56-8310-acd2c9888dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37362
91275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3736291275
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.73732724
Short name T19
Test name
Test status
Simulation time 135537260 ps
CPU time 12.7 seconds
Started Jul 05 04:43:18 PM PDT 24
Finished Jul 05 04:43:33 PM PDT 24
Peak memory 256232 kb
Host smart-de6d15f7-f519-4bf2-af32-a766e7704bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73732
724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.73732724
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2248920492
Short name T97
Test name
Test status
Simulation time 223863312666 ps
CPU time 1998.17 seconds
Started Jul 05 04:43:16 PM PDT 24
Finished Jul 05 05:16:36 PM PDT 24
Peak memory 283688 kb
Host smart-d02c3edb-9b61-46ea-83c5-69be76bb3671
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248920492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2248920492
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3311578285
Short name T208
Test name
Test status
Simulation time 25710911 ps
CPU time 2.45 seconds
Started Jul 05 04:42:42 PM PDT 24
Finished Jul 05 04:42:47 PM PDT 24
Peak memory 249556 kb
Host smart-f2ec87dd-c268-40a0-af68-cf5e55f88bd9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3311578285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3311578285
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1679144339
Short name T95
Test name
Test status
Simulation time 105152941587 ps
CPU time 1610.67 seconds
Started Jul 05 04:42:39 PM PDT 24
Finished Jul 05 05:09:33 PM PDT 24
Peak memory 271012 kb
Host smart-ed5aef1a-eed1-4e8b-948e-1c459fc559fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679144339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1679144339
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1101012276
Short name T186
Test name
Test status
Simulation time 940071732 ps
CPU time 39.9 seconds
Started Jul 05 04:42:44 PM PDT 24
Finished Jul 05 04:43:25 PM PDT 24
Peak memory 249264 kb
Host smart-b290d0b8-7283-4891-9c47-9b34c392ce14
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1101012276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1101012276
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1048429516
Short name T2
Test name
Test status
Simulation time 4368055258 ps
CPU time 71.1 seconds
Started Jul 05 04:42:45 PM PDT 24
Finished Jul 05 04:43:57 PM PDT 24
Peak memory 256984 kb
Host smart-00010474-528d-4c36-8a6b-bfdbd3c16585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10484
29516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1048429516
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.609982536
Short name T564
Test name
Test status
Simulation time 2312715487 ps
CPU time 46.49 seconds
Started Jul 05 04:42:49 PM PDT 24
Finished Jul 05 04:43:38 PM PDT 24
Peak memory 249344 kb
Host smart-698919bf-eb80-4bc2-9c4e-38a4de5c6692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60998
2536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.609982536
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2402589464
Short name T711
Test name
Test status
Simulation time 155383092240 ps
CPU time 2221.14 seconds
Started Jul 05 04:42:45 PM PDT 24
Finished Jul 05 05:19:48 PM PDT 24
Peak memory 290252 kb
Host smart-04f7975b-b4ee-429e-8aa5-c71d86a485b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402589464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2402589464
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3428819149
Short name T680
Test name
Test status
Simulation time 57955111425 ps
CPU time 1722.58 seconds
Started Jul 05 04:42:44 PM PDT 24
Finished Jul 05 05:11:28 PM PDT 24
Peak memory 273780 kb
Host smart-09219dfd-5267-4783-867e-d081693dadad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428819149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3428819149
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3589465837
Short name T356
Test name
Test status
Simulation time 613195701 ps
CPU time 18.02 seconds
Started Jul 05 04:42:41 PM PDT 24
Finished Jul 05 04:43:02 PM PDT 24
Peak memory 256556 kb
Host smart-7a12c1ee-a908-4f53-9ce6-81b1d8566cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35894
65837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3589465837
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3673394483
Short name T12
Test name
Test status
Simulation time 1313965577 ps
CPU time 25.92 seconds
Started Jul 05 04:42:46 PM PDT 24
Finished Jul 05 04:43:15 PM PDT 24
Peak memory 267560 kb
Host smart-e8311542-f89f-4446-9c29-c48f339d2c4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3673394483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3673394483
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.875059625
Short name T402
Test name
Test status
Simulation time 373921392 ps
CPU time 6.68 seconds
Started Jul 05 04:42:42 PM PDT 24
Finished Jul 05 04:42:51 PM PDT 24
Peak memory 251520 kb
Host smart-8b3b1506-3185-43c0-a101-ffb8c9f0a464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87505
9625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.875059625
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.125489314
Short name T560
Test name
Test status
Simulation time 346679821 ps
CPU time 18.67 seconds
Started Jul 05 04:42:41 PM PDT 24
Finished Jul 05 04:43:03 PM PDT 24
Peak memory 256284 kb
Host smart-77f742ad-aa25-4d1d-be95-6899d62260e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12548
9314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.125489314
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.991587280
Short name T50
Test name
Test status
Simulation time 13572480446 ps
CPU time 1175.98 seconds
Started Jul 05 04:42:42 PM PDT 24
Finished Jul 05 05:02:21 PM PDT 24
Peak memory 287996 kb
Host smart-24ba19f6-41e5-4d06-962a-3d245a961135
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991587280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.991587280
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3795014240
Short name T380
Test name
Test status
Simulation time 4757876396 ps
CPU time 161.65 seconds
Started Jul 05 04:43:23 PM PDT 24
Finished Jul 05 04:46:07 PM PDT 24
Peak memory 256952 kb
Host smart-f5f66dc7-3c0b-4222-ac59-f1f7e1c62e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37950
14240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3795014240
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3556100335
Short name T407
Test name
Test status
Simulation time 7723845994 ps
CPU time 25.17 seconds
Started Jul 05 04:43:18 PM PDT 24
Finished Jul 05 04:43:45 PM PDT 24
Peak memory 257544 kb
Host smart-c8cd8828-8148-4327-889f-0f77768b5c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35561
00335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3556100335
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2778029300
Short name T388
Test name
Test status
Simulation time 8673893697 ps
CPU time 618.81 seconds
Started Jul 05 04:43:15 PM PDT 24
Finished Jul 05 04:53:36 PM PDT 24
Peak memory 265796 kb
Host smart-b4e4ed07-d058-4daf-ab91-036fe1a1a9c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778029300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2778029300
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3599159011
Short name T610
Test name
Test status
Simulation time 3170765142 ps
CPU time 37.03 seconds
Started Jul 05 04:43:17 PM PDT 24
Finished Jul 05 04:43:55 PM PDT 24
Peak memory 256560 kb
Host smart-884ff5e4-3b5d-4791-a212-92cbfaa39cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35991
59011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3599159011
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2620012596
Short name T78
Test name
Test status
Simulation time 2368530848 ps
CPU time 30.81 seconds
Started Jul 05 04:43:29 PM PDT 24
Finished Jul 05 04:44:01 PM PDT 24
Peak memory 257248 kb
Host smart-98de3755-5cc9-45e4-b577-77014c9a2a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26200
12596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2620012596
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1401155587
Short name T58
Test name
Test status
Simulation time 355396176 ps
CPU time 42.03 seconds
Started Jul 05 04:43:18 PM PDT 24
Finished Jul 05 04:44:02 PM PDT 24
Peak memory 249580 kb
Host smart-6a7d1457-91cd-4e6f-b053-dd902ceeea10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14011
55587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1401155587
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3359008271
Short name T219
Test name
Test status
Simulation time 748739807 ps
CPU time 34.87 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 04:44:01 PM PDT 24
Peak memory 256512 kb
Host smart-477095ad-ae25-4c68-adea-a0dc2e8c0238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33590
08271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3359008271
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2875467609
Short name T478
Test name
Test status
Simulation time 31186188847 ps
CPU time 1753.83 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 05:12:40 PM PDT 24
Peak memory 274016 kb
Host smart-727ba32c-4259-4c01-ade8-9da51ad7c53b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875467609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2875467609
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4033390184
Short name T460
Test name
Test status
Simulation time 12212388085 ps
CPU time 172.55 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:46:16 PM PDT 24
Peak memory 257504 kb
Host smart-5d9d432a-bcbb-4be3-8e60-89c3bbb10f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40333
90184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4033390184
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.849627478
Short name T455
Test name
Test status
Simulation time 2383770632 ps
CPU time 21.65 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 04:43:47 PM PDT 24
Peak memory 256328 kb
Host smart-81bb52aa-b792-4649-b65f-f263b5777e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84962
7478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.849627478
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.89672805
Short name T697
Test name
Test status
Simulation time 37719785014 ps
CPU time 2226.04 seconds
Started Jul 05 04:43:29 PM PDT 24
Finished Jul 05 05:20:37 PM PDT 24
Peak memory 284080 kb
Host smart-5d45da89-52ab-441f-8b2e-2646e1e3c89d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89672805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.89672805
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1756894645
Short name T424
Test name
Test status
Simulation time 50837403426 ps
CPU time 1153.54 seconds
Started Jul 05 04:43:32 PM PDT 24
Finished Jul 05 05:02:48 PM PDT 24
Peak memory 273480 kb
Host smart-fb161497-de5b-45aa-b2e5-8c13db4c7343
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756894645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1756894645
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2101901511
Short name T216
Test name
Test status
Simulation time 4623763024 ps
CPU time 73.04 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:44:36 PM PDT 24
Peak memory 257600 kb
Host smart-6194b3c9-b1ad-4b3c-9729-59fc9deb2190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21019
01511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2101901511
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2598128636
Short name T629
Test name
Test status
Simulation time 753004979 ps
CPU time 51.06 seconds
Started Jul 05 04:43:23 PM PDT 24
Finished Jul 05 04:44:17 PM PDT 24
Peak memory 257184 kb
Host smart-a7d10840-e4c4-4332-833e-0b8ca544f850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25981
28636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2598128636
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2659476174
Short name T272
Test name
Test status
Simulation time 275714494300 ps
CPU time 3386.27 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 05:39:50 PM PDT 24
Peak memory 289528 kb
Host smart-c104bcf7-361d-40c8-9c5a-98266529d686
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659476174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2659476174
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3377532565
Short name T539
Test name
Test status
Simulation time 92262965654 ps
CPU time 1930.1 seconds
Started Jul 05 04:43:17 PM PDT 24
Finished Jul 05 05:15:30 PM PDT 24
Peak memory 273828 kb
Host smart-ff93c4df-0ebd-4661-8d7f-316a79cb8875
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377532565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3377532565
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1163492083
Short name T482
Test name
Test status
Simulation time 9192071346 ps
CPU time 121.7 seconds
Started Jul 05 04:43:23 PM PDT 24
Finished Jul 05 04:45:27 PM PDT 24
Peak memory 257056 kb
Host smart-1eb75b59-2130-4134-9658-01cf403451fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11634
92083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1163492083
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2891748096
Short name T527
Test name
Test status
Simulation time 1560546819 ps
CPU time 24.92 seconds
Started Jul 05 04:43:15 PM PDT 24
Finished Jul 05 04:43:42 PM PDT 24
Peak memory 249224 kb
Host smart-47716cc0-81e3-4f0e-83a7-8c62cb09ea5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28917
48096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2891748096
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3881522090
Short name T321
Test name
Test status
Simulation time 42932465423 ps
CPU time 1461.88 seconds
Started Jul 05 04:43:21 PM PDT 24
Finished Jul 05 05:07:46 PM PDT 24
Peak memory 273288 kb
Host smart-524fdcb5-23d2-4949-b62e-135a1237fa4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881522090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3881522090
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3699616772
Short name T373
Test name
Test status
Simulation time 9915529137 ps
CPU time 1346.47 seconds
Started Jul 05 04:43:25 PM PDT 24
Finished Jul 05 05:05:54 PM PDT 24
Peak memory 289644 kb
Host smart-c956a148-4360-48b6-8300-dd7f9b7a8862
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699616772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3699616772
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.4009103989
Short name T628
Test name
Test status
Simulation time 13050204148 ps
CPU time 543.93 seconds
Started Jul 05 04:43:21 PM PDT 24
Finished Jul 05 04:52:28 PM PDT 24
Peak memory 255840 kb
Host smart-0a99e50b-2b39-43e2-a56b-08a3ae39152d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009103989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.4009103989
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.556793704
Short name T490
Test name
Test status
Simulation time 74600330 ps
CPU time 5.35 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 04:43:31 PM PDT 24
Peak memory 241024 kb
Host smart-d9853ebf-52fc-4c0d-a984-006c77cadf67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55679
3704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.556793704
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2374283119
Short name T500
Test name
Test status
Simulation time 523294554 ps
CPU time 33.84 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:43:57 PM PDT 24
Peak memory 256900 kb
Host smart-743c247f-dd4f-45e1-86cd-05d095e5a30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23742
83119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2374283119
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.4216572072
Short name T691
Test name
Test status
Simulation time 4898613201 ps
CPU time 36.55 seconds
Started Jul 05 04:43:18 PM PDT 24
Finished Jul 05 04:43:56 PM PDT 24
Peak memory 248892 kb
Host smart-f9c7ddef-c9f1-4c1d-b1e4-284bc23033e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42165
72072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.4216572072
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1870274966
Short name T440
Test name
Test status
Simulation time 2660436107 ps
CPU time 45.89 seconds
Started Jul 05 04:43:19 PM PDT 24
Finished Jul 05 04:44:08 PM PDT 24
Peak memory 257532 kb
Host smart-4a4e0737-a97e-43e3-b256-c1ed1e0bbd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18702
74966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1870274966
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.535490692
Short name T253
Test name
Test status
Simulation time 104224698217 ps
CPU time 6392.6 seconds
Started Jul 05 04:43:25 PM PDT 24
Finished Jul 05 06:30:00 PM PDT 24
Peak memory 371644 kb
Host smart-58347289-6601-4d18-848d-de0872f947fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535490692 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.535490692
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.96401602
Short name T92
Test name
Test status
Simulation time 30949216034 ps
CPU time 1594.38 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 05:09:58 PM PDT 24
Peak memory 269888 kb
Host smart-9e313285-d790-408b-8899-62bb624c02b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96401602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.96401602
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.628770232
Short name T534
Test name
Test status
Simulation time 4289229347 ps
CPU time 58.81 seconds
Started Jul 05 04:43:29 PM PDT 24
Finished Jul 05 04:44:29 PM PDT 24
Peak memory 257020 kb
Host smart-8f05674b-108f-4e12-90e0-560db30a97b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62877
0232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.628770232
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2684838013
Short name T91
Test name
Test status
Simulation time 807559200 ps
CPU time 50.97 seconds
Started Jul 05 04:43:26 PM PDT 24
Finished Jul 05 04:44:19 PM PDT 24
Peak memory 257096 kb
Host smart-ac229283-84ea-4726-aaee-0e8c93777581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26848
38013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2684838013
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.34880147
Short name T104
Test name
Test status
Simulation time 112369769065 ps
CPU time 1723.25 seconds
Started Jul 05 04:43:16 PM PDT 24
Finished Jul 05 05:12:01 PM PDT 24
Peak memory 273924 kb
Host smart-cd6d5f74-feef-4f11-9398-cbd7a28ba5f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34880147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.34880147
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.442962597
Short name T93
Test name
Test status
Simulation time 3218455627 ps
CPU time 140.3 seconds
Started Jul 05 04:43:23 PM PDT 24
Finished Jul 05 04:45:45 PM PDT 24
Peak memory 255656 kb
Host smart-33f3d713-c773-4ce5-90be-e25e073affdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442962597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.442962597
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1197779034
Short name T250
Test name
Test status
Simulation time 2810690336 ps
CPU time 27.19 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 04:43:54 PM PDT 24
Peak memory 249404 kb
Host smart-ccc0e862-194c-4e28-b574-11d12eace01d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11977
79034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1197779034
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.561055432
Short name T442
Test name
Test status
Simulation time 1116805292 ps
CPU time 70.7 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 04:44:37 PM PDT 24
Peak memory 250252 kb
Host smart-cedbebfc-18f4-442d-b4dd-dda21d3bb697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56105
5432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.561055432
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4184572365
Short name T658
Test name
Test status
Simulation time 571868470 ps
CPU time 31.74 seconds
Started Jul 05 04:43:26 PM PDT 24
Finished Jul 05 04:44:00 PM PDT 24
Peak memory 249016 kb
Host smart-cbf5cd35-c15a-46ed-a198-2983c9a89945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41845
72365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4184572365
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.4243640697
Short name T647
Test name
Test status
Simulation time 610115109 ps
CPU time 35.16 seconds
Started Jul 05 04:43:20 PM PDT 24
Finished Jul 05 04:43:58 PM PDT 24
Peak memory 257260 kb
Host smart-732eee5e-bed4-41b1-8bd2-9c3b22548337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42436
40697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.4243640697
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1776268557
Short name T398
Test name
Test status
Simulation time 26014859251 ps
CPU time 1507.82 seconds
Started Jul 05 04:43:21 PM PDT 24
Finished Jul 05 05:08:32 PM PDT 24
Peak memory 289404 kb
Host smart-4eafda85-09a1-4917-a929-65589c13d8c3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776268557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1776268557
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.4141437644
Short name T57
Test name
Test status
Simulation time 24462129302 ps
CPU time 2614.89 seconds
Started Jul 05 04:43:29 PM PDT 24
Finished Jul 05 05:27:06 PM PDT 24
Peak memory 322920 kb
Host smart-2f664d88-90fe-4bf4-8174-e23f82b17182
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141437644 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.4141437644
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2061009112
Short name T602
Test name
Test status
Simulation time 145234807933 ps
CPU time 2135.79 seconds
Started Jul 05 04:43:29 PM PDT 24
Finished Jul 05 05:19:07 PM PDT 24
Peak memory 288344 kb
Host smart-eb965d75-0b3b-47cc-9ecf-001b44f523ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061009112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2061009112
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1713612349
Short name T505
Test name
Test status
Simulation time 1389709669 ps
CPU time 32.47 seconds
Started Jul 05 04:43:22 PM PDT 24
Finished Jul 05 04:43:57 PM PDT 24
Peak memory 256996 kb
Host smart-296878e2-1926-42c2-a53f-c14bc1cc13ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17136
12349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1713612349
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3010288981
Short name T376
Test name
Test status
Simulation time 1592356773 ps
CPU time 32.51 seconds
Started Jul 05 04:43:33 PM PDT 24
Finished Jul 05 04:44:07 PM PDT 24
Peak memory 249276 kb
Host smart-93b8659a-3ffb-4b20-9cdd-faa97bce477f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30102
88981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3010288981
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2945420579
Short name T556
Test name
Test status
Simulation time 26070067198 ps
CPU time 579.67 seconds
Started Jul 05 04:43:31 PM PDT 24
Finished Jul 05 04:53:12 PM PDT 24
Peak memory 273848 kb
Host smart-1f6b92ca-2ed2-4580-bd66-4d1103ac2272
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945420579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2945420579
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2837250455
Short name T635
Test name
Test status
Simulation time 99952157185 ps
CPU time 736.94 seconds
Started Jul 05 04:43:30 PM PDT 24
Finished Jul 05 04:55:49 PM PDT 24
Peak memory 273888 kb
Host smart-32b26a9c-c1bd-4da6-9393-b303e6d6b23b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837250455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2837250455
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.5584523
Short name T484
Test name
Test status
Simulation time 5408745589 ps
CPU time 124.06 seconds
Started Jul 05 04:43:27 PM PDT 24
Finished Jul 05 04:45:33 PM PDT 24
Peak memory 249412 kb
Host smart-3d6fea30-c7dd-4bbf-a31b-1efb63603c88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5584523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.5584523
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3112099478
Short name T435
Test name
Test status
Simulation time 491557137 ps
CPU time 13.29 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 04:43:40 PM PDT 24
Peak memory 249300 kb
Host smart-0b85b0c8-b1b8-48ff-b43e-1b2f959fbf5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31120
99478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3112099478
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1321461766
Short name T648
Test name
Test status
Simulation time 3006625222 ps
CPU time 28.62 seconds
Started Jul 05 04:43:25 PM PDT 24
Finished Jul 05 04:43:56 PM PDT 24
Peak memory 256588 kb
Host smart-c2989027-3b8b-46b5-b4d0-51967ff7f4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13214
61766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1321461766
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1848011277
Short name T283
Test name
Test status
Simulation time 1331166046 ps
CPU time 38.41 seconds
Started Jul 05 04:43:28 PM PDT 24
Finished Jul 05 04:44:08 PM PDT 24
Peak memory 257392 kb
Host smart-66678d95-4cd1-4a43-b007-4f842f3edffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18480
11277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1848011277
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3771222008
Short name T387
Test name
Test status
Simulation time 583840321 ps
CPU time 19.43 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 04:43:46 PM PDT 24
Peak memory 255940 kb
Host smart-9403ce96-71ff-4a81-9c4f-4f9f49db01a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37712
22008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3771222008
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3257092418
Short name T676
Test name
Test status
Simulation time 61663546732 ps
CPU time 1045.45 seconds
Started Jul 05 04:43:23 PM PDT 24
Finished Jul 05 05:00:51 PM PDT 24
Peak memory 282384 kb
Host smart-9e90778f-7184-4dcb-88f4-716e9b4f06d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257092418 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3257092418
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.347715413
Short name T52
Test name
Test status
Simulation time 18714906034 ps
CPU time 1268.53 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 05:04:34 PM PDT 24
Peak memory 273760 kb
Host smart-529f601c-1153-42d6-a3f4-ce2c54447fa5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347715413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.347715413
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3718194399
Short name T510
Test name
Test status
Simulation time 8657600579 ps
CPU time 119.15 seconds
Started Jul 05 04:43:25 PM PDT 24
Finished Jul 05 04:45:27 PM PDT 24
Peak memory 257500 kb
Host smart-e621c3a6-0d07-4853-b838-fa0845f7fc51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37181
94399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3718194399
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1054878162
Short name T354
Test name
Test status
Simulation time 516997301 ps
CPU time 28.97 seconds
Started Jul 05 04:43:29 PM PDT 24
Finished Jul 05 04:43:59 PM PDT 24
Peak memory 248852 kb
Host smart-714af120-4ad3-47d2-8d23-2e81003ee890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10548
78162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1054878162
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3236128096
Short name T238
Test name
Test status
Simulation time 10495780247 ps
CPU time 1422.67 seconds
Started Jul 05 04:43:37 PM PDT 24
Finished Jul 05 05:07:21 PM PDT 24
Peak memory 290292 kb
Host smart-5a90086a-8aeb-4241-8fcd-9b1f7969bf26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236128096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3236128096
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.517338226
Short name T379
Test name
Test status
Simulation time 10409323840 ps
CPU time 212.32 seconds
Started Jul 05 04:43:30 PM PDT 24
Finished Jul 05 04:47:04 PM PDT 24
Peak memory 255304 kb
Host smart-1bd58742-01ab-4d3d-a27a-45ab69745ca9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517338226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.517338226
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1939479728
Short name T444
Test name
Test status
Simulation time 412294773 ps
CPU time 26.43 seconds
Started Jul 05 04:43:27 PM PDT 24
Finished Jul 05 04:43:55 PM PDT 24
Peak memory 256484 kb
Host smart-ca07f063-7368-453f-ad09-3ea1289dfa69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19394
79728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1939479728
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.4054199240
Short name T251
Test name
Test status
Simulation time 1304782647 ps
CPU time 42.91 seconds
Started Jul 05 04:43:26 PM PDT 24
Finished Jul 05 04:44:11 PM PDT 24
Peak memory 256624 kb
Host smart-ac71ab9f-b2c2-49aa-ada5-570b9110d028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40541
99240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4054199240
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.29507873
Short name T492
Test name
Test status
Simulation time 56863350 ps
CPU time 4.92 seconds
Started Jul 05 04:43:25 PM PDT 24
Finished Jul 05 04:43:32 PM PDT 24
Peak memory 240512 kb
Host smart-6544f8ae-bd88-40de-95e5-b8b83872e3dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29507
873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.29507873
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.763293386
Short name T622
Test name
Test status
Simulation time 250499011 ps
CPU time 8.45 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 04:43:34 PM PDT 24
Peak memory 249212 kb
Host smart-888e6c14-7477-4a6e-9fa7-3d7b43e5306e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76329
3386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.763293386
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2186247425
Short name T26
Test name
Test status
Simulation time 266194394387 ps
CPU time 4693.91 seconds
Started Jul 05 04:43:26 PM PDT 24
Finished Jul 05 06:01:43 PM PDT 24
Peak memory 316096 kb
Host smart-2f25d966-0aa9-4ba6-8a84-e1aaa2e6fdb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186247425 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2186247425
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1847322065
Short name T416
Test name
Test status
Simulation time 21167551768 ps
CPU time 1257.14 seconds
Started Jul 05 04:43:28 PM PDT 24
Finished Jul 05 05:04:27 PM PDT 24
Peak memory 289820 kb
Host smart-ef8db669-6293-4d94-a524-1248d773973f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847322065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1847322065
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2460366772
Short name T399
Test name
Test status
Simulation time 219889169 ps
CPU time 5.38 seconds
Started Jul 05 04:43:27 PM PDT 24
Finished Jul 05 04:43:34 PM PDT 24
Peak memory 240568 kb
Host smart-7fd92f6c-4dc6-46fe-8401-2df9be487eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24603
66772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2460366772
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.111678069
Short name T596
Test name
Test status
Simulation time 5014592463 ps
CPU time 25.79 seconds
Started Jul 05 04:43:27 PM PDT 24
Finished Jul 05 04:43:54 PM PDT 24
Peak memory 249356 kb
Host smart-15c66e07-c4b0-4604-9f54-0aeb54762d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11167
8069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.111678069
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1411041359
Short name T223
Test name
Test status
Simulation time 21325585429 ps
CPU time 1220.54 seconds
Started Jul 05 04:43:29 PM PDT 24
Finished Jul 05 05:03:52 PM PDT 24
Peak memory 273912 kb
Host smart-27d619b2-e742-46b8-98be-fdc698dd3181
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411041359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1411041359
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.4085459780
Short name T623
Test name
Test status
Simulation time 74905918524 ps
CPU time 3446.26 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 05:40:53 PM PDT 24
Peak memory 290076 kb
Host smart-7b612216-6cb1-4471-a35f-fcee1f6667fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085459780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.4085459780
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2421625744
Short name T695
Test name
Test status
Simulation time 30981061816 ps
CPU time 322.01 seconds
Started Jul 05 04:43:26 PM PDT 24
Finished Jul 05 04:48:50 PM PDT 24
Peak memory 249120 kb
Host smart-729c55f7-f0ba-4516-8354-62ebdbeaee15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421625744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2421625744
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1712430949
Short name T213
Test name
Test status
Simulation time 558741331 ps
CPU time 9.07 seconds
Started Jul 05 04:43:26 PM PDT 24
Finished Jul 05 04:43:37 PM PDT 24
Peak memory 249284 kb
Host smart-a9b0cd05-5ea4-43e7-ab6f-8ca39902921e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17124
30949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1712430949
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3904139811
Short name T570
Test name
Test status
Simulation time 94437932 ps
CPU time 7.76 seconds
Started Jul 05 04:43:32 PM PDT 24
Finished Jul 05 04:43:41 PM PDT 24
Peak memory 248828 kb
Host smart-b9293d5f-0222-475f-bd38-164008e9b3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39041
39811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3904139811
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1008326376
Short name T94
Test name
Test status
Simulation time 175847831 ps
CPU time 22.42 seconds
Started Jul 05 04:43:27 PM PDT 24
Finished Jul 05 04:43:52 PM PDT 24
Peak memory 249276 kb
Host smart-b1679fa2-75f9-431f-ab52-8b02c8cbb97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10083
26376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1008326376
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3155088683
Short name T462
Test name
Test status
Simulation time 746191344 ps
CPU time 27.76 seconds
Started Jul 05 04:43:28 PM PDT 24
Finished Jul 05 04:43:57 PM PDT 24
Peak memory 257416 kb
Host smart-bef32b29-e364-49bc-8a6e-d1cc92c991a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31550
88683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3155088683
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2198111008
Short name T46
Test name
Test status
Simulation time 199169956859 ps
CPU time 2673.73 seconds
Started Jul 05 04:43:26 PM PDT 24
Finished Jul 05 05:28:02 PM PDT 24
Peak memory 290300 kb
Host smart-935c0bc1-6b9d-42b6-b232-198450531348
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198111008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2198111008
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3743264324
Short name T451
Test name
Test status
Simulation time 7981089706 ps
CPU time 875.53 seconds
Started Jul 05 04:43:27 PM PDT 24
Finished Jul 05 04:58:04 PM PDT 24
Peak memory 273892 kb
Host smart-b4187ae0-cac1-4630-adaa-53480338f76d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743264324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3743264324
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3831105421
Short name T372
Test name
Test status
Simulation time 2769475969 ps
CPU time 61.7 seconds
Started Jul 05 04:43:24 PM PDT 24
Finished Jul 05 04:44:28 PM PDT 24
Peak memory 257116 kb
Host smart-f6d4bf39-6f58-4623-a7af-d3f68bdd5326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38311
05421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3831105421
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3029484990
Short name T453
Test name
Test status
Simulation time 173499113 ps
CPU time 4.03 seconds
Started Jul 05 04:43:25 PM PDT 24
Finished Jul 05 04:43:31 PM PDT 24
Peak memory 240572 kb
Host smart-5a518468-efe6-4a5c-b3b6-d7b261f3e57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30294
84990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3029484990
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1646607329
Short name T652
Test name
Test status
Simulation time 23295768572 ps
CPU time 557.74 seconds
Started Jul 05 04:43:33 PM PDT 24
Finished Jul 05 04:52:52 PM PDT 24
Peak memory 273536 kb
Host smart-965a2a5b-edfc-416c-8f80-8f06f6b39ab4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646607329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1646607329
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3730726984
Short name T33
Test name
Test status
Simulation time 165030820303 ps
CPU time 2435.75 seconds
Started Jul 05 04:43:27 PM PDT 24
Finished Jul 05 05:24:05 PM PDT 24
Peak memory 286068 kb
Host smart-51ac37ea-b344-4b37-9d63-54a56c7fe154
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730726984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3730726984
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1002268717
Short name T297
Test name
Test status
Simulation time 26558052631 ps
CPU time 291.65 seconds
Started Jul 05 04:43:26 PM PDT 24
Finished Jul 05 04:48:20 PM PDT 24
Peak memory 255940 kb
Host smart-f1c944d4-2612-42d1-a19b-d61287ccbdd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002268717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1002268717
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2573350980
Short name T598
Test name
Test status
Simulation time 1144986688 ps
CPU time 38.72 seconds
Started Jul 05 04:43:26 PM PDT 24
Finished Jul 05 04:44:07 PM PDT 24
Peak memory 256284 kb
Host smart-3269f959-8d42-4466-9bff-8fb97b6e5ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25733
50980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2573350980
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1208219546
Short name T415
Test name
Test status
Simulation time 5576666950 ps
CPU time 55.67 seconds
Started Jul 05 04:43:30 PM PDT 24
Finished Jul 05 04:44:28 PM PDT 24
Peak memory 257040 kb
Host smart-43d241e3-5134-481a-88bb-a8390966586d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12082
19546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1208219546
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.710249536
Short name T284
Test name
Test status
Simulation time 73078297 ps
CPU time 9.12 seconds
Started Jul 05 04:43:28 PM PDT 24
Finished Jul 05 04:43:39 PM PDT 24
Peak memory 249192 kb
Host smart-859b5863-3dfe-447f-afd4-df9e608728f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71024
9536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.710249536
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.874562078
Short name T665
Test name
Test status
Simulation time 160273820 ps
CPU time 15.89 seconds
Started Jul 05 04:43:34 PM PDT 24
Finished Jul 05 04:43:51 PM PDT 24
Peak memory 249268 kb
Host smart-9312c479-2a5b-41f2-9af4-6e2ba103281f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87456
2078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.874562078
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2092694159
Short name T497
Test name
Test status
Simulation time 33033273358 ps
CPU time 2283.02 seconds
Started Jul 05 04:43:33 PM PDT 24
Finished Jul 05 05:21:38 PM PDT 24
Peak memory 288680 kb
Host smart-45fe8929-5487-49a0-84d6-e5a7cff99fe6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092694159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2092694159
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2610012964
Short name T642
Test name
Test status
Simulation time 15813537945 ps
CPU time 245.81 seconds
Started Jul 05 04:43:31 PM PDT 24
Finished Jul 05 04:47:38 PM PDT 24
Peak memory 257508 kb
Host smart-7230617b-bd70-4e1b-b732-0a85a72fd135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26100
12964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2610012964
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3755294381
Short name T475
Test name
Test status
Simulation time 144210027 ps
CPU time 9.31 seconds
Started Jul 05 04:43:25 PM PDT 24
Finished Jul 05 04:43:37 PM PDT 24
Peak memory 248732 kb
Host smart-49228ba4-559a-455a-9b12-f24f2239f30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37552
94381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3755294381
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.197576589
Short name T287
Test name
Test status
Simulation time 40084853859 ps
CPU time 1282.71 seconds
Started Jul 05 04:43:27 PM PDT 24
Finished Jul 05 05:04:52 PM PDT 24
Peak memory 273756 kb
Host smart-c06ae46f-ae1f-404a-817d-8ac5af403fc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197576589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.197576589
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2761089561
Short name T363
Test name
Test status
Simulation time 9379020064 ps
CPU time 776.89 seconds
Started Jul 05 04:43:23 PM PDT 24
Finished Jul 05 04:56:22 PM PDT 24
Peak memory 273712 kb
Host smart-39216d8b-b41e-4266-a826-865d4b347c71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761089561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2761089561
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.675425388
Short name T312
Test name
Test status
Simulation time 3209020144 ps
CPU time 125.03 seconds
Started Jul 05 04:43:29 PM PDT 24
Finished Jul 05 04:45:35 PM PDT 24
Peak memory 249236 kb
Host smart-f29e8807-07b5-4308-a944-6066bd9ff604
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675425388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.675425388
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2742678647
Short name T476
Test name
Test status
Simulation time 2990654996 ps
CPU time 20.46 seconds
Started Jul 05 04:43:29 PM PDT 24
Finished Jul 05 04:43:51 PM PDT 24
Peak memory 256860 kb
Host smart-aa95344e-f4ae-4056-878d-142b62dd0f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27426
78647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2742678647
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.128357119
Short name T217
Test name
Test status
Simulation time 3275168809 ps
CPU time 40.43 seconds
Started Jul 05 04:43:28 PM PDT 24
Finished Jul 05 04:44:10 PM PDT 24
Peak memory 257504 kb
Host smart-ec9b7868-b7b5-4eba-a151-141b5cdfc208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12835
7119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.128357119
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2377650960
Short name T601
Test name
Test status
Simulation time 248832785 ps
CPU time 5.35 seconds
Started Jul 05 04:43:29 PM PDT 24
Finished Jul 05 04:43:36 PM PDT 24
Peak memory 240544 kb
Host smart-f4a5c55f-91d0-4dde-a649-38c7854e1074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23776
50960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2377650960
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2843684433
Short name T16
Test name
Test status
Simulation time 4157712020 ps
CPU time 33.6 seconds
Started Jul 05 04:43:30 PM PDT 24
Finished Jul 05 04:44:06 PM PDT 24
Peak memory 257580 kb
Host smart-4bd61ded-ceb3-4bc3-8be8-9228183a3eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28436
84433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2843684433
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3140050492
Short name T631
Test name
Test status
Simulation time 55054554783 ps
CPU time 3122.39 seconds
Started Jul 05 04:43:31 PM PDT 24
Finished Jul 05 05:35:35 PM PDT 24
Peak memory 289644 kb
Host smart-9967de2c-f994-4981-a1ec-79ab596b76df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140050492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3140050492
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1368186187
Short name T248
Test name
Test status
Simulation time 23907633229 ps
CPU time 1227.79 seconds
Started Jul 05 04:43:28 PM PDT 24
Finished Jul 05 05:03:58 PM PDT 24
Peak memory 290152 kb
Host smart-1d4beea3-3161-4746-842c-c6af1344a3cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368186187 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1368186187
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2478096284
Short name T64
Test name
Test status
Simulation time 42828009002 ps
CPU time 131.58 seconds
Started Jul 05 04:43:31 PM PDT 24
Finished Jul 05 04:45:44 PM PDT 24
Peak memory 256892 kb
Host smart-2523f8e2-632f-4348-ae48-d98de503f08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24780
96284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2478096284
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1805689220
Short name T69
Test name
Test status
Simulation time 899044845 ps
CPU time 36.22 seconds
Started Jul 05 04:43:31 PM PDT 24
Finished Jul 05 04:44:09 PM PDT 24
Peak memory 256860 kb
Host smart-d9d6c810-2a62-4ec8-b8f3-852d832eb383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18056
89220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1805689220
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.954050276
Short name T392
Test name
Test status
Simulation time 41766138362 ps
CPU time 1347.44 seconds
Started Jul 05 04:43:28 PM PDT 24
Finished Jul 05 05:05:57 PM PDT 24
Peak memory 273580 kb
Host smart-9e370ccb-ca96-45fd-8d5c-f77e89a1bd5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954050276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.954050276
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3313991451
Short name T347
Test name
Test status
Simulation time 111945184 ps
CPU time 13.4 seconds
Started Jul 05 04:43:28 PM PDT 24
Finished Jul 05 04:43:43 PM PDT 24
Peak memory 249316 kb
Host smart-95a8a724-9e60-433f-94bf-b700a1a92103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33139
91451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3313991451
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3483952108
Short name T344
Test name
Test status
Simulation time 1476049362 ps
CPU time 30.16 seconds
Started Jul 05 04:43:32 PM PDT 24
Finished Jul 05 04:44:04 PM PDT 24
Peak memory 256560 kb
Host smart-be521804-8828-4c2f-96df-1ce5aaa8bb77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34839
52108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3483952108
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1727731701
Short name T285
Test name
Test status
Simulation time 2919802554 ps
CPU time 38.61 seconds
Started Jul 05 04:43:34 PM PDT 24
Finished Jul 05 04:44:13 PM PDT 24
Peak memory 249400 kb
Host smart-8bb8261d-c42c-4567-b1e8-d99664e171a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17277
31701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1727731701
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1020702625
Short name T394
Test name
Test status
Simulation time 179426640 ps
CPU time 6.62 seconds
Started Jul 05 04:43:28 PM PDT 24
Finished Jul 05 04:43:36 PM PDT 24
Peak memory 249656 kb
Host smart-6ac99fa5-a0cd-4296-ab0c-dce23b3f0239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10207
02625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1020702625
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1480105639
Short name T75
Test name
Test status
Simulation time 170894652123 ps
CPU time 2710.52 seconds
Started Jul 05 04:43:36 PM PDT 24
Finished Jul 05 05:28:47 PM PDT 24
Peak memory 289780 kb
Host smart-3a59dd9d-2df5-4bc4-9f24-9b05e391e0ab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480105639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1480105639
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1181650936
Short name T275
Test name
Test status
Simulation time 95916647208 ps
CPU time 2957.1 seconds
Started Jul 05 04:43:31 PM PDT 24
Finished Jul 05 05:32:51 PM PDT 24
Peak memory 304300 kb
Host smart-bee55417-fb7b-427a-96c8-d478d8e72ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181650936 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1181650936
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1726356999
Short name T203
Test name
Test status
Simulation time 17158663 ps
CPU time 2.76 seconds
Started Jul 05 04:42:54 PM PDT 24
Finished Jul 05 04:42:58 PM PDT 24
Peak memory 249508 kb
Host smart-55e03bb7-4650-4166-a2ad-3d27452e48c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1726356999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1726356999
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2049815063
Short name T479
Test name
Test status
Simulation time 243630198675 ps
CPU time 1809.62 seconds
Started Jul 05 04:42:43 PM PDT 24
Finished Jul 05 05:12:55 PM PDT 24
Peak memory 273144 kb
Host smart-318f7317-1305-4f08-8808-f9ec2f1928cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049815063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2049815063
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3355076567
Short name T414
Test name
Test status
Simulation time 383314764 ps
CPU time 10.47 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 04:43:01 PM PDT 24
Peak memory 249248 kb
Host smart-df6bacde-2e8c-4b59-b58b-f3193cd12523
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3355076567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3355076567
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2220680353
Short name T345
Test name
Test status
Simulation time 2781697818 ps
CPU time 85.35 seconds
Started Jul 05 04:42:45 PM PDT 24
Finished Jul 05 04:44:12 PM PDT 24
Peak memory 257588 kb
Host smart-d2f02340-2e0b-4268-8b0d-2517e0513cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22206
80353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2220680353
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2245127883
Short name T563
Test name
Test status
Simulation time 341219970 ps
CPU time 31.19 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 04:43:22 PM PDT 24
Peak memory 249216 kb
Host smart-a196d86e-243b-4e50-b2f9-38450083ae06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22451
27883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2245127883
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2022007855
Short name T332
Test name
Test status
Simulation time 60682466215 ps
CPU time 3362.27 seconds
Started Jul 05 04:42:47 PM PDT 24
Finished Jul 05 05:38:52 PM PDT 24
Peak memory 290276 kb
Host smart-3afb91d5-1d49-45c7-bce0-f2af44810374
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022007855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2022007855
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3976725029
Short name T172
Test name
Test status
Simulation time 65940017635 ps
CPU time 2075.48 seconds
Started Jul 05 04:42:53 PM PDT 24
Finished Jul 05 05:17:29 PM PDT 24
Peak memory 273816 kb
Host smart-cbbc746c-ed24-4047-a86f-a7fbd98a9e82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976725029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3976725029
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1993451182
Short name T546
Test name
Test status
Simulation time 6794222375 ps
CPU time 146.87 seconds
Started Jul 05 04:42:46 PM PDT 24
Finished Jul 05 04:45:15 PM PDT 24
Peak memory 249380 kb
Host smart-f9d3b864-9089-472f-8a79-5e2b31145575
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993451182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1993451182
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.831212713
Short name T633
Test name
Test status
Simulation time 406973471 ps
CPU time 25.99 seconds
Started Jul 05 04:42:41 PM PDT 24
Finished Jul 05 04:43:10 PM PDT 24
Peak memory 248612 kb
Host smart-96cd2bfa-299d-4016-a5d9-061515a6efbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83121
2713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.831212713
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.850284875
Short name T13
Test name
Test status
Simulation time 587909457 ps
CPU time 25.63 seconds
Started Jul 05 04:42:43 PM PDT 24
Finished Jul 05 04:43:11 PM PDT 24
Peak memory 276672 kb
Host smart-f611019f-1367-42ac-998a-e5128a38571a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=850284875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.850284875
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.4198751405
Short name T447
Test name
Test status
Simulation time 513256569 ps
CPU time 25.39 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 04:43:16 PM PDT 24
Peak memory 249224 kb
Host smart-aa8f4354-84d5-497f-b16a-65ed03ea0610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41987
51405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.4198751405
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3849177053
Short name T367
Test name
Test status
Simulation time 420873727 ps
CPU time 24.94 seconds
Started Jul 05 04:42:50 PM PDT 24
Finished Jul 05 04:43:17 PM PDT 24
Peak memory 256920 kb
Host smart-1575a25d-2a36-4e9f-a96a-01f571b1865c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38491
77053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3849177053
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1980255710
Short name T473
Test name
Test status
Simulation time 54156951387 ps
CPU time 1600.54 seconds
Started Jul 05 04:43:38 PM PDT 24
Finished Jul 05 05:10:20 PM PDT 24
Peak memory 273568 kb
Host smart-961a899e-6c72-4612-8cb2-38460d578afa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980255710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1980255710
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3458123266
Short name T65
Test name
Test status
Simulation time 5984304531 ps
CPU time 138.97 seconds
Started Jul 05 04:43:32 PM PDT 24
Finished Jul 05 04:45:53 PM PDT 24
Peak memory 257048 kb
Host smart-1463a48f-df10-457a-ad5f-72c7e4a27857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34581
23266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3458123266
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1639403178
Short name T663
Test name
Test status
Simulation time 165573351 ps
CPU time 15.26 seconds
Started Jul 05 04:43:36 PM PDT 24
Finished Jul 05 04:43:52 PM PDT 24
Peak memory 248928 kb
Host smart-4a41e3fc-0011-4ffd-9066-85a374e073d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16394
03178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1639403178
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.761048730
Short name T322
Test name
Test status
Simulation time 36518846648 ps
CPU time 2206.06 seconds
Started Jul 05 04:43:32 PM PDT 24
Finished Jul 05 05:20:20 PM PDT 24
Peak memory 289744 kb
Host smart-7cc6f828-31dc-4e28-9c19-e845e6e587ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761048730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.761048730
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.4271406105
Short name T489
Test name
Test status
Simulation time 52986387661 ps
CPU time 1139.76 seconds
Started Jul 05 04:43:30 PM PDT 24
Finished Jul 05 05:02:32 PM PDT 24
Peak memory 290276 kb
Host smart-e6c3b433-3925-4c20-8429-15cfdd31b21e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271406105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.4271406105
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2501670045
Short name T307
Test name
Test status
Simulation time 35904336774 ps
CPU time 379 seconds
Started Jul 05 04:43:35 PM PDT 24
Finished Jul 05 04:49:54 PM PDT 24
Peak memory 256212 kb
Host smart-ccbd5f38-0f03-4a1a-8f91-1976c9031670
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501670045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2501670045
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3183437029
Short name T349
Test name
Test status
Simulation time 1015405141 ps
CPU time 56.7 seconds
Started Jul 05 04:43:31 PM PDT 24
Finished Jul 05 04:44:29 PM PDT 24
Peak memory 256688 kb
Host smart-8cba0e5a-255e-49ec-80bd-62eb5a245044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31834
37029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3183437029
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2616380481
Short name T423
Test name
Test status
Simulation time 701821037 ps
CPU time 46.02 seconds
Started Jul 05 04:43:31 PM PDT 24
Finished Jul 05 04:44:19 PM PDT 24
Peak memory 248724 kb
Host smart-5b5c719d-2542-40fa-a3b5-30d1ebc4ee03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26163
80481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2616380481
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3650631912
Short name T267
Test name
Test status
Simulation time 286984670 ps
CPU time 18.8 seconds
Started Jul 05 04:43:31 PM PDT 24
Finished Jul 05 04:43:52 PM PDT 24
Peak memory 255912 kb
Host smart-3dd41661-0fad-43e6-b11a-14ee54fee48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36506
31912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3650631912
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3052965270
Short name T520
Test name
Test status
Simulation time 1125301295 ps
CPU time 69.14 seconds
Started Jul 05 04:43:32 PM PDT 24
Finished Jul 05 04:44:43 PM PDT 24
Peak memory 257404 kb
Host smart-be6fdee3-1949-4e3c-9410-7d613b21e747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30529
65270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3052965270
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2839120598
Short name T53
Test name
Test status
Simulation time 26696887863 ps
CPU time 1150.41 seconds
Started Jul 05 04:43:35 PM PDT 24
Finished Jul 05 05:02:46 PM PDT 24
Peak memory 289244 kb
Host smart-68dfebae-cf99-4959-b32d-677d8c72bdb6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839120598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2839120598
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3032798157
Short name T404
Test name
Test status
Simulation time 34164270538 ps
CPU time 871.11 seconds
Started Jul 05 04:43:37 PM PDT 24
Finished Jul 05 04:58:09 PM PDT 24
Peak memory 273952 kb
Host smart-2ac43d20-50c1-403b-a5c4-d0ce61eb9035
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032798157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3032798157
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.4051568483
Short name T350
Test name
Test status
Simulation time 14651067136 ps
CPU time 195.56 seconds
Started Jul 05 04:43:39 PM PDT 24
Finished Jul 05 04:46:55 PM PDT 24
Peak memory 257112 kb
Host smart-f87b6765-6849-40d9-8ee8-d92a56d16f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40515
68483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4051568483
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2267557707
Short name T214
Test name
Test status
Simulation time 2598336678 ps
CPU time 20.29 seconds
Started Jul 05 04:43:36 PM PDT 24
Finished Jul 05 04:43:57 PM PDT 24
Peak memory 249324 kb
Host smart-b4eb01d6-7e79-4891-9d05-09b338a9a6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22675
57707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2267557707
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2389603681
Short name T555
Test name
Test status
Simulation time 30015656116 ps
CPU time 910.19 seconds
Started Jul 05 04:43:35 PM PDT 24
Finished Jul 05 04:58:46 PM PDT 24
Peak memory 273916 kb
Host smart-e9e8f88b-89df-471a-aaff-e295bdd0205b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389603681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2389603681
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.173575543
Short name T614
Test name
Test status
Simulation time 38493521606 ps
CPU time 1348.06 seconds
Started Jul 05 04:43:34 PM PDT 24
Finished Jul 05 05:06:03 PM PDT 24
Peak memory 290096 kb
Host smart-c1368fa9-48a5-486e-a572-328af990d55e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173575543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.173575543
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1600313175
Short name T657
Test name
Test status
Simulation time 8310908955 ps
CPU time 342.59 seconds
Started Jul 05 04:43:36 PM PDT 24
Finished Jul 05 04:49:19 PM PDT 24
Peak memory 249220 kb
Host smart-fc69f031-25e0-404e-9de5-4cc5020848a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600313175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1600313175
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2904753267
Short name T600
Test name
Test status
Simulation time 296030434 ps
CPU time 15.96 seconds
Started Jul 05 04:43:37 PM PDT 24
Finished Jul 05 04:43:54 PM PDT 24
Peak memory 256716 kb
Host smart-0b78a0f8-f17e-49a8-ab24-e16776105840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29047
53267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2904753267
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2584889060
Short name T261
Test name
Test status
Simulation time 228778417 ps
CPU time 13.27 seconds
Started Jul 05 04:43:32 PM PDT 24
Finished Jul 05 04:43:47 PM PDT 24
Peak memory 248652 kb
Host smart-ceaeec96-968f-40c9-9291-32c2349a64af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25848
89060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2584889060
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.129937636
Short name T474
Test name
Test status
Simulation time 639934591 ps
CPU time 12.13 seconds
Started Jul 05 04:43:42 PM PDT 24
Finished Jul 05 04:43:56 PM PDT 24
Peak memory 249624 kb
Host smart-ca5e6c67-fa62-4c3d-997b-01df1f9aa922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12993
7636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.129937636
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3350714560
Short name T636
Test name
Test status
Simulation time 3812891788 ps
CPU time 35.82 seconds
Started Jul 05 04:43:37 PM PDT 24
Finished Jul 05 04:44:13 PM PDT 24
Peak memory 257584 kb
Host smart-4c6f9a9a-c186-4acf-8db5-e2f3db5ef857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33507
14560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3350714560
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2025653299
Short name T660
Test name
Test status
Simulation time 13801110715 ps
CPU time 1230.83 seconds
Started Jul 05 04:43:31 PM PDT 24
Finished Jul 05 05:04:04 PM PDT 24
Peak memory 287528 kb
Host smart-4b534c61-9814-4065-b3ad-e515bfe9e59c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025653299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2025653299
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.4059577227
Short name T515
Test name
Test status
Simulation time 133476026394 ps
CPU time 3561.87 seconds
Started Jul 05 04:43:34 PM PDT 24
Finished Jul 05 05:42:57 PM PDT 24
Peak memory 305968 kb
Host smart-446735c6-70e3-4a2a-8908-919e6d714118
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059577227 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.4059577227
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1460124243
Short name T701
Test name
Test status
Simulation time 24531448744 ps
CPU time 1565.32 seconds
Started Jul 05 04:43:30 PM PDT 24
Finished Jul 05 05:09:37 PM PDT 24
Peak memory 282960 kb
Host smart-a93e4956-4aba-4619-96a7-20f430df7a3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460124243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1460124243
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.835424944
Short name T437
Test name
Test status
Simulation time 32262386269 ps
CPU time 236.98 seconds
Started Jul 05 04:43:33 PM PDT 24
Finished Jul 05 04:47:31 PM PDT 24
Peak memory 257540 kb
Host smart-25d39608-15cc-470c-abbb-e17459077516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83542
4944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.835424944
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1276601454
Short name T604
Test name
Test status
Simulation time 1296560683 ps
CPU time 36.07 seconds
Started Jul 05 04:43:39 PM PDT 24
Finished Jul 05 04:44:16 PM PDT 24
Peak memory 249232 kb
Host smart-bbb9f788-abfd-42bf-a2b4-807f54446ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12766
01454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1276601454
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3184949626
Short name T677
Test name
Test status
Simulation time 15575964015 ps
CPU time 1222.11 seconds
Started Jul 05 04:43:39 PM PDT 24
Finished Jul 05 05:04:02 PM PDT 24
Peak memory 282524 kb
Host smart-cff8b4e3-ee0a-4a4a-80ac-1da295fc3001
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184949626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3184949626
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1924315371
Short name T544
Test name
Test status
Simulation time 76533544441 ps
CPU time 1161.5 seconds
Started Jul 05 04:43:39 PM PDT 24
Finished Jul 05 05:03:02 PM PDT 24
Peak memory 288076 kb
Host smart-6a4b8b7e-c15a-4170-810d-d2bcfeed2279
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924315371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1924315371
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2997353185
Short name T306
Test name
Test status
Simulation time 34305746345 ps
CPU time 365.1 seconds
Started Jul 05 04:43:35 PM PDT 24
Finished Jul 05 04:49:41 PM PDT 24
Peak memory 248160 kb
Host smart-4fbdfe29-27e7-4772-97d3-9d77e5a37eb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997353185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2997353185
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1309335254
Short name T593
Test name
Test status
Simulation time 1207560099 ps
CPU time 20.82 seconds
Started Jul 05 04:43:37 PM PDT 24
Finished Jul 05 04:43:58 PM PDT 24
Peak memory 249272 kb
Host smart-d57d29cd-9392-43b9-bab9-ddcd6480ffe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13093
35254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1309335254
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2045727930
Short name T76
Test name
Test status
Simulation time 372957895 ps
CPU time 21.89 seconds
Started Jul 05 04:43:39 PM PDT 24
Finished Jul 05 04:44:02 PM PDT 24
Peak memory 256048 kb
Host smart-21ac3b1c-9cc8-44a5-a9c6-5513f5c5c70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20457
27930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2045727930
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3361173484
Short name T268
Test name
Test status
Simulation time 655321501 ps
CPU time 42.24 seconds
Started Jul 05 04:43:36 PM PDT 24
Finished Jul 05 04:44:19 PM PDT 24
Peak memory 257196 kb
Host smart-91f4f3c3-3a76-43eb-8000-bb0d10a80dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33611
73484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3361173484
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1816937099
Short name T429
Test name
Test status
Simulation time 124856187 ps
CPU time 8.37 seconds
Started Jul 05 04:43:38 PM PDT 24
Finished Jul 05 04:43:47 PM PDT 24
Peak memory 252280 kb
Host smart-6cd46cf3-58b2-410d-a9ea-b03b383706cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18169
37099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1816937099
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3563033188
Short name T89
Test name
Test status
Simulation time 143702179776 ps
CPU time 2060.34 seconds
Started Jul 05 04:43:36 PM PDT 24
Finished Jul 05 05:17:57 PM PDT 24
Peak memory 288088 kb
Host smart-1c13d970-7db2-47df-8126-3184c14dc01a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563033188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3563033188
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.807714990
Short name T634
Test name
Test status
Simulation time 11191060276 ps
CPU time 154.64 seconds
Started Jul 05 04:43:39 PM PDT 24
Finished Jul 05 04:46:15 PM PDT 24
Peak memory 257500 kb
Host smart-2d896a32-b142-43e5-9a0d-245c8be95f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80771
4990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.807714990
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2428677883
Short name T548
Test name
Test status
Simulation time 1727327646 ps
CPU time 48.97 seconds
Started Jul 05 04:43:45 PM PDT 24
Finished Jul 05 04:44:35 PM PDT 24
Peak memory 249212 kb
Host smart-5d3bd903-956a-4958-a868-a1a86aa79cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24286
77883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2428677883
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.874402327
Short name T585
Test name
Test status
Simulation time 24880588258 ps
CPU time 577.92 seconds
Started Jul 05 04:43:36 PM PDT 24
Finished Jul 05 04:53:14 PM PDT 24
Peak memory 268800 kb
Host smart-ad96d922-35e2-4470-bf1f-dfe771f3a7a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874402327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.874402327
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2691981721
Short name T10
Test name
Test status
Simulation time 13944927277 ps
CPU time 322.52 seconds
Started Jul 05 04:43:45 PM PDT 24
Finished Jul 05 04:49:09 PM PDT 24
Peak memory 248232 kb
Host smart-7bf57f75-4b72-4962-901f-ad6b91f41f19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691981721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2691981721
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2980653039
Short name T434
Test name
Test status
Simulation time 445747651 ps
CPU time 35.78 seconds
Started Jul 05 04:43:45 PM PDT 24
Finished Jul 05 04:44:22 PM PDT 24
Peak memory 256792 kb
Host smart-b1435c6d-110b-475d-8aff-d77e74588fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29806
53039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2980653039
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2475392430
Short name T608
Test name
Test status
Simulation time 37097061 ps
CPU time 3.23 seconds
Started Jul 05 04:43:40 PM PDT 24
Finished Jul 05 04:43:44 PM PDT 24
Peak memory 240344 kb
Host smart-ba774322-e813-46e4-bd47-9c6902b8fd23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24753
92430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2475392430
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3319378379
Short name T499
Test name
Test status
Simulation time 237336287 ps
CPU time 35.42 seconds
Started Jul 05 04:43:46 PM PDT 24
Finished Jul 05 04:44:22 PM PDT 24
Peak memory 256960 kb
Host smart-d50f79c5-2c32-4ff2-88f0-b7dfd4224cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33193
78379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3319378379
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2296892981
Short name T694
Test name
Test status
Simulation time 2675705861 ps
CPU time 14.7 seconds
Started Jul 05 04:43:42 PM PDT 24
Finished Jul 05 04:43:58 PM PDT 24
Peak memory 257500 kb
Host smart-9e7902a9-9bde-460c-bcdd-9dc9a418e165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22968
92981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2296892981
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2955051045
Short name T432
Test name
Test status
Simulation time 69789788483 ps
CPU time 1225.66 seconds
Started Jul 05 04:43:41 PM PDT 24
Finished Jul 05 05:04:08 PM PDT 24
Peak memory 289364 kb
Host smart-c34a327d-b920-4f2f-9988-0d1e80bf2532
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955051045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2955051045
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.355759076
Short name T228
Test name
Test status
Simulation time 113915600736 ps
CPU time 1370.56 seconds
Started Jul 05 04:43:39 PM PDT 24
Finished Jul 05 05:06:32 PM PDT 24
Peak memory 284892 kb
Host smart-2b170779-42ef-4b50-8610-c44f88e9a657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355759076 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.355759076
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3901396931
Short name T366
Test name
Test status
Simulation time 12559190689 ps
CPU time 1539.73 seconds
Started Jul 05 04:43:45 PM PDT 24
Finished Jul 05 05:09:26 PM PDT 24
Peak memory 289696 kb
Host smart-b2a9e88c-adb6-49c9-b0d6-d334d0640cd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901396931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3901396931
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.16796504
Short name T661
Test name
Test status
Simulation time 981599473 ps
CPU time 58.54 seconds
Started Jul 05 04:43:43 PM PDT 24
Finished Jul 05 04:44:42 PM PDT 24
Peak memory 256960 kb
Host smart-290585ed-83ac-444e-bc9b-84884b900d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16796
504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.16796504
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3468758343
Short name T496
Test name
Test status
Simulation time 1238612437 ps
CPU time 42.29 seconds
Started Jul 05 04:43:41 PM PDT 24
Finished Jul 05 04:44:25 PM PDT 24
Peak memory 248960 kb
Host smart-f0b6bf2d-2d60-4699-bf76-e85cf0dbf6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34687
58343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3468758343
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1283194527
Short name T571
Test name
Test status
Simulation time 19855591492 ps
CPU time 727.11 seconds
Started Jul 05 04:43:48 PM PDT 24
Finished Jul 05 04:55:55 PM PDT 24
Peak memory 273768 kb
Host smart-d36b3e36-fe50-42b5-a53f-88c9f7bd449b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283194527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1283194527
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2140281299
Short name T488
Test name
Test status
Simulation time 144296727296 ps
CPU time 1607.35 seconds
Started Jul 05 04:43:46 PM PDT 24
Finished Jul 05 05:10:34 PM PDT 24
Peak memory 273808 kb
Host smart-5deb0cdc-be04-4189-ba2f-621ba653fce3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140281299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2140281299
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.461896381
Short name T296
Test name
Test status
Simulation time 34095155479 ps
CPU time 391.55 seconds
Started Jul 05 04:43:47 PM PDT 24
Finished Jul 05 04:50:19 PM PDT 24
Peak memory 249324 kb
Host smart-3b9b5297-76c2-4c60-ac72-7cc2eafa36f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461896381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.461896381
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1420056685
Short name T173
Test name
Test status
Simulation time 65129832 ps
CPU time 4.95 seconds
Started Jul 05 04:43:45 PM PDT 24
Finished Jul 05 04:43:51 PM PDT 24
Peak memory 249256 kb
Host smart-3fb1fd7c-3598-4ec6-9143-7ec310e65c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14200
56685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1420056685
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.715395153
Short name T405
Test name
Test status
Simulation time 3443214151 ps
CPU time 54.68 seconds
Started Jul 05 04:43:41 PM PDT 24
Finished Jul 05 04:44:37 PM PDT 24
Peak memory 249024 kb
Host smart-5ca12c6c-6e5e-4333-9e36-7ee582c24d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71539
5153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.715395153
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2125163595
Short name T80
Test name
Test status
Simulation time 687340670 ps
CPU time 53.61 seconds
Started Jul 05 04:43:41 PM PDT 24
Finished Jul 05 04:44:37 PM PDT 24
Peak memory 256524 kb
Host smart-0c5f5005-74b6-4229-a987-79682c67ebc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21251
63595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2125163595
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.435191755
Short name T364
Test name
Test status
Simulation time 400284291 ps
CPU time 20.13 seconds
Started Jul 05 04:43:38 PM PDT 24
Finished Jul 05 04:43:59 PM PDT 24
Peak memory 257440 kb
Host smart-c9d958c8-39c7-41ee-9b12-4b23f1bda99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43519
1755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.435191755
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1448520658
Short name T471
Test name
Test status
Simulation time 159709526067 ps
CPU time 2043.15 seconds
Started Jul 05 04:43:45 PM PDT 24
Finished Jul 05 05:17:49 PM PDT 24
Peak memory 305912 kb
Host smart-f07f8451-850e-4d00-a4ba-834064cc99b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448520658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1448520658
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2138067192
Short name T30
Test name
Test status
Simulation time 32570855072 ps
CPU time 1389.54 seconds
Started Jul 05 04:43:46 PM PDT 24
Finished Jul 05 05:06:56 PM PDT 24
Peak memory 289224 kb
Host smart-0383236a-45ac-4e55-9e07-0faca5da041b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138067192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2138067192
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2181271017
Short name T553
Test name
Test status
Simulation time 14327300403 ps
CPU time 191.67 seconds
Started Jul 05 04:43:46 PM PDT 24
Finished Jul 05 04:46:59 PM PDT 24
Peak memory 257248 kb
Host smart-cd5c7ceb-42fc-4e14-88ee-e7fa57684832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21812
71017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2181271017
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3507823514
Short name T673
Test name
Test status
Simulation time 344394057 ps
CPU time 24.38 seconds
Started Jul 05 04:43:45 PM PDT 24
Finished Jul 05 04:44:10 PM PDT 24
Peak memory 248832 kb
Host smart-fd47fb47-2ac7-40ab-afa3-9ad8e0640a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35078
23514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3507823514
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2464026910
Short name T288
Test name
Test status
Simulation time 29051942764 ps
CPU time 1317.5 seconds
Started Jul 05 04:43:44 PM PDT 24
Finished Jul 05 05:05:42 PM PDT 24
Peak memory 282108 kb
Host smart-f2dc0637-2124-48b1-9f70-211c8aa000b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464026910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2464026910
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3213991198
Short name T582
Test name
Test status
Simulation time 18477738177 ps
CPU time 1454.7 seconds
Started Jul 05 04:43:47 PM PDT 24
Finished Jul 05 05:08:02 PM PDT 24
Peak memory 289656 kb
Host smart-4acfa711-1182-4277-8909-dc2cd183adce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213991198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3213991198
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1332336997
Short name T545
Test name
Test status
Simulation time 8841935105 ps
CPU time 391.85 seconds
Started Jul 05 04:43:45 PM PDT 24
Finished Jul 05 04:50:18 PM PDT 24
Peak memory 249248 kb
Host smart-2b7429a1-b770-461e-8f4a-489c2fe379d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332336997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1332336997
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.970813769
Short name T175
Test name
Test status
Simulation time 9245803301 ps
CPU time 41.98 seconds
Started Jul 05 04:43:48 PM PDT 24
Finished Jul 05 04:44:31 PM PDT 24
Peak memory 257020 kb
Host smart-c718c76d-b736-4715-b73f-c7f7611fd2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97081
3769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.970813769
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1290075905
Short name T498
Test name
Test status
Simulation time 250767624 ps
CPU time 25.79 seconds
Started Jul 05 04:43:45 PM PDT 24
Finished Jul 05 04:44:12 PM PDT 24
Peak memory 248636 kb
Host smart-1b7a6d1b-96c7-4ff8-8d27-5d6dd99b0f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12900
75905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1290075905
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.156137120
Short name T431
Test name
Test status
Simulation time 408340529 ps
CPU time 14.79 seconds
Started Jul 05 04:43:46 PM PDT 24
Finished Jul 05 04:44:02 PM PDT 24
Peak memory 249228 kb
Host smart-622356db-70cc-46c0-ba67-c18d42adaa16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15613
7120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.156137120
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2823932097
Short name T403
Test name
Test status
Simulation time 5463357773 ps
CPU time 41.58 seconds
Started Jul 05 04:43:49 PM PDT 24
Finished Jul 05 04:44:31 PM PDT 24
Peak memory 257584 kb
Host smart-92e84839-ed15-4cd5-ac5f-b73b6d79b795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28239
32097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2823932097
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1737256661
Short name T56
Test name
Test status
Simulation time 26229433617 ps
CPU time 1265.41 seconds
Started Jul 05 04:43:46 PM PDT 24
Finished Jul 05 05:04:52 PM PDT 24
Peak memory 289572 kb
Host smart-a0d23f18-32e3-4e9e-94f8-5e377b3f524d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737256661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1737256661
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.4223504795
Short name T171
Test name
Test status
Simulation time 22463561099 ps
CPU time 2042.15 seconds
Started Jul 05 04:43:55 PM PDT 24
Finished Jul 05 05:17:58 PM PDT 24
Peak memory 306624 kb
Host smart-5863a44b-a49c-4cba-a3d4-7f58fe690812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223504795 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.4223504795
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3181481987
Short name T494
Test name
Test status
Simulation time 13350385512 ps
CPU time 852.43 seconds
Started Jul 05 04:43:54 PM PDT 24
Finished Jul 05 04:58:07 PM PDT 24
Peak memory 272988 kb
Host smart-d9e4f272-a5b1-419c-b63b-4336c2fb0447
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181481987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3181481987
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2508785279
Short name T670
Test name
Test status
Simulation time 8508448101 ps
CPU time 181.31 seconds
Started Jul 05 04:43:52 PM PDT 24
Finished Jul 05 04:46:55 PM PDT 24
Peak memory 257604 kb
Host smart-118ade1f-38e2-4858-a32a-3427186d6736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25087
85279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2508785279
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.4136593613
Short name T411
Test name
Test status
Simulation time 305711316 ps
CPU time 19.37 seconds
Started Jul 05 04:43:54 PM PDT 24
Finished Jul 05 04:44:14 PM PDT 24
Peak memory 248620 kb
Host smart-874b6281-44fe-47b6-957d-bcc0c85634a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41365
93613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.4136593613
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3055668048
Short name T682
Test name
Test status
Simulation time 26102966959 ps
CPU time 843.34 seconds
Started Jul 05 04:43:55 PM PDT 24
Finished Jul 05 04:57:59 PM PDT 24
Peak memory 273284 kb
Host smart-443cde72-f490-40db-8858-07f0f3d0fae7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055668048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3055668048
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1983688800
Short name T566
Test name
Test status
Simulation time 209412567813 ps
CPU time 2607.52 seconds
Started Jul 05 04:43:53 PM PDT 24
Finished Jul 05 05:27:22 PM PDT 24
Peak memory 284048 kb
Host smart-2575ae0b-f7e0-4df3-bb1e-ab71d70a98b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983688800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1983688800
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.843249838
Short name T298
Test name
Test status
Simulation time 34371761572 ps
CPU time 426.02 seconds
Started Jul 05 04:43:52 PM PDT 24
Finished Jul 05 04:50:59 PM PDT 24
Peak memory 248236 kb
Host smart-de13d9f3-4bec-4a26-8675-46b570a79667
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843249838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.843249838
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.359968793
Short name T241
Test name
Test status
Simulation time 628039311 ps
CPU time 25.35 seconds
Started Jul 05 04:43:55 PM PDT 24
Finished Jul 05 04:44:22 PM PDT 24
Peak memory 249228 kb
Host smart-0b1b6606-bbf1-4f17-aa32-2bb751c720b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35996
8793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.359968793
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2705406725
Short name T692
Test name
Test status
Simulation time 107788959 ps
CPU time 7.86 seconds
Started Jul 05 04:43:53 PM PDT 24
Finished Jul 05 04:44:02 PM PDT 24
Peak memory 251960 kb
Host smart-7b6ed31e-2a03-435c-970c-c416adbd817d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27054
06725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2705406725
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1222145040
Short name T273
Test name
Test status
Simulation time 592876791 ps
CPU time 36.42 seconds
Started Jul 05 04:43:53 PM PDT 24
Finished Jul 05 04:44:30 PM PDT 24
Peak memory 248636 kb
Host smart-3090f788-4090-432a-aa19-6fb4d6466d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12221
45040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1222145040
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.618980029
Short name T386
Test name
Test status
Simulation time 1043976195 ps
CPU time 25.59 seconds
Started Jul 05 04:43:55 PM PDT 24
Finished Jul 05 04:44:22 PM PDT 24
Peak memory 256400 kb
Host smart-64340c98-1c50-48b2-90a9-4c3a3269ada6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61898
0029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.618980029
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2847993751
Short name T549
Test name
Test status
Simulation time 159631379437 ps
CPU time 2531.56 seconds
Started Jul 05 04:43:54 PM PDT 24
Finished Jul 05 05:26:06 PM PDT 24
Peak memory 289980 kb
Host smart-b767c7be-3cb2-4e4d-812e-e2378448a425
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847993751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2847993751
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1215351686
Short name T246
Test name
Test status
Simulation time 27854911812 ps
CPU time 1833.27 seconds
Started Jul 05 04:43:54 PM PDT 24
Finished Jul 05 05:14:28 PM PDT 24
Peak memory 269364 kb
Host smart-ed80f09b-4426-45cd-9afe-5bf1e5e1afbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215351686 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1215351686
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.215688146
Short name T472
Test name
Test status
Simulation time 14084417486 ps
CPU time 1219.33 seconds
Started Jul 05 04:43:55 PM PDT 24
Finished Jul 05 05:04:15 PM PDT 24
Peak memory 285388 kb
Host smart-f40cdf57-e786-43c5-9d6a-4f95ba4f7027
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215688146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.215688146
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3581422079
Short name T421
Test name
Test status
Simulation time 1568787212 ps
CPU time 33.84 seconds
Started Jul 05 04:43:56 PM PDT 24
Finished Jul 05 04:44:30 PM PDT 24
Peak memory 256684 kb
Host smart-966eb218-4870-4676-871b-08e330aacfbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35814
22079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3581422079
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1277478176
Short name T378
Test name
Test status
Simulation time 1493800630 ps
CPU time 50.86 seconds
Started Jul 05 04:43:52 PM PDT 24
Finished Jul 05 04:44:44 PM PDT 24
Peak memory 249116 kb
Host smart-e120a6b1-0803-4ce7-aa4c-2358441c3d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12774
78176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1277478176
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2289094095
Short name T329
Test name
Test status
Simulation time 226216076745 ps
CPU time 3110.82 seconds
Started Jul 05 04:43:54 PM PDT 24
Finished Jul 05 05:35:46 PM PDT 24
Peak memory 289660 kb
Host smart-f4b8d03f-49ea-4368-8aff-58a7b62d076b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289094095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2289094095
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.349351982
Short name T518
Test name
Test status
Simulation time 69897356014 ps
CPU time 1733.77 seconds
Started Jul 05 04:43:54 PM PDT 24
Finished Jul 05 05:12:49 PM PDT 24
Peak memory 289636 kb
Host smart-c0711fb1-2ea0-4473-97c8-1cf1357c37c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349351982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.349351982
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1332871156
Short name T384
Test name
Test status
Simulation time 3542317146 ps
CPU time 141.72 seconds
Started Jul 05 04:43:56 PM PDT 24
Finished Jul 05 04:46:18 PM PDT 24
Peak memory 249020 kb
Host smart-c4808f2e-e528-4d1b-9e71-0fe82e951f41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332871156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1332871156
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.571643459
Short name T382
Test name
Test status
Simulation time 592192432 ps
CPU time 19.79 seconds
Started Jul 05 04:43:52 PM PDT 24
Finished Jul 05 04:44:13 PM PDT 24
Peak memory 256604 kb
Host smart-3d5a4efa-1684-459b-8138-bf6013a1cf1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57164
3459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.571643459
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.4011043024
Short name T526
Test name
Test status
Simulation time 673167117 ps
CPU time 37.65 seconds
Started Jul 05 04:43:54 PM PDT 24
Finished Jul 05 04:44:33 PM PDT 24
Peak memory 257476 kb
Host smart-7eca99be-ca04-4cbb-9b51-5c9c0d4c234c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40110
43024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.4011043024
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.534549203
Short name T290
Test name
Test status
Simulation time 2394431568 ps
CPU time 41.31 seconds
Started Jul 05 04:43:55 PM PDT 24
Finished Jul 05 04:44:37 PM PDT 24
Peak memory 257476 kb
Host smart-041c502c-05df-44a9-8fb0-968cd7ab26b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53454
9203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.534549203
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1423051367
Short name T365
Test name
Test status
Simulation time 2311832056 ps
CPU time 32.88 seconds
Started Jul 05 04:43:55 PM PDT 24
Finished Jul 05 04:44:29 PM PDT 24
Peak memory 257100 kb
Host smart-858335f9-fc52-48ca-a7a7-71b22682ff9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14230
51367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1423051367
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.870190869
Short name T395
Test name
Test status
Simulation time 14980786617 ps
CPU time 1757.07 seconds
Started Jul 05 04:44:01 PM PDT 24
Finished Jul 05 05:13:20 PM PDT 24
Peak memory 298064 kb
Host smart-5b93c4c7-4c9c-4ca3-9669-a816969d8afa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870190869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.870190869
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.4016628780
Short name T263
Test name
Test status
Simulation time 255044205019 ps
CPU time 3081.97 seconds
Started Jul 05 04:44:04 PM PDT 24
Finished Jul 05 05:35:27 PM PDT 24
Peak memory 305816 kb
Host smart-0155e033-8fc2-4f0e-9139-c36b426178a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016628780 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.4016628780
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1095965534
Short name T452
Test name
Test status
Simulation time 39724986389 ps
CPU time 1285.71 seconds
Started Jul 05 04:44:02 PM PDT 24
Finished Jul 05 05:05:29 PM PDT 24
Peak memory 289112 kb
Host smart-d6a0303d-81a6-4fcd-901f-8dc3c2b235fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095965534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1095965534
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.4074703762
Short name T449
Test name
Test status
Simulation time 627189639 ps
CPU time 35.12 seconds
Started Jul 05 04:44:01 PM PDT 24
Finished Jul 05 04:44:38 PM PDT 24
Peak memory 256548 kb
Host smart-9a4b7a2e-0f24-4d38-82c3-74bb90ed1e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40747
03762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.4074703762
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.102476605
Short name T438
Test name
Test status
Simulation time 253375656 ps
CPU time 15.7 seconds
Started Jul 05 04:44:01 PM PDT 24
Finished Jul 05 04:44:18 PM PDT 24
Peak memory 249744 kb
Host smart-dcc1dbc6-2df2-4394-bd82-231f25c07214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10247
6605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.102476605
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1300719219
Short name T324
Test name
Test status
Simulation time 65112401816 ps
CPU time 2170.63 seconds
Started Jul 05 04:44:01 PM PDT 24
Finished Jul 05 05:20:12 PM PDT 24
Peak memory 283148 kb
Host smart-eadaf049-2524-437e-ab49-9a1ef29bb83d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300719219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1300719219
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2260644859
Short name T252
Test name
Test status
Simulation time 170266479801 ps
CPU time 1727.41 seconds
Started Jul 05 04:44:00 PM PDT 24
Finished Jul 05 05:12:49 PM PDT 24
Peak memory 273744 kb
Host smart-bb429907-df3a-43c0-9d38-43b3b758701f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260644859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2260644859
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1059937441
Short name T618
Test name
Test status
Simulation time 245962194 ps
CPU time 5.36 seconds
Started Jul 05 04:44:00 PM PDT 24
Finished Jul 05 04:44:07 PM PDT 24
Peak memory 249272 kb
Host smart-8d8b22f3-ba83-43b9-89b7-30d4cd341747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10599
37441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1059937441
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3299433451
Short name T235
Test name
Test status
Simulation time 294976326 ps
CPU time 26.89 seconds
Started Jul 05 04:44:02 PM PDT 24
Finished Jul 05 04:44:30 PM PDT 24
Peak memory 256560 kb
Host smart-4ed40d1a-e120-438c-bf84-ba53bc9aa950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32994
33451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3299433451
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3056321259
Short name T233
Test name
Test status
Simulation time 765100815 ps
CPU time 33.11 seconds
Started Jul 05 04:44:00 PM PDT 24
Finished Jul 05 04:44:34 PM PDT 24
Peak memory 248720 kb
Host smart-224fe7b7-9ea6-4cdc-86a0-60176ed24213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30563
21259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3056321259
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.4139082474
Short name T370
Test name
Test status
Simulation time 2363885722 ps
CPU time 36.13 seconds
Started Jul 05 04:44:01 PM PDT 24
Finished Jul 05 04:44:39 PM PDT 24
Peak memory 257132 kb
Host smart-bd2241cc-a2df-404f-8921-c4d3ec454402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41390
82474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.4139082474
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.744443244
Short name T381
Test name
Test status
Simulation time 13799027961 ps
CPU time 1238.95 seconds
Started Jul 05 04:44:00 PM PDT 24
Finished Jul 05 05:04:40 PM PDT 24
Peak memory 288172 kb
Host smart-35ab0df7-8e89-4b56-8155-ab29f12b3051
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744443244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.744443244
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3510965344
Short name T583
Test name
Test status
Simulation time 50350766509 ps
CPU time 1570.9 seconds
Started Jul 05 04:44:08 PM PDT 24
Finished Jul 05 05:10:19 PM PDT 24
Peak memory 267700 kb
Host smart-6fc04cc1-fa47-418a-8eb1-10ea3b39ceab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510965344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3510965344
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2785719342
Short name T417
Test name
Test status
Simulation time 4876300657 ps
CPU time 268.78 seconds
Started Jul 05 04:44:18 PM PDT 24
Finished Jul 05 04:48:49 PM PDT 24
Peak memory 257520 kb
Host smart-ae290916-3e74-4437-b3db-eb7582b40278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27857
19342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2785719342
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3162213399
Short name T568
Test name
Test status
Simulation time 830455021 ps
CPU time 32.52 seconds
Started Jul 05 04:44:01 PM PDT 24
Finished Jul 05 04:44:35 PM PDT 24
Peak memory 257480 kb
Host smart-bfd73462-abcd-489f-b413-650fc2da4de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31622
13399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3162213399
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.636201730
Short name T328
Test name
Test status
Simulation time 74552644417 ps
CPU time 2098.96 seconds
Started Jul 05 04:44:10 PM PDT 24
Finished Jul 05 05:19:09 PM PDT 24
Peak memory 273440 kb
Host smart-53502390-ac86-40f1-b94b-cdf5bd4eec24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636201730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.636201730
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.4259015003
Short name T632
Test name
Test status
Simulation time 16891918840 ps
CPU time 1073.36 seconds
Started Jul 05 04:44:10 PM PDT 24
Finished Jul 05 05:02:04 PM PDT 24
Peak memory 273908 kb
Host smart-34fa1641-66b3-4f69-99c7-44e2092bcceb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259015003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.4259015003
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2497949653
Short name T309
Test name
Test status
Simulation time 10872512387 ps
CPU time 149.23 seconds
Started Jul 05 04:44:09 PM PDT 24
Finished Jul 05 04:46:39 PM PDT 24
Peak memory 255320 kb
Host smart-62570bcb-fbb5-46e3-bc66-0d4525474a76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497949653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2497949653
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.937152396
Short name T190
Test name
Test status
Simulation time 738044422 ps
CPU time 45.51 seconds
Started Jul 05 04:44:00 PM PDT 24
Finished Jul 05 04:44:47 PM PDT 24
Peak memory 256732 kb
Host smart-e3ae80ec-e86d-49d1-be9f-288e037a70c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93715
2396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.937152396
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2359179784
Short name T456
Test name
Test status
Simulation time 1084068155 ps
CPU time 23.4 seconds
Started Jul 05 04:43:59 PM PDT 24
Finished Jul 05 04:44:24 PM PDT 24
Peak memory 248684 kb
Host smart-80246c16-5fb5-4e0f-81da-591aae64a58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23591
79784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2359179784
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2630448939
Short name T43
Test name
Test status
Simulation time 265964510 ps
CPU time 29.2 seconds
Started Jul 05 04:44:16 PM PDT 24
Finished Jul 05 04:44:47 PM PDT 24
Peak memory 249220 kb
Host smart-10169612-0916-405c-928a-549764bf645f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26304
48939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2630448939
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.98675476
Short name T187
Test name
Test status
Simulation time 1895639175 ps
CPU time 53.53 seconds
Started Jul 05 04:44:04 PM PDT 24
Finished Jul 05 04:44:58 PM PDT 24
Peak memory 249292 kb
Host smart-9843f3e3-d7c2-4d8d-96b6-8549bae9d9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98675
476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.98675476
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1890809500
Short name T258
Test name
Test status
Simulation time 52059608040 ps
CPU time 1134.32 seconds
Started Jul 05 04:44:10 PM PDT 24
Finished Jul 05 05:03:05 PM PDT 24
Peak memory 274020 kb
Host smart-5d1eae37-5837-4861-981c-7f30c162f398
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890809500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1890809500
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3328348222
Short name T194
Test name
Test status
Simulation time 93392312 ps
CPU time 2.88 seconds
Started Jul 05 04:42:40 PM PDT 24
Finished Jul 05 04:42:46 PM PDT 24
Peak memory 249524 kb
Host smart-a1313ab9-6525-4f9a-bce0-61e19d26174f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3328348222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3328348222
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.4159849980
Short name T513
Test name
Test status
Simulation time 49905239942 ps
CPU time 1470.73 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 05:07:22 PM PDT 24
Peak memory 273548 kb
Host smart-64ec0f7e-d3f8-4e6f-bc0f-b83b431b4784
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159849980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.4159849980
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.345321680
Short name T480
Test name
Test status
Simulation time 5737927855 ps
CPU time 24.36 seconds
Started Jul 05 04:42:47 PM PDT 24
Finished Jul 05 04:43:14 PM PDT 24
Peak memory 249192 kb
Host smart-1f5aa837-69f1-49dc-8a9f-a50ba0408ea6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=345321680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.345321680
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3610951308
Short name T659
Test name
Test status
Simulation time 1665791758 ps
CPU time 101.41 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 04:44:32 PM PDT 24
Peak memory 257480 kb
Host smart-87c3e248-7118-4ceb-9426-3661324684bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109
51308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3610951308
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3944463892
Short name T82
Test name
Test status
Simulation time 194645998 ps
CPU time 12.76 seconds
Started Jul 05 04:42:47 PM PDT 24
Finished Jul 05 04:43:02 PM PDT 24
Peak memory 249304 kb
Host smart-c2e1355d-deb9-486d-a945-c9f4d279624c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39444
63892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3944463892
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.4190913905
Short name T626
Test name
Test status
Simulation time 186935671814 ps
CPU time 2715.41 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 05:28:06 PM PDT 24
Peak memory 289328 kb
Host smart-fc4f94ba-e73f-4cc1-914c-a68f262e3284
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190913905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.4190913905
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3295112762
Short name T385
Test name
Test status
Simulation time 165429194466 ps
CPU time 2772.73 seconds
Started Jul 05 04:42:45 PM PDT 24
Finished Jul 05 05:29:00 PM PDT 24
Peak memory 290152 kb
Host smart-37937d09-ee6c-423c-8a64-dec4f79b4216
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295112762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3295112762
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3661120935
Short name T686
Test name
Test status
Simulation time 1431180952 ps
CPU time 12.38 seconds
Started Jul 05 04:42:45 PM PDT 24
Finished Jul 05 04:42:59 PM PDT 24
Peak memory 255736 kb
Host smart-7d802c67-1c4c-4e56-ae46-9cf309028bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36611
20935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3661120935
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2029780529
Short name T48
Test name
Test status
Simulation time 3406182425 ps
CPU time 50.57 seconds
Started Jul 05 04:42:50 PM PDT 24
Finished Jul 05 04:43:43 PM PDT 24
Peak memory 249324 kb
Host smart-d18ce798-67b1-48b8-ba15-f8dac9f5f7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20297
80529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2029780529
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.511485648
Short name T627
Test name
Test status
Simulation time 447202739 ps
CPU time 17.86 seconds
Started Jul 05 04:42:44 PM PDT 24
Finished Jul 05 04:43:03 PM PDT 24
Peak memory 256960 kb
Host smart-a57a4ad2-36a2-4db0-9ca8-552d9cfa536c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51148
5648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.511485648
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2856957556
Short name T174
Test name
Test status
Simulation time 504386698 ps
CPU time 27.47 seconds
Started Jul 05 04:42:43 PM PDT 24
Finished Jul 05 04:43:13 PM PDT 24
Peak memory 256316 kb
Host smart-475e93d7-93e9-4244-b678-edf0c639932c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28569
57556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2856957556
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3287919873
Short name T276
Test name
Test status
Simulation time 175408819382 ps
CPU time 2799.62 seconds
Started Jul 05 04:42:50 PM PDT 24
Finished Jul 05 05:29:32 PM PDT 24
Peak memory 289748 kb
Host smart-e690a830-122f-4891-ab28-4377b8f5c30a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287919873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3287919873
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3063322867
Short name T49
Test name
Test status
Simulation time 195926320240 ps
CPU time 7643.82 seconds
Started Jul 05 04:42:54 PM PDT 24
Finished Jul 05 06:50:20 PM PDT 24
Peak memory 322472 kb
Host smart-3fa7cc26-c41c-46ec-b4d7-0c08278f2904
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063322867 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3063322867
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2670417108
Short name T32
Test name
Test status
Simulation time 6717345883 ps
CPU time 951.91 seconds
Started Jul 05 04:44:09 PM PDT 24
Finished Jul 05 05:00:01 PM PDT 24
Peak memory 273400 kb
Host smart-46c37083-fed2-410d-8170-90114756f3ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670417108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2670417108
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3828519485
Short name T528
Test name
Test status
Simulation time 5097660599 ps
CPU time 164.39 seconds
Started Jul 05 04:44:11 PM PDT 24
Finished Jul 05 04:46:56 PM PDT 24
Peak memory 257544 kb
Host smart-adb845cf-a939-477a-8239-71c1d42a7ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38285
19485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3828519485
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1572341527
Short name T68
Test name
Test status
Simulation time 176688717 ps
CPU time 2.85 seconds
Started Jul 05 04:44:10 PM PDT 24
Finished Jul 05 04:44:13 PM PDT 24
Peak memory 240208 kb
Host smart-434bc244-a1d2-4517-afbb-04035353f162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15723
41527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1572341527
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.4261885545
Short name T264
Test name
Test status
Simulation time 190597613377 ps
CPU time 1865.21 seconds
Started Jul 05 04:44:16 PM PDT 24
Finished Jul 05 05:15:23 PM PDT 24
Peak memory 273260 kb
Host smart-389c2c0e-a08d-4354-befb-69c45e2e3ab1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261885545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.4261885545
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1487071887
Short name T625
Test name
Test status
Simulation time 14609704868 ps
CPU time 302.8 seconds
Started Jul 05 04:44:11 PM PDT 24
Finished Jul 05 04:49:14 PM PDT 24
Peak memory 248380 kb
Host smart-e68ba2fc-0bc3-474e-8003-dd8b7f43a8c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487071887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1487071887
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2253272492
Short name T441
Test name
Test status
Simulation time 385717214 ps
CPU time 41.96 seconds
Started Jul 05 04:44:10 PM PDT 24
Finished Jul 05 04:44:53 PM PDT 24
Peak memory 257400 kb
Host smart-ca35cd3c-4184-46fe-85a8-62961898cbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22532
72492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2253272492
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3791633468
Short name T243
Test name
Test status
Simulation time 1840613570 ps
CPU time 21.87 seconds
Started Jul 05 04:44:12 PM PDT 24
Finished Jul 05 04:44:35 PM PDT 24
Peak memory 249232 kb
Host smart-31c67cb7-739e-4209-8d74-e409e8c39d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37916
33468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3791633468
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1659115076
Short name T588
Test name
Test status
Simulation time 1176448209 ps
CPU time 50.31 seconds
Started Jul 05 04:44:12 PM PDT 24
Finished Jul 05 04:45:03 PM PDT 24
Peak memory 248804 kb
Host smart-1690e574-cf4c-4a18-a686-1b8a01e3e71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16591
15076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1659115076
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1600584917
Short name T215
Test name
Test status
Simulation time 844048432 ps
CPU time 27 seconds
Started Jul 05 04:44:09 PM PDT 24
Finished Jul 05 04:44:37 PM PDT 24
Peak memory 249716 kb
Host smart-83622997-3d08-4809-9d47-9d87a544e894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16005
84917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1600584917
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1721606324
Short name T612
Test name
Test status
Simulation time 51863920599 ps
CPU time 2065.21 seconds
Started Jul 05 04:44:17 PM PDT 24
Finished Jul 05 05:18:45 PM PDT 24
Peak memory 298500 kb
Host smart-c7674cdc-3473-4941-a88d-6bb9afb48cf1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721606324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1721606324
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2617354849
Short name T179
Test name
Test status
Simulation time 43325521284 ps
CPU time 5294.68 seconds
Started Jul 05 04:44:18 PM PDT 24
Finished Jul 05 06:12:36 PM PDT 24
Peak memory 339284 kb
Host smart-b16b6c81-e735-4bc3-9e2f-b20e0b56046c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617354849 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2617354849
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2418551315
Short name T502
Test name
Test status
Simulation time 89602598763 ps
CPU time 2224.27 seconds
Started Jul 05 04:44:21 PM PDT 24
Finished Jul 05 05:21:27 PM PDT 24
Peak memory 283184 kb
Host smart-4990cfaf-f9d1-403b-bb02-ba68f6a68ff3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418551315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2418551315
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2159120907
Short name T427
Test name
Test status
Simulation time 12958824882 ps
CPU time 60.71 seconds
Started Jul 05 04:44:16 PM PDT 24
Finished Jul 05 04:45:18 PM PDT 24
Peak memory 256792 kb
Host smart-e58240b7-7be1-4cb6-80fc-edde6c9e5a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21591
20907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2159120907
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.479618189
Short name T317
Test name
Test status
Simulation time 141514932852 ps
CPU time 1724.09 seconds
Started Jul 05 04:44:16 PM PDT 24
Finished Jul 05 05:13:01 PM PDT 24
Peak memory 265768 kb
Host smart-2a72772a-e58c-43fa-896d-a745467e3887
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479618189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.479618189
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3711544169
Short name T459
Test name
Test status
Simulation time 207521984417 ps
CPU time 3200.37 seconds
Started Jul 05 04:44:15 PM PDT 24
Finished Jul 05 05:37:37 PM PDT 24
Peak memory 290104 kb
Host smart-fcfb91e2-9340-485b-b30d-7829121508f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711544169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3711544169
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2389260905
Short name T291
Test name
Test status
Simulation time 8662431347 ps
CPU time 347.69 seconds
Started Jul 05 04:44:17 PM PDT 24
Finished Jul 05 04:50:07 PM PDT 24
Peak memory 249324 kb
Host smart-aa279df6-4ae1-4af1-9a7d-d7ccb3f0c111
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389260905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2389260905
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2623338621
Short name T396
Test name
Test status
Simulation time 4941468825 ps
CPU time 38.32 seconds
Started Jul 05 04:44:18 PM PDT 24
Finished Jul 05 04:44:59 PM PDT 24
Peak memory 249420 kb
Host smart-d63edcd5-da5a-4050-a1ba-13da98c14921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26233
38621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2623338621
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3797578630
Short name T189
Test name
Test status
Simulation time 988024140 ps
CPU time 30.62 seconds
Started Jul 05 04:44:17 PM PDT 24
Finished Jul 05 04:44:50 PM PDT 24
Peak memory 257420 kb
Host smart-c93ceb61-c271-4ebf-8458-aa8f2814cfe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37975
78630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3797578630
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.481010194
Short name T558
Test name
Test status
Simulation time 19299148 ps
CPU time 3.02 seconds
Started Jul 05 04:44:21 PM PDT 24
Finished Jul 05 04:44:26 PM PDT 24
Peak memory 241020 kb
Host smart-321899b6-7434-4c90-8a26-035d185e9fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48101
0194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.481010194
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.4134043329
Short name T643
Test name
Test status
Simulation time 878931653 ps
CPU time 30.4 seconds
Started Jul 05 04:44:18 PM PDT 24
Finished Jul 05 04:44:50 PM PDT 24
Peak memory 256444 kb
Host smart-e7b32b14-d895-4699-8d28-29863d6fd379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41340
43329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.4134043329
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1904290253
Short name T178
Test name
Test status
Simulation time 240090142640 ps
CPU time 3184.92 seconds
Started Jul 05 04:44:18 PM PDT 24
Finished Jul 05 05:37:25 PM PDT 24
Peak memory 300984 kb
Host smart-49a2299e-b639-4cd7-9a9f-fe3d031b2578
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904290253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1904290253
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1293881895
Short name T96
Test name
Test status
Simulation time 55495783262 ps
CPU time 1300.16 seconds
Started Jul 05 04:44:17 PM PDT 24
Finished Jul 05 05:06:00 PM PDT 24
Peak memory 282204 kb
Host smart-c77c77c3-9c3c-4f9b-bb4d-baf394a85298
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293881895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1293881895
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.565977645
Short name T645
Test name
Test status
Simulation time 935733642 ps
CPU time 65.16 seconds
Started Jul 05 04:44:17 PM PDT 24
Finished Jul 05 04:45:24 PM PDT 24
Peak memory 257452 kb
Host smart-c3915bae-510f-4d98-a48c-cd912d9227f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56597
7645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.565977645
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.794420340
Short name T567
Test name
Test status
Simulation time 2493285218 ps
CPU time 38.77 seconds
Started Jul 05 04:44:15 PM PDT 24
Finished Jul 05 04:44:55 PM PDT 24
Peak memory 255984 kb
Host smart-bafda68f-c330-4883-a6e2-a1db58dc4536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79442
0340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.794420340
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3694129850
Short name T220
Test name
Test status
Simulation time 8007359733 ps
CPU time 808.6 seconds
Started Jul 05 04:44:19 PM PDT 24
Finished Jul 05 04:57:50 PM PDT 24
Peak memory 273272 kb
Host smart-69c61fb8-dfe6-4ce6-a8fa-e6c3c92a53d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694129850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3694129850
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3250777266
Short name T5
Test name
Test status
Simulation time 35507086659 ps
CPU time 2372.89 seconds
Started Jul 05 04:44:16 PM PDT 24
Finished Jul 05 05:23:51 PM PDT 24
Peak memory 290144 kb
Host smart-0c0519bb-5fde-48ee-b0cf-ff958f463a38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250777266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3250777266
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2671228406
Short name T301
Test name
Test status
Simulation time 45276175628 ps
CPU time 377.46 seconds
Started Jul 05 04:44:16 PM PDT 24
Finished Jul 05 04:50:36 PM PDT 24
Peak memory 249352 kb
Host smart-42525fdf-7739-4cd3-bb0b-c52e75b37aa4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671228406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2671228406
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.301872737
Short name T671
Test name
Test status
Simulation time 40207412 ps
CPU time 7.7 seconds
Started Jul 05 04:44:19 PM PDT 24
Finished Jul 05 04:44:29 PM PDT 24
Peak memory 249300 kb
Host smart-13a6c073-ea56-4277-b911-2fab55062805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30187
2737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.301872737
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2907228248
Short name T443
Test name
Test status
Simulation time 29414414 ps
CPU time 5.18 seconds
Started Jul 05 04:44:19 PM PDT 24
Finished Jul 05 04:44:26 PM PDT 24
Peak memory 251444 kb
Host smart-e520f5ff-b6c1-438d-a9c3-a0c2c4728109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29072
28248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2907228248
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.735304316
Short name T256
Test name
Test status
Simulation time 3080988962 ps
CPU time 48.66 seconds
Started Jul 05 04:44:16 PM PDT 24
Finished Jul 05 04:45:06 PM PDT 24
Peak memory 249276 kb
Host smart-a2045eb0-36c6-44a3-b527-343606600911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73530
4316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.735304316
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2013298569
Short name T703
Test name
Test status
Simulation time 56609515 ps
CPU time 4.12 seconds
Started Jul 05 04:44:18 PM PDT 24
Finished Jul 05 04:44:24 PM PDT 24
Peak memory 249224 kb
Host smart-f0299028-8ca4-4cf5-962e-33ff6398c188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20132
98569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2013298569
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2345312472
Short name T639
Test name
Test status
Simulation time 1828619868 ps
CPU time 161.11 seconds
Started Jul 05 04:44:16 PM PDT 24
Finished Jul 05 04:46:58 PM PDT 24
Peak memory 257408 kb
Host smart-d4d2e573-5d5d-4ea7-8f56-ad9f7ffbb616
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345312472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2345312472
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1900051368
Short name T410
Test name
Test status
Simulation time 7640509718 ps
CPU time 601.47 seconds
Started Jul 05 04:44:20 PM PDT 24
Finished Jul 05 04:54:24 PM PDT 24
Peak memory 265784 kb
Host smart-48cc3ce8-205a-4a7e-ac50-30ed0efbb6ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900051368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1900051368
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3589220151
Short name T430
Test name
Test status
Simulation time 804587312 ps
CPU time 71.17 seconds
Started Jul 05 04:44:16 PM PDT 24
Finished Jul 05 04:45:28 PM PDT 24
Peak memory 256512 kb
Host smart-f2cff242-665a-4d29-8e4b-b75fa000fc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35892
20151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3589220151
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1250090197
Short name T640
Test name
Test status
Simulation time 188769164 ps
CPU time 26.47 seconds
Started Jul 05 04:44:15 PM PDT 24
Finished Jul 05 04:44:42 PM PDT 24
Peak memory 256360 kb
Host smart-194cf573-9dc3-4a1e-ae00-1bec763200d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12500
90197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1250090197
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1720086930
Short name T641
Test name
Test status
Simulation time 32422438450 ps
CPU time 2179.86 seconds
Started Jul 05 04:44:23 PM PDT 24
Finished Jul 05 05:20:44 PM PDT 24
Peak memory 282004 kb
Host smart-d630c8c5-2b39-4a65-9fc8-95d1de435579
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720086930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1720086930
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.478853667
Short name T464
Test name
Test status
Simulation time 75390179611 ps
CPU time 1129.88 seconds
Started Jul 05 04:44:24 PM PDT 24
Finished Jul 05 05:03:15 PM PDT 24
Peak memory 265600 kb
Host smart-f3a4c0b8-d0b5-446c-80cf-fa151bbd318e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478853667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.478853667
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1185954637
Short name T305
Test name
Test status
Simulation time 11044214183 ps
CPU time 243.34 seconds
Started Jul 05 04:44:23 PM PDT 24
Finished Jul 05 04:48:27 PM PDT 24
Peak memory 249140 kb
Host smart-88a854bb-622f-4262-8cef-9bb05c55b7d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185954637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1185954637
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.4237309542
Short name T531
Test name
Test status
Simulation time 1162392029 ps
CPU time 36.79 seconds
Started Jul 05 04:44:18 PM PDT 24
Finished Jul 05 04:44:57 PM PDT 24
Peak memory 249200 kb
Host smart-6f6e62b7-7a51-410c-a608-64074e5d73ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42373
09542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.4237309542
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3056172166
Short name T698
Test name
Test status
Simulation time 1451917812 ps
CPU time 51.76 seconds
Started Jul 05 04:44:17 PM PDT 24
Finished Jul 05 04:45:10 PM PDT 24
Peak memory 248804 kb
Host smart-b680300b-e1c2-4182-89d3-4a9741b47561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30561
72166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3056172166
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2553921607
Short name T368
Test name
Test status
Simulation time 393256227 ps
CPU time 12.66 seconds
Started Jul 05 04:44:17 PM PDT 24
Finished Jul 05 04:44:32 PM PDT 24
Peak memory 248452 kb
Host smart-a99b5178-a59e-4b3d-a9dd-8bccf114c953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25539
21607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2553921607
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2019247859
Short name T664
Test name
Test status
Simulation time 4573919075 ps
CPU time 72.69 seconds
Started Jul 05 04:44:21 PM PDT 24
Finished Jul 05 04:45:35 PM PDT 24
Peak memory 257548 kb
Host smart-061b39c1-6769-478d-ab95-210d847430de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20192
47859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2019247859
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.959958089
Short name T679
Test name
Test status
Simulation time 88618320198 ps
CPU time 2497.09 seconds
Started Jul 05 04:44:24 PM PDT 24
Finished Jul 05 05:26:03 PM PDT 24
Peak memory 289788 kb
Host smart-2933f1c8-1602-4937-9ca0-1f1e58d90c85
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959958089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.959958089
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3017083544
Short name T360
Test name
Test status
Simulation time 37377199992 ps
CPU time 1424.84 seconds
Started Jul 05 04:44:24 PM PDT 24
Finished Jul 05 05:08:10 PM PDT 24
Peak memory 290300 kb
Host smart-42ccc2dd-db72-4686-8db0-fa1412e577f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017083544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3017083544
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3184355303
Short name T501
Test name
Test status
Simulation time 1705058680 ps
CPU time 94.25 seconds
Started Jul 05 04:44:24 PM PDT 24
Finished Jul 05 04:46:00 PM PDT 24
Peak memory 257420 kb
Host smart-924214cf-6c63-468b-8e35-07d33f457f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31843
55303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3184355303
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1367671238
Short name T506
Test name
Test status
Simulation time 1958286376 ps
CPU time 55.4 seconds
Started Jul 05 04:44:26 PM PDT 24
Finished Jul 05 04:45:22 PM PDT 24
Peak memory 249328 kb
Host smart-2a70f196-fc37-4263-be7b-d85703a6141d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13676
71238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1367671238
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2297440061
Short name T333
Test name
Test status
Simulation time 20599869961 ps
CPU time 1674.09 seconds
Started Jul 05 04:44:24 PM PDT 24
Finished Jul 05 05:12:20 PM PDT 24
Peak memory 290252 kb
Host smart-ebc9047d-52aa-4b2c-8416-af251e00b8df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297440061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2297440061
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.292177962
Short name T389
Test name
Test status
Simulation time 118314455698 ps
CPU time 3370.78 seconds
Started Jul 05 04:44:25 PM PDT 24
Finished Jul 05 05:40:37 PM PDT 24
Peak memory 290384 kb
Host smart-9255a8cc-10fb-4122-acef-3910d1173e75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292177962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.292177962
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.977088945
Short name T690
Test name
Test status
Simulation time 17375727142 ps
CPU time 384.96 seconds
Started Jul 05 04:44:23 PM PDT 24
Finished Jul 05 04:50:50 PM PDT 24
Peak memory 249388 kb
Host smart-5258c82a-3c6a-4938-a04e-c7bd1e121c51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977088945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.977088945
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1996629161
Short name T41
Test name
Test status
Simulation time 462125551 ps
CPU time 11.03 seconds
Started Jul 05 04:44:22 PM PDT 24
Finished Jul 05 04:44:34 PM PDT 24
Peak memory 255628 kb
Host smart-c7fa29e5-ac92-4fc7-82f5-d56b467895df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19966
29161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1996629161
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.852771884
Short name T418
Test name
Test status
Simulation time 593230698 ps
CPU time 39.85 seconds
Started Jul 05 04:44:27 PM PDT 24
Finished Jul 05 04:45:07 PM PDT 24
Peak memory 249028 kb
Host smart-364c5333-3964-489f-bf6e-c62c647650e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85277
1884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.852771884
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.212705646
Short name T584
Test name
Test status
Simulation time 1918574943 ps
CPU time 28.53 seconds
Started Jul 05 04:44:26 PM PDT 24
Finished Jul 05 04:44:56 PM PDT 24
Peak memory 249468 kb
Host smart-85a13ffc-01bd-4cbb-86d4-0b08affe3104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21270
5646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.212705646
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.4237048206
Short name T61
Test name
Test status
Simulation time 47277585849 ps
CPU time 2911.47 seconds
Started Jul 05 04:44:24 PM PDT 24
Finished Jul 05 05:32:57 PM PDT 24
Peak memory 306432 kb
Host smart-cc8c5dd6-ecb3-40f7-887c-c1622f18612e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237048206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.4237048206
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3615072105
Short name T229
Test name
Test status
Simulation time 70969405011 ps
CPU time 2159 seconds
Started Jul 05 04:44:23 PM PDT 24
Finished Jul 05 05:20:23 PM PDT 24
Peak memory 290280 kb
Host smart-b38ebc38-67e8-46ab-b86a-9ac4caa4b84e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615072105 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3615072105
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2942432459
Short name T669
Test name
Test status
Simulation time 59887761107 ps
CPU time 2012.96 seconds
Started Jul 05 04:44:31 PM PDT 24
Finished Jul 05 05:18:06 PM PDT 24
Peak memory 282144 kb
Host smart-1d0187c3-70a4-41b5-a8c6-33bf495ac53e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942432459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2942432459
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.852025941
Short name T619
Test name
Test status
Simulation time 1724271162 ps
CPU time 129.39 seconds
Started Jul 05 04:44:32 PM PDT 24
Finished Jul 05 04:46:43 PM PDT 24
Peak memory 257372 kb
Host smart-edf3d280-70f5-46e7-98cf-39d2f17c6aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85202
5941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.852025941
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.767274485
Short name T63
Test name
Test status
Simulation time 4074729800 ps
CPU time 69.06 seconds
Started Jul 05 04:44:33 PM PDT 24
Finished Jul 05 04:45:43 PM PDT 24
Peak memory 249252 kb
Host smart-54dfe451-84fa-46e0-bb4c-5ed83dc60747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76727
4485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.767274485
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1868284713
Short name T542
Test name
Test status
Simulation time 101605084455 ps
CPU time 1763.95 seconds
Started Jul 05 04:44:31 PM PDT 24
Finished Jul 05 05:13:56 PM PDT 24
Peak memory 274052 kb
Host smart-09006881-2ab7-460e-9013-a175f54c08eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868284713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1868284713
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1482798450
Short name T304
Test name
Test status
Simulation time 27400640387 ps
CPU time 297.76 seconds
Started Jul 05 04:44:29 PM PDT 24
Finished Jul 05 04:49:28 PM PDT 24
Peak memory 256260 kb
Host smart-b576798e-b883-4a90-9b87-3087f69bc7bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482798450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1482798450
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.173860260
Short name T576
Test name
Test status
Simulation time 493586718 ps
CPU time 29.67 seconds
Started Jul 05 04:44:25 PM PDT 24
Finished Jul 05 04:44:56 PM PDT 24
Peak memory 249300 kb
Host smart-10cd0bf8-9c57-4776-aaac-87da4feb7a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17386
0260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.173860260
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3876751089
Short name T599
Test name
Test status
Simulation time 213290449 ps
CPU time 4.14 seconds
Started Jul 05 04:44:24 PM PDT 24
Finished Jul 05 04:44:30 PM PDT 24
Peak memory 241020 kb
Host smart-edac736f-64bc-48cc-b3db-56ba21e9e8d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38767
51089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3876751089
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2352621832
Short name T44
Test name
Test status
Simulation time 2418801406 ps
CPU time 20.88 seconds
Started Jul 05 04:44:31 PM PDT 24
Finished Jul 05 04:44:53 PM PDT 24
Peak memory 248924 kb
Host smart-5fd412f5-d0c7-4e17-bdd5-3f68e8e0f569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23526
21832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2352621832
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3814109773
Short name T605
Test name
Test status
Simulation time 1812721465 ps
CPU time 29.08 seconds
Started Jul 05 04:44:25 PM PDT 24
Finished Jul 05 04:44:56 PM PDT 24
Peak memory 256512 kb
Host smart-6ae33c6d-0212-40fc-8503-6e71ce8b2bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38141
09773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3814109773
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1121119447
Short name T107
Test name
Test status
Simulation time 36499642797 ps
CPU time 1177.57 seconds
Started Jul 05 04:44:29 PM PDT 24
Finished Jul 05 05:04:08 PM PDT 24
Peak memory 273876 kb
Host smart-20fda271-808c-4e93-8c36-25dfe9e77864
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121119447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1121119447
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2074993636
Short name T27
Test name
Test status
Simulation time 42154358531 ps
CPU time 1565.99 seconds
Started Jul 05 04:44:30 PM PDT 24
Finished Jul 05 05:10:37 PM PDT 24
Peak memory 287612 kb
Host smart-93f89430-2fac-429d-bbba-e6c051778e5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074993636 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2074993636
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3506367543
Short name T457
Test name
Test status
Simulation time 24033121468 ps
CPU time 1468.05 seconds
Started Jul 05 04:44:30 PM PDT 24
Finished Jul 05 05:09:00 PM PDT 24
Peak memory 271964 kb
Host smart-729669c2-c1a3-4f7a-a221-961d16df1c05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506367543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3506367543
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3906230342
Short name T23
Test name
Test status
Simulation time 2383591150 ps
CPU time 31.85 seconds
Started Jul 05 04:44:31 PM PDT 24
Finished Jul 05 04:45:04 PM PDT 24
Peak memory 256884 kb
Host smart-8b46612c-64c5-42ef-ab8b-91fff333c4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39062
30342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3906230342
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1062301669
Short name T485
Test name
Test status
Simulation time 64554540 ps
CPU time 3.09 seconds
Started Jul 05 04:44:31 PM PDT 24
Finished Jul 05 04:44:35 PM PDT 24
Peak memory 240464 kb
Host smart-4d710e72-992e-467a-9111-ef8daee9891c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10623
01669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1062301669
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.676562659
Short name T320
Test name
Test status
Simulation time 78364732807 ps
CPU time 1191.95 seconds
Started Jul 05 04:44:30 PM PDT 24
Finished Jul 05 05:04:24 PM PDT 24
Peak memory 273276 kb
Host smart-cf579815-a44f-4fbb-b043-a709bbf16446
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676562659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.676562659
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3832460351
Short name T668
Test name
Test status
Simulation time 395983173461 ps
CPU time 2259.94 seconds
Started Jul 05 04:44:33 PM PDT 24
Finished Jul 05 05:22:14 PM PDT 24
Peak memory 289996 kb
Host smart-b6ea54b5-f8d8-435f-8654-7473baad97e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832460351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3832460351
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2812013748
Short name T11
Test name
Test status
Simulation time 7208601041 ps
CPU time 262.48 seconds
Started Jul 05 04:44:31 PM PDT 24
Finished Jul 05 04:48:55 PM PDT 24
Peak memory 249132 kb
Host smart-51095551-fb76-4bcb-8eb8-03970dfe9ee3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812013748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2812013748
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2025964916
Short name T397
Test name
Test status
Simulation time 1107835433 ps
CPU time 19.34 seconds
Started Jul 05 04:44:30 PM PDT 24
Finished Jul 05 04:44:51 PM PDT 24
Peak memory 249176 kb
Host smart-7ff8aefe-dc16-4b17-9996-09476332d7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20259
64916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2025964916
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1029112937
Short name T282
Test name
Test status
Simulation time 953133971 ps
CPU time 11.99 seconds
Started Jul 05 04:44:32 PM PDT 24
Finished Jul 05 04:44:45 PM PDT 24
Peak memory 248740 kb
Host smart-d9d8a61f-afd8-474c-8fea-e0c487212dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10291
12937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1029112937
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3600975240
Short name T353
Test name
Test status
Simulation time 686361204 ps
CPU time 54.75 seconds
Started Jul 05 04:44:32 PM PDT 24
Finished Jul 05 04:45:28 PM PDT 24
Peak memory 256996 kb
Host smart-e46eb297-2685-4f33-9eff-3778b8ab4615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36009
75240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3600975240
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.926543738
Short name T532
Test name
Test status
Simulation time 376076927 ps
CPU time 22.79 seconds
Started Jul 05 04:44:30 PM PDT 24
Finished Jul 05 04:44:54 PM PDT 24
Peak memory 257312 kb
Host smart-9c916b1b-ff38-443e-8bc3-0bcd2728c698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92654
3738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.926543738
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2459825082
Short name T493
Test name
Test status
Simulation time 37683267129 ps
CPU time 1187.35 seconds
Started Jul 05 04:44:37 PM PDT 24
Finished Jul 05 05:04:25 PM PDT 24
Peak memory 273472 kb
Host smart-af9fbfcd-3fa7-43df-8be6-dac7a40361ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459825082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2459825082
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3811215706
Short name T704
Test name
Test status
Simulation time 259005886 ps
CPU time 15.52 seconds
Started Jul 05 04:44:39 PM PDT 24
Finished Jul 05 04:44:56 PM PDT 24
Peak memory 256956 kb
Host smart-0ece35eb-8cd8-4aaf-a047-a1b0eed80463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38112
15706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3811215706
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2209614473
Short name T710
Test name
Test status
Simulation time 300871642 ps
CPU time 31.41 seconds
Started Jul 05 04:44:32 PM PDT 24
Finished Jul 05 04:45:04 PM PDT 24
Peak memory 257008 kb
Host smart-77824306-8719-490d-b241-835f165b3e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22096
14473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2209614473
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.4237417993
Short name T7
Test name
Test status
Simulation time 32965752042 ps
CPU time 1284.34 seconds
Started Jul 05 04:44:39 PM PDT 24
Finished Jul 05 05:06:05 PM PDT 24
Peak memory 289452 kb
Host smart-7fc43186-2845-4af3-bc2f-ba8cb1f7edad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237417993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.4237417993
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3215534707
Short name T450
Test name
Test status
Simulation time 7035548770 ps
CPU time 859.38 seconds
Started Jul 05 04:44:38 PM PDT 24
Finished Jul 05 04:58:59 PM PDT 24
Peak memory 271940 kb
Host smart-d9cc6255-b410-41f6-9481-9e8f320787cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215534707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3215534707
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.152410176
Short name T308
Test name
Test status
Simulation time 16796600947 ps
CPU time 179.1 seconds
Started Jul 05 04:44:38 PM PDT 24
Finished Jul 05 04:47:37 PM PDT 24
Peak memory 256248 kb
Host smart-33e5d4c0-5102-4cad-95b0-cd338d477ce3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152410176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.152410176
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.4267991005
Short name T674
Test name
Test status
Simulation time 10784126034 ps
CPU time 57.64 seconds
Started Jul 05 04:44:30 PM PDT 24
Finished Jul 05 04:45:29 PM PDT 24
Peak memory 257180 kb
Host smart-6f49700a-41a4-4b74-b58a-46fcaff1ce95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42679
91005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.4267991005
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1952054887
Short name T693
Test name
Test status
Simulation time 1012975783 ps
CPU time 64.74 seconds
Started Jul 05 04:44:30 PM PDT 24
Finished Jul 05 04:45:36 PM PDT 24
Peak memory 256872 kb
Host smart-be4ec61d-c1a6-43ba-802f-85c56f295cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19520
54887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1952054887
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2604353790
Short name T211
Test name
Test status
Simulation time 86127918 ps
CPU time 10.35 seconds
Started Jul 05 04:44:37 PM PDT 24
Finished Jul 05 04:44:48 PM PDT 24
Peak memory 256764 kb
Host smart-9ba8d27d-8a83-4c9c-bc67-fa7544129764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26043
53790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2604353790
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.458957274
Short name T239
Test name
Test status
Simulation time 4467703923 ps
CPU time 59.35 seconds
Started Jul 05 04:44:30 PM PDT 24
Finished Jul 05 04:45:30 PM PDT 24
Peak memory 249716 kb
Host smart-80223f6b-127c-414d-bf47-ee074990161e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45895
7274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.458957274
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.597164287
Short name T401
Test name
Test status
Simulation time 470649974 ps
CPU time 57.48 seconds
Started Jul 05 04:44:37 PM PDT 24
Finished Jul 05 04:45:36 PM PDT 24
Peak memory 250256 kb
Host smart-eb0465d3-22b5-40c5-b110-7aa58c68273e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597164287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.597164287
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3695462184
Short name T653
Test name
Test status
Simulation time 25087486786 ps
CPU time 1820.95 seconds
Started Jul 05 04:44:38 PM PDT 24
Finished Jul 05 05:15:01 PM PDT 24
Peak memory 282992 kb
Host smart-4d154dae-dc00-44d4-a42c-4569cf36e998
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695462184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3695462184
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.4034210290
Short name T503
Test name
Test status
Simulation time 3429790011 ps
CPU time 159.07 seconds
Started Jul 05 04:44:38 PM PDT 24
Finished Jul 05 04:47:19 PM PDT 24
Peak memory 256836 kb
Host smart-d3b20fed-9418-494a-a39c-d9e6085fd252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40342
10290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.4034210290
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2870535296
Short name T466
Test name
Test status
Simulation time 3571627448 ps
CPU time 29.42 seconds
Started Jul 05 04:44:39 PM PDT 24
Finished Jul 05 04:45:10 PM PDT 24
Peak memory 257568 kb
Host smart-95fb4c1f-3a8f-47eb-88f6-a28398e6fa5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28705
35296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2870535296
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2139642397
Short name T330
Test name
Test status
Simulation time 24965603454 ps
CPU time 1603.36 seconds
Started Jul 05 04:44:38 PM PDT 24
Finished Jul 05 05:11:23 PM PDT 24
Peak memory 273236 kb
Host smart-1346bba1-47d6-4539-98b6-8f599d67e09f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139642397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2139642397
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3904319317
Short name T177
Test name
Test status
Simulation time 29355266319 ps
CPU time 1786.19 seconds
Started Jul 05 04:44:38 PM PDT 24
Finished Jul 05 05:14:25 PM PDT 24
Peak memory 282216 kb
Host smart-58f71bb7-fed4-4b74-83d3-7ce615a391c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904319317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3904319317
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1542556880
Short name T66
Test name
Test status
Simulation time 18068543000 ps
CPU time 372.66 seconds
Started Jul 05 04:44:38 PM PDT 24
Finished Jul 05 04:50:52 PM PDT 24
Peak memory 256088 kb
Host smart-479d09df-b7c0-43f2-a719-8710dad29315
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542556880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1542556880
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2939738382
Short name T580
Test name
Test status
Simulation time 328518644 ps
CPU time 21.05 seconds
Started Jul 05 04:44:38 PM PDT 24
Finished Jul 05 04:45:01 PM PDT 24
Peak memory 249220 kb
Host smart-ac35daa2-351e-402e-b3ed-093294c94a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29397
38382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2939738382
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1892559840
Short name T374
Test name
Test status
Simulation time 667001892 ps
CPU time 43.62 seconds
Started Jul 05 04:44:38 PM PDT 24
Finished Jul 05 04:45:24 PM PDT 24
Peak memory 248712 kb
Host smart-f0290420-30f7-427d-81e0-caf6da78959e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18925
59840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1892559840
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3572629463
Short name T100
Test name
Test status
Simulation time 170893634 ps
CPU time 20.72 seconds
Started Jul 05 04:44:38 PM PDT 24
Finished Jul 05 04:45:00 PM PDT 24
Peak memory 249236 kb
Host smart-7db39f03-c77e-4ae1-8927-9596b026262a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35726
29463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3572629463
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3532628633
Short name T591
Test name
Test status
Simulation time 338538274 ps
CPU time 27.15 seconds
Started Jul 05 04:44:37 PM PDT 24
Finished Jul 05 04:45:05 PM PDT 24
Peak memory 257008 kb
Host smart-44ae1a8b-f498-410a-bdb3-51d4264d828b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35326
28633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3532628633
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2980559969
Short name T88
Test name
Test status
Simulation time 5624128095 ps
CPU time 471.84 seconds
Started Jul 05 04:44:38 PM PDT 24
Finished Jul 05 04:52:30 PM PDT 24
Peak memory 265732 kb
Host smart-dd69a1d4-880c-4bc2-998f-fe28c96be164
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980559969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2980559969
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2487126218
Short name T581
Test name
Test status
Simulation time 38314979786 ps
CPU time 582.29 seconds
Started Jul 05 04:44:46 PM PDT 24
Finished Jul 05 04:54:30 PM PDT 24
Peak memory 273876 kb
Host smart-c39b695c-aa7a-45c2-9750-80e6289d6937
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487126218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2487126218
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.959847318
Short name T611
Test name
Test status
Simulation time 11493297553 ps
CPU time 171.76 seconds
Started Jul 05 04:44:36 PM PDT 24
Finished Jul 05 04:47:28 PM PDT 24
Peak memory 257600 kb
Host smart-af8e1a7e-c0f1-4d26-8f36-f6c4f7c01786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95984
7318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.959847318
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3468770653
Short name T269
Test name
Test status
Simulation time 173554445 ps
CPU time 13.05 seconds
Started Jul 05 04:44:38 PM PDT 24
Finished Jul 05 04:44:53 PM PDT 24
Peak memory 248796 kb
Host smart-42e8a131-24c9-4ee2-b47a-d547b776a329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34687
70653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3468770653
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1545926349
Short name T260
Test name
Test status
Simulation time 325475440627 ps
CPU time 1793.75 seconds
Started Jul 05 04:44:46 PM PDT 24
Finished Jul 05 05:14:41 PM PDT 24
Peak memory 273868 kb
Host smart-febf6439-07ad-4ce5-b8fc-38f916a747d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545926349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1545926349
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2867611008
Short name T579
Test name
Test status
Simulation time 9713514793 ps
CPU time 860.42 seconds
Started Jul 05 04:44:44 PM PDT 24
Finished Jul 05 04:59:06 PM PDT 24
Peak memory 273432 kb
Host smart-0b355638-e741-4765-af80-7a9472b98602
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867611008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2867611008
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1010323201
Short name T313
Test name
Test status
Simulation time 6055162173 ps
CPU time 254.72 seconds
Started Jul 05 04:44:45 PM PDT 24
Finished Jul 05 04:49:01 PM PDT 24
Peak memory 249372 kb
Host smart-57d04081-e4a9-4081-986f-5bc55911e286
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010323201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1010323201
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1494223679
Short name T597
Test name
Test status
Simulation time 358892166 ps
CPU time 11.57 seconds
Started Jul 05 04:44:39 PM PDT 24
Finished Jul 05 04:44:52 PM PDT 24
Peak memory 249300 kb
Host smart-f753f174-3590-4fcd-9f23-cd093685cffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14942
23679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1494223679
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3612074004
Short name T655
Test name
Test status
Simulation time 65249178 ps
CPU time 6.89 seconds
Started Jul 05 04:44:37 PM PDT 24
Finished Jul 05 04:44:45 PM PDT 24
Peak memory 254044 kb
Host smart-15ff5fc0-2e82-4b18-87fc-c3ab0f6f7c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36120
74004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3612074004
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.522964745
Short name T390
Test name
Test status
Simulation time 346683105 ps
CPU time 35.9 seconds
Started Jul 05 04:44:39 PM PDT 24
Finished Jul 05 04:45:16 PM PDT 24
Peak memory 249272 kb
Host smart-f7ae144d-1342-4afd-bd89-4901fbd78aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52296
4745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.522964745
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2823499053
Short name T210
Test name
Test status
Simulation time 56623143 ps
CPU time 3.05 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 04:42:53 PM PDT 24
Peak memory 249572 kb
Host smart-bb7ec7e6-16ca-464a-ae17-f7aa4d1f4d83
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2823499053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2823499053
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1300212840
Short name T293
Test name
Test status
Simulation time 167875663447 ps
CPU time 1185.05 seconds
Started Jul 05 04:42:49 PM PDT 24
Finished Jul 05 05:02:37 PM PDT 24
Peak memory 290388 kb
Host smart-ad49c31f-afce-4a9f-949d-396d522c1f0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300212840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1300212840
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.4037548254
Short name T551
Test name
Test status
Simulation time 347367049 ps
CPU time 16.27 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 04:43:07 PM PDT 24
Peak memory 249140 kb
Host smart-8cc4f6d1-2702-4377-b1e9-aa9b5d88fd7a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4037548254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.4037548254
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2567943460
Short name T630
Test name
Test status
Simulation time 4433499748 ps
CPU time 65.54 seconds
Started Jul 05 04:42:51 PM PDT 24
Finished Jul 05 04:43:58 PM PDT 24
Peak memory 256740 kb
Host smart-32ac69c2-0948-4ae3-b764-5887175f0028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25679
43460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2567943460
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3203282315
Short name T74
Test name
Test status
Simulation time 97347087 ps
CPU time 10.78 seconds
Started Jul 05 04:42:53 PM PDT 24
Finished Jul 05 04:43:05 PM PDT 24
Peak memory 257476 kb
Host smart-8d543190-bc4d-49d4-9282-4e3833b84721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32032
82315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3203282315
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.853057885
Short name T323
Test name
Test status
Simulation time 16954346782 ps
CPU time 1189.49 seconds
Started Jul 05 04:42:49 PM PDT 24
Finished Jul 05 05:02:41 PM PDT 24
Peak memory 283704 kb
Host smart-7d698bf6-83af-4583-9bfe-a65512a91cd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853057885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.853057885
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2323763919
Short name T538
Test name
Test status
Simulation time 165270372082 ps
CPU time 1118.7 seconds
Started Jul 05 04:42:47 PM PDT 24
Finished Jul 05 05:01:28 PM PDT 24
Peak memory 289960 kb
Host smart-6c5944c4-900b-4c5b-8df0-76e90111772b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323763919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2323763919
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2222609615
Short name T687
Test name
Test status
Simulation time 9306826051 ps
CPU time 372.19 seconds
Started Jul 05 04:42:53 PM PDT 24
Finished Jul 05 04:49:06 PM PDT 24
Peak memory 256044 kb
Host smart-06ff4ea6-f564-4e2f-8394-c1b4a0c350c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222609615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2222609615
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3820440414
Short name T37
Test name
Test status
Simulation time 78188387 ps
CPU time 6.36 seconds
Started Jul 05 04:42:53 PM PDT 24
Finished Jul 05 04:43:00 PM PDT 24
Peak memory 249272 kb
Host smart-d6b2b5eb-83c8-4df3-853a-d2facad943b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38204
40414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3820440414
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1941217251
Short name T530
Test name
Test status
Simulation time 120175193 ps
CPU time 8.02 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 04:43:10 PM PDT 24
Peak memory 248500 kb
Host smart-87b01969-60f4-493a-bb25-d35aeb0d8561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19412
17251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1941217251
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.334913889
Short name T409
Test name
Test status
Simulation time 325315988 ps
CPU time 30.33 seconds
Started Jul 05 04:42:53 PM PDT 24
Finished Jul 05 04:43:25 PM PDT 24
Peak memory 256952 kb
Host smart-112040a9-bc09-4287-a3eb-1ead3009dd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33491
3889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.334913889
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2601294546
Short name T529
Test name
Test status
Simulation time 1429685079 ps
CPU time 52.87 seconds
Started Jul 05 04:43:03 PM PDT 24
Finished Jul 05 04:43:58 PM PDT 24
Peak memory 256588 kb
Host smart-c171f6f1-068a-4148-bb0c-bb17db100232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26012
94546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2601294546
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2635049419
Short name T554
Test name
Test status
Simulation time 45921302296 ps
CPU time 2433.89 seconds
Started Jul 05 04:42:49 PM PDT 24
Finished Jul 05 05:23:26 PM PDT 24
Peak memory 290208 kb
Host smart-107f5479-1ea0-4543-b0ce-7efe85fdc1e9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635049419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2635049419
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2312515456
Short name T198
Test name
Test status
Simulation time 38839542 ps
CPU time 3.43 seconds
Started Jul 05 04:42:58 PM PDT 24
Finished Jul 05 04:43:02 PM PDT 24
Peak memory 249600 kb
Host smart-39817083-13a8-4002-b3ee-96cff86b1cc8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2312515456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2312515456
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2239446422
Short name T8
Test name
Test status
Simulation time 26075507932 ps
CPU time 1405.53 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 05:06:31 PM PDT 24
Peak memory 273924 kb
Host smart-c8970b20-a13f-4030-b78b-c3091113ffc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239446422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2239446422
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.548107776
Short name T523
Test name
Test status
Simulation time 356229472 ps
CPU time 10.15 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 04:43:01 PM PDT 24
Peak memory 249184 kb
Host smart-89179c5e-4dc2-4454-a5f6-70b98b90a7da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=548107776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.548107776
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3014534424
Short name T467
Test name
Test status
Simulation time 2100408072 ps
CPU time 52.92 seconds
Started Jul 05 04:42:47 PM PDT 24
Finished Jul 05 04:43:42 PM PDT 24
Peak memory 256660 kb
Host smart-502a1b7a-1810-47f3-8675-59aeb778ba0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30145
34424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3014534424
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.209818089
Short name T624
Test name
Test status
Simulation time 30627610 ps
CPU time 2.93 seconds
Started Jul 05 04:42:49 PM PDT 24
Finished Jul 05 04:42:55 PM PDT 24
Peak memory 240536 kb
Host smart-dc86dbf1-c315-4a14-ac68-40073dea8cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20981
8089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.209818089
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3723796779
Short name T331
Test name
Test status
Simulation time 8224456802 ps
CPU time 707.76 seconds
Started Jul 05 04:42:54 PM PDT 24
Finished Jul 05 04:54:42 PM PDT 24
Peak memory 273976 kb
Host smart-7cdd03b1-4729-47b0-a36b-5cb07ce0133a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723796779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3723796779
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.465464197
Short name T536
Test name
Test status
Simulation time 39242409889 ps
CPU time 962.07 seconds
Started Jul 05 04:43:06 PM PDT 24
Finished Jul 05 04:59:10 PM PDT 24
Peak memory 290028 kb
Host smart-db93339a-8194-45d3-805f-19cc2da72d69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465464197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.465464197
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1403191966
Short name T621
Test name
Test status
Simulation time 10450189078 ps
CPU time 212.22 seconds
Started Jul 05 04:42:55 PM PDT 24
Finished Jul 05 04:46:28 PM PDT 24
Peak memory 255688 kb
Host smart-15ed3794-b5b0-4570-8455-9b5a6561dfe5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403191966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1403191966
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3543028286
Short name T512
Test name
Test status
Simulation time 862345705 ps
CPU time 50.32 seconds
Started Jul 05 04:42:55 PM PDT 24
Finished Jul 05 04:43:46 PM PDT 24
Peak memory 249160 kb
Host smart-da3893c7-29ce-430c-b9a5-07c24212634b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35430
28286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3543028286
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.238139977
Short name T428
Test name
Test status
Simulation time 637650109 ps
CPU time 36.61 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 04:43:41 PM PDT 24
Peak memory 249292 kb
Host smart-6fff8aaa-56e6-413e-9255-b60b5eac60e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23813
9977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.238139977
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.159815974
Short name T672
Test name
Test status
Simulation time 303904340 ps
CPU time 32.63 seconds
Started Jul 05 04:42:55 PM PDT 24
Finished Jul 05 04:43:28 PM PDT 24
Peak memory 249244 kb
Host smart-fe573e36-2c8d-4412-9606-22860821522b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15981
5974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.159815974
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1971227560
Short name T511
Test name
Test status
Simulation time 453964625 ps
CPU time 26.38 seconds
Started Jul 05 04:42:53 PM PDT 24
Finished Jul 05 04:43:21 PM PDT 24
Peak memory 257052 kb
Host smart-e14b8144-45fd-437a-b152-d70610129441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19712
27560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1971227560
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1198182536
Short name T234
Test name
Test status
Simulation time 31626805799 ps
CPU time 1997.64 seconds
Started Jul 05 04:42:47 PM PDT 24
Finished Jul 05 05:16:07 PM PDT 24
Peak memory 288212 kb
Host smart-ad694b34-5466-479f-b280-38fca95605e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198182536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1198182536
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3201561276
Short name T358
Test name
Test status
Simulation time 18084721524 ps
CPU time 1236.66 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 05:03:28 PM PDT 24
Peak memory 274116 kb
Host smart-26cfd9c4-3dcd-42fb-b20d-86527ffea2be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201561276 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3201561276
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1473314139
Short name T202
Test name
Test status
Simulation time 55644009 ps
CPU time 3.94 seconds
Started Jul 05 04:42:56 PM PDT 24
Finished Jul 05 04:43:01 PM PDT 24
Peak memory 249520 kb
Host smart-126fd978-63fc-48d3-a4b3-feded6e36635
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1473314139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1473314139
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2868230027
Short name T522
Test name
Test status
Simulation time 42244121622 ps
CPU time 2548.04 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 05:25:19 PM PDT 24
Peak memory 290064 kb
Host smart-df5ee78f-668d-4228-82d5-258660473d6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868230027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2868230027
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2800591045
Short name T176
Test name
Test status
Simulation time 285049683 ps
CPU time 8.31 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 04:42:59 PM PDT 24
Peak memory 249260 kb
Host smart-23261611-1581-486c-a6e0-84a5e5e8b490
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2800591045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2800591045
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1025701113
Short name T221
Test name
Test status
Simulation time 2214291265 ps
CPU time 56.51 seconds
Started Jul 05 04:42:55 PM PDT 24
Finished Jul 05 04:43:52 PM PDT 24
Peak memory 250448 kb
Host smart-103a276d-864c-4f1e-9e62-565d177f21b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10257
01113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1025701113
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3014009770
Short name T355
Test name
Test status
Simulation time 8904595815 ps
CPU time 49.79 seconds
Started Jul 05 04:42:53 PM PDT 24
Finished Jul 05 04:43:44 PM PDT 24
Peak memory 249036 kb
Host smart-5c75b014-cee5-40ab-a44c-5c2fa162102c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30140
09770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3014009770
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.613348588
Short name T242
Test name
Test status
Simulation time 60245623319 ps
CPU time 946.19 seconds
Started Jul 05 04:42:49 PM PDT 24
Finished Jul 05 04:58:38 PM PDT 24
Peak memory 273936 kb
Host smart-61a04d37-aa95-4e36-9656-f41ba1b8a7be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613348588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.613348588
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.417095056
Short name T377
Test name
Test status
Simulation time 31171067322 ps
CPU time 1850.14 seconds
Started Jul 05 04:42:53 PM PDT 24
Finished Jul 05 05:13:44 PM PDT 24
Peak memory 273940 kb
Host smart-9d2f04cc-7710-4c94-9866-455ef26decd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417095056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.417095056
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.4004714032
Short name T706
Test name
Test status
Simulation time 2609307125 ps
CPU time 28.66 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 04:43:32 PM PDT 24
Peak memory 256968 kb
Host smart-c3546883-b945-42e2-b766-cf1fb8629eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40047
14032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.4004714032
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2079151548
Short name T705
Test name
Test status
Simulation time 2099951119 ps
CPU time 53.85 seconds
Started Jul 05 04:42:55 PM PDT 24
Finished Jul 05 04:43:50 PM PDT 24
Peak memory 257412 kb
Host smart-8923b4e4-9624-4411-9c52-afcecab84611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20791
51548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2079151548
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2835592670
Short name T470
Test name
Test status
Simulation time 320025155 ps
CPU time 10.57 seconds
Started Jul 05 04:42:55 PM PDT 24
Finished Jul 05 04:43:06 PM PDT 24
Peak memory 249192 kb
Host smart-6d53df0d-f931-4f85-9783-c1847de1d208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28355
92670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2835592670
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1124890287
Short name T620
Test name
Test status
Simulation time 301335672 ps
CPU time 24.36 seconds
Started Jul 05 04:42:47 PM PDT 24
Finished Jul 05 04:43:14 PM PDT 24
Peak memory 257392 kb
Host smart-068a33e8-881a-4301-94fe-6101c33dda38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11248
90287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1124890287
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.469397691
Short name T348
Test name
Test status
Simulation time 3562258428 ps
CPU time 215.43 seconds
Started Jul 05 04:42:50 PM PDT 24
Finished Jul 05 04:46:27 PM PDT 24
Peak memory 257456 kb
Host smart-381ce430-9577-4cd9-9f11-99159ff284bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469397691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.469397691
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3858931556
Short name T230
Test name
Test status
Simulation time 457435266029 ps
CPU time 5208.98 seconds
Started Jul 05 04:42:54 PM PDT 24
Finished Jul 05 06:09:44 PM PDT 24
Peak memory 315040 kb
Host smart-d09134a1-0310-497b-8d8d-8947998f459f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858931556 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3858931556
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2376197895
Short name T204
Test name
Test status
Simulation time 39584860 ps
CPU time 3.05 seconds
Started Jul 05 04:43:06 PM PDT 24
Finished Jul 05 04:43:11 PM PDT 24
Peak memory 249560 kb
Host smart-65bf63d5-20ae-4dfe-9fc3-2912f69c11a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2376197895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2376197895
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3858940450
Short name T72
Test name
Test status
Simulation time 37591453991 ps
CPU time 833.71 seconds
Started Jul 05 04:42:55 PM PDT 24
Finished Jul 05 04:56:50 PM PDT 24
Peak memory 268764 kb
Host smart-5c9c4c57-d9c7-4fe5-9046-b5fee0500c54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858940450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3858940450
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1547304642
Short name T541
Test name
Test status
Simulation time 848240781 ps
CPU time 37.16 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 04:43:39 PM PDT 24
Peak memory 249160 kb
Host smart-52cc5bd7-5e80-4640-b69a-ebc4f033ada5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1547304642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1547304642
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2115408
Short name T646
Test name
Test status
Simulation time 1681782018 ps
CPU time 123.79 seconds
Started Jul 05 04:42:48 PM PDT 24
Finished Jul 05 04:44:55 PM PDT 24
Peak memory 257336 kb
Host smart-415b4301-f13b-4c3a-95eb-aa7377ec7312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21154
08 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2115408
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.122801337
Short name T477
Test name
Test status
Simulation time 488814921 ps
CPU time 27.66 seconds
Started Jul 05 04:42:53 PM PDT 24
Finished Jul 05 04:43:21 PM PDT 24
Peak memory 249244 kb
Host smart-84586d5c-d7a0-478f-a0de-bd43d57a9b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12280
1337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.122801337
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.742446919
Short name T318
Test name
Test status
Simulation time 28438736961 ps
CPU time 1605.99 seconds
Started Jul 05 04:42:53 PM PDT 24
Finished Jul 05 05:09:40 PM PDT 24
Peak memory 273928 kb
Host smart-179b50b3-0b63-41f6-b1f0-ba9b4dc73bca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742446919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.742446919
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.958675447
Short name T577
Test name
Test status
Simulation time 26554273256 ps
CPU time 1618.52 seconds
Started Jul 05 04:42:59 PM PDT 24
Finished Jul 05 05:09:58 PM PDT 24
Peak memory 284484 kb
Host smart-31716366-e557-47cc-bb37-85c381ebf3fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958675447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.958675447
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.847036137
Short name T426
Test name
Test status
Simulation time 3364076798 ps
CPU time 144.2 seconds
Started Jul 05 04:42:55 PM PDT 24
Finished Jul 05 04:45:20 PM PDT 24
Peak memory 249144 kb
Host smart-5312b4fa-cb31-4451-93dc-36687c143874
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847036137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.847036137
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3223007441
Short name T521
Test name
Test status
Simulation time 4767921883 ps
CPU time 25.21 seconds
Started Jul 05 04:42:54 PM PDT 24
Finished Jul 05 04:43:20 PM PDT 24
Peak memory 256656 kb
Host smart-f5fe6470-a393-419d-897f-fe664781d066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32230
07441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3223007441
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3892611511
Short name T59
Test name
Test status
Simulation time 786238622 ps
CPU time 21.32 seconds
Started Jul 05 04:42:49 PM PDT 24
Finished Jul 05 04:43:13 PM PDT 24
Peak memory 256232 kb
Host smart-3b83927e-02de-43f7-81e6-c68c4df9a8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38926
11511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3892611511
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.225260568
Short name T280
Test name
Test status
Simulation time 49301582 ps
CPU time 4.41 seconds
Started Jul 05 04:42:50 PM PDT 24
Finished Jul 05 04:42:57 PM PDT 24
Peak memory 249584 kb
Host smart-38f5d1d6-08d8-4dbf-9bc0-15de481a0bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22526
0568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.225260568
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2707552198
Short name T578
Test name
Test status
Simulation time 2446570694 ps
CPU time 28.75 seconds
Started Jul 05 04:42:53 PM PDT 24
Finished Jul 05 04:43:22 PM PDT 24
Peak memory 257496 kb
Host smart-087ef1ed-6e4f-4b9d-ab4f-cc9c86d562a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27075
52198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2707552198
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3518326084
Short name T707
Test name
Test status
Simulation time 216996577742 ps
CPU time 2984.29 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 05:32:47 PM PDT 24
Peak memory 289732 kb
Host smart-c0187697-c331-4255-9141-8ea9c23e3099
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518326084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3518326084
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.76001977
Short name T281
Test name
Test status
Simulation time 36050872605 ps
CPU time 3100.9 seconds
Started Jul 05 04:43:04 PM PDT 24
Finished Jul 05 05:34:48 PM PDT 24
Peak memory 322192 kb
Host smart-6c637704-8055-4828-b6a2-10771b04c362
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76001977 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.76001977
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3222698973
Short name T206
Test name
Test status
Simulation time 58234481 ps
CPU time 4.7 seconds
Started Jul 05 04:43:06 PM PDT 24
Finished Jul 05 04:43:13 PM PDT 24
Peak memory 249528 kb
Host smart-a69c692e-16ce-447d-99a9-4292621d70db
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3222698973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3222698973
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3387254647
Short name T495
Test name
Test status
Simulation time 195465956040 ps
CPU time 2721.17 seconds
Started Jul 05 04:43:03 PM PDT 24
Finished Jul 05 05:28:27 PM PDT 24
Peak memory 290204 kb
Host smart-63c87610-761a-42a0-a7b7-21c5194f805d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387254647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3387254647
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.4258853104
Short name T637
Test name
Test status
Simulation time 1534348114 ps
CPU time 33.39 seconds
Started Jul 05 04:43:18 PM PDT 24
Finished Jul 05 04:43:53 PM PDT 24
Peak memory 249268 kb
Host smart-0ca501d6-66ff-4e1e-966d-a7cef9131087
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4258853104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.4258853104
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1938289012
Short name T533
Test name
Test status
Simulation time 14234260568 ps
CPU time 183.9 seconds
Started Jul 05 04:43:09 PM PDT 24
Finished Jul 05 04:46:15 PM PDT 24
Peak memory 257140 kb
Host smart-41c9eae6-63c1-41b1-a28e-45110cd5eefd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19382
89012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1938289012
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3507581730
Short name T369
Test name
Test status
Simulation time 1312747798 ps
CPU time 41.61 seconds
Started Jul 05 04:43:09 PM PDT 24
Finished Jul 05 04:43:53 PM PDT 24
Peak memory 249636 kb
Host smart-8329cca9-bee5-44db-9cc7-3fa515abaf33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35075
81730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3507581730
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1377444870
Short name T651
Test name
Test status
Simulation time 170040356085 ps
CPU time 2622.59 seconds
Started Jul 05 04:42:55 PM PDT 24
Finished Jul 05 05:26:39 PM PDT 24
Peak memory 290332 kb
Host smart-5cce1d01-0dd4-4a14-8e5f-9047580e0878
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377444870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1377444870
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2753524199
Short name T45
Test name
Test status
Simulation time 43923333494 ps
CPU time 2089.64 seconds
Started Jul 05 04:43:02 PM PDT 24
Finished Jul 05 05:17:54 PM PDT 24
Peak memory 289184 kb
Host smart-122d26ef-4365-4336-99df-61cef11909e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753524199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2753524199
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.335976838
Short name T685
Test name
Test status
Simulation time 12906426873 ps
CPU time 559.5 seconds
Started Jul 05 04:43:10 PM PDT 24
Finished Jul 05 04:52:31 PM PDT 24
Peak memory 249348 kb
Host smart-707e8366-ba56-49cc-8385-6c266cba2a24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335976838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.335976838
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.87140896
Short name T42
Test name
Test status
Simulation time 984362914 ps
CPU time 53.18 seconds
Started Jul 05 04:43:00 PM PDT 24
Finished Jul 05 04:43:54 PM PDT 24
Peak memory 257320 kb
Host smart-7072a77e-0e22-44c1-8214-f08255f69856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87140
896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.87140896
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1098147903
Short name T561
Test name
Test status
Simulation time 171958600 ps
CPU time 12.65 seconds
Started Jul 05 04:43:09 PM PDT 24
Finished Jul 05 04:43:23 PM PDT 24
Peak memory 254428 kb
Host smart-d07bbccb-e0fb-4188-948e-5640b141290a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10981
47903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1098147903
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1706684919
Short name T412
Test name
Test status
Simulation time 237311723 ps
CPU time 19.91 seconds
Started Jul 05 04:43:01 PM PDT 24
Finished Jul 05 04:43:23 PM PDT 24
Peak memory 257400 kb
Host smart-c65bf4bf-f328-4036-9f32-69944cb52d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17066
84919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1706684919
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.755955823
Short name T572
Test name
Test status
Simulation time 968864971 ps
CPU time 15.08 seconds
Started Jul 05 04:43:10 PM PDT 24
Finished Jul 05 04:43:27 PM PDT 24
Peak memory 249220 kb
Host smart-c53aa5e5-1942-4e7b-8f47-680b180b02ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75595
5823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.755955823
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1086843474
Short name T552
Test name
Test status
Simulation time 12298371506 ps
CPU time 138.8 seconds
Started Jul 05 04:43:17 PM PDT 24
Finished Jul 05 04:45:38 PM PDT 24
Peak memory 257504 kb
Host smart-dcefcbae-9a87-40e6-b446-08e5e96e0ec0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086843474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1086843474
Directory /workspace/9.alert_handler_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%