Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	88837	1			T1	545		T6	3638		T13	7
class_i[0x1]	84785	1			T1	173		T4	4		T15	1
class_i[0x2]	42008	1			T4	10		T5	7		T13	2516
class_i[0x3]	82187	1			T1	21		T6	5		T17	433

---

Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	75109	1			T1	485		T4	4		T6	886
alert[0x1]	77298	1			T1	54		T6	971		T17	96
alert[0x2]	73895	1			T1	159		T4	2		T5	6
alert[0x3]	71515	1			T1	41		T4	8		T5	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

297520

1

T1

739

T4

10

T5

7

esc_ping_fail

297

1

T4

4

T7

6

T9

6

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	75023	1			T1	485		T4	3		T6	886
esc_integrity_fail	alert[0x1]	77223	1			T1	54		T6	971		T17	96
esc_integrity_fail	alert[0x2]	73820	1			T1	159		T4	1		T5	6
esc_integrity_fail	alert[0x3]	71454	1			T1	41		T4	6		T5	1
esc_ping_fail	alert[0x0]	86	1			T4	1		T7	2		T9	2
esc_ping_fail	alert[0x1]	75	1			T7	2		T9	1		T14	1
esc_ping_fail	alert[0x2]	75	1			T4	1		T7	2		T9	2
esc_ping_fail	alert[0x3]	61	1			T4	2		T9	1		T15	2

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	88749	1			T1	545		T6	3638		T13	7
esc_integrity_fail	class_i[0x1]	84718	1			T1	173		T48	9		T49	10
esc_integrity_fail	class_i[0x2]	41913	1			T4	10		T5	7		T13	2516
esc_integrity_fail	class_i[0x3]	82140	1			T1	21		T6	5		T17	433
esc_ping_fail	class_i[0x0]	88	1			T7	6		T9	6		T14	6
esc_ping_fail	class_i[0x1]	67	1			T4	4		T15	1		T227	1
esc_ping_fail	class_i[0x2]	95	1			T15	8		T194	1		T213	1
esc_ping_fail	class_i[0x3]	47	1			T15	1		T213	1		T308	4